1
Features
•Operating Supply Range 3.0V to 3.6V
•Power Dissipation 1W Max
•Low-power Sleep Mode (<0.5 mW)
•RF Data Channel
– Automatic Gain Control or Programmable Gain Mode
– Wide Bandwidth VGA
– VGA Accepts Inputs from 30–300 mV Peak-to-peak Differential (PPD),
60–600 mVPPD or 110–1100 mVPPD
– Programmable Equalization via 7th-order Equiripple Filter with Programmable
Symmetric Zeros
– Programmable 5-to-1 Filter Cutoff Range
– Data Slicer with DC Restore Circuit
– Wide Frequency Range Clock Extraction
– Frequency Synthesizer with Independent 7-bit M and 6-bit N Dividers,
Better than 1% Resolution
– Highly Programmable to Accommodate DVD (1–5X) and CD (6–30X)
– Write Asymmetry Measurement for Adjusting Write-mode Power
– Data Recovery Supports CLV, ZCLV, ZCAV Recording
– Optional Internally-generated Timing for AGC and Timing Recovery
•Synthesizer Functions
– Supports Wobble Clock Synthesis, Using Low-jitter PLL
•Servo Algebra and OPC Functions
– 45 MHz Bandwidth for Differential Phase Tracking Detector
– Land and Groove Detector for DVD RAM
– Supports One Beam Push/Pull Tracking Output
– Supports One Beam Differential Phase Tracking
– Supports Three-beam Push/Pull Tracking Output, Using E, F, G, H
– Focus Error Signal Output
– Focus OK Signal
– Track Crossing Detection
– Mirror Signal Output
– Wobble Detection for DVD RAM, DVD-RW, DVD-R
– Detects Tracking Error OK
– Provides Sample and Hold Functions for CD and DVD OPC
– Formats Pre-pit Data, Using Raw Pre-pit Information from AT78C1503
•Header Detection for DVD RAM
Description
The AT78C1503 is a programmable DVD/CD channel responsible for servo algebra, gain con-
trol, equalization, bit detection and clock extraction for CD-ROM, DVD-ROM, DVD-R, DVD-RW
and DVD-RAM formats. Programmable features allow data rates up to 5X DVD. Also, for DVD-
RAM functionality, the channel serves the write path providing laser power control and pit asym-
metry detection. Up to 2X DVD write speeds are supported for DVD-R, DVD-RW and DVD-
RAM. The extracted wobble frequency is supplied to the AT78C1507 companion chip which in
turn synthesizes the write clock.
The AT78C1507 is the companion chip to the AT78C1503 – DVD/CD Read Channel – and the
AT78C1504 – DVD/CD Automatic Laser Power Controller. Working in conjunction with the read
channel, the AT78C1507 is responsible for wobble clock synthesis for DVD-R and DVD-RAM
formats. In addition, the two parts working together also support pre-pit data and clock recovery
for the DVD-R format. Four separate inputs are provided to enable the AT78C1507 to perform
tracking servo algebra, using just the outrigger photo detector signals (E, F, G, H for example)
coming from the OPU. This extends the range of supported tracking servo algebra functions for
the 1503-1507 combination. Lastly, OPC capability is supported for efficient writing of DVD-R,
DVD-RAM and CD-R disks.
Based on CMOS technology, both the AT78C1503 and AT78C1507 operate from a single 3.3V
supply and are fully programmable through serial interfaces for both CD and DVD modes.
DVD/CD Read
Channel
AT78C1503
AT78C1507
Rev. 2054A–DVD–07/02
2DVD/CD Read Channel
2054A–DVD–07/02
Figure 1. DVD System Block Diagram
Sled
Focus Spindle
Laser
T08XX
Laser Amp
AT78C1505
Pre-amp
Power
Drivers
DRAM
AT78C1501
ATAPI I/F
Controller
DBM
ECC
SRAM
ARM7TDMI
AT78C1502
Servo
Control
System
Flash
AT78C1503
Read
Channel
AT78C1504
Laser Power
Controller
AT78C1507
Read
Channel Adj.
3
DVD/CD Read Channel
2054A–DVD–07/02
Figure 2. AT78C1503 Block Diagram
VGA
VGA
VGA
VGA
VGA
FREF
DATA 7
DATA 6
DATA 5
DATA 4
DATA 3
DATA 2
DATA 1
DATA 0
RCLK
IDFIELD
RDSZ
TOK
TZC
TE
WOBBLE
ID12
ID34
FE
FOK
MIRROR
SLOWSUM
RFDROP
RG
WG
PD
FREQUENCY
SYNTHESIZER
DATA
PLL
DC
RESTORE
MUX
TRACK OK
TRACK
ZERO
CROSS
MUX
58
70
69
68
67
66
65
64
63
62
01
09
48
47
28
44
45
46
27
49
50
29
59
41
77
40
AUTO
INV
VGA
AGC
CONTROL
7th ORDER
FILTER/
EQUALIZER
MUX
SERREG
FCDAC
REG9 <4 0>
BST1 / BST2
REG 8
CAGC
100
(RF Sequencer)
Control
RFGEN
Sum of
Selectable
Buffer Sum of
Difference
AGC
Control
Voltage
Sum of
Selectable
Buffer
DIFFERENTIAL
TRACKING
DETECTOR
DTR2
Slow Arithmetic
and Normalization
Push/Pull
Tracking
Focus Error
Mirror Detector
Wobble Detector
Land-groove
Detector
16
17
18
19
13
FO1-CD
FO2-CD
TR1-CD
TR2-CD
REXT VREF
D/SE
D/SE
D/SE
D/SE
TEST
SERIAL
REGISTER MODE
CONTROL
/
127
P N P N P N P N
TP1 TP2 TP3 TP4
93 92 91 90 93 82 85 84 51 53 52
NA
C
LK
A
TA
AGCLZ
AGCHLD
RFP/N
98
94
2/3
4/5
6/7
8/9
FO1P/N
FO2P/N
TR1P/N
TR2P/N 10/
11
FOCUS OK
4DVD/CD Read Channel
2054A–DVD–07/02
Figure 3. AT78C1503 Pin-out
Table 1. AT78C1503 Pin List
Pin # Pin Name Type Description
1 IDFIELD Digital Output Signal to Preamp to Drive ID Select
2 RFP Analog Input High-speed Signal Input
3 RFN Analog Input High-speed Signal Input
4 FO1P Diff Input Focus 1 Pos
5 FO1N Diff Input Focus 1 Neg
6 FO2P Diff Input Focus 2 Pos
7 FO2N Diff Input Focus 2 Neg
8 TR1P Diff Input Track 1 Pos
9 TR1N Diff Input Track 1 Neg
10 TR2P Diff Input Track 2 Pos
11 TR2N Diff Input Track 2 Neg
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AT78C1503
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IDFEILD
RFP
RFN
FO1P
FO1N
FO2P
FO2N
TR1P
TR1N
TR2P
TR2N
FOHG
REXT
VDD1
VSS1
FO1_CD
FO2_CD
TR1_CD
TR2_CD
VDD6
SS_H
VSS6
REFFRONT
REFBACK
LENSPOS
CACG
RDSZ
ACGLZ
VDD10
VSS10
AGCFST
AGCHLD
TP1P
TP1N
TP2P
TP2N
VSS2
VDD2
CDCRP
CDCRN
TSDDTP2P
TSDDTP2N
TSDDTP1P
TSDDTP1N
TRSIN1P
TRSIN1N
TRSIN2P
TRSIN2N
WG
WCLK
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TRCST
VDD3
VSS3
VDD11
VSS11
D ATA 7
D ATA 6
D ATA 5
D ATA 4
D ATA 3
D ATA 2
D ATA 1
D ATA 0
RCLK
RFDROP
VDD5
VSS5
FREF
VDD7
VSS7
VDD4
VSS4
SCLK
S D ATA
SENA
ATP1
FE
TE
SLOWSUM
PORB
VSS8
VDD8
IDSEL
LHIPWR
SHLD
ADCSTRT
BWUP
BWDWN
IDINT
PD
RG
VSS9
VDD9
WOBBLE
ID12
ID34
TZC
TOK
FOK
MIRROR
5
DVD/CD Read Channel
2054A–DVD–07/02
12 FOHG Digital Input Focus High Gain
13 REXT Passive Passive for 0 TC Current Reference (16.5 K_, 1%)
14 VDD1 3.3V Supply DPD, IBIAS
15 VSS1 0V Supply DPD, IBIAS
16 FO1_CD Analog Input Focus 1, CD Input
17 FO2_CD Analog Input Focus 2, CD Input
18 TR1_CD Analog Input Track 1, CD Input
19 TR2_CD Analog Input Track 2, CD Input
20 VDD6 3.3V Supply Slow Servo Analog
21 SS_H Digital Input Servo Sample and Hold
22 VSS6 0V Supply Slow Servo Analog
23 REFFRONT Input/Output Servo Front-end Reference Level
24 REFBACK Input/Output Servo back-end Reference Level
25 LENSPOS Analog Input Lens Position Error Input
26 ATP1 Analog Output Servo Analog Test Point
27 FE Analog Output Focus Error Output
28 TE Analog Output Tracking Error Output
29 SLOWSUM Analog Output Low-pass Filtered Sum of Photodetector Outputs
30 PORB Digital Input Power-on Reset, Bar (active-low)
31 VSS8 0V Supply Servo DACs
32 VDD8 3.3V Supply Servo DACs
33 IDSEL Digital Input ID Field Select
34 LHIPWR Digital Input Laser High Power
35 SHLD Digital Input Servo Hold
36 ADCSTRT Digital Input Start On-chip 6-bit ADC
37 BWUP Digital Input Bandwidth Up
38 BWDN Digital Input Bandwidth Down
39 IDINT Digital Input Mode Select of Sequencer
40 PD Digital Input Power-down
41 RG Digital Input User Data Read Gate
42 VSS9 0V Supply Servo DAC Rings
43 VDD9 3.3V Supply Servo DAC Rings
44 WOBBLE Digital Output Wobble Detect Output
45 ID12 Digital Output ID Field 12 Detected
46 ID34 Digital Output ID Field 34 Detected
47 TZC Digital Output Track Zero Crossing
Table 1. AT78C1503 Pin List (Continued)
Pin # Pin Name Type Description
6DVD/CD Read Channel
2054A–DVD–07/02
48 TOK Digital Output Track OK
49 FOK Digital Output Focus OK
50 MIRROR Digital Output Mirror Detect (ROM)/Mirror Field Detect (RAM)
51 SENA Digital Input Serial Data Enable; Must Be High to Read or Write
Serial Registers
52 SDATA Input/Output Serial Data, Input (write data) or Output (read data)
53 SCLK Digital Input Serial Data Clock
54 VSS4 0V Supply ESD Ring, Digital Ring
55 VDD4 3.3V Supply ESD Ring, Digital Ring
56 VSS7 0V Supply Slow Servo Digital, Synthesizer Dividers
57 VDD7 3.3V Supply Slow Servo Digital, Synthesizer Dividers
58 FREF Digital Input Reference Clock Input to Synthesizer
59 VSS5 0V Supply Digital I/O Supply
60 VDD5 3.3V Supply Digital I/O Supply
61 RFDROP Digital Output RF Dropout Detected
62 RCLK Digital Output Recovered Clock Divided by 4 or 8
63 DATA0 Digital Output Recovered Data Out, Bit 0 (last in time)
64 DATA1 Digital Output Recovered Data Out, Bit 1
65 DATA2 Digital Output Recovered Data Out, Bit 2
66 DATA3 Digital Output Recovered Data Out, Bit 3
67 DATA4 Digital Output Recovered Data Out, Bit 4
68 DATA5 Digital Output Recovered Data Out, Bit 5
69 DATA6 Digital Output Recovered Data Out, Bit 6
70 DATA7 Digital Output Recovered Data Out, Bit 7 (first in time)
71 VSS11 0V Supply Digital I/O Ring
72 VDD11 3.3V Supply Digital I/O Ring
73 VSS3 0V Supply TR CML, Synthesizer CML, DC Restore
74 VDD3 3.3V Supply TR CML, Synthesizer CML, DC Restore
75 TRCST Digital Input Timing Recovery Coast
76 WCLK Digital Output Write Clock
77 WG Digital Input Write Gate (enables write clock)
78 TRSIN2N Diff Input Timing Recovery/Synthesizer Test Input
79 TRSIN2P Diff Input Timing Recovery/Synthesizer Test Input
80 TRSIN1N Diff Input Timing Recovery/Synthesizer Test Input
81 TRSIN1P Diff Input Timing Recovery/Synthesizer Test Input
82 TSDDTP1N Test Output TR/Detector/Phase Detector Test Input
Table 1. AT78C1503 Pin List (Continued)
Pin # Pin Name Type Description
7
DVD/CD Read Channel
2054A–DVD–07/02
83 TSDDTP1P Test Output TR/Detector/Phase Detector Test Point
84 TSDDTP2N Test Output TR/Detector/Phase Detector Test Input
85 TSDDTP2P Test Output TR/Detector/Phase Detector Test Input
86 CDCRN Diff Passive Detector Duty Cycle Feedback Cap
87 CDCRP Diff Passive Detector Duty Cycle Feedback Cap
88 VDD2 3.3V Supply RF Front-end Ring
89 VSS2 0V Supply RF Front-end Ring
90 TP2N Diff Output Test Point 2 Output
91 TP2P Diff Output Test Point 2 Output
92 TP1N Diff Output Test Point 1 Output
93 TP1P Diff Output Test Point 1 Output
94 AGCHLD Digital Input AGC Hold Input
95 AGCFST Digital Input AGC Fast Recovery Input
96 VSS10 0V Supply AGC, LPF
97 VDD10 3.3V Supply AGC, LPF
98 AGCLZ Digital Input Low Z Control for AGC Input
99 RDSZ Analog Output AGC Cap/Detector Cap Voltage Outputs
100 CAGC Passive External Capacitor for AGC Loop
Table 2. Supply Pins
Supply Pin Circuitry
VDD/SS1 DPD, IBIAS, RTRIM
VDD/SS2 RF Front-end Ring
VDD/SS3 TR & Synth CML, DC Restore, RF Dropout Analog
VDD/SS4 ESD & Digital Ring
VDD/SS5 Digital I/O Supply
VDD/SS6 Servo Analog
VDD/SS7 Servo, Synth and RF Dropout Digital, CMOSTPMUX, Serial Registers 1
and 3, Calibrator
VDD/SS8 Servo DACs
VDD/SS9 Servo DAC Rings
VDD/SS10 AGC, LPF
VDD/SS11 Digital I/O Ring
Table 1. AT78C1503 Pin List (Continued)
Pin # Pin Name Type Description
8DVD/CD Read Channel
2054A–DVD–07/02
Figure 4. AT78C1507 Block Diagram – Wobble PLL and OPC Sample and Hold
VCO
Q Pump
Phase/Frequency
Comparator
1/186
1/(P+1)
76
WCLK
86
87
Reg50
<3:2> 61
27
37
38
19
WOB2X
SELOPC
CD/DVD
SHCD
SHDVD
DVDOPC
OPCOUT
S&H
for
OPC
PCLK
PTSEL
PTOP
PBOT
98
95
94
62
PDATA
FF
RS
D
Q
WOBBLE
WOBLE X 186
WOBBLE + 180 DEG
MUX
MUX
75 SFLTP
SFLTN
WBLIN
18 CDOPC
9
DVD/CD Read Channel
2054A–DVD–07/02
Figure 5. AT78C1507 –Tracking Error Path
SHSB GSEL
Reg 49<7:4>
BWSEL
Reg 49<3:0> SE
TP2
29
SE
TP2
30
SE
TP2
31
SE
TP2
32
Reg. 51–58 <7:3>
Reg. 62–65
(E+F) − (G+H)
+
Normalization
(−)
(+)
Gain &
Offset
Adj
Gain &
Offset
Adj
Gain &
Offset
Adj
Gain &
Offset
Adj
V21
V21
V21
V21
BW/LPF
BW/LPF
BW/LPF
BW/LPF
D2SE
D2SE
D2SE
D2SE
21
Sample
& Hold
Sample
& Hold
Sample
& Hold
Sample
& Hold
4/5
6/7
8/9
10/11
"E"
P/N
"F"
P/N
"G"
P/N
"H"
P/N
Outrigger
Signals
SUMSB 29
Outrigger Tracking Error
REFBACK
SE
TP2
28
24
12V
TRI2VHIG
Reg 56<2>
TEG1\I2VLOG
Reg 68 <3:0>
TEG1\I2VHIG
Reg 68 <7:4>
SELTE
Reg 56 <0>
IDINT
Reg 32 <6>
VGA
TEGOUT
Reg 69 <3:0>
LPF
100 kHz
TE
28
POLMB
Reg 66 <2>
TEMB
Pin 25 25
From 1503
GSELMB
Reg 68 <7:4>
Vref
Main Beam
DC
Offset
TEOFF
Reg 57 <2:0>
+
SGNTEOFF
Reg 56 <1>
SE
TP2
25
ENMB
Reg 66<1>
10 DVD/CD Read Channel
2054A–DVD–07/02
Figure 6. AT78C1507 Pin-out
Table 3. AT78C1507 Pin List
Pin # Pin Name Type Description
1 NC0 Digital Output Not Used
2 NC1 Analog Input Not Used
3 NC2 Analog Input Not Used
4 EP Diff Input “E”Input Pos
5 EN Diff Input “E”Input Neg
6 FP Diff Input “F”Input Pos
7 FN Diff Input “F”Input Neg
8 GP Diff Input “G”Input Pos
9 GN Diff Input “G”Input Neg
10 HP Diff Input “H”Input Pos
11 HN Diff Input “H”Input Neg
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AT78C1507
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC0
NC1
NC2
EP
EN
FP
FN
GP
GN
HP
HN
WBLCOAST
REXT
VDD1
VSS1
TLOW2
TLOW3
CDOPC
DVDOPC
VDD6
SHSB
VSS6
REFFRONT
REFBACK
TEMB
ATP1
OPCOUT
TE
SUMSB
PORB
VSS6
VDD8
TLOW4
LHIPWR
THI1
ADCSTRT
SHCD
SHDVD
TLOW7
TLOW8
THI2
VSS9
VDD9
NC4
NC9
NC10
TZC
TOK
NC5
ND6
WBLIN
VDD3
VSS3
VDD11
VSS11
CTP7
CTP6
CTP5
CTP4
CTP3
CTP2
CTP1
CTP0
P D ATA
PCLK
VDD5
VSS6
FREF
VDD7
VSS7
VDD4
VSS4
SCLK
S D ATA
SENA
11
DVD/CD Read Channel
2054A–DVD–07/02
12 WBLCOAST Digital Input Coast Wobble Clock Synthesizer
13 REXT Passive 16 K_, 1% Resistor to 0V Supply
(for on-chip biasing)
14 VDD1 3.3V Supply Power Supply
15 VSS1 0V Supply Power Supply
16 TLOW2 0V Tie-down to a 0V Supply
17 TLOW3 0V Tie-down to a 0V Supply
18 CDOPC Analog Input CD Monitor Diode
19 DVDOPC Analog Input DVD Monitor Diode
20 VDD6 3.3V Supply Power Supply
21 SHSB Digital Input Sample/Hold Control for E, F, G, H
(1 = Sample, 0 = Hold)
22 VSS6 0V Supply Power Supply
23 REFFRONT Input/Output Front-end Reference Voltage
24 REFBACK Input/Output Back-end Reference Voltage
25 TEMB Analog Input Tracking Error Main Beam from AT78C1503
(generated using A, B, C, D)
26 ATP1 Analog Output Analog Test Point (single-ended)
27 OPCOUT Analog Output Sampled Monitor Diode Output
28 TE Analog Output Tracking Error Output
29 SUMSB AnalogOutput E+F+G+H
30 PORB Digital Input Power-on Reset, Bar (active-low)
31 VSS8 0V Supply Power Supply
32 VDD8 3.3V Supply Power Supply
33 TLOW4 0V Tie-down to a 0V Supply
34 LHIPWR Digital Input Laser High Power
35 THI1 3.3V Tie-up to a 3.3V Supply
36 ADCSTRT Digital Input Start on-chip 6-bit ADC
37 SHCD Digital Input Sample/Hold Control for CD Monitor Diode
(1 = Sample, 0 = Hold)
38 SHDVD Digital Input Sample/Hold Control for DVD Monitor Diode
(1 = Sample, 0 = Hold)
39 TLOW7 0V Tie-down to a 0V Supply
40 TLOW8 0V Tie-down to a 0V Supply
41 THI2 3.3V Tie-up to a 3.3V Supply
42 VSS9 0V Supply Power Supply
43 VDD9 3.3V Supply Power Supply
Table 3. AT78C1507 Pin List (Continued)
Pin # Pin Name Type Description
12 DVD/CD Read Channel
2054A–DVD–07/02
44 NC4 Digital Output Not Used
45 NC9 Digital Output Not Used
46 NC10 Digital Output Not Used
47 TZC Digital Output Track Zero Crossing
48 TOK Digital Output Tracking Error OK
49 NC5 Digital Output Not Used
50 NC6 Digital Output Not Used
51 SENA Digital Input Serial Data Enable
(mustbehightoreadorwriteserialregisters)
52 SDATA Input/Output Serial Data, Input (write data) or Output (read
data)
53 SCLK Digital Input Serial Data Clock
54 VSS4 0V Supply Power Supply
55 VDD4 3.3V Supply Power Supply
56 VSS7 0V Supply Power Supply
57 VDD7 3.3V Supply Power Supply
58 FREF Digital Input Frequency Reference for Wobble Clock
Synthesizer
59 VSS5 0V Supply Power Supply
60 VDD5 3.3V Supply Power Supply
61 PCLK Digital Output Pre-pit Clock
62 PDATA Digital Output Pre-pit Data
63 CTP0 Digital Output Digital Test Point Out, Bit 0
64 CTP1 Digital Output Digital Test Point Out, Bit 1
65 CTP2 Digital Output Digital Test Point Out, Bit 2
66 CTP3 Digital Output Digital Test Point Out, Bit 3
67 CTP4 Digital Output Digital Test Point Out, Bit 4
68 CTP5 Digital Output Digital Test Point Out, Bit 5
69 CTP6 Digital Output Digital Test Point Out, Bit 6
70 CTP7 Digital Output Digital Test Point Out, Bit 7
71 VSS11 0V Supply Power Supply
72 VDD11 3.3V Supply Power Supply
73 VSS3 0V Supply Power Supply
74 VDD3 3.3V Supply Power Supply
75 WBLIN Digital Input Raw Digital Wobble from AT78C1503
76 WCLK Digital Output Write Clock (synthesized wobble clock)
77 WCLKEN Digital Input Write Clock Enable
Table 3. AT78C1507 Pin List (Continued)
Pin # Pin Name Type Description
13
DVD/CD Read Channel
2054A–DVD–07/02
78 TLOW9 0V Tie-down to a 0V Supply
79 TLOW10 0V Tie-down to a 0V Supply
80 TLOW11 0V Tie-down to a 0V Supply
81 TLOW12 0V Tie-down to a 0V Supply
82 TSDDTP1N Test Output Differential Analog/CML Test Point1 Neg
83 TSDDTP1P Test Output Differential Analog/CML Test Point1 Pos
84 TSDDTP2N Test Output Differential Analog/CML Test Point2 Neg
85 TSDDTP2P Test Output Differential Analog/CML Test Point2 Pos
86 SFILTN Diff Passive Wobble Synthesizer Filter Neg
87 SFILTP Diff Passive Wobble Synthesizer Filter Pos
88 VDD2 3.3V Supply Power Supply
89 VSS2 0V Supply Power Supply
90 TP2N Diff Output Not Used
91 TP2P Diff Output Not Used
92 TP1N Diff Output Not Used
93 TP1P Diff Output Not Used
94 PBOT Digital Input Bottom Pre-pit Detect from AT78C1503
95 PTOP Digital Input Top Pre-pit Detect from AT78C1503
96 VSS10 0V Supply Power Supply
97 VDD10 3.3V Supply Power Supply
98 PTSEL Digital Input
Pre-pit Top Select
(PTSEL = 1 selects input on pin PTOP;
PTSEL = 0 selects input on PBOT)
99 NC7 Analog Output Not Used
100 NC8 Passive Not Used
Table 3. AT78C1507 Pin List (Continued)
Pin # Pin Name Type Description
Printed on recycled paper.
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Atmel Headquarters Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
2054A–DVD–07/02
AT M E L ®is the registered trademark of Atmel.
