FEATURES 10 mV sensitivity rail to rail at VCC = 2.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V Low glitch CMOS-/TTL-compatible output stage Complementary outputs 3 ns propagation delay 15 mW at 3.3 V Shutdown pin Single-pin control for programmable hysteresis and latch Power supply rejection > 60 dB -40C to +125C operation FUNCTIONAL BLOCK DIAGRAM VP NONINVERTING INPUT Q OUTPUT ADCMP603 TTL Q OUTPUT VN INVERTING INPUT 05915-001 Preliminary Technical Data Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator ADCMP603 LE/HYS INPUT SDN INPUT 10 Q TOP VIEW (Not to Scale) VP 4 VEE 3 ADCMP603 9 VEE 8 LE/HYS 7 SDN 05915-002 VCCI 2 PIN 1 INDICATOR VN 6 VCCO 1 VEE 5 High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) 12 Q APPLICATIONS 11 VEE Figure 1. Figure 2. LFCSP Pin Configuration GENERAL DESCRIPTION The ADCMP603 is a very fast comparator fabricated on Analog Devices' proprietary XFCB2 process. This comparator is exceptionally versatile and easy to use. Features include an input range from VEE - 0.5 V to VCC + 0.5 V, low noise complementary TTL-/CMOS-compatible output drivers, and latch inputs with adjustable hysteresis and/or a shutdown input. The device offers 3 ns propagation delay with 5 mV overdrive on 4 mA typical supply current. A flexible power supply scheme allows the device to operate with a single +2.5 V positive supply and a -0.5 V to +3.0 V input signal range up to a +5.5 V positive supply with a -0.5 V to +6 V input signal range. Split input/output supplies with no sequencing restrictions support a wide input signal range while still allowing independent output swing control and power savings. The complementary TTL-/CMOS-compatible output stage is designed to drive up to 5 pF with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP603 is available in a 12-lead LSCFP package. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. ADCMP603 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Application Information...................................................................9 Applications....................................................................................... 1 Power/Ground Layout and Bypassing........................................9 Functional Block Diagram .............................................................. 1 TTL-/CMOS-Compatible Output Stage ....................................9 General Description ......................................................................... 1 Using/Disabling the Latch Feature..............................................9 Revision History ............................................................................... 2 Optimizing Performance........................................................... 10 Electrical Characteristics ................................................................. 3 Comparator Propagation Delay Dispersion ........................... 10 Absolute Maximum Ratings............................................................ 5 Comparator Hysteresis .............................................................. 10 Thermal Resistance ...................................................................... 5 Crossover Bias Point .................................................................. 11 ESD Caution.................................................................................. 5 Minimum Input Slew Rate Requirement ................................ 11 Pin Configuration and Function Descriptions............................. 6 Typical Application Circuits ......................................................... 12 Typical Performance Characteristics ............................................. 7 Timing Information ....................................................................... 13 REVISION HISTORY 3/06--Revision PrA: Preliminary Version Rev. PrA | Page 2 of 16 Preliminary Technical Data ADCMP603 ELECTRICAL CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Hysteresis LATCH ENABLE PIN CHARACTERISTICS VIH VIL IIH IOL HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS VIH VIL IIH IOL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Symbol Conditions Min VP, VN VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V -0.5 -0.2 VOS IP, IN -5.0 -5.0 2.0 CP, CN 0.1 V to VCC -0.5 V to VCC + 0.5 V AV CMRR VCCI = 2.5 V, VCCO = 2.5 V, VCM = -0.2 V to 2.7 V VCCI = 5.5 V, VCCO = 5.5 V, VCM = -0.2 V to 5.7 V RHYS = tS tH tPLOH, tPLOL tPL tSD tH VOH VOL Hysteresis is shut off Latch mode guaranteed VIH = VCCV VIL = 0.4 V 2.0 -0.2 Current sink 0 A Hysteresis = 16 mV VOD = 100 mV VOD = 100 mV VOD = 100 mV VOD = 100 mV 1.145 150 Comparator is operating Shutdown guaranteed VIH = VCC VIL = 0 V ICC < 300 A VOD = 10 mV VCCO = 2.5 V to 6 V IOH = 12 mA VCCO = 2.5 V IOL = 12 mA, VCCO = 2.5 V 2.0 -0.2 Rev. PrA | Page 3 of 16 Typ Max Unit VCC + 0.5 V VCC + 0.2 V VCC +5.0 +5.0 2.0 TBD 100 100 85 50 V V V mV A A pF k k dB dB 60 dB 0.1 mV 2 +0.4 1.25 VCC +0.8 0.2 -0.2 V V mA mA 1.35 V k ns ns ns ns VCCO +0.6 0.3 -0.3 V V mA mA ns ns 2 5 3 3 +0.4 60 40 VCC - 0.4 0.4 V V ADCMP603 Parameter AC PERFORMANCE Propagation Delay Propagation Delay Skew--Rising to Falling Transition Overdrive Dispersion Slew Rate Dispersion Pulse-Width Dispersion 10% to 90% Duty Cycle Dispersion Common-Mode Dispersion Toggle Rate Deterministic Jitter TTL/CMOS Outputs RMS Random Jitter Minimum Pulse Width Rise Time Fall Time Output skew POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential Positive Supply Differential Input Section Supply Current Output Section Supply Current Power Dissipation Power Supply Rejection Preliminary Technical Data Symbol Conditions tPD VCCO = 2.5 V to 5.5 V, VOD = 5 mV VCCO = 2.5 V to 5.5 V, VOD = 200 mV VOD = 5 mV DJ RJ PWMIN tR tF tSKEW VCCI VCCO VCCI - VCCO VCCI - VCCO IVCCI IVCCO PD PD PSRR Min 10 mV < VOD < 2.5 V 0.05 V/ns to 2.5 V/ns 3 ns to 20 ns 1 V/ns, VCM = 2.5 V 0 < VCM < VCC >50% output swing VOD = 200 mV, 5 V/ns, PRBS31 - 1 NRZ, 0.25 Gbps VOD = 200 mV, 5 V/ns tPD/PW < 50 ps 10% to 90%, CLOAD = 5 pF, VCCO = 5 V 10% to 90%, CLOAD = 5 pF, VCCO = 5 V 50% CLOAD = 5 pF Typ Max Unit 3 ns 2.5 ns 200 ps TBD TBD TBD TBD TBD TBD TBD ps ps ps ps ps Mbps ns TBD 3 2.0 ps ns ns 2.0 ns 300 ps Operating 2.5 2.5 -3.0 5.5 5.5 +3.0 V V V Nonoperating -5.5 +5.5 V VCCI = 2.5 V to 5 V VCCI = 5.5 V VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V to 5 V Rev. PrA | Page 4 of 16 0.8 2.8 9 20 -50 mA mA mW mW dB Preliminary Technical Data ADCMP603 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI - VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating -0.5 V to +6.0 V -0.5 V to +6.0 V -6.0 V to +6.0 V -0.5 V to VCCI + 0.5 V (VCCI + 0.5 V) 50 mA THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance -0.5 V to VCCO + 0.5 V 50 mA -0.5 V to VCCO + 0.5 V 50 mA 50 mA Package Type ADCMP603 LSCFP 12-lead 1 Measurement in still air. -40C to +125C 150C -65C to +150C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA | Page 5 of 16 JA 1 62 Unit C/W ADCMP603 Preliminary Technical Data 10 Q 9 VEE 8 LE/HYS 7 SDN 05915-002 TOP VIEW (Not to Scale) VP 4 VEE 3 ADCMP603 VN 6 VCCI 2 PIN 1 INDICATOR VEE 5 VCCO 1 11 VEE 12 Q PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. ADCMP603 Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VCCO VCCI VEE VP VEE VN SDN LE/HYS VEE Q 11 12 VEE Q Heat Sink Paddle VEE Description Output Section Supply. Input Section Supply. Negative Supply Voltage. Noninverting Analog Input. Negative Supply Voltage. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. Negative Supply Voltage. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE pin description (Pin 8) for more information. Negative Supply Voltage. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE pin description (Pin 8) for more information. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. PrA | Page 6 of 16 Preliminary Technical Data ADCMP603 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = VCCO = 2.5 V, TA = 25C, unless otherwise noted. Figure 4. Propagation Delay vs. Input Overdrive Figure 7. Hysteresis vs. VCC Figure 5. Propagation Delay vs. Input Common Mode Figure 8. Hysteresis vs. RHYS Control Resistor Figure 6. Propagation Delay vs. Temperature Figure 9. Input Bias Current vs. Input Common Mode Rev. PrA | Page 7 of 16 ADCMP603 Preliminary Technical Data Figure 10. Input Bias Current vs. Temperature Figure 12. Latch/Hysteresis Control Pin I/V Characteristics Figure 11. Input Offset Voltage vs. Temperature Rev. PrA | Page 8 of 16 Preliminary Technical Data ADCMP603 APPLICATION INFORMATION The ADCMP603 comparator is a very high speed device. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 F bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the VCCO pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. If the input and output supplies have been connected separately such that VCCI VCCO, care should be taken to bypass each of these supplies separately to the GND plane. A bypass capacitor should never be connected between them. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. This enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI = VCCO, coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs. TTL-/CMOS-COMPATIBLE OUTPUT STAGE Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. The low skew complementary outputs of the ADCMP603 are designed to directly drive one Schottky TTL or three low power Schottky TTL loads or equivalent. For large fan outputs, buses, or transmission lines, an appropriate buffer should be used to maintain the comparator's excellent speed and stability. With the rated 5 pF load capacitance applied, more than half of the total device propagation delay is output stage slew time, even at 2.5 V VCC. Because of this, the total prop delay decreases as VCCO decreases, and instability in the power supply may appear as excess delay dispersion. This delay is measured to the 50% point for the supply in use; therefore, the fastest times are observed with the VCC supply at 2.5 V, and larger values are observed when driving loads that switch at other levels. When duty cycle accuracy is critical, the logic being driven should switch at 50% of VCC and load capacitance should be minimized. When in doubt, it is best to power VCCO or the entire device from the logic supply and rely on the input PSRR and CMRR to reject noise. Overdrive and input slew rate dispersions are not significantly affected by output loading and VCC variations. The TTL-/CMOS-compatible output stage is shown in the simplified schematic diagram (Figure 13). Because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. VLOGIC A1 Q1 +IN -IN OUTPUT AV A2 GAIN STAGE Q2 OUTPUT STAGE 05915-012 POWER/GROUND LAYOUT AND BYPASSING Figure 13. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage USING/DISABLING THE LATCH FEATURE The latch input is designed for maximum versatility. It can safely be left floating for fixed hysteresis or be tied to VCC to remove the hysteresis, or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 7000 , allowing the comparator hysteresis to be easily controlled by either a resistor or an inexpensive CMOS DAC. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V regardless of VCC. Rev. PrA | Page 9 of 16 ADCMP603 Preliminary Technical Data OPTIMIZING PERFORMANCE INPUT VOLTAGE 1V/ns COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP603 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI - 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). VN VOS 10V/ns Figure 15. Propagation Delay--Slew Rate Dispersion COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. Figure 16 shows the transfer function for a comparator with hysteresis. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2, and the new switching threshold becomes -VH/2. The comparator remains in the high state until the new threshold, -VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by VH/2. Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 14 and Figure 15). OUTPUT VOH VOL ADCMP603 dispersion is typically <TBD ps as the overdrive varies from 5 mV to 500 mV and the input slew rate varies from 2 V/ns to 10 V/ns. This specification applies to both positive and negative signals because the device has very closely matched delays for both positive-going and negative-going inputs. 500mV OVERDRIVE 10mV OVERDRIVE 05915-013 VN VOS DISPERSION -VH 2 0 +VH 2 INPUT Figure 16. Comparator Hysteresis Transfer Function The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. INPUT VOLTAGE Q/Q OUTPUT 05915-014 DISPERSION Q/Q OUTPUT 05915-015 As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input and output transmission lines can also limit the specified pulsewidth dispersion performance. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling. Figure 14. Propagation Delay--Overdrive Dispersion The ADCMP603 comparator offers a programmable hysteresis feature that can significantly improve accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND, varies the amount of hysteresis in a predictable, stable manner. Leaving the LE/HYS pin disconnected or driving it high removes the hysteresis. The Rev. PrA | Page 10 of 16 Preliminary Technical Data ADCMP603 maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 17 illustrates the amount of hysteresis applied as a function of the external resistor value, and Figure TBD illustrates hysteresis as a function of the current. The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7k 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it impairs the latch function and often degrades the jitter performance of the device. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function. Figure 17. Hysteresis vs. RHYS Control Resistor CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT In both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and the measured offset voltages and currents change. (Remove if device is stable.) The ADCMP603 slightly elaborates on this scheme. With VCC less than 4 V, this crossover is at the expected VCC/2, but with VCC greater than 4 V, the crossover point instead follows VCC 1:1, bringing it to approximately 3 V with VCC at 5 V. This means that when VCC is greater than 4, the comparator input characteristics more closely resemble those of common types of inputs that are not rail to rail. As with most high speed comparators without hysteresis, a minimum slew rate must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics inherent in the package and PC board. A minimum slew rate of TBD V/s ensures clean output transitions from the ADCMP603 comparator without hysteresis. In many applications, chattering is not harmful. Rev. PrA | Page 11 of 16 ADCMP603 Preliminary Technical Data TYPICAL APPLICATION CIRCUITS 5V 2.5V TO 5V 10k INPUT ADCMP603 2k 2k ADCMP603 VREF CMOS OUTPUT 0.1F 0.02F 10k 0.1F + OUTPUT - LE/HYS 05915-017 INPUT 05915-020 0.1F Figure 21. Duty Cycle to Differential Voltage Converter Figure 18. Self-Biased, 50% Slicer 2.5V ADCMP603 INPUT 1.25V 50mV INPUT 1.25V REF CMOS VDD 2.5V TO 5V ADCMP601 CMOS OUTPUT ADCMP603 10k 82pF LE/HYS 100k 05915-021 100 10k 10k 05915-018 LVDS CMOS PWM OUTPUT Figure 22. Oscillator and Pulse-Width Modulator Figure 19. LVDS-to-CMOS Receiver 2.5V TO 5V 5V 10k ADCMP603 ADCMP603 OUTPUT DIGITAL INPUT CONTROL VOLTAGE 0V TO 2.5V 10k 150k 150k 05915-019 LE/HYS HYSTERESIS CURRENT 74 AHC 1G07 LE/HYS 10k Figure 23. Hysteresis Adjustment with Latch Figure 20. Voltage-Controlled Oscillator Rev. PrA | Page 12 of 16 05915-022 150pF Preliminary Technical Data ADCMP603 TIMING INFORMATION Figure 24 illustrates the ADCMP603 latch timing relationships. Table 5 provides definitions of the terms shown in the figure. 1.1V LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VN VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH tPLOL tR 05915-023 50% Q OUTPUT Figure 24. System Timing Diagram Table 5. Timing Descriptions Symbol tPDH Timing Input to output high delay tPDL Input to output low delay tPLOH Latch enable to output high delay tPLOL Latch enable to output low delay tH Minimum hold time tPL tS Minimum latch enable pulse width Minimum setup time tR Output rise time tF Output fall time VOD Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB. Rev. PrA | Page 13 of 16 ADCMP603 Preliminary Technical Data NOTES Rev. PrA | Page 14 of 16 Preliminary Technical Data ADCMP603 NOTES Rev. PrA | Page 15 of 16 ADCMP603 Preliminary Technical Data NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05915-0-3/06(PrA) T T Rev. PrA | Page 16 of 16