Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparator
Preliminary Technical Data ADCMP603
Rev. PrA
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FEATURES
10 mV sensitivity rail to rail at VCC = 2.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
Low glitch CMOS-/TTL-compatible output stage
Complementary outputs
3 ns propagation delay
15 mW at 3.3 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB
−40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
V
P
NONINVERTING
INPUT
V
N
INVERTING
INPUT
S
DN
INPUT
Q OUTPUT
Q OUTPUT
LE/HYS INPUT
05915-001
ADCMP603
TTL
Figure 1.
PIN 1
INDICATOR
1V
CCO
2V
CCI
3V
EE
9V
EE
8LE/HYS
7S
DN
4
V
P
5
V
EE
6
V
N
12 Q
11 V
EE
10 Q
TOP VIEW
(Not to Scale)
ADCMP603
05915-002
Figure 2. LFCSP Pin Configuration
GENERAL DESCRIPTION
The ADCMP603 is a very fast comparator fabricated on Analog
Devices’ proprietary XFCB2 process. This comparator is
exceptionally versatile and easy to use. Features include an input
range from VEE − 0.5 V to VCC + 0.5 V, low noise complementary
TTL-/CMOS-compatible output drivers, and latch inputs with
adjustable hysteresis and/or a shutdown input.
The device offers 3 ns propagation delay with 5 mV overdrive
on 4 mA typical supply current.
A flexible power supply scheme allows the device to operate
with a single +2.5 V positive supply and a −0.5 V to +3.0 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +6 V input signal range. Split input/output supplies with no
sequencing restrictions support a wide input signal range while
still allowing independent output swing control and power
savings.
The complementary TTL-/CMOS-compatible output stage is
designed to drive up to 5 pF with full timing specs and to
degrade in a graceful and linear fashion as additional
capacitance is added. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded.
High speed latch and programmable hysteresis features are also
provided with a unique single-pin control option.
The ADCMP603 is available in a 12-lead LSCFP package.
ADCMP603 Preliminary Technical Data
Rev. PrA | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Electrical Characteristics ................................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Application Information...................................................................9
Power/Ground Layout and Bypassing........................................9
TTL-/CMOS-Compatible Output Stage ....................................9
Using/Disabling the Latch Feature..............................................9
Optimizing Performance........................................................... 10
Comparator Propagation Delay Dispersion ........................... 10
Comparator Hysteresis .............................................................. 10
Crossover Bias Point .................................................................. 11
Minimum Input Slew Rate Requirement................................ 11
Typical Application Circuits ......................................................... 12
Timing Information ....................................................................... 13
REVISION HISTORY
3/06—Revision PrA: Preliminary Version
Preliminary Technical Data ADCMP603
Rev. PrA | Page 3 of 16
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range VP, VNVCC = 2.5 V to 5.5 V −0.5 VCC + 0.5 V V
Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V V
Differential Voltage VCC = 2.5 V to 5.5 V VCC V
Offset Voltage VOS −5.0 +5.0 mV
Bias Current IP, IN −5.0 ±2 +5.0 µA
Offset Current 2.0 2.0 µA
Capacitance CP, CN TBD pF
Resistance, Differential Mode 0.1 V to VCC 100 kΩ
Resistance, Common Mode −0.5 V to VCC + 0.5 V 100 kΩ
Active Gain AV 85 dB
VCCI = 2.5 V, VCCO = 2.5 V,
VCM = −0.2 V to 2.7 V
50 dB Common-Mode Rejection CMRR
VCCI = 5.5 V, VCCO = 5.5 V,
VCM = −0.2 V to 5.7 V
60 dB
Hysteresis RHYS = ∞ 0.1 mV
LATCH ENABLE PIN CHARACTERISTICS
VIH Hysteresis is shut off 2.0 VCC V
VIL Latch mode guaranteed −0.2 +0.4 +0.8 V
IIH V
IH = VCCV 0.2 mA
IOL V
IL = 0.4 V −0.2 mA
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage Current sink 0 A 1.145 1.25 1.35 V
Minimum Resistor Value Hysteresis = 16 mV 150 kΩ
Latch Setup Time tSVOD = 100 mV 2 ns
Latch Hold Time tHVOD = 100 mV 5 ns
Latch-to-Output Delay tPLOH, tPLOL VOD = 100 mV 3 ns
Latch Minimum Pulse Width tPL VOD = 100 mV 3 ns
SHUTDOWN PIN CHARACTERISTICS
VIH Comparator is operating 2.0 VCCO V
VIL Shutdown guaranteed −0.2 +0.4 +0.6 V
IIH V
IH = VCC 0.3 mA
IOL V
IL = 0 V −0.3 mA
Sleep Time tSD ICC < 300 A 60 ns
Wake-Up Time tHVOD = 10 mV 40 ns
DC OUTPUT CHARACTERISTICS VCCO = 2.5 V to 6 V
Output Voltage High Level VOH IOH = 12 mA VCCO = 2.5 V VCC − 0.4 V
Output Voltage Low Level VOL IOL = 12 mA, VCCO = 2.5 V 0.4 V
ADCMP603 Preliminary Technical Data
Rev. PrA | Page 4 of 16
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE
Propagation Delay tPD VCCO = 2.5 V to 5.5 V,
VOD = 5 mV
3 ns
VCCO = 2.5 V to 5.5 V,
VOD = 200 mV
2.5 ns
Propagation Delay Skew—Rising to
Falling Transition
V
OD = 5 mV 200 ps
Overdrive Dispersion 10 mV < VOD < 2.5 V TBD ps
Slew Rate Dispersion 0.05 V/ns to 2.5 V/ns TBD ps
Pulse-Width Dispersion 3 ns to 20 ns TBD ps
10% to 90% Duty Cycle Dispersion 1 V/ns, VCM = 2.5 V TBD ps
Common-Mode Dispersion 0 < VCM < VCC TBD ps
Toggle Rate >50% output swing TBD Mbps
Deterministic Jitter
TTL/CMOS Outputs
DJ VOD = 200 mV, 5 V/ns,
PRBS31 − 1 NRZ, 0.25 Gbps
TBD ns
RMS Random Jitter RJ VOD = 200 mV, 5 V/ns TBD ps
Minimum Pulse Width PWMIN tPD/PW < 50 ps 3 ns
Rise Time tR10% to 90%, CLOAD = 5 pF,
VCCO = 5 V
2.0 ns
Fall Time tF10% to 90%, CLOAD = 5 pF,
VCCO = 5 V
2.0 ns
Output skew tSKEW 50% CLOAD = 5 pF 300 ps
POWER SUPPLY
Input Supply Voltage Range VCCI 2.5 5.5 V
Output Supply Voltage Range VCCO 2.5 5.5 V
Positive Supply Differential VCCI −
VCCO
Operating −3.0 +3.0 V
Positive Supply Differential VCCI −
VCCO
Nonoperating −5.5 +5.5 V
Input Section Supply Current IVCCI VCCI = 2.5 V to 5 V 0.8 mA
Output Section Supply Current IVCCO VCCI = 5.5 V 2.8 mA
Power Dissipation PDVCC = 2.5 V 9 mW
P
DVCC = 5.5 V 20 mW
Power Supply Rejection PSRR VCCI = 2.5 V to 5 V −50 dB
Preliminary Technical Data ADCMP603
Rev. PrA | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltages
Input Supply Voltage (VCCI to GND) −0.5 V to +6.0 V
Output Supply Voltage
(VCCO to GND)
−0.5 V to +6.0 V
Positive Supply Differential
(VCCI − VCCO)
−6.0 V to +6.0 V
Input Voltages
Input Voltage −0.5 V to VCCI + 0.5 V
Differential Input Voltage ±(VCCI + 0.5 V)
Maximum Input/Output Current ±50 mA
Shutdown Control Pin
Applied Voltage (HYS to GND) −0.5 V to VCCO + 0.5 V
Maximum Input/Output Current ±50 mA
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND) −0.5 V to VCCO + 0.5 V
Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Temperature
Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA1Unit
ADCMP603 LSCFP 12-lead 62 °C/W
1 Measurement in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADCMP603 Preliminary Technical Data
Rev. PrA | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1V
CCO
2V
CCI
3V
EE
9V
EE
8LE/HYS
7S
DN
4
V
P
5
V
EE
6
V
N
12 Q
11 V
EE
10 Q
TOP VIEW
(Not to Scale)
ADCMP603
05915-002
Figure 3. ADCMP603 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCCO Output Section Supply.
2 VCCI Input Section Supply.
3 VEE Negative Supply Voltage.
4 VPNoninverting Analog Input.
5 VEE Negative Supply Voltage.
6 VNInverting Analog Input.
7 SDN Shutdown. Drive this pin low to shut down the device.
8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.
9 VEE Negative Supply Voltage.
10 QInverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See
the LE pin description (Pin 8) for more information.
11 VEE Negative Supply Voltage.
12 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater
than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode.
See the LE pin description (Pin 8) for more information.
Heat Sink
Paddle
VEE The metallic back surface of the package is electrically connected to VEE. It can be left floating because
Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the
application board if improved thermal and/or mechanical stability is desired.
Preliminary Technical Data ADCMP603
Rev. PrA | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
Figure 4. Propagation Delay vs. Input Overdrive
Figure 5. Propagation Delay vs. Input Common Mode
Figure 6. Propagation Delay vs. Temperature
Figure 7. Hysteresis vs. VCC
Figure 8. Hysteresis vs. RHYS Control Resistor
Figure 9. Input Bias Current vs. Input Common Mode
ADCMP603 Preliminary Technical Data
Rev. PrA | Page 8 of 16
Figure 10. Input Bias Current vs. Temperature
Figure 11. Input Offset Voltage vs. Temperature
Figure 12. Latch/Hysteresis Control Pin I/V Characteristics
Preliminary Technical Data ADCMP603
Rev. PrA | Page 9 of 16
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP603 comparator is a very high speed device.
Despite the low noise output stage, it is essential to use proper
high speed design techniques to achieve the specified
performance. Because comparators are uncompensated
amplifiers, feedback in any phase relationship is likely to cause
oscillations or undesired hysteresis. Of critical importance is the
use of low impedance supply planes, particularly the output
supply plane (VCCO) and the ground plane (GND). Individual
supply planes are recommended as part of a multilayer board.
Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO supply
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the VCCO pin. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.
If the input and output supplies have been connected separately
such that VCCI ≠ VCCO, care should be taken to bypass each of
these supplies separately to the GND plane. A bypass capacitor
should never be connected between them. It is recommended
that the GND plane separate the VCCI and VCCO planes when the
circuit board layout is designed to minimize coupling between
the two supplies and to take advantage of the additional bypass
capacitance from each respective supply to the ground plane.
This enhances the performance when split input/output supplies
are used. If the input and output supplies are connected together
for single-supply operation such that VCCI = VCCO, coupling between
the two supplies is unavoidable; however, careful board placement
can help keep output return currents away from the inputs.
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
Specified propagation delay performance can be achieved only
by keeping the capacitive load at or below the specified minimums.
The low skew complementary outputs of the ADCMP603 are
designed to directly drive one Schottky TTL or three low power
Schottky TTL loads or equivalent. For large fan outputs, buses,
or transmission lines, an appropriate buffer should be used to
maintain the comparator’s excellent speed and stability.
With the rated 5 pF load capacitance applied, more than half of
the total device propagation delay is output stage slew time,
even at 2.5 V VCC. Because of this, the total prop delay decreases
as VCCO decreases, and instability in the power supply may
appear as excess delay dispersion.
This delay is measured to the 50% point for the supply in use;
therefore, the fastest times are observed with the VCC supply at
2.5 V, and larger values are observed when driving loads that
switch at other levels.
When duty cycle accuracy is critical, the logic being driven
should switch at 50% of VCC and load capacitance should be
minimized. When in doubt, it is best to power VCCO or the
entire device from the logic supply and rely on the input PSRR
and CMRR to reject noise.
Overdrive and input slew rate dispersions are not significantly
affected by output loading and VCC variations.
The TTL-/CMOS-compatible output stage is shown in the
simplified schematic diagram (Figure 13). Because of its
inherent symmetry and generally good behavior, this output
stage is readily adaptable for driving various filters and other
unusual loads.
OUTPUT
Q2
Q1
+
IN
–
IN
OUTPUT STAGE
V
LOGIC
GAIN STAGE
A2
A1
A
V
0
5915-012
Figure 13. Simplified Schematic Diagram of
TTL-/CMOS-Compatible Output Stage
USING/DISABLING THE LATCH FEATURE
The latch input is designed for maximum versatility. It can
safely be left floating for fixed hysteresis or be tied to VCC to
remove the hysteresis, or it can be driven low by any standard
TTL/CMOS device as a high speed latch.
In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 Ω, allowing the comparator hysteresis to be
easily controlled by either a resistor or an inexpensive CMOS DAC.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
parallel to the hysteresis control resistor or current source.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of VCC.
ADCMP603 Preliminary Technical Data
Rev. PrA | Page 10 of 16
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse-
width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals; higher impedances encourage undesired
coupling.
COMPARATOR PROPAGATION
DELAY DISPERSION
The ADCMP603 comparator is designed to reduce propagation
delay dispersion over a wide input overdrive range of 5 mV to
VCCI – 1 V. Propagation delay dispersion is the variation in
propagation delay that results from a change in the degree of
overdrive or slew rate (that is, how far or how fast the input
signal exceeds the switching threshold).
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (Figure 14
and Figure 15).
ADCMP603 dispersion is typically <TBD ps as the overdrive
varies from 5 mV to 500 mV and the input slew rate varies from
2 V/ns to 10 V/ns. This specification applies to both positive
and negative signals because the device has very closely matched
delays for both positive-going and negative-going inputs.
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIVE
10mV OVERDRIVE
DISPERSION
V
N
± V
OS
05915-013
Figure 14. Propagation Delay—Overdrive Dispersion
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
± V
OS
05915-014
Figure 15. Propagation Delay—Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. Figure 16 shows the transfer
function for a comparator with hysteresis. As the input voltage
approaches the threshold (0.0 V, in this example) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +VH/2, and the
new switching threshold becomes −VH/2. The comparator remains
in the high state until the new threshold, −VH/2, is crossed from
below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0.0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by ±VH/2.
OUTPUT
INPUT
0
VOL
VOH
+VH
2
–VH
2
05915-015
Figure 16. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.
The ADCMP603 comparator offers a programmable hysteresis
feature that can significantly improve accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND, varies the amount of hysteresis
in a predictable, stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes the hysteresis. The
Preliminary Technical Data ADCMP603
Rev. PrA | Page 11 of 16
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 17 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure TBD illustrates hysteresis as a function of the current.
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7k ± 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the Using/Disabling the Latch Feature section,
hysteresis control need not compromise the latch function.
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCC rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, normally VCC/2, the direction of the bias current reverses
and the measured offset voltages and currents change.
The ADCMP603 slightly elaborates on this scheme. With VCC
less than 4 V, this crossover is at the expected VCC/2, but with
VCC greater than 4 V, the crossover point instead follows VCC 1:1,
bringing it to approximately 3 V with VCC at 5 V. This means that
when VCC is greater than 4, the comparator input characteristics
more closely resemble those of common types of inputs that are
not rail to rail.
Figure 17. Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENT
(Remove if device is stable.)
As with most high speed comparators without hysteresis, a
minimum slew rate must be met to ensure that the device does
not oscillate as the input signal crosses the threshold. This
oscillation is due to the high gain bandwidth of the comparator
in combination with feedback parasitics inherent in the package
and PC board. A minimum slew rate of TBD V/μs ensures clean
output transitions from the ADCMP603 comparator without
hysteresis. In many applications, chattering is not harmful.
ADCMP603 Preliminary Technical Data
Rev. PrA | Page 12 of 16
TYPICAL APPLICATION CIRCUITS
ADCMP603
CMOS
OUTPUT
0.1µF
2.5V TO 5
V
0.1µF
2kΩ
2kΩ
INPUT
05915-017
Figure 18. Self-Biased, 50% Slicer
ADCMP603
CMOS
V
DD
2.5V TO 5V
100ΩLVDS
05915-018
CMOS
OUTPUT
Figure 19. LVDS-to-CMOS Receiver
LE/HYS
ADCMP603
5
V
150pF
10kΩ
150kΩ
10kΩ
150kΩ
CONTROL
VOLTAGE
0V TO 2.5V
05915-019
OUTPUT
Figure 20. Voltage-Controlled Oscillator
ADCMP603
OUTPUT
+
–
5
V
0.1µF
10kΩ
10kΩ
INPUT
V
REF
05915-020
0.02µF
LE/HYS
Figure 21. Duty Cycle to Differential Voltage Converter
CMOS
PWM
OUTPUT
ADCMP603
2.5
V
INPUT
1.25V
REF
INPUT
1.25V
±
50m
V
LE/HYS
ADCMP601
82pF
10kΩ
10kΩ
100kΩ
10kΩ
05915-021
Figure 22. Oscillator and Pulse-Width Modulator
ADCMP603
2.5V TO 5
V
10kΩ
LE/HYS
DIGITAL
INPUT
HYSTERESIS
CURRENT
74 AHC
1G07
0
5915-022
Figure 23. Hysteresis Adjustment with Latch
Preliminary Technical Data ADCMP603
Rev. PrA | Page 13 of 16
TIMING INFORMATION
Figure 24 illustrates the ADCMP603 latch timing relationships. Table 5 provides definitions of the terms shown in the figure.
1.1V
50%
VN ± VOS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
t
H
t
PDL
t
PLOH
t
F
VIN
VOD
t
S
t
PL
05915-023
50%
Q OUTPUT
t
PDH
t
PLOL
t
R
Figure 24. System Timing Diagram
Table 5. Timing Descriptions
Symbol Timing Description
tPDH Input to output high delay Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL Input to output low delay Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH Latch enable to output high delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL Latch enable to output low delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tHMinimum hold time Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
tPL Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change.
tSMinimum setup time Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
tROutput rise time Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
tFOutput fall time Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
VOD Voltage overdrive Difference between the input voltages VA and VB.
ADCMP603 Preliminary Technical Data
Rev. PrA | Page 14 of 16
NOTES
Preliminary Technical Data ADCMP603
Rev. PrA | Page 15 of 16
NOTES
ADCMP603 Preliminary Technical Data
Rev. PrA | Page 16 of 16
T
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05915-0-3/06(PrA)
TTT
