M41ST85W-70MH6TR - STMicroelectronics

1/32

PRELIMINARY DATA

January 2001

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M41ST85Y

M41ST85W

512 Kbit (64 bit x 8) Serial Access RTC

and NVRAM SUPERVISOR

FEATURES SUMMARY

■3V or 5V OPERATING VOLTAGE

■SERIAL INTERFACE SUPPORTS I2C BUS

(400 KHz)

■NVRAM SUPERVISOR for EXTERNAL

LPSRAM

■OPTIMIZED for MINIMAL INTERCONNECT to

MCU

■2.5 to 5.5V CLOCK OPERATING VOLTAGE

■AUTOMATIC SWITCH-OVER and DESELECT

CIRCUITRY

■CHOICE of POWER-FAIL DESELECT

VOLTAGES

– M41ST85Y: VCC =4.5 to 5.5V;

VPFD = 4.40 ±0.10V

– M41ST85W: VCC = 2.7 to 3.6V;

VPFD = 2.65 ±0.05V

■1.25V REFERENCE (for PFI/PFO)

■COUNTERS FOR TENTHS/HUNDREDTHS of

SECONDS, SECONDS, MINUTES, HOURS,

DAY, DATE, MONTH, YEAR, and CENTURY

■44 BYTES of GENERAL PURPOSE RAM

■PROGRAMMABLE ALARM AND INTERRUPT

FUNCTION (VALID EVEN DURINGBATTERY

BACK-UP MODE)

■WATCHDOG TIMER

■MICROPROCESSOR POWER-ON RESET

■BATTERY LOW FLAG

■ULTRA-LOW BATTERY SUPPLY CURRENT

of 500nA (MAX)

■PACKAGING INCLUDES a28-LEADSOIC and

SNAPHAT TOP (to be Ordered Separately)

■SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP WHICH

CONTAINS the BATTERY and CRYSTAL

Figure 1. Packages

SOH28 (MH)

SNAPHAT (SH)

Battery & Crystal

M41ST85Y, M41ST85W

2/32

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . ...................................................4

Logic Diagram (Figure 2.) . . . . . . ...................................................5

Signal Names (Table 1.) . . ........................................................5

SOIC Connections (Figure 3.). . . . . . . . . . . . . . . . . . ....................................5

Block Diagram (Figure 4.) . . .. . . . . . . . . . ............................................6

Hardware Hookup (Figure 5.) . . . . . . . . . . ............................................7

OPERATING MODES . . . . . . . . . . . . . . . . . . . ............................................8

2-Wire Bus Characteristics . . . . . ...................................................8

Serial Bus Data Transfer Sequence (Figure 6.) . . . .....................................9

Write Cycle Timing: RTC & External SRAM Control Signals (Figure 8.). . . . . . ................9

Bus Timing Requirements Sequence (Figure 9.) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 10

AC Characteristics (Table 2.) . . . ..................................................10

Read Mode . . . ................................................................11

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . ...........................................11

Battery Low Warning. . ..........................................................11

Slave Address Location (Figure 10.) . . . . . . . . . . . . . . . .................................12

Read Mode Sequences (Figure 11.) . . . . . . . . . . . . . . . . . . ..............................12

Alternate Read Mode Sequences (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....12

Write Mode Sequence (Figure 13.) . . . . . . . . . . . . .....................................13

CLOCK OPERATION . . . . . . . . . . . . . . . . ..............................................14

Data Retention Mode. . . . . .......................................................14

TIMEKEEPERRegisters. . . . . . . . . . . . . ...........................................15

TIMEKEEPER Register Map (Table 3.). . . . . . . .......................................15

Setting Alarm Clock Registers.....................................................16

Back-Up Mode Alarm Waveform (Figure 14.) . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Alarm Interrupt Reset Waveforms (Figure 15.) . .......................................17

Alarm Repeat Modes(Table 4.) . . . .. . . . . . .. . . . . . . . . . ..............................17

Watchdog Timer . ..............................................................17

Square Wave Output. . . . . . . . . . . . . . . . . . . .. . . . . . ..................................18

Square Wave Output Frequency (Table 5.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-on Reset. . . . . . . . . . . . . . . . . . . . . ...........................................19

Reset Inputs (RSTIN1 & RSTIN2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

RSTIN1 & RSTIN2 Timing Waveforms (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . ...........19

Reset AC Characteristics (Table 6.) . . ..............................................19

Power-fail INPUT/OUTPUT.......................................................20

Calibrating the Clock . . . . . . ......................................................20

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...........21

Initial Power-on Defaults . . . ......................................................21

Century Bit. . . . . . . . . . . . . . ......................................................21

Crystal Accuracy Across Temperature(Figure 17.) ....................................21

Calibration Waveform (Figure 18.) . . . ..............................................21

3/32

M41ST85Y, M41ST85W

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . ...........................................22

Absolute Maximum Ratings (Table 7.) ..............................................22

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . ..............................23

DC and AC Measurement Conditions (Table 8.). . . . . . . . . . . . . . . . . . . . . . . . . ..............23

AC Testing Load Circuit (Figure 19.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

AC Testing Input/Output Waveforms (Figure 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . ...........23

Capacitance (Table 9.) . . . . . . . . . . .. . . . . . . . . . . . . . .................................23

DC Characteristics(Table 10.) . . ..................................................24

Operating Modes (Table 11.). . . ...................................................25

Crystal Electrical Characteristics (Table 12.). . . . . . . . . . . . ..............................25

Power Down/Up Mode AC Waveforms(Figure 21.) . . . . . . . . . . . . . . .. . . . . . .. . . ...........26

Power Down/Up AC Characteristics(Table 13.) . . . . . . . . . . .. . . . . . . . . . . . . . . . . ...........26

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PART NUMBERING . . . . . . . . . ......................................................30

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................31

M41ST85Y, M41ST85W

4/32

SUMMARY DESCRIPTION

The M41ST85Y/W Serial TIMEKEEPER/Control-

ler SRAM is a low power 512 bit static CMOS

SRAM organized as 64 words by 8 bits. A built-in

32.768 kHz oscillator (external crystal controlled)

and 8 bytes of the SRAM (see Table 6, page 19)

are used for the clock/calendar function and are

configured in binary coded decimal (BCD) format.

An additional 12 bytes of RAM provide status/con-

trol of Alarm, Watchdog and Square Wave func-

tions. Addresses and data are transferred serially

via a two line, bi-directional I2C interface. The

built-in address register is incremented automati-

cally after each write or read data byte. The

M41ST85Y/W has a built-in power sense circuit

which detects power failures and automatically

switches to the battery supply when a power fail-

ure occurs. The energy needed to sustain the

SRAM and clock operations can be supplied by a

small lithium button-cell supply when a power fail-

ure occurs.

Functions available to the user include a non-vol-

atile, time-of-day clock/calendar, Alarm interrupts,

Watchdog Timer and programmable Square

Wave output. Other features include a Power-On

Reset as well as two additional debounced inputs

(RSTIN1 and RSTIN2) which can also generatean

output Reset (RST). The eight clock addressloca-

tions contain the century, year, month, date, day,

hour, minute, second and tenths/hundredths of a

second in 24hour BCD format. Corrections for 28,

29 (leap year - valid until year 2100), 30 and 31

day months are made automatically. The ninth

clock address location controls user access to the

clock information and also stores the clock soft-

ware calibration setting.

The M41ST85Y/W is supplied in a 28 lead SOIC

SNAPHAT package (which integrates both crystal

and battery ina singleSNAPHAT top). The 28 pin

330mil SOIC provides sockets with gold plated

contacts at both ends for direct connection to a

separate SNAPHAT housing containing the bat-

tery and crystal. The unique design allows the

SNAPHAT battery/crystal package to be mounted

on top ofthe SOIC packageafter the completion of

the surface mount process.

Insertion of the SNAPHAT housing after reflow

prevents potential battery andcrystal damage due

to the high temperatures required for device sur-

face-mounting. The SNAPHAT housing is also

keyed to prevent reverse insertion.

The SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubesor in

Tape & Reel form. For the 28 lead SOIC, the bat-

tery/crystal package (i.e. SNAPHAT) part number

is “M4TXX-BR12SH” (see Table 18, page 30).

Caution: Donotplace the SNAPHAT battery/crys-

tal topin conductive foam, asthis will drain the lith-

ium button-cell battery.

5/32

M41ST85Y, M41ST85W

Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. SOIC Connections

AI03658

SCL

VCC

M41ST85Y

M41ST85W

VSS

SDA

RSTIN1 IRQ/FT/OUT

SQW

WDI

RSTIN2

PFI

ECON

RST

PFO

VOUT

ECON Conditioned Chip Enable Output

EX External Chip Enable

IRQ/FT/OUT Interrupt/Frequency Test/Out

Output (Open Drain)

PFI Power Fail Input

PFO Power Fail Output

RST Reset Output (Open Drain)

RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

SCL Serial Clock Input

SDA Serial Data Input/Output

SQW Square Wave Output

WDI Watchdog Input

VCC Supply Voltage

VOUT Voltage Output

VSS Ground

AI03659

RSTIN1

RSTIN2

WDI

IRQ/FT/OUT

VOUT

PFI

SCL

NCNC

PFO ECON

VSS SDA

RST

SQW VCC

M41ST85Y

M41ST85W

M41ST85Y, M41ST85W

6/32

Figure 4. Block Diagram

AI03932

COMPARE

VPFD

4.4V

VCC

COMPARE

VSO

2.5V

VOUT

VBL

2.5V

COMPARE

Crystal

INTERFACE

REAL TIME

CLOCK

CALENDAR

44 BYTES

USER RAM

RTC w/ALARM

& CALIBRATION

WATCHDOG

SQUARE WAVE

SDA

SCL

1.25V

PFI PFO

RSTIN1

POR

SQW

RST

WDI

WDF

IRQ/FT/OUT(1)

(1)

VBAT

32KHz

OSCILLATOR

COMPARE

Note:1.Open drain output

RSTIN2

EX ECON

(2.65V for ST85W)

7/32

M41ST85Y, M41ST85W

Figure 5. Hardware Hookup

AI03660

VCC

PFO

SCL

WDI

RSTIN1

RSTIN2

PFI

VSS

IRQ/FT/OUT

SQW

RST

VOUT

ECON

SDA

Unregulated

Voltage

Regulator

VCC

VIN

Pushbutton

Reset

From MCU

M68Z128Y/W

M68Z512Y/W

VCC

RST

To LED Display

To NMI

To INT

M41ST85Y, M41ST85W

8/32

OPERATING MODES

The M41ST85Y/W clock operates as a slave de-

vice on the serial bus. Access is obtained by im-

plementing a start condition followed by the

correct slave address (D0h). The 64 bytes con-

tained inthe device can then beaccessed sequen-

tially in the following order:

1. Tenths/Hundredths of a Second Register

2. Seconds Register

3. Minutes Register

4. Century/Hours Register

5. Day Register

6. Date Register

7. MonthRegister

8. Year Register

9. Control Register

10. Watchdog Register

11 - 16. Alarm Registers

17 - 19. Reserved

20. Square Wave Register

21 - 64. User RAM

The M41ST85Y/W clock continually monitors VCC

for an out-of tolerance condition. Should VCC fall

below VPFD, the device terminates an access in

progress and resets the device address counter.

Inputs to the device will not be recognized at this

time to prevent erroneous data from being written

to the device from a an out-of-tolerance system.

When VCC falls below VSO, the device automati-

cally switches over to the battery and powers

down intoan ultra low currentmode ofoperationto

conserve battery life.Assystem power returns and

VCC rises above VSO, the battery is disconnected,

and the power supply is switched to external VCC.

Write protection continues until VCC reachesVPFD

plus tREC.

For more information on Battery Storage Life refer

to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. Itconsists of two lines: a bi-direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines must be connected to

a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the bus

is not busy.

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while the clock line is

High, will be interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer. A change in the state of the

data line, from High toLow, while the clock isHigh,

defines the START condition.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock isHigh,

defines the STOP condition.

Data Valid. The state of the data line represents

valid data when after a start condition, thedata line

is stable for the duration of the high period of the

clock signal.The data on theline may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiatedwith a start condition

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each receiver acknowl-

edges with a ninth bit.

By definition a device that gives out a message is

called “transmitter”, the receiving device that gets

the message is called “receiver”. The device that

controls the message is called “master”. The de-

vices that are controlled by the master are called

“slaves”.

Acknowledge. Each byte of eight bits is followed

by one acknowledge bit. This acknowledge bit is a

low level put on the bus by the receiver whereas

the master generates an extra acknowledge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA lineis a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times must

be taken into account. A master receivermust sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. In this case the

transmitter must leave the data line High to enable

the master to generate the STOP condition.

9/32

M41ST85Y, M41ST85W

Figure 6. Serial Bus Data Transfer Sequence

Figure 7. Acknowledgement Sequence

Figure 8. Write Cycle Timing: RTC & External SRAM Control Signals

AI00587

DATA

CLOCK

DATA

LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL

FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

AI03663

ECON

tEXPD

M41ST85Y, M41ST85W

10/32

Figure 9. Bus Timing Requirements Sequence

Table 2. AC Characteristics

Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.

Symbol Parameter Min Max Unit

fSCL SCL Clock Frequency 0 400 kHz

tBUF Time the bus must be free before a new transmission can start 1.3 µs

tEXPD EX to ECON Propagation Delay M41ST85Y 10 ns

M41ST85W 15

tFSDA and SCL Fall Time 300 ns

tHD:DAT Data Hold Time 0 µs

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 600 ns

tHIGH Clock High Period 600 ns

tLOW Clock Low Period 1.3 µs

tRSDA and SCL Rise Time 300 ns

tSU:DAT(1) Data Setup Time 100 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:STO STOP Condition Setup Time 600 ns

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

11/32

M41ST85Y, M41ST85W

Read Mode

In this mode the master reads the M41ST85Y/W

slave after setting the slave address (see Figure

10, page 12). Following the write mode control bit

(R/W=0) and the acknowledge bit, the word ad-

dress ‘An’ iswritten to the on-chip address pointer.

Next the START condition and slave address are

repeated followed by the READ mode control bit

(R/W=1). At this point the master transmitter be-

comes the master receiver.

The data byte which was addressed will be trans-

mitted and the master receiver will send an ac-

knowledge bit to the slave transmitter. The

address pointer is only incremented on reception

of an acknowledge bit. The M41ST85Y/W slave

transmitter will now place the data byte at address

An+1 on the bus, the master receiver reads and

acknowledges the new byte and the address

pointer is incremented to An+2.

This cycle of reading consecutive addresses will

continue until the master receiver sends a STOP

condition to the slave transmitter (see Figure 11,

page 12).

The system-to-user transfer of clock data will be

halted whenever the addressbeing readis a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to a RAM address.

An alternateREAD mode may also be implement-

ed whereby the master reads the M41ST85Y/W

slave without first writing to the (volatile) address

pointer. The first address that is read is the last

one storedin the pointer(see Figure12, page 12).

Write Mode

In this mode the master transmitter transmits to

the M41ST85Y/W slave receiver. Bus protocol is

shown in Figure 13, page 13. Following the

START condition and slave address, a logic ‘0’ (R/

W=0) is placed on the bus and indicates tothe ad-

dressed device that word address An will follow

and is tobe written to the on-chip addresspointer.

The data word to be written to the memory is

strobed in next and the internal address pointer is

incremented to the next memory location within

the RAM on the reception of an acknowledge

clock. The M41ST85Y/W slave receiver will send

an acknowledge clock to the master transmitter af-

ter it has received the slave address (see Figure

10, page 12) and again after it has received the

word address and each data byte.

Battery Low Warning

The M41ST85Y/W automatically performs battery

voltage monitoring upon power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) bit, Bit D4 of Flags

is found to be less than approximately 2.5V. The

BL bit will remain asserted until completion of bat-

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interval.

If a battery low is generated during a power-up

sequence, this indicates that the battery is below

approximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct. A

fresh battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is near end of life. However, data is not com-

promised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent periods of battery back-up mode, the

battery should be replaced. The SNAPHAT top

may be replaced while VCC is applied to the

device.

Note: This will cause the clock to lose time during

the interval the SNAPHAT battery/crystal top is

disconnected.

The M41ST85Y/W only monitors the battery when

a nominalVCC isapplied to the device. Thus appli-

cations which require extensive durations in the

battery back-up mode should be powered-up peri-

odically (at least once every few months) in order

for this technique to be beneficial. Additionally, if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

M41ST85Y, M41ST85W

12/32

Figure 10. Slave Address Location

Figure 11. Read Mode Sequences

Figure 12. Alternate Read Mode Sequences

AI00602

R/W

SLAVE ADDRESSSTART A

0100011

MSB

LSB

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (n)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

13/32

M41ST85Y, M41ST85W

Figure 13. Write Mode Sequence

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (n)

SLAVE

ADDRESS

M41ST85Y, M41ST85W

14/32

CLOCK OPERATION

The eight byte clock register (see Table 3, page

15) is used to both set the clock and to read the

date and time from the clock, in a binary coded

decimal format. Tenths/Hundredths of Seconds,

Seconds, Minutes, and Hours arecontained within

the firstfour registers. Bits D6 and D7 of clock reg-

ister 3 (Century/Hours Register) contain the CEN-

TURY ENABLE Bit (CEB) and the CENTURY Bit

(CB). Setting CEB to a ‘1’ will cause CB to toggle,

either from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn of

the century (depending upon its initial state). If

CEB is set to a ‘0’, CB will not toggle. Bits D0

through D2 of register 4 contain the Day (day of

week). Registers 5, 6 and 7 contain the Date (day

of month), Month and Years. The ninth clock reg-

ister is the ControlRegister (this is described in the

Clock Calibration section). BitD7 ofregister 1 con-

tains the STOP Bit (ST). Setting this bit to a ‘1’ will

cause the oscillator to stop. If the device is

expected to spend a significant amount of time on

the shelf, the oscillator may be stopped to reduce

current drain. When reset to a ‘0’ the oscillator

restarts within one second.

The eight Clock Registers may be read onebyte at

a time, or in a sequential block. The Control Reg-

ister (Address location 08h) may be accessed

independently. Provision has been made to

assure that a clock update does not occur while

any of the seven clock addresses are being read.

If a clock address is being read, an update of the

clock registers will be halted. This will prevent a

transition of data during the read.

Note: Upon power-up following a power failure,

the HT bit will automatically be set to a ‘1’. This will

prevent theclock from updating theTIMEKEEPER

registers, and will allow the user to read the exact

time of the power-downevent. Resetting the HTbit

to a ‘0’ will allow the clock to update the TIME-

KEEPER registers with the current time.

Data Retention Mode

With valid VCC applied, the M41ST85Y/W can be

accessed as described above with read or write

cycles. Should the supply voltage decay, the

M41ST85Y/W will automatically deselect, write

protecting itself (and any external SRAM) when

VCC falls between VPFD (max) and VPFD (min).

This is accomplished by internally inhibiting

access to the clock registers. At this time, the

Reset pin (RST) is driven active and will remain

active until VCC returnsto nominal levels. External

RAM access is inhibited in a similar manner by

forcing ECON to a high level. This level is within 0.2

volts of the VBAT.E

CON will remain at this level as

long as VCC remains at an out-of tolerance condi-

tion. When VCC falls below the Battery Back-up

Switchover Voltage (VSO), power input isswitched

from the VCC pin to the SNAPHAT battery and the

clock registers and external SRAM are maintained

from the attached battery supply.

All outputs become high impedance. The VOUT pin

is capable of supplying 100 µA of current to the

attached memory with less than 0.3 volts drop

under this condition. On power up, when VCC

returns to a nominalvalue, write protection contin-

ues for tREC by inhibiting ECON. The RST signal

also remains active during this time (see Figure

21, page 26).

Note: Most low power SRAMs on the market

today can be used with the M41ST85Y/W RTC

SUPERVISOR. There are, however some criteria

which should be used in making the final choice of

an SRAM to use. The SRAM must be designed in

a way where the chip enable input disables all

other inputs to the SRAM. This allows inputs to the

M41ST85Y/W and SRAMs to be Don’t Care once

VCC fallsbelow VPFD(min). The SRAM should also

guarantee data retention down to VCC=2.0 volts.

The chip enable access time must be sufficient to

meet the system needs with the chip enable output

propagation delays included.If theSRAM includes

a second chip enable pin (E2), this pin should be

tied to VOUT.

If data retention lifetime is a critical parameter for

the system, itis important to review the data reten-

tion current specifications for the particular

SRAMs being evaluated. Most SRAMs specify a

data retention current at 3.0 volts. Manufacturers

generally specify a typical condition for room tem-

perature along with a worst case condition (gener-

ally at elevated temperatures). The system level

requirements will determine the choice of which

value to use. The data retention current value of

the SRAMs can then be added to the IBAT value of

the M41ST85Y/W to determine the total current

requirements fordata retention. The available bat-

tery capacity for the SNAPHAT of your choice can

then be divided by this current to determine the

amount of data retention available (see Table 18,

page 30).

For afurther more detailed review oflifetime calcu-

lations, please see Application Note AN1012.

15/32

M41ST85Y, M41ST85W

TIMEKEEPERRegisters

The M41ST85Y/W offers 20 internal registers

which contain Clock, Alarm, Watchdog, Flag,

Square Wave and Control data. These registers

are memory locations whichcontain external (user

accessible) and internal copies of the data (usually

referred to as BiPORTTM TIMEKEEPER cells).

The external copies are independent of internal

functions except that they are updated periodically

by the simultaneous transfer of the incremented

internal copy. TIMEKEEPER and Alarm Registers

store data in BCD. Control, Watchdog and Square

Wave Registers store data in Binary Format.

Table 3. TIMEKEEPER Register Map

Keys: S = Sign Bit

FT = Frequency Test Bit

ST = Stop Bit

0 = Must be set to zero

BL = Battery Low Flag

BMB0-BMB4 = Watchdog Multiplier Bits

CEB = Century Enable Bit

CB = Century Bit

OUT = Output level

AFE = Alarm Flag Enable Flag

RB0-RB1 = Watchdog Resolution Bits

WDS = Watchdog Steering Bit

ABE = Alarm in Battery Back-Up Mode Enable Bit

RPT1-RPT5 = Alarm Repeat Mode Bits

WDF = Watchdog flag

AF = Alarm flag

SQWE = Square Wave Enable

RS0-RS3 = SQW Frequency

HT = Halt Update Bit

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

00h 0.1 Seconds 0.01 Seconds Seconds 00-99

01h ST 10 Seconds Seconds Seconds 00-59

02h 0 10 Minutes Minutes Minutes 00-59

03h CEB CB 10 Hours Hours (24 Hour Format) Century/Hour 0-1/00-23

04h 0 0 0 0 0 Day of Week Day 01-7

05h 0 0 10 Date Date: Day of Month Date 01-31

06h 0 0 0 10M Month Month 01-12

07h 10 Years Year Year 00-99

08h OUT FT S Calibration Control

09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

0Ah AFE SQWE ABE Al 10M Alarm Month Al Month 01-12

0Bh RPT4 RPT5 AI 10 Date Alarm Date Al Date 01-31

0Ch RPT3 HT AI 10 Hour Alarm Hour Al Hour 00-23

0Dh RPT2 Alarm 10 Minutes Alarm Minutes Al Min 00-59

0Eh RPT1 Alarm 10 Seconds Alarm Seconds Al Sec 00-59

0Fh WDF AF 0 BL 0 0 0 0 Flags

10h 0 0 0 0 0 0 0 0 Reserved

11h 0 0 0 0 0 0 0 0 Reserved

12h 0 0 0 0 0 0 0 0 Reserved

13h RS3 RS2 RS1 RS0 0 0 0 0 SQW

M41ST85Y, M41ST85W

16/32

Setting Alarm Clock Registers

Address locations 0Ah-0Eh contain the alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed togo off while the M41ST85Y/W is in the

battery back-up to serve asa system wake-upcall.

Bits RPT5–RPT1 put the alarm in the repeat mode

of operation. Table 4, page 17 shows the possible

configurations. Codesnot listed in the tabledefault

to the once per second mode to quickly alert the

user of an incorrect alarm setting.

When the clock information matches the alarm

clock settings based on the match criteria defined

by RPT5–RPT1, the AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion activates the IRQ/FT/OUT pin. To disable

alarm, write ‘0’ to the Alarm Date Register and to

RPT5–RPT1. The IRQ/FT/OUT output is cleared

by a read to the Flags register. This read of the

Flags register will also reset the Alarm Flag (D6;

The IRQ/FT/OUT pin can also be activated in the

battery back-up mode. The IRQ/FT/OUT will go

low if an alarm occurs and both ABE (Alarmin Bat-

tery Back-up Mode Enable) and AFE are set. The

ABE and AFE bits are reset during power-up,

therefore an alarm generated during power-up will

only set AF. The user can read the Flag Register

at system boot-up to determine if an alarm was

generated while the M41ST85Y/W was in the de-

select mode during power-up. Figure 14, page 16

illustrates the back-up mode alarm timing.

Figure 14. Back-Up Mode Alarm Waveform

AI03920

VCC

IRQ/FT/OUT

VPFD

AFE bit in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

HIGH-Z

tREC

17/32

M41ST85Y, M41ST85W

Figure 15. Alarm Interrupt Reset Waveforms

Table 4. Alarm Repeat Modes

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The user programs the

watchdog timer by setting the desired amount of

time-out intothe Watchdog Register,address 09h.

Bits BMB4-BMB0 store a binary multiplier and the

two lower order bits RB1-RB0 select the resolu-

tion, where 00=1/16 second, 01=1/4 second, 10=1

second, and 11=4 seconds. The amount of time-

out is then determined to be the multiplication of

the five bit multiplier value with the resolution. (For

example: writing 00001110 in the Watchdog Reg-

ister = 3*1 or 3 seconds). If the processor does not

reset the timer within the specified period, the

M41ST85Y/W sets the WDF (Watchdog Flag) and

generates a watchdog interrupt or a microproces-

sor reset.

Note: If the Square Wave function is enabled, the

accuracy of the Watchdog Timer will be a function

of the selected resolution.

The most significant bit of the Watchdog Register

is the Watchdog Steering Bit (WDS). When set to

a ‘0’, the watchdog will activate the IRQ/FT/OUT

pin when timed-out. When WDS is set to a ‘1’, the

watchdog will output a negative pulse on the RST

pin for tREC. The Watchdogregister, FT, AFE,ABE

and SQWE Bits will reset to a ‘0’ at the end of a

Watchdog time-out when the WDS bit is set to a

‘1’.

The watchdog timer can be reset by two methods:

1) a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI) or 2) the

microprocessor can perform a write of the Watch-

dog Register.The time-out period then starts over.

Note: The WDI pin should be tied to VSS if not

used.

In order to perform a software reset of the watch-

dog timer, the original time-out period can be writ-

ten into the Watchdog Register, effectively

restarting the count-down cycle.

Should the watchdog timer time-out,and the WDS

bit is programmed to output an interrupt, a value of

00h needs to be written to the Watchdog Register

in order to clearthe IRQ/FT/OUT pin. This willalso

disable the watchdog function until it is again pro-

grammed correctly. A read of the Flags Register

will reset the Watchdog Flag (Bit D7; Register

0Fh).

The watchdog function is automatically disabled

upon power-up and the Watchdog Register is

cleared. If the watchdog function is set to output to

the IRQ/FT/OUT pin and the frequency test func-

tion is activated, the watchdog function prevails

and the frequency test function is denied. The

OUT function has the lowest priority and will only

be enabled when the Watchdog Register (09h),

AFE Bit and FT Bit are ‘0.’

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

11111OnceperSecond

11110OnceperMinute

11100OnceperHour

11000Once per Day

10000Once per Month

00000OnceperYear

AI03664

IRQ/FT/OUT

ACTIVE FLAG

0Fh0Eh 10h

HIGH-Z

M41ST85Y, M41ST85W

18/32

Square Wave Output

The M41ST85Y/W offers the user a programma-

ble square wave function which is output on the

SQW pin. RS3-RS0 bits located in 13h establish

the square wave output frequency. These fre-

quencies are listed in Table 5. Once the selection

of the SQW frequency has been completed, the

SQW pin can be turned on and off under software

control with the Square Wave Enable Bit (SQWE)

located in Register 0Ah.

Table 5. Square Wave Output Frequency

Square Wave Bits Square Wave

RS3 RS2 RS1 RS0 Frequency Units

0 0 0 0 None –

0 0 0 1 32.768 kHz

0 0 1 0 8.192 kHz

0 0 1 1 4.096 kHz

0 1 0 0 2.048 kHz

0 1 0 1 1.024 kHz

0 1 1 0 512 Hz

0 1 1 1 256 Hz

1 0 0 0 128 Hz

1 0 0 1 64 Hz

1 0 1 0 32 Hz

1 0 1 1 16 Hz

11008Hz

11014Hz

11102Hz

11111Hz

19/32

M41ST85Y, M41ST85W

Power-on Reset

The M41ST85Y/W continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RST pulls low (open drain) and remains lowon

power-up for tREC after VCC passes VPFD. The

RST pin is an open drain output and an appropri-

ate pull-up resistor should be chosen to control

rise time.

Reset Inputs (RSTIN1 & RSTIN2)

The M41ST85Y/W provides two independent in-

puts which can generate an output reset. The du-

ration and function of these resets is identical to a

reset generated bya power cycle.Table 6 and Fig-

ure 16 illustrate the AC reset characteristics ofthis

function. Pulses shorter than tR1 and tR2 will not

generate a reset condition. RSTIN1 and RSTIN2

are each internally pulled up to VCC through a

100kΩresistor.

Figure 16. RSTIN1 & RSTIN2 Timing Waveforms

Table 6. Reset AC Characteristics

Note: 1. Pulse width less than 50ns will result in no RESET (for noise immunity).

2. Pulse width less than 20ms will result in no RESET (for noise immunity).

3. CL= 5pF (see Figure 19, page 23).

Symbol Parameter Min Max Unit

tR1(1) RSTIN1 Low to RSTIN1 High 200 ns

tR2(2) RSTIN2 Low to RSTIN2 High 100 ms

tR1HRH(3) RSTIN1 High to RST High 40 200 ms

tR2HRH(3) RSTIN2 High to RST High 40 200 ms

AI03665

RSTIN2

RST (1)

RSTIN1

tR1

tR2

tR1HRH tR2HRH

Note: 1. With pull-up resistor

M41ST85Y, M41ST85W

20/32

Power-fail INPUT/OUTPUT

The Power-Fail Input (PFI) is compared to an in-

ternal reference voltage (independent from the

VPFD comparator).If PFI is less thanthe power-fail

threshold (VPFI), the Power-Fail Output (PFO) will

go low. This function is intended for use as an un-

dervoltage detector to signal a failing power sup-

ply. TypicallyPFI is connected through an external

voltage divider (see Figure 4, page 6) to either the

unregulated DC input (if it is available) or the reg-

ulated output of the VCC regulator. The voltage di-

vider can be set up such that the voltage at PFI

falls below VPFI several milliseconds before the

regulated VCC inputtothe M41ST85Y/W orthe mi-

croprocessor drops below the minimum operating

voltage.

During battery back-up, the power-fail comparator

turns off and PFO goes (or remains) low. Thisoc-

curs afterVCC dropsbelow VPFD(min). Whenpow-

er returns, PFO is forced high, irrespective of VPFI

for the write protect time (tREC), which is the time

from VPFD(max) untilthe inputs arerecognized. At

the end of this time, the power-fail comparator is

enabled and PFO follows PFI. If the comparator is

unused, PFI should be connected to VSS and PFO

left unconnected.

Calibrating the Clock

The M41ST85Y/W is driven by a quartz controlled

oscillator with a nominal frequency of 32,768 Hz.

The devices are tested not exceed +/–35 PPM

(parts per million) oscillator frequency error at

25oC, which equates to about +/–1.53 minutes per

month. When theCalibration circuit is properly em-

ployed, accuracy improves to better than +1/–2

PPM at 25°C.

The oscillation rate of crystals changes with tem-

perature (see Figure 17, page 21). Therefore, the

M41ST85Y/W design employs periodic counter

correction. Thecalibration circuit addsor subtracts

counts from the oscillator divider circuit at the di-

vide by 256stage,as shown inFigure 18, page21.

The number of times pulses which are blanked

(subtracted, negative calibration) or split (added,

positive calibration) depends upon the value load-

ed intothe five Calibrationbits found in theControl

tracting counts slows the clock down.

The Calibration bits occupy the five lower order

bits (D4-D0) in the Control Register (8h). These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign bit; ‘1’ indi-

cates positive calibration, ‘0’ indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes in the cycle may, once

per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary ‘1’ is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 PPM of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillator is running at exactly 32,768 Hz, each

of the 31 increments in the Calibration byte would

represent +10.7 or –5.35 seconds per month

which correspondsto a total range of +5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M41ST85Y/W may re-

quire.

The first involves setting the clock, letting itrun for

a month andcomparing it to a known accurate ref-

erence and recording deviation overa fixed period

of time.Calibration values,including thenumber of

seconds lost or gained in a given period, can be

found in Application Note AN934: TIMEKEEPER

CALIBRATION. This allows the designer to give

the end user the ability to calibrate the clock as the

environment requires, even if the final product is

packaged in a non-user serviceable enclosure.

The designer could provide a simple utility that ac-

cesses the Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT/OUT pin. The pin will toggle at 512Hz,

whenthe Stop bit(ST, D7 of1h) is‘0’,the Frequen-

cy Test bit (FT, D6 of 8h) is ‘1’, the Alarm Flag En-

able bit (AFE, D7 of Ah) is ‘0’, and the Watchdog

Steering bit(WDS,D7of 9h) is ‘1’or theWatchdog

Any deviation from 512 Hz indicates the degree

and direction of oscillatorfrequency shift at the test

temperature. For example, a reading of

512.010124 Hz would indicate a +20 PPM oscilla-

tor frequency error, requiring a –10 (XX001010) to

be loaded into the Calibration Byte for correction.

Note that setting or changing the Calibration Byte

does not affect the Frequency testoutput frequen-

cy.

The IRQ/FT/OUT pin is an open drain output

which requires a pull-up resistor to VCC for proper

operation. A500 to10k resistor is recommended in

order to control the rise time. The FT bit is cleared

on power-down.

21/32

M41ST85Y, M41ST85W

Output Driver Pin

When the FT bit, AFE bit and watchdog register

are not set, the IRQ/FT/OUT pin becomes an out-

put driver that reflects the contents of D7 of the

Control Register. In other words, when D6 of loca-

tion 08h is a ‘0’, D7 of location 08h and 0Ah and

the watchdog register are a ‘0’ then the IRQ/FT/

OUT pin will be driven low.

Note: The IRQ/FT/OUT pin is an open drain which

requires an external pull-up resistor.

Initial Power-on Defaults

Upon initial application of power to the device, the

following register bits are set to a ‘0’ state: Watch-

dog Register; FT; AFE; ABE and SQWE. The fol-

lowing bits areset to a‘1’ state: ST; OUT; and HT.

Century Bit

Bits D7 and D6 of Clock Register 03h contain the

CENTURY ENABLEBit (CEB) andthe CENTURY

Bit (CB). Setting CEB to a “1”will cause CB to tog-

gle, either from a “0” to “1” or from “1” to “0” at the

turn of the century (depending upon its initial

state). If CEB is set to a “0”, CB will not toggle.

Figure 17. Crystal Accuracy Across Temperature

Figure 18. Calibration Waveform

AI00999

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= -0.038 (T - T0)2±10%

Fppm

T0=25°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M41ST85Y, M41ST85W

22/32

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings” table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 7. Absolute Maximum Ratings

Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Symbol Parameter Value Unit

TSTG Storage Temperature (VCC Off,Oscillator

Off) SNAPHAT –40 to 85 °C

SOIC –55 to 125 °C

TSLD (1) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltage –0.3 to VCC+0.3 V

VCC Supply Voltage M41ST85Y –0.3 to 7 V

M41ST85W –0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

23/32

M41ST85Y, M41ST85W

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should checkthatthe operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 8. DC and AC Measurement Conditions

Note: Output High Z is defined as the point where data is no longer driven (see Table 11, page 25).

Figure 19. AC Testing Load Circuit

Note: 1. CL= 100pF for the M41ST85Y, 50pF for the M41ST85W

Figure 20. AC Testing Input/Output Waveforms

Table 9. Capacitance

Note: Effective capacitance measured with power supply at 5V. Outputs are deselected.

1. Sampled only, not 100% tested.

Parameter M41ST85Y M41ST85W

VCC Supply Voltage 4.5 to 5.5V 2.7 to 3.6V

Ambient Operating Temperature –40 to 85°C –40 to 85°C

Load Capacitance (CL)100pF 50pF

Input Rise and Fall Times ≤50ns ≤50ns

Input Pulse Voltages 0.2 to 0.8VCC 0.2 to 0.8VCC

Input and Output Timing Ref.Voltages 0.3 to 0.7VCC 0.3 to 0.7VCC

AI03916

CL=100pF(1)

or 50pF

CLincludes JIG capacitance

645Ω

DEVICE

UNDER

TEST

1.75V

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter Min Max Unit

CIN Input Capacitance 7 pF

COUT (1) Output Capacitance 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

M41ST85Y, M41ST85W

24/32

Table 10. DC Characteristics

Note: 1. Outputs Deselected.

2. RSTIN1 andRSTIN2 internally pulled-upto VCC through 100KΩresistor. WDI internally pulled-down to VSS through 100KΩresistor.

3. For IRQ/FT/OUT, RST pins (Open Drain).

4. Conditioned output (ECON) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will re-

duce battery life.

5. External SRAM must match RTC SUPERVISOR chip VCC specification.

6. Measured with VOUT and ECON open.

Symb. Parameter Test Condition Min Typ Max Unit

IBAT(6) Battery Current OSC ON TA=25°C, VCC =0V,

BAT =3V 400 500 nA

Battery Current OSC OFF 50 nA

ICC1 Supply Current M41ST85Y f = 400kHz 1.4 mA

M41ST85W 750 µA

ICC2 Supply Current (Standby) M41ST85Y SCL, SDA = VCC – 0.3V 1mA

M41ST85W 500 µA

ILI(1,2) Input Leakage Current 0V ≤VIN ≤VCC ±1µA

Input Leakage Current (PFI) 0V ≤VIN ≤VCC –25 2 25 nA

ILO(1) Output Leakage Current 0V ≤VOUT ≤VCC ±1µA

IOUT1(5) VOUT Current (Active) M41ST85Y VOUT1 >V

CC –0.3V 175 mA

M41ST85W 100 mA

IOUT2 VOUT Current (Battery Back-up) VOUT2 >V

BAT – 0.3V 100 µA

VIH Input High Voltage 0.7VCC VCC + 0.3 V

VIL Input Low Voltage –0.3 0.3VCC V

VBAT Battery Voltage 3.0 V

VOH Output High Voltage IOH = –1.0mA 2.4 V

VOHB(4) VOH (Battery Back-up) IOUT2 = –1.0µA2.5 2.9 3.6 V

VOL Output Low Voltage IOL = 3.0mA 0.4 V

Output Low Voltage (Open Drain) (3) IOL = 10mA 0.4 V

VPFD PowerFail Deselect M41ST85Y 4.30 4.40 4.50 V

M41ST85W 2.60 2.65 2.70 V

VPFI PFI Input Threshold 1.225 1.250 1.275 V

VSO Battery Back-up Switchover 2.5 V

25/32

M41ST85Y, M41ST85W

Table 11. Operating Modes

Note: X = VIH or VIL.

7. See Table 10, page 24 for details.

Table 12. Crystal Electrical Characteristics

Note: These are externally supplied

1. Load capacitors are integrated within the M41ST85Y/W. Circuit board layout considerations for the 32.768 kHz crystal of minimum

trace lengths and isolation from RF generating signals should be taken into account.

ST Microelectronics recommends the KDS DT-38 Tuning Fork Type (thru-hole) or DMX-26 (SMD) quartz crystal for industrial tem-

perature operations.

KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type.

Mode VCC E G W DQ0-DQ7 Power

Deselect 4.5 to 5.5V

3.0 to 3.6V

VIH X X High Z Standby

Write VIL XVIL DIN Active

Read VIL VIL VIH DOUT Active

Read VIL VIH VIH High Z Active

Deselect VSO to VPFD (min) (1) X X X High Z CMOS Standby

Deselect ≤VSO (1) X X X High Z Battery Back-up Mode

Symbol Parameter Typ Min Max Unit

f0Resonant Frequency 32.768 kHz

RSSeries Resistance 60 kΩ

CL(1) Load Capacitance 12.5 pF

M41ST85Y, M41ST85W

26/32

Figure 21. Power Down/Up Mode AC Waveforms

Table 13. Power Down/Up AC Characteristics

Note: 1. VPFD (max) to VPFD (min) fall time of less than tFmay result in deselection/write protection not occurring until

200µs after VCC passes VPFD (min).

2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

Symbol Parameter Min Typ Max Unit

tF(1) VPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB(2) VPFD (min) to VSS VCC FallTime 10 µs

tPD EX at VIH before Power Down 0 µs

tPFD PFI to PFO Propagation Delay 15 25 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1µs

tREC Power up Deselect Time 40 200 ms

AI03661

VCC

INPUTS

(PER CONTROLINPUT)

OUTPUTS

DON’T CARE

HIGH-Z

tF tFB tR

tPD tRB

tDR

VALID VALID

(PER CONTROLINPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

tREC

RST

ECON

PFO

27/32

M41ST85Y, M41ST85W

PACKAGE MECHANICAL

Figure 22. SOH28 - 28 lead Plastic Small Outline, Battery SNAPHAT, Package Outline

Note: Drawing is not to scale.

Table 14. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 1.27 – – 0.050 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0°8°0°8°

N28 28

CP 0.10 0.004

SOH-A

LA1 α

M41ST85Y, M41ST85W

28/32

Figure 23. SH - SNAPHAT Housing for48 mAhBattery & Crystal, Package Outline

Note: Drawing is not to scale.

Table 15. SH - SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 9.78 0.3850

A1 6.73 7.24 0.2650 0.2850

A2 6.48 6.99 0.2551 0.2752

A3 0.38 0.0150

B 0.46 0.56 0.0181 0.0220

D 21.21 21.84 0.8350 0.8598

E 14.22 14.99 0.5598 0.5902

eA 15.55 15.95 0.6122 0.6280

eB 3.20 3.61 0.1260 0.1421

L 2.03 2.29 0.0799 0.0902

SHTK-A

A1 A

29/32

M41ST85Y, M41ST85W

Figure 24. SH - SNAPHAT Housing for 120 mAhBattery & Crystal, Package Outline

Note: Drawing is not to scale.

Table 16. SH -SNAPHAT Housing for120 mAh Battery & Crystal, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 10.54 0.4150

A1 6.73 7.24 0.2650 0.2850

A2 6.48 6.99 0.2551 0.2752

A3 0.38 0.0150

B 0.46 0.56 0.0181 0.0220

D 21.21 21.84 0.8350 0.8598

E 14.22 14.99 0.5598 0.5902

eA 15.55 15.95 0.6122 0.6280

eB 3.20 3.61 0.1260 0.1421

L 2.03 2.29 0.0799 0.0902

SHTK-A

A1 A

M41ST85Y, M41ST85W

30/32

PART NUMBERING

Table 17. Ordering Information Scheme

Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part

number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.

Caution: Do not place the SNAPHATbattery package ”M4TXX-BR12SH” in conductive foam sincewill drain the lithium button-cell battery.

For a list ofavailable options (e.g.,Speed, Package) or for further information on any aspect ofthisdevice,

please contact the ST Sales Office nearest to you.

Table 18. SNAPHAT Battery Table

Example: M41ST 85Y –70 MH 6 TR

Device Type

M41ST

Supply Voltage and Write Protect Voltage

85Y = VCC = 4.5 to 5.5V; VPFD = 4.3 to 4.5V

85W = VCC = 2.7 to 3.6V; VPFD = 2.6 to 2.7V

Speed

–70 = 70ns

–85 = 85ns

Package

MH(1) =SO28

Temperature Range

6=–40to85°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) and Crystal SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) and Crystal SNAPHAT SH

31/32

M41ST85Y, M41ST85W

REVISION HISTORY

Table 19. Document Revision History

Date Revision Details

August 2000 First issue

08/24/00 Block Diagram added (Figure 3)

10/12/00 tREC Tableremoved, cross references corrected

12/18/00 Reformatted, TOC added, and PFI Input Leakage Current added (Table 10)

M41ST85Y, M41ST85W

32/32

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of useof such information norfor any infringement of patents or other rights of third parties which may result from itsuse. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in lifesupport devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.