LMK00301 3-GHz 10-Output Differential Clock Buffer/Level Translator 1.0 General Description Servers, Workstations, and Computing The LMK00301 is a 3-GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 5 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies. The LMK00301 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. 3.0 Features 2.0 Target Applications Clock Distribution and Level Translation for high-speed ADCs, DACs, Serial Interfaces (Multi-Gigabit Ethernet, XAUI, Fibre Channel, PCIe, SATA/SAS, SONET/SDH, CPRI), and high-frequency backplanes Remote Radio Units (RRU) and Baseband Units (BBU) Switches and Routers 3:1 Input Multiplexer -- Two universal inputs operate up to 3.1 GHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL (ACcoupled), or single-ended clocks -- One crystal input accepts 10 to 40 MHz crystal or single-ended clock Two Banks with 5 Differential Outputs each -- LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank) -- LVPECL Additive Jitter with LMK03806 clock source 20 fs RMS at 156.25 MHz (10 kHz - 1 MHz) 51 fs RMS at 156.25 MHz (12 kHz - 20 MHz) High PSRR: -65 / -76 dBc (LVPECL/LVDS) at 156.25 MHz LVCMOS output with synchronous enable input Pin-controlled configuration VCC Core Supply: 3.3 V 5% 3 Independent VCCO Output Supplies: 3.3 V/2.5 V 5% Industrial temperature range: -40C to +85C Package: 48-pin LLP (7.0 x 7.0 x 0.8 mm) 4.0 Functional Block Diagram 30147001 (c) 2012 Texas Instruments Incorporated 301470 SNAS512E www.ti.com LMK00301 3-GHz 10-Output Differential Clock Buffer/Level Translator May 30, 2012 LMK00301 5.0 Connection Diagram 48-Pin LLP Package 30147002 www.ti.com 2 Pin # Pin Name(s) Type DAP DAP GND Description 1, 2 CLKoutA0, CLKoutA0* O Differential clock output A0. Output type set by CLKoutA_TYPE pins. 3, 4 CLKoutA1, CLKoutA1* O Differential clock output A1. Output type set by CLKoutA_TYPE pins. 5, 8 VCCOA PWR Die Attach Pad. Connect to the PCB ground plane for heat dissipation. Power supply for Bank A Output buffers. VCCOA can operate from 3.3 V or 2.5 V. The VCCOA pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (Note 1) 6, 7 CLKoutA2, CLKoutA2* O Differential clock output A2. Output type set by CLKoutA_TYPE pins. 9, 10 CLKoutA3, CLKoutA3* O Differential clock output A3. Output type set by CLKoutA_TYPE pins. 11, 12 CLKoutA4, CLKoutA4* O Differential clock output A4. Output type set by CLKoutA_TYPE pins. 13, 18, 24, 37, 43, 48 GND GND 14, 47 CLKoutA_TYPE0, CLKoutA_TYPE1 I 15, 42 Vcc PWR 16 OSCin I Input for crystal. Can also be driven by a XO, TCXO, or other external single-ended clock. 17 OSCout O Output for crystal. Leave OSCout floating if OSCin is driven by a singleended clock. 19, 22 CLKin_SEL0, CLKin_SEL1 I Clock input selection pins (Note 2) 20, 21 CLKin0, CLKin0* I Universal clock input 0 (differential/single-ended) 23, 39 CLKoutB_TYPE0, CLKoutB_TYPE1 I Bank B output buffer type selection pins (Note 2) 25, 26 CLKoutB4*, CLKoutB4 O Differential clock output B4. Output type set by CLKoutB_TYPE pins. 27, 28 CLKoutB3*, CLKoutB3 O Differential clock output B3. Output type set by CLKoutB_TYPE pins. 29, 32 VCCOB PWR 30, 31 CLKoutB2*, CLKoutB2 O Differential clock output B2. Output type set by CLKoutB_TYPE pins. 33, 34 CLKoutB1*, CLKoutB1 O Differential clock output B1. Output type set by CLKoutB_TYPE pins. 35, 36 CLKoutB0*, CLKoutB0 O Differential clock output B0. Output type set by CLKoutB_TYPE pins. 38 NC -- Not connected internally. Pin may be floated, grounded, or otherwise tied to any potential within the Supply Voltage range stated in Section 8.0 Absolute Maximum Ratings. 40, 41 CLKin1*, CLKin1 I Universal clock input 1 (differential/single-ended) 44 REFout O LVCMOS reference output. Enable output by pulling REFout_EN pin high. 45 VCCOC PWR Power supply for REFout Output buffer. VCCOC can operate from 3.3 V or 2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (Note 1) 46 REFout_EN I REFout enable input. Enable signal is internally synchronized to selected clock input. (Note 2) Ground Bank A output buffer type selection pins (Note 2) Power supply for Core and Input Buffer blocks. The Vcc supply operates from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcc pin. Power supply for Bank B Output buffers. VCCOB can operate from 3.3 V or 2.5 V. The VCCOB pins are internally tied together. Bypass with a 0.1 uF low-ESR capacitor placed very close to each Vcco pin. (Note 1) Note 1: The output supply voltages or pins (VCCOA, VCCOB, and VCCOC) will be called VCCO in general when no distinction is needed, or when the output supply can be inferred from the output bank/type. Note 2: CMOS control input with internal pull-down resistor. Note 3: Any unused output pin should be left floating with minimum copper length (Note 5), or properly terminated if connected to a transmission line, or disabled/ Hi-Z if possible. See Section 7.3 Clock Outputs for output configuration and Section 14.3 Termination and Use of Clock Drivers for output interface and termination techniques. 3 www.ti.com LMK00301 6.0 Pin Descriptions LMK00301 7.3 Clock Outputs The differential output buffer type for Bank A and Bank B outputs can be separately configured using the CLKoutA_TYPE [1:0] and CLKoutB_TYPE[1:0] inputs, respectively, as shown in Table 3. For applications where all differential outputs are not needed, any unused output pin should be left floating with a minimum copper length (Note 5) to minimize capacitance and potential coupling and reduce power consumption. If an entire output bank will not be used, it is recommended to disable (Hi-Z) the bank to reduce power. Refer to Section 14.3 Termination and Use of Clock Drivers for more information on output interface and termination techniques. 7.0 Functional Description The LMK00301 is a 10-output differential clock fanout buffer with low additive jitter that can operate up to 3.1 GHz. It features a 3:1 input multiplexer with an optional crystal oscillator input, two banks of 5 differential outputs with multi-mode buffers (LVPECL, LVDS, HCSL, or Hi-Z), one LVCMOS output, and 3 independent output buffer supplies. The input selection and output buffer modes are controlled via pin strapping. The device is offered in a 48-pin LLP package and leverages much of the high-speed, low-noise circuit design employed in the LMK04800 family of clock conditioners. Note 5: For best soldering practices, the minimum trace length for any unused output pin should extend to include the pin solder mask. This way during reflow, the solder has the same copper area as connected pins. This allows for good, uniform fillet solder joints helping to keep the IC level during reflow. 7.1 VCC and VCCO Power Supplies The LMK00301 has separate 3.3 V core (VCC) and 3 independent 3.3 V/2.5 V output power supplies (VCCOA, VCCOB, VCCOC) supplies. Output supply operation at 2.5 V enables lower power consumption and output-level compatibility with 2.5 V receiver devices. The output levels for LVPECL (VOH, VOL) and LVCMOS (VOH) are referenced to its respective Vcco supply, while the output levels for LVDS and HCSL are relatively constant over the specified Vcco range. Refer to Section 14.4 Power Supply and Thermal Considerations for additional supply related considerations, such as power dissipation, power supply bypassing, and power supply ripple rejection (PSRR). TABLE 3. Differential Output Buffer Type Selection Note 4: Care should be taken to ensure the Vcco voltages do not exceed the Vcc voltage to prevent turning-on the internal ESD protection circuitry. CLKin_SEL0 Selected Input 0 CLKin0, CLKin0* 0 1 CLKin1, CLKin1* 1 X OSCin TABLE 2. CLKin Input vs. Output States www.ti.com State of Enabled Outputs CLKinX and CLKinX* inputs floating Logic low CLKinX and CLKinX* inputs shorted together Logic low CLKin logic low Logic low CLKin logic high Logic high 0 0 LVPECL 0 1 LVDS 1 0 HCSL 1 1 Disabled (Hi-Z) REFout_EN REFout State 0 Disabled (Hi-Z) 1 Enabled The REFout_EN input is internally synchronized with the selected input clock by the SYNC block. This synchronizing function prevents glitches and runt pulses from occurring on the REFout clock when enabled or disabled. REFout will be enabled within 3 cycles (tEN) of the input clock after REFout_EN is toggled high. REFout will be disabled within 3 cycles (tDIS) of the input clock after REFout_EN is toggled low. When REFout is disabled, the use of a resistive loading can be used to set the output to a predetermined level. For example, if REFout is configured with a 1 k load to ground, then the output will be pulled to low when disabled. Table 2 shows the output logic state vs. input state when either CLKin0/CLKin0* or CLKin1/CLKin1* is selected. When OSCin is selected, the output state will be an inverted copy of the OSCin input state. State of Selected CLKin CLKoutX Buffer Type (Bank A or B) TABLE 4. Reference Output Enable TABLE 1. Input Selection 0 CLKoutX_ TYPE0 7.3.1 Reference Output The reference output (REFout) provides a LVCMOS copy of the selected input clock. The LVCMOS output high level is referenced to the Vcco voltage. REFout can be enabled or disabled using the enable input pin, REFout_EN, as shown in Table 4. 7.2 Clock Inputs The input clock can be selected from CLKin0/CLKin0*, CLKin1/CLKin1*, or OSCin. Clock input selection is controlled using the CLKin_SEL[1:0] inputs as shown in Table 1. Refer to Section 14.1 Driving the Clock Inputs for clock input requirements. When CLKin0 or CLKin1 is selected, the crystal circuit is powered down. When OSCin is selected, the crystal oscillator circuit will start-up and its clock will be distributed to all outputs. Refer to Section 14.2 Crystal Interface for more information. Alternatively, OSCin may be driven by a singleended clock (up to 250 MHz) instead of a crystal. CLKin_SEL1 CLKoutX_ TYPE1 4 If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Parameter Supply Voltages Symbol VCC, VCCO Ratings Units -0.3 to 3.6 V VIN -0.3 to (VCC + 0.3) V Input Voltage TSTG -65 to +150 C Lead Temperature (solder 4 s) TL +260 C Junction Temperature TJ +150 C Storage Temperature Range 9.0 Recommended Operating Conditions Parameter Symbol TA Ambient Temperature Range Min Typ Max Units -40 25 85 C 125 C VCC 3.15 3.3 3.45 V VCCO 3.3 - 5% 2.5 - 5% 3.3 2.5 3.3 + 5% 2.5 + 5% V TJ Junction Temperature Core Supply Voltage Range Output Supply Voltage Range (Note 1, Note 8) Note 6: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see Section 11.0 Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed. Note 7: This device is a high-performance integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and up to 750 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations. Note 8: Vcco for any output bank should be less than or equal to Vcc (Vcco Vcc). 10.0 Package Thermal Resistance Package JA JC (DAP) 48-Lead LLP (Note 9) 28.5 C/W 7.2 C/W Note 9: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout. 11.0 Electrical Characteristics Unless otherwise specified: Vcc = 3.3 V 5%, Vcco = 3.3 V 5%, 2.5 V 5%, -40 C TA 85 C, CLKin driven differentially, input slew rate 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, TA = 25 C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. (Note 10) Symbol Parameter Conditions Min Typ Max Units CLKinX selected 8.5 10.5 mA OSCin selected 10 13.5 mA Current Consumption ICC_CORE Core Supply Current, All Outputs Disabled ICC_PECL Additive Core Supply Current, Per LVPECL Bank Enabled 20 27 mA ICC_LVDS Additive Core Supply Current, Per LVDS Bank Enabled 26 32.5 mA ICC_HCSL Additive Core Supply Current, Per HCSL Bank Enabled 35 42 mA ICC_CMOS Additive Core Supply Current, LVCMOS Output Enabled 3.5 5.5 mA ICCO_PECL Additive Output Supply Current, Per LVPECL Bank Enabled 165 197 mA ICCO_LVDS Additive Output Supply Current, Per LVDS Bank Enabled 34 44.5 mA Includes Output Bank Bias and Load Currents, RT = 50 to Vcco - 2V on all outputs in bank 5 www.ti.com LMK00301 8.0 Absolute Maximum Ratings (Note 6, Note 7) LMK00301 Symbol Parameter Conditions ICCO_HCSL Additive Output Supply Current, Per HCSL Bank Enabled Includes Output Bank Bias and Load Currents, RT = 50 on all outputs in bank ICCO_CMOS Additive Output Supply Current, LVCMOS Output Enabled 200 MHz, CL = 5 pF Min Typ Max Units 87 104 mA Vcco = 3.3 V 5% 9 10 mA Vcco = 2.5 V 5% 7 8 mA Power Supply Ripple Rejection (PSRR) PSRRPECL Ripple-Induced Phase Spur Level (Note 12) Differential LVPECL Output PSRRLVDS Ripple-Induced Phase Spur Level (Note 12) Differential LVDS Output PSRRHCSL Ripple-Induced Phase Spur Level (Note 12) Differential HCSL Output VIH High-Level Input Voltage 100 kHz, 100 mVpp Ripple Injected on Vcco, Vcco = 2.5 V 156.25 MHz -65 312.5 MHz -63 156.25 MHz -76 312.5 MHz -74 156.25 MHz -72 312.5 MHz -63 dBc dBc dBc CMOS Control Inputs (CLKin_SELn, CLKoutX_TYPEn, REFout_EN) VIL Low-Level Input Voltage IIH High-Level Input Current VIH = Vcc, Internal pull-down resistor IIL Low-Level Input Current VIL = 0 V, Internal pull-down resistor 1.6 Vcc GND 0.4 V 50 A -5 0.1 V A Clock Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*) fCLKin Input Frequency Range (Note 19) VIHD Differential Input High Voltage VILD Differential Input Low Voltage VID Differential Input Voltage Swing (Note 13) VCMD Differential Input Common Mode Voltage VIH Single-Ended Input High Voltage VIL Single-Ended Input Low Voltage VCM Single-Ended Input Common Mode Voltage ISOMUX www.ti.com Mux Isolation, CLKin0 to CLKin1 Functional up to 3.1 GHz Output frequency range and timing specified per output type (refer to LVPECL, LVDS, HCSL, LVCMOS output specifications) CLKin driven differentially DC 3.1 GHz Vcc V GND V 0.15 1.3 VID = 150 mV 0.5 Vcc 1.2 VID = 350 mV 0.5 Vcc 1.1 VID = 800 mV 0.5 Vcc 0.9 VCM + 0.15 Vcc V GND VCM -0.15 V 0.5 Vcc 1.2 V CLKinX driven single-ended, CLKinX* AC coupled to GND fOFFSET > 50 kHz, PCLKinX = 0 dBm 6 fCLKin0 = 100 MHz -84 fCLKin0 = 200 MHz -82 fCLKin0 = 500 MHz -71 fCLKin0 = 1000 MHz -65 V V dBc Parameter FCLK External Clock Frequency Range (Note 19) Conditions Min Typ Max Units 250 MHz 40 MHz Crystal Interface (OSCin, OSCout) OSCin driven single-ended, OSCout floating Fundamental mode crystal FXTAL Crystal Frequency Range CIN OSCin Input Capacitance ESR 200 (10 to 30 MHz) ESR 125 (30 to 40 MHz) (Note 14) 10 1 pF LVPECL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) fCLKout_FS fCLKout_RS Maximum Output Frequency Full VOD Swing (Note 19, Note 20) VOD 600 mV, Maximum Output Frequency Reduced VOD Swing (Note 19, Note 20) VOD 400 mV, Additive RMS Jitter Integration Bandwidth 1 MHz to 20 MHz (Note 15) Vcco = 3.3 V, RT = 160 to GND, RL = 100 differential RL = 100 differential Vcco = 3.3 V 5%, RT = 160 to GND 1.0 Vcco = 2.5 V 5%, RT = 91 to GND 0.75 1.0 Vcco = 3.3 V 5%, RT = 160 to GND 1.5 3.1 Vcco = 2.5 V 5%, RT = 91 to GND 1.5 2.3 GHz GHz CLKin: 100 MHz, Slew JitterADD RL = 100 differential 59 rate 3 V/ns CLKin: 156.25 MHz, 64 Slew rate 2.7 V/ns CLKin: 625 MHz, Slew JitterADD CLKin: 156.25 MHz, Vcco = 3.3 V, JSOURCE = 190 fs RMS (10 kHz to 1 MHz) RT = 160 to GND, RL = 100 differential 20 fs CLKin: 156.25 MHz, JSOURCE = 195 fs RMS (12 kHz to 20 MHz) 51 CLKin: 100 MHz, Slew Noise Floor Noise Floor fOFFSET 10 MHz Vcco = 3.3 V, RT = 160 to GND, RL = 100 differential -162.5 rate 3 V/ns CLKin: 156.25 MHz, -158.1 Slew rate 2.7 V/ns CLKin: 625 MHz, Slew Duty Cycle (Note 19) VOH Output High Voltage VOL Output Low Voltage VOD Output Voltage Swing (Note 13) tR Output Rise Time 20% to 80% tF Output Fall Time 80% to 20% 50% input clock duty cycle TA = 25 C, DC Measurement, RT = 50 to Vcco - 2 V RT = 160 to GND, RL = 100 differential 7 dBc/Hz -154.4 rate 3 V/ns DUTY fs 30 rate 3 V/ns Additive RMS Jitter with LVPECL clock source from LMK03806 (Note 15, Note 16) 1.2 55 % Vcco 1.2 45 Vcco 0.9 Vcco 0.7 V Vcco 2.0 Vcco 1.75 Vcco 1.5 V 600 830 1000 mV 175 ps 175 ps www.ti.com LMK00301 Symbol LMK00301 Symbol Parameter Conditions fCLKout_FS Maximum Output Frequency Full VOD Swing (Note 19, Note 20) RL = 100 differential fCLKout_RS Maximum Output Frequency Reduced VOD Swing (Note 19, Note 20) RL = 100 differential Min Typ Max Units LVDS Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) VOD 250 mV, VOD 200 mV, 1.0 1.6 GHz 1.5 2.1 GHz CLKin: 100 MHz, Slew JitterADD Additive RMS Jitter Integration Bandwidth 1 MHz to 20 MHz (Note 15) 89 rate 3 V/ns Vcco = 3.3 V, RL = 100 differential CLKin: 156.25 MHz, CLKin: 625 MHz, Slew 37 rate 3 V/ns CLKin: 100 MHz, Slew Noise Floor Noise Floor fOFFSET 10 MHz -159.5 rate 3 V/ns Vcco = 3.3 V, RL = 100 differential CLKin: 156.25 MHz, -157.0 Slew rate 2.7 V/ns CLKin: 625 MHz, Slew Duty Cycle (Note 19) VOD Output Voltage Swing (Note 13) VOD Change in Magnitude of VOD for Complementary Output States 50% input clock duty cycle 45 55 % 450 mV 50 mV 1.375 V -35 35 mV 250 TA = 25 C, DC Measurement, RL = 100 differential dBc/Hz -152.7 rate 3 V/ns DUTY fs 77 Slew rate 2.7 V/ns 400 -50 VOS Output Offset Voltage VOS Change in Magnitude of VOS for Complementary Output States ISA ISB Output Short Circuit Current Single Ended TA = 25 C, Single ended outputs shorted to GND -24 24 mA ISAB Output Short Circuit Current Differential Complementary outputs tied together -12 12 mA tR Output Rise Time 20% to 80% tF www.ti.com Output Fall Time 80% to 20% 1.125 1.25 175 ps 175 ps RL = 100 differential 8 Parameter fCLKout Output Frequency Range (Note 19) JitterADD Additive RMS Jitter Integration Bandwidth 1 MHz to 20 MHz (Note 15) Conditions Min Typ Max Units 400 MHz HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*) RL = 50 to GND, CL 5 pF DC CLKin: 100 MHz, Slew Vcco = 3.3 V, RT = 50 to GND 77 rate 3 V/ns fs CLKin: 156.25 MHz, 86 Slew rate 2.7 V/ns CLKin: 100 MHz, Slew Noise Floor Noise Floor fOFFSET 10 MHz Vcco = 3.3 V, RT = 50 to GND -161.3 rate 3 V/ns dBc/Hz CLKin: 156.25 MHz, -156.3 Slew rate 2.7 V/ns DUTY Duty Cycle (Note 19) 50% input clock duty cycle 45 VOH Output High Voltage TA = 25 C, DC Measurement, 520 VOL Output Low Voltage RT = 50 to GND -150 VCROSS Absolute Crossing Voltage (Note 19, Note 21) RL = 50 to GND, 160 VCROSS Total Variation of VCROSS (Note 19, Note 21) tR Output Rise Time 20% to 80% (Note 21) tF Output Fall Time 80% to 20% (Note 21) fCLKout Output Frequency Range (Note 19) JitterADD Additive RMS Jitter Integration Bandwidth 1 MHz to 20 MHz (Note 15) 55 % 810 920 mV 0.5 150 mV 350 460 mV 140 mV CL 5 pF 250 MHz, RL = 50 to GND, CL 5 pF 300 ps 300 ps LVCMOS Output (REFout) CL 5 pF Vcco = 3.3 V, 100 MHz, Input Slew CL 5 pF rate 3 V/ns Noise Floor Noise Floor Vcco = 3.3 V, 100 MHz, Input Slew fOFFSET 10 MHz CL 5 pF rate 3 V/ns DUTY Duty Cycle (Note 19) DC 50% input clock duty cycle 45 1 mA load Vcco 0.1 VOH Output High Voltage VOL Output Low Voltage IOH Output High Current (Source) IOL Output Low Current (Sink) tR Output Rise Time 20% to 80% (Note 21) tF Output Fall Time 80% to 20% (Note 21) CL 5 pF tEN Output Enable Time (Note 22) tDIS Output Disable Time (Note 22) CL 5 pF 250 95 fs -159.3 dBc/Hz 55 Vcco = 3.3 V 28 Vcco = 2.5 V 20 Vcco = 3.3 V 28 Vcco = 2.5 V 20 250 MHz, RL = 50 to GND, 9 % V 0.1 Vo = Vcco / 2 MHz V mA mA 225 ps 225 ps 3 cycles 3 cycles www.ti.com LMK00301 Symbol LMK00301 Symbol Parameter Conditions tPD_PECL Propagation Delay CLKin-to-LVPECL RL = 100 differential tPD_LVDS Propagation Delay CLKin-to-LVDS RL = 100 differential tPD_HCSL Propagation Delay CLKin-to-HCSL (Note 21) RT = 50 to GND, tPD_CMOS Propagation Delay CLKin-to-LVCMOS (Note 21) tSK(O) Output Skew LVPECL/LVDS/HCSL (Note 19, Note 21, Note 23) tSK(PP) Part-to-Part Output Skew LVPECL/LVDS/HCSL (Note 21, Note 23) Min Typ Max Units Propagation Delay and Output Skew RT = 160 to GND, CL 5 pF CL 5 pF 360 ps 400 ps 590 ps Vcco = 3.3 V 1475 Vcco = 2.5 V 1550 Skew specified between any two CLKouts with the same buffer type. Load conditions per output type are the same as propagation delay specifications. 30 ps 50 80 ps ps Note 10: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 11: See Section 14.4 Power Supply and Thermal Considerations for more information on current consumption and power dissipation calculations. Note 12: Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 * 10(PSRR / 20)) / ( * fCLK) ] * 1E12 Note 13: See Section 12.1 Differential Voltage Measurement Terminology for definition of VID and VOD voltages. Note 14: The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Section 14.2 Crystal Interface for crystal drive level considerations. Note 15: For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2 - JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625 MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2*10dBc/10) / (2**fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 1 to 20 MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10*log10(20 MHz - 1 MHz). The additive RMS jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method #1. Refer to the "Noise Floor vs. CLKin Slew Rate" and "RMS Jitter vs. CLKin Slew Rate" plots in Section 13.0 Typical Performance Characteristics. Note 16: 156.25 MHz LVPECL clock source from LMK03806 with 20 MHz crystal reference (crystal part number: ECS-200-20-30BU-DU). Typical JSOURCE = 190 fs RMS (10 kHz to 1 MHz) and 195 fs RMS (12 kHz to 20 MHz). Refer to the LMK03806 datasheet for more information. Note 17: The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is 10 MHz, but for lower frequencies this measurement offset can be as low as 5 MHz due to measurement equipment limitations. Note 18: Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs. Note 19: Specification is guaranteed by characterization and is not tested in production. Note 20: See Section 13.0 Typical Performance Characteristics for output operation over frequency. Note 21: AC timing parameters for HCSL or CMOS are dependent on output capacitive loading. Note 22: Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement. Note 23: Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions. www.ti.com 10 12.1 Differential Voltage Measurement Terminology The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used. The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described. The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description. Figure 1 illustrates the two different definitions side-by-side for inputs and Figure 2 illustrates the two different definitions side-byside for outputs. The VID (or VOD) definition show the DC levels, VIH and VOL (or VOH and VOL), that the non-inverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the differential signal can be measured. VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP). 30147007 FIGURE 1. Two Different Definitions for Differential Input Signals 30147008 FIGURE 2. Two Different Definitions for Differential Output Signals Note 24: Refer to Application Note AN-912 Common Data Transmission Parameters and their Definitions for more information. 11 www.ti.com LMK00301 12.0 Measurement Definitions TA = 25 C, CLKin driven differentially, input slew rate 3 V/ns. LVPECL Output Swing (VOD) vs. Frequency 1.0 Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V, LVDS Output Swing (VOD) vs. Frequency 0.45 Vcco=2.5 V, Rterm=91 Vcco=3.3 V, Rterm=160 0.40 0.8 OUTPUT SWING (V) OUTPUT SWING (V) 0.9 0.7 0.6 0.5 0.4 0.3 0.2 0.0 100 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.1 0.00 1000 FREQUENCY (MHz) 10000 100 1000 FREQUENCY (MHz) 10000 30147076 30147075 LVDS Output Swing @ 156.25 MHz 0.8 0.4 0.6 0.3 0.4 0.2 OUTPUT SWING (V) OUTPUT SWING (V) LVPECL Output Swing @ 156.25 MHz 0.2 0.0 -0.2 -0.4 0.1 0.0 -0.1 -0.2 -0.6 -0.3 -0.8 -0.4 0.0 2.5 5.0 TIME (ns) 7.5 10.0 0.0 2.5 5.0 TIME (ns) 7.5 30147091 LVDS Output Swing @ 1.5 GHz 0.4 0.3 0.3 0.2 0.2 OUTPUT SWING (V) 0.4 0.1 0.0 -0.1 -0.2 -0.3 0 -0.1 -0.2 -0.4 0.25 0.50 TIME (ns) 0.75 1.00 0.00 30147093 www.ti.com 0.1 -0.3 -0.4 0.00 10.0 30147092 LVPECL Output Swing @ 1.5 GHz OUTPUT SWING (V) LMK00301 13.0 Typical Performance Characteristics 0.25 0.50 TIME (ns) 0.75 1.00 30147094 12 LVCMOS Output Swing @ 250 MHz 1.0 1.00 Vcco=3.3 V, AC coupled, 50 load Vcco=2.5 V, AC coupled, 50 load 0.75 OUTPUT SWING (V) 0.8 OUTPUT SWING (V) LMK00301 HCSL Output Swing @ 250 MHz 0.6 0.4 0.2 0.0 0.50 0.25 0.00 -0.25 -0.50 -0.75 -0.2 -1.00 0 1 2 3 TIME (ns) 4 5 0 1 2 3 4 TIME (ns) 5 6 30147098 30147099 Noise Floor vs. CLKin Slew Rate @ 100 MHz -145 LVPECL LVDS HCSL LVCMOS CLKin Source -135 Fclk=100 MHz Foffset=20 MHz NOISE FLOOR (dBc/Hz) NOISE FLOOR (dBc/Hz) -140 Noise Floor vs. CLKin Slew Rate @ 156.25 MHz -150 -155 -160 -165 -170 -140 LVPECL LVDS HCSL CLKin Source Fclk=156.25 MHz Foffset=20 MHz -145 -150 -155 -160 -165 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIFFERENTIAL INPUT SLEW RATE (V/ns) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIFFERENTIAL INPUT SLEW RATE (V/ns) 30147077 30147078 Noise Floor vs. CLKin Slew Rate @ 625 MHz -140 LVPECL LVDS CLKin Source RMS Jitter vs. CLKin Slew Rate @ 100 MHz (Note 25) 400 Fclk=625 MHz Foffset=20 MHz 350 RMS JITTER (fs) NOISE FLOOR (dBc/Hz) -135 -145 -150 -155 -160 300 LVPECL LVDS HCSL LVCMOS CLKin Source Fclk=100 MHz Int. BW=1-20 MHz 250 200 150 100 50 -165 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIFFERENTIAL INPUT SLEW RATE (V/ns) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIFFERENTIAL INPUT SLEW RATE (V/ns) 30147079 30147080 13 www.ti.com 500 LVPECL LVDS HCSL CLKin Source 450 200 Fclk=156.25 MHz Int. BW=1-20 MHz LVPECL LVDS CLKin Source 175 350 RMS JITTER (fs) RMS JITTER (fs) 400 300 250 200 150 100 Fclk=625 MHz Int. BW=1-20 MHz 150 125 100 75 50 25 50 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIFFERENTIAL INPUT SLEW RATE (V/ns) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIFFERENTIAL INPUT SLEW RATE (V/ns) 30147082 30147081 -50 LVPECL LVDS HCSL -55 PSRR vs. Ripple Frequency @ 312.5 MHz RIPPLE INDUCED SPUR LEVEL (dBc) RIPPLE INDUCED SPUR LEVEL (dBc) PSRR vs. Ripple Frequency @ 156.25 MHz Fclk=156.25 MHz Vcco Ripple=100 mVpp -60 -65 -70 -75 -80 -85 -90 .1 1 RIPPLE FREQUENCY (MHz) 10 650 Right Y-axis plot 1850 1750 1650 450 1550 350 1450 250 1350 -25 0 25 50 75 TEMPERATURE (C) -60 -65 -70 -75 -80 -85 -90 1 RIPPLE FREQUENCY (MHz) 10 LVPECL Phase Noise @ 100 MHz (Note 25) 1950 550 -50 Fclk=312.5 MHz Vcco Ripple=100 mVpp REFout PROPAGATION DELAY (ps) 750 LVPECL (0.35 ps/C) LVDS (0.35 ps/C) HCSL (0.35 ps/C) LVCMOS (2.2 ps/C) LVPECL LVDS HCSL -55 30147084 Propagation Delay vs. Temperature 850 -50 .1 30147083 CLKout PROPAGATION DELAY (ps) LMK00301 RMS Jitter vs. CLKin Slew Rate @ 625 MHz RMS Jitter vs. CLKin Slew Rate @ 156.25 MHz (Note 25) 100 30147085 30147095 www.ti.com 14 HCSL Phase Noise @ 100 MHz (Note 25) 30147097 Crystal Power Dissipation vs. RLIM (Note 26, Note 27) LVDS Phase Noise in Crystal Mode (Note 26, Note 27) 200 -60 20 MHz Crystal 40 MHz Crystal PHASE NOISE (dBc/Hz) CRYSTAL POWER DISSIPATION (W) 30147096 175 LMK00301 LVDS Phase Noise @ 100 MHz (Note 25) 150 125 100 75 50 25 20 MHz Crystal, Rlim = 1.5 k 40 MHz Crystal, Rlim = 1.0 k -80 -100 -120 -140 -160 -180 0 0 10 500 1k 1.5k 2k 2.5k 3k 3.5k 4k RLIM () 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 30147032 30147031 Note 25: The typical RMS jitter values in the plots show the total output RMS jitter (JOUT) for each output buffer type and the source clock RMS jitter (JSOURCE). From these values, the Additive RMS Jitter can be calculated as: JADD = SQRT(JOUT2 - JSOURCE2). Note 26: 20 MHz crystal characteristics: Abracon ABL series, AT cut, CL = 18 pF , C0 = 4.4 pF measured (7 pF max), ESR = 8.5 measured (40 max), and Drive Level = 1 mW max (100 W typical). Note 27: 40 MHz crystal characteristics: Abracon ABLS2 series, AT cut, CL = 18 pF , C0 = 5 pF measured (7 pF max), ESR = 5 measured (40 max), and Drive Level = 1 mW max (100 W typical). 15 www.ti.com LMK00301 14.0 Application Information 14.1 Driving the Clock Inputs The LMK00301 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept AC- or DC-coupled 3.3V/2.5V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet the input requirements specified in Section 11.0 Electrical Characteristics. The device can accept a wide range of signals due to its wide input common mode voltage range (VCM ) and input voltage swing (VID) / dynamic range. For 50% duty cycle and DC-balanced signals, AC coupling may also be employed to shift the input signal to within the VCM range. Refer to Section 14.3 Termination and Use of Clock Drivers for signal interfacing and termination techniques. To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have high slew rate of 3 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. For this reason, a differential signal input is recommended over singleended because it typically provides higher slew rate and common-mode-rejection. Refer to the "Noise Floor vs. CLKin Slew Rate" and "RMS Jitter vs. CLKin Slew Rate" plots in Section 13.0 Typical Performance Characteristics. While it is recommended to drive the CLKin0 and CLKin1 with a differential signal input, it is possible to drive them with a single-ended clock. Again, the single-ended input slew rate should be as high as possible to minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4 V, so the input can be AC coupled as shown in Figure 3. 30147029 FIGURE 4. Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external clock as shown in Figure 5. The input clock should be AC coupled to the OSCin pin, which has an internally-generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative input to multiplex an external clock, it is recommended to use either universal input (CLKinX) since it offers higher operating frequency, better common mode and power supply noise rejection, and greater performance over supply voltage and temperature variations. 30147030 FIGURE 5. Driving OSCin with a Single-Ended Input 14.2 Crystal Interface The LMK00301 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The crystal interface is shown in Figure 6. 30147028 FIGURE 3. Single-Ended LVCMOS Input, AC Coupling A single-ended clock may also be DC coupled to CLKinX as shown in Figure 4. If the DC coupled input swing has a common mode level near the device's internal bias voltage of 1.4 V, then only a 0.1 uF bypass cap is required on CLKinX*. Otherwise, if the input swing is not optimally centered near the internal bias voltage, then CLKinX* should be externally biased to the midpoint voltage of the input swing. This can be achieved using external biasing resistors, RB1 and RB2, or another low-noise voltage reference. The external bias voltage should be within the specified input common voltage (VCM) range. This will ensure the input swing crosses the threshold voltage at a point where the input slew rate is the highest. 30147009 FIGURE 6. Crystal Interface The load capacitance (CL) is specific to the crystal, but usually on the order of 18 - 20 pF. While CL is specified for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY ~ 1~3 pF) can affect the discrete load capacitor values, C1 and C2. For the parallel resonant circuit, the discrete capacitor values can be calculated as follows: CL = (C1 * C2) / (C1 + C2) + CIN + CSTRAY www.ti.com 16 (1) LMK00301 Typically, C1 = C2 for optimum symmetry, so Equation 1 can be rewritten in terms of C1 only: CL = C12 / (2 * C1) + CIN + CSTRAY (2) Finally, solve for C1: C1 = (CL - CIN - CSTRAY)*2 (3) 30147020 Section 11.0 Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start-up and maintain steady-state operation. The power dissipated in the crystal, PXTAL, can be computed by: PXTAL = IRMS2 * RESR*(1 + C0/CL)2 FIGURE 7. Differential LVDS Operation, DC Coupling, No Biasing by the Receiver For DC coupled operation of an HCSL driver, terminate with 50 to ground near the driver output as shown in Figure 8. Series resistors, Rs, may be used to limit overshoot due to the fast transient current. Because HCSL drivers require a DC path to ground, AC coupling is not allowed between the output drivers and the 50 termination resistors. (4) Where: * IRMS is the RMS current through the crystal. * RESR is the max. equivalent series resistance specified for the crystal * CL is the load capacitance specified for the crystal * C0 is the min. shunt capacitance specified for the crystal IRMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active. As shown in Figure 6, an external resistor, RLIM, can be used to limit the crystal drive level, if necessary. If the power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a suggested value for RLIM is 1.5 k. 30147090 FIGURE 8. HCSL Operation, DC Coupling For DC coupled operation of an LVPECL driver, terminate with 50 to Vcco - 2 V as shown in Figure 9. Alternatively terminate with a Thevenin equivalent circuit as shown in Figure 10 for Vcco (output driver supply voltage) = 3.3 V and 2.5 V. In the Thevenin equivalent circuit, the resistor dividers set the output termination voltage (VTT) to Vcco - 2 V. 14.3 Termination and Use of Clock Drivers When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance: * Transmission line theory should be followed for good impedance matching to prevent reflections. * Clock drivers should be presented with the proper loads. -- LVDS outputs are current drivers and require a closed current loop. -- HCSL drivers are switched current outputs and require a DC path to ground via 50 termination. -- LVPECL outputs are open emitter and require a DC path to ground. * Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level; in this case, the signal should normally be AC coupled. It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure the receiver is biased at the optimum DC voltage (common mode voltage). 30147021 FIGURE 9. Differential LVPECL Operation, DC Coupling 14.3.1 Termination for DC Coupled Differential Operation For DC coupled operation of an LVDS driver, terminate with 100 as close as possible to the LVDS receiver as shown in Figure 7. 17 www.ti.com LMK00301 V and 2.5 V. Note: this Thevenin circuit is different from the DC coupled example in Figure 10, since the voltage divider is setting the input common mode voltage of the receiver. 30147022 FIGURE 10. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent 30147024 FIGURE 12. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent 14.3.2 Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver, it is important to ensure the receiver is biased to its ideal DC level. When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors; however the proper DC bias point needs to be established at the receiver. One way to do this is with the termination circuitry in Figure 11. When driving self-biased LVDS receivers, the circuit shown in Figure 11 may be modified by replacing the 50 terminations to Vbias with a single 100 resistor across the input pins of the receiver. When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to capacitor charging. The previous example uses a 0.1 F capacitor, but this may need to be adjusted to meet the startup requirements for the particular application. Another variant of AC coupling to a selfbiased LVDS receiver is to move the 0.1 uF capacitors between the 100 differential termination and the receiver inputs. 14.3.3 Termination for Single-Ended Operation A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal. It is possible to use an LVPECL driver as one or two separate 800 mV p-p signals. When DC coupling one of the LMK00301 LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminate the unused driver. When DC coupling on of the LMK00301 LVPECL drivers, the termination should be 50 to Vcco - 2 V as shown in Figure 13. The Thevenin equivalent circuit is also a valid termination as shown in Figure 14 for Vcco = 3.3 V. 30147025 FIGURE 13. Single-Ended LVPECL Operation, DC Coupling 30147023 FIGURE 11. Differential LVDS Operation, AC Coupling, No Biasing by the Receiver LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 160 emitter resistors (or 91 for Vcco = 2.5 V) close to the LVPECL driver to provide a DC path to ground as shown in Figure 15. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage (common mode voltage) for LVPECL receivers is 2 V. Alternatively, a Thevenin equivalent circuit forms a valid termination as shown in Figure 12 for Vcco = 3.3 www.ti.com 30147026 FIGURE 14. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent 18 LMK00301 When AC coupling an LVPECL driver use a 160 emitter resistor (or 91 for Vcco = 2.5 V) to provide a DC path to ground and ensure a 50 termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V. If the companion driver is not used, it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50 termination the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 15. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused driver. 30147027 FIGURE 15. Single-Ended LVPECL Operation, AC Coupling 19 www.ti.com LMK00301 14.4 Power Supply and Thermal Considerations 14.4.1 Current Consumption and Power Dissipation Calculations The current consumption values specified in Section 11.0 Electrical Characteristics can be used to calculate the total power dissipation and IC power dissipation for any device configuration. The total VCC core supply current (ICC_TOTAL) can be calculated using Equation 5: (5) ICC_TOTAL = ICC_CORE + ICC_BANK_A + ICC_BANK_B + ICC_CMOS Where: * * * * ICC_CORE is the current for core logic and input blocks and depends on selected input (CLKinX or OSCin). ICC_BANK_A is the current for Bank A and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0 mA if disabled). ICC_BANK_B is the current for Bank B and depends on output type (ICC_PECL, ICC_LVDS, ICC_HCSL, or 0 mA if disabled). ICC_CMOS is the current for the LVCMOS output (or 0 mA if REFout is disabled). Since the output supplies (VCCOA, VCCOB, VCCOC) can be powered from 3 independent voltages, the respective output supply currents (ICCO_BANK_A, ICCO_BANK_B, ICCO_CMOS) should be calculated separately. ICCO_BANK for either Bank A or B can be directly taken from the corresponding output supply current specification (ICCO_PECL, ICCO_LVDS, or ICCO_HCSL) provided the output loading matches the specified conditions. Otherwise, ICCO_BANK should be calculated as follows: ICCO_BANK = IBANK_BIAS + (N * IOUT_LOAD) (6) Where: * * * IBANK_BIAS is the output bank bias current (fixed value). IOUT_LOAD is the DC load current per loaded output pair. N is the number of loaded output pairs in the bank (N = 0 to 5). Table 5 shows the typical IBANK_BIAS values and IOUT_LOAD expressions for the 3 differential output types. For LVPECL, it is possible to use a larger termination resistor (RT) to ground instead of terminating with 50 to VTT = Vcco - 2 V; this technique is commonly used to eliminate the extra termination voltage supply (VTT) and potentially reduce device power dissipation at the expense of lower output swing. For example, when Vcco is 3.3 V, a RT value of 160 to ground will eliminate the 1.3 V termination supply without sacrificing much output swing. In this case, the typical IOUT_LOAD is 25 mA, so ICCO_PECL for a fully-loaded bank reduces to 158 mA (vs. 165 mA with 50 resistors to Vcco - 2 V). TABLE 5. Typical Output Bank Bias and Load Currents Current Parameter LVPECL LVDS HCSL IBANK_BIAS 33 mA 34 mA 6 mA IOUT_LOAD (VOH - VTT)/RT + (VOL - VTT)/RT 0 mA (No DC load current) VOH/RT Once the current consumption is calculated or known for each supply, the total power dissipation (PTOTAL) can be calculated as: PTOTAL = (VCC*ICC_TOTAL) + (VCCOA*ICCO_BANK_A) + (VCCOB*ICCO_BANK_B) + (VCCOC*ICCO_CMOS) (7) If the device configuration has LVPECL or HCSL outputs, then it is also necessary to calculate the power dissipated in any termination resistors (PRT_ PECL and PRT_HCSL) and in any termination voltages (PVTT). The external power dissipation values can be calculated as follows: PRT_PECL (per LVPECL pair) = (VOH - VTT)2/RT + (VOL - VTT)2/RT (8) PVTT_PECL (per LVPECL pair) = VTT * [(VOH - VTT)/RT + (VOL - VTT)/RT] (9) 2 PRT_HCSL (per HCSL pair) = VOH / RT (10) Finally, the IC power dissipation (PDEVICE) can be computed by subtracting the external power dissipation values from PTOTAL as follows: PDEVICE = PTOTAL - N1*(PRT_PECL + PVTT_PECL) - N2*PRT_HCSL Where: * * N1 is the number of LVPECL output pairs with termination resistors to VTT (usually Vcco - 2 V or GND). N2 is the number of HCSL output pairs with termination resistors to GND. www.ti.com 20 (11) This example shows how to calculate IC power dissipation for a configuration with separate VCC and VCCO supplies and unused outputs. Because some outputs are not used, the ICCO_PECL value specified in Section 11.0 Electrical Characteristics cannot be used directly, and output bank current (ICCO_BANK) should be calculated to accurately estimate the IC power dissipation. * * * * * * VCC = 3.3 V, VCCOA = 3.3 V, VCCOB = 2.5 V. Typical ICC and ICCO values. CLKin0/CLKin0* input is selected. Bank A is configured for LVPECL: 4 pairs used with RT = 50 to VT = Vcco - 2 V (1 pair unused). Bank B is configured for LVDS: 3 pairs used with RL = 100 differential (2 pairs unused). REFout is disabled. TA = 85 C Using the current and power calculations from the previous section, we can compute PTOTAL and PDEVICE. * * * * * * * * From Equation 5: ICC_TOTAL = 8.5 mA + 20 mA + 26 mA + 0 mA = 54.5 mA From Table 5: IOUT_LOAD (LVPECL) = (1.6 V - 0.5 V)/50 + (0.75 V - 0.5 V)/50 = 27 mA From Equation 6: ICCO_BANK_A = 33 mA + (4 * 27 mA) = 141 mA From Equation 7: PTOTAL = (3.3 V * 54.5 mA) + (3.3 V * 141 mA) + (2.5 V * 34 mA)] = 730 mW From Equation 8: PRT_PECL = ((2.4 V - 1.3 V)2/50 ) + ((1.55 V - 1.3 V)2/50 ) = 25.5 mW (per output pair) From Equation 9: PVTT_PECL = 0.5 V * [ ((2.4 V - 1.3 V) / 50 ) + ((1.55 V - 1.3 V) / 50 ) ] = 13.5 mW (per output pair) From Equation 10: PRT_HCSL = 0 mW (no HCSL outputs) From Equation 11: PDEVICE = 730 mW - (4 * (25.5 mW + 13.5 mW)) - 0 mW = 574 mW In this example, the IC device will dissipate about 574 mW or 79% of the total power (730 mW), while the remaining 21% will be dissipated in the emitter resistors (102 mW for 4 pairs) and termination voltage (54 mW into Vcco - 2 V). Based on the thermal resistance junction-to-case (JA) of 28.5 C/W, the estimated die junction temperature would be about 16.4 C above ambient, or 101.4 C when TA = 85 C. 14.4.1.2 Power Dissipation Example #2: Worst-Case Dissipation This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power dissipation. In this case, the maximum supply voltage and supply current values specified in Section 11.0 Electrical Characteristics are used. * * * * * Max VCC = VCCO = 3.465 V. Max ICC and ICCO values. CLKin0/CLKin0* input is selected. Banks A and B are configured for LVPECL: all outputs terminated with 50 to VT = Vcco - 2 V. REFout is enabled with 5 pF load. TA = 85 C Using the maximum supply current and power calculations from the previous section, we can compute PTOTAL and PDEVICE. * * * * * * * From Equation 5: ICC_TOTAL = 10.5 mA + 27 mA + 27 mA + 5.5 mA = 70 mA From ICCO_PECL max spec: ICCO_BANK_A = ICCO_BANK_B = 197 mA From Equation 7: PTOTAL = 3.465 V * (70 mA + 197 mA + 197 mA + 10 mA) = 1642.4 mW From Equation 8: PRT_PECL = ((2.57 V - 1.47 V)2/50 ) + ((1.72 V - 1.47 V)2/50 ) = 25.5 mW (per output pair) From Equation 9: PVTT_PECL = 1.47 V * [ ((2.57 V - 1.47 V) / 50 ) + ((1.72 V - 1.47 V) / 50 ) ] = 39.5 mW (per output pair) From Equation 10: PRT_HCSL = 0 mW (no HCSL outputs) From Equation 11: PDEVICE = 1642.4 mW - (10 * (25.5 mW + 39.5 mW)) - 0 mW = 992.4 mW In this worst-case example, the IC device will dissipate about 992.4 mW or 60% of the total power (1642.4 mW), while the remaining 40% will be dissipated in the LVPECL emitter resistors (255 mW for 10 pairs) and termination voltage (395 mW into Vcco - 2 V). Based on JA of 28.5 C/W, the estimated die junction temperature would be about 28.3 C above ambient, or 113.3 C when TA = 85 C. 21 www.ti.com LMK00301 14.4.1.1 Power Dissipation Example #1: Separate Vcc and Vcco Supplies with Unused Outputs LMK00301 phase spur levels for the differential output types at 156.25 MHz and 312.5 MHz . The LMK00301 exhibits very good and well-behaved PSRR characteristics across the ripple frequency range for all differential output types. The phase spur levels for LVPECL are below -64 dBc at 156.25 MHz and below -62 dBc at 312.5 MHz. Using Equation 12, these phase spur levels translate to Deterministic Jitter values of 2.57 ps pk-pk at 156.25 MHz and 1.62 ps pk-pk at 312.5 MHz. Testing has shown that the PSRR performance of the device improves for Vcco = 3.3 V under the same ripple amplitude and frequency conditions. 14.4.2 Power Supply Bypassing The Vcc and Vcco power supplies should have a high-frequency bypass capacitor, such as 0.1 uF or 0.01 uF, placed very close to each supply pin. 1 uF to 10 uF decoupling capacitors should also be placed nearby the device between the supply and ground planes. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance. 14.4.2.1 Power Supply Ripple Rejection In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00301, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the singleside band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc). For the LMK00301, power supply ripple rejection, or PSRR, was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vcco supply. The PSRR test setup is shown in Figure 16. 14.4.3 Thermal Management Power dissipation in the LMK00301 device can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 C. That is, as an estimate, TA (ambient temperature) plus device power dissipation times JA should not exceed 125 C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 17. More information on soldering LLP packages can be obtained at: http://www.national.com/analog/packaging/. A recommended footprint including recommended solder mask and solder paste layers can be found at: http:// www.national.com/analog/packaging/gerber for the SQA48A package. 30147040 FIGURE 16. PSRR Test Setup A signal generator was used to inject a sinusoidal signal onto the Vcco supply of the DUT board, and the peak-to-peak ripple amplitude was measured at the Vcco pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 156.25 MHz and 312.5 MHz under the following power supply ripple conditions: * Ripple amplitude: 100 mVpp on Vcco = 2.5 V * Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [(2*10(PSRR / 20)) / (*fCLK)] * 1012 30147073 FIGURE 17. Recommended Land and Via Pattern To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 17 should connect these top and bottom copper layers and to the ground layer. These vias act as "heat pipes" to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. (12) The "PSRR vs. Ripple Frequency" plots in Section 13.0 Typical Performance Characteristics show the ripple-induced www.ti.com 22 LMK00301 15.0 Physical Dimensions inches (millimeters) unless otherwise noted 48 Pin LLP (SQA48A) Package Order Number Package Marking LMK00301SQX LMK00301SQ Packing 2500 Unit Tape and Reel LMK00301 1000 Unit Tape and Reel LMK00301SQE 250 Unit Tape and Reel 23 www.ti.com LMK00301 3-GHz 10-Output Differential Clock Buffer/Level Translator Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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