Document Number: MMA52xxAKW Rev. 0, 09/2012 Freescale Semiconductor Data Sheet: Technical Data Xtrinsic MMA52xxAKW PSI5 Inertial Sensor MMA52xxAKW The MMA52xxAKW family, a SafeAssure solution, includes the PSI5 Version 1.3 asynchronous mode compatible overdamped X-axis satellite accelerometers. Features Bottom View * * * * 60g to 480g Full-Scale Range 400 Hz, 3-Pole Low-Pass Filter Single Pole, High-Pass Filter with Fast Startup and Output Rate Limiting PSI5 Version 1.3 Asynchronous Mode Compatible - PSI5-A10P-228/1L Compatible - Baud Rate: 125 kBaud - 10-bit Data - Even Parity Error Detection * 16 s Internal Sample Rate, with Interpolation to 1 s * Pb-Free 16-Pin QFN, 6 by 6 Package * Qualified AECQ100, Revision G, Grade 1 (-40C to +125C) (http://www.aecouncil.com/) 16-PIN QFN CASE 2086-01 VBUF * Airbag Front and Side Crash Detection TEST VSSA Typical Applications NC Top View 16 15 14 13 VCC 1 12 VSSA 17 VSS 2 IDATA Package Shipping MMA5206AKW X 60g 2086-01 Tubes MMA5212AKW X 120g 2086-01 Tubes MMA5224AKW X 240g 2086-01 Tubes MMA5248AKW X 480g 2086-01 Tubes MMA5206AKWR2 X 60g 2086-01 Tape & Reel MMA5212AKWR2 X 120g 2086-01 Tape & Reel MMA5224AKWR2 X 240g 2086-01 Tape & Reel MMA5248AKWR2 X 480g 2086-01 Tape & Reel (c) 2012 Freescale Semiconductor, Inc. All rights reserved. VSS 4 9 VREG 5 6 7 8 DIN Range DOUT Axis NC Device 10 CS SLCK ORDERING INFORMATION 11 VREGA 3 PIN CONNECTIONS Application Diagram VVBUF VBUF VCC VREG IDATA VREGA C4 C5 C6 VCE R1 R2 MMA51xx C2 C3 C1 VSSA CS SCLK VSS VSS DO Note: Pin names and references may differ from PSI5 V1.3 pin names and references DI Figure 1. Application Diagram External Component Recommendations Ref Des Type Description Purpose C1 Ceramic 2.2 nF, 10%, 50V minimum, X7R VCC Power Supply Decoupling and Signal Damping C3 Ceramic 470 pF, 10%, 50V minimum, X7R IDATA Filtering and Signal Damping C2 Ceramic 15 nF, 10%, 50V minimum, X7R VCC Power Supply Decoupling C4, C5, C6 Ceramic 1 F, 10%, 10V minimum, X7R Voltage Regulator Output Capacitor(s) R1 General Purpose 82, 5%, 200 PPM VCC Filtering and Signal Damping R2 General Purpose 27, 5%, 200 PPM IDATA Filtering and Signal Damping xxxxxxx xxxxxxx X: 0g X: +1g xxxxxxx xxxxxxx xxxxxxx xxxxxxx Device Orientation X: 0g xxxxxxx xxxxxxx X: -1g X: 0g X: 0g EARTH GROUND Figure 2. Device Orientation Diagram MMA52xxAKW 2 Sensors Freescale Semiconductor, Inc. Internal Block Diagram VCC Buffer Voltage Regulator Reference Voltage VBUF VBUF VREF Digital Voltage Regulator VREG Analog Voltage Regulator VREGA CS VREG VREGA VBUF VSSA SCLK Low Voltage Detection SPI DIN Sync Pulse Detection Control Logic DOUT VCC Programming Interface IDATA OTP Serial Encoder Array VSS VREG Self-Test Interface VREGA VREG Control In Status Out DSP g-cell Converter SINC Filter IIR LPF Compensation Offset Monitor HPF Figure 3. Block Diagram MMA52xxAKW Sensors Freescale Semiconductor, Inc. 3 VBUF TEST NC Pin Connections VSSA 1 16 15 14 13 VCC 1 12 VSSA 17 VSS 2 11 VREGA IDATA 3 10 CS 5 6 7 8 SLCK DOUT DIN 9 VREG NC VSS 4 Figure 4. Top View, 16-Pin QFN Package Table 1. Pin Description Pin Pin Name Formal Name Definition 1 VCC Supply This pin is connected to the PSI5 power and data line through a resistor and supplies power to the device. An external capacitor must be connected between this pin and VSS. Reference Figure 1. 2 VSS Digital GND 3 IDATA Response Current 4 VSS Digital GND 5 NC Not Connected 6 SCLK SPI Clock This input pin provides the serial clock to the SPI port for test purposes. An internal pulldown device is connected to this pin. This pin must be grounded or left unconnected in the application. 7 DOUT SPI Data Out This pin functions as the serial data output from the SPI port for test purposes. This pin must be left unconnected in the application. 8 DIN SPI Data In This pin functions as the serial data input to the SPI port for test purposes. An internal pulldown device is connected to this pin. This pin must be grounded or left unconnected in the application. 9 VREG Digital Supply This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1. 10 CS Chip Select This input pin provides the chip select to the SPI port for test purposes. An internal pullup device is connected to this pin.This pin must be left unconnected in the application. 11 VREGA Analog Supply This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1. 12 VSSA Analog GND 13 VBUF Power Supply 14 TEST Test Pin 15 NC Not Connected 16 VSSA Analog GND PAD Die Attach Pad Corner Pads Corner Pads 17 This pin is the power supply return node for the digital circuitry. This pin is connected to the PSI5 power and data line through a resistor and modulates the response current for PSI5 communication. Reference Figure 1. This pin is the power supply return node for the digital circuitry. This pin must be left unconnected in the application. This pin is the power supply return node for the analog circuitry. This pin is connected to a buffer regulator for the internal circuitry. The buffer regulator supplies both the analog (VREGA) and digital (VREG) supplies to provide immunity from EMC and supply dropouts on VCC. An external capacitor must be connected between this pin and VSS. Reference Figure 1. This pin is must be grounded or left unconnected in the application. This pin must be left unconnected in the application. This pin is the power supply return node for the analog circuitry. This pin is the die attach flag, and is internally connected to VSS. The corner pads are internally connected to VSS. MMA52xxAKW 4 Sensors Freescale Semiconductor, Inc. 2 Electrical Characteristics 2.1 Maximum Ratings Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. # Rating Symbol Value Unit VCC_REV VCC_MAX VCC_TRANS -0.7 +20.0 +25.0 V V V (3) (3) (9) 1 2 3 Supply Voltage (VCC, IDATA) Reverse Current 160 mA, t 80 ms Continuous Transient (< 10 s) 4 VBUF, Test -0.3 to +4.2 V (3) 5 VREG, VREGA, SCLK, CS, DIN, DOUT -0.3 to +3.0 V (3) 6 Powered Shock (six sides, 0.5 ms duration) gpms 2000 g (3) 7 Unpowered Shock (six sides, 0.5 ms duration) gshock 2500 g (3) 8 Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation) hDROP 1.2 m (5) 9 10 11 12 Electrostatic Discharge (per AECQ100) External Pins (VCC, IDATA, VSS, VSSA), HBM (100 pF, 1.5 k) HBM (100 pF, 1.5 k) CDM (R = 0) MM (200 pF, 0) VESD VESD VESD VESD 4000 2000 1500 200 V V V V (5) (5) (5) (5) 13 14 Temperature Range Storage Junction Tstg TJ -40 to +125 -40 to +150 C C (3) (9) 15 Thermal Resistance JC 2.5 C/W (9, 14) 2.2 Operating Range VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # 16 17 Characteristic Supply Voltage Symbol Min VCC VL 4.2 VCC_UV TA TA Operating Temperature Range 18 19 Typ Max Units VVCC_UV_F -- -- VH 17.0 VL V V (1) (9) TL -40 -40 TH +105 +125 C C (1) (3) MMA52xxAKW Sensors Freescale Semiconductor, Inc. 5 2.3 Electrical Characteristics - Supply and I/O VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units 20 Quiescent Supply Current * IIDLE 4.0 -- 8.0 mA (1) 21 Modulation Supply Current * IMOD IIDLE+ 22.0 IIDLE+ 26.0 IIDLE+ 30.0 mA (1) 22 Inrush Current (Power On until VBUF, VREG, VREGA Stable) IINRUSH -- -- 30 mA (3) 23 24 25 Internally Regulated Voltages VBUF VREG VREGA VBUF VREG VREGA 3.60 2.425 2.425 3.80 2.50 2.50 4.00 2.575 2.575 V V V (1) (1) (1) VVCC_UV_F VBUF_UV_F VREG_UV_F VREGA_UV_F 3.40 2.95 2.15 2.15 3.70 3.15 2.25 2.25 4.0 3.35 2.35 2.35 V V V V (3, 6) (3, 6) (3, 6) (3, 6) VCC_HYST VBUF_HYST VREG_HYST VREGA_HYST 0.10 0.05 0.05 0.05 0.25 0.10 0.10 0.10 0.40 0.15 0.15 0.15 V V V V (3) (3) (3) (3) 26 27 28 29 30 31 32 33 Low Voltage Detection Threshold VCC Falling VBUF Falling VREG Falling VREGA Falling Hysteresis VCC VBUF VREG VREGA * * * 34 35 External Capacitor (VBUF, VREG, VREGA) Capacitance ESR (including interconnect resistance) ESR 500 0 1000 -- 1500 200 nF m (9) (9) 36 Output High Voltage (DO) ILoad = 100 A VOH VREG - 0.1 -- -- V (9) 37 Output Low Voltage (DO) ILoad = 100 A VOL -- -- 0.1 V (9) 38 Input High Voltage CS, SCLK, DI VIH 0.7 * VREG -- -- V (9) 39 Input Low Voltage CS, SCLK, DI VIL -- -- 0.3 * VREG V (9) 40 41 Input Current High (at VIH) (DI) Low (at VIL) (CS) IIH IIL -100 10 -- -- -10 100 A A (9) (9) 42 Pulldown Resistance (SCLK) RPD 20 ae 100 k (9) MMA52xxAKW 6 Sensors Freescale Semiconductor, Inc. 2.4 Electrical Characteristics - Sensor and Signal Chain VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units * * * * SENS SENS SENS SENS -- -- -- -- 8 4 2 1 -- -- -- -- LSB/g LSB/g LSB/g LSB/g (1) (1) (1) (1) * * SENS_240 SENS_240 SENS_240 SENS_480 SENS_480 SENS_480 -5 -7 -7 -5 -7 -7 -- -- -- -- -- -- +5 +7 +7 +5 +7 +7 % % % % % % (1) (1) (9) (1) (1) (9) * OFF10Bit OFF10Bit -52 -52 0 0 +52 +52 LSB LSB (1) (9) * * OFF10Bit OFF10Bit -1 -2 0 0 +1 +2 LSB LSB (1) (9) 47 48 49 50 51 52 Sensitivity (10-bit output @ 100 Hz, referenced to 0 Hz) 60g Range 120g Range 240g Range 480g Range Total Sensitivity Error (including non-linearity) TA = 25C, 240g TL TA TH, 240g TL TA TH, 240g, VVCC_UV_F VCC VL TA = 25C, > 240g TL TA TH, > 240g TL TA TH, > 240g, VVCC_UV_F VCC VL 53 54 Digital Offset Before Offset Cancellation 10-bit 10-bit, TL TA TH, VVCC_UV_F VCC VL 55 56 Digital Offset After Offset Cancellation 10-bit, 0.3 Hz HPF or 0.1 Hz HPF 10-bit, 0.04 Hz HPF 57 Continuous Offset Monitor Limit 10-bit output, before compensation OFFMON -66 -- +66 LSB (3) 58 Range of Output (10-bit Mode) Acceleration RANGE -480 -- +480 LSB (3) 59 60 Cross-Axis Sensitivity Z-axis to X-axis Y-axis to X-axis * * VZX VYX -5 -5 -- -- +5 +5 % % (3) (3) 61 System Output Noise Peak (10-bit Mode, 1 Hz - 1 kHz, All Ranges) * nPeak -4 -- +4 LSB (3) 62 System Output Noise RMS (10-bit mode, 1 Hz - 1 kHz, All Ranges) * nRMS -- -- +1.0 LSB (3) 63 64 Non-linearity 10-bit output, 240g 10-bit output, > 240g NLOUT_240g NLOUT_480g -2 -2 -- -- +2 +2 % % (3) (3) 43 44 45 46 * * MMA52xxAKW Sensors Freescale Semiconductor, Inc. 7 2.5 Electrical Characteristics - Self-Test and Overload VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified. # Characteristic Symbol Min Typ Max Units gST10_60X gST10_120X gST10_240X gST10_480X 120 40 56 8 -- -- -- -- 280 160 184 112 LSB LSB LSB LSB (3) (3) (3) (3) 65 66 67 68 10-Bit Output During Active Self-Test (TL TA TH) 60g Range 120g Range 240g Range 480g Range 69 Acceleration (without hitting internal g-cell stops) 60g Range Positive/Negative gg-cell_Clip60X 400 456 500 g (9) 70 Acceleration (without hitting internal g-cell stops) 120g Range Positive/Negative gg-cell_Clip120X 400 456 500 g (9) 71 Acceleration (without hitting internal g-cell stops) 240g Range Positive/Negative gg-cell_Clip240X 1750 2065 2300 g (9) 72 Acceleration (without hitting internal g-cell stops) 480g Range Positive/Negative gg-cell_Clip480X 1750 2065 2300 g (9) 73 and Sinc Filter Clipping Limit 60g Range Positive/Negative gADC_Clip60X 191 210 233 g (9) 74 and Sinc Filter Clipping Limit 120g Range Positive/Negative gADC_Clip120X 353 380 410 g (9) 75 and Sinc Filter Clipping Limit 240g Range Positive/Negative gADC_Clip240X 928 1055 1218 g (9) 76 and Sinc Filter Clipping Limit 480g Range Positive/Negative gADC_Clip480X 1690 1879 2106 g (9) * * * * MMA52xxAKW 8 Sensors Freescale Semiconductor, Inc. 2.6 Dynamic Electrical Characteristics - PSI5 VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified # Characteristic Symbol Min Typ Max Units tPSI5_INIT1 tPSI5_INIT2_10a0 tPSI5_INIT3_10a0 tOC1 tOC2 tST1 tST2 tST3 ST_RPT tPME -- -- -- -- -- -- -- -- 0 -- 532000 / fOSC 512 * tASYNC 19 * tASYNC 320000 / fOSC 280000 / fOSC 128000 / fOSC 128000 / fOSC 128000 / fOSC -- 300000 / fOSC -- -- -- -- -- -- -- -- 5 -- s s s s s s s s s (7) (7) (7, 12) (7) (7) (7) (7) (7) (7, 12) (7) tBIT_LOW 7.6000 8.0000 8.4000 s (7) tRISE 324 463 602 ns (3) 77 78 79 80 81 82 83 84 85 86 Initialization Timing Phase 1 Phase 2 (10-Bit, Asynchronous Mode 0, k = 8) Phase 3 (10-Bit, Asynchronous Mode 0, ST_RPT = 0) Offset Cancellation Stage 1 Operating Time Offset Cancellation Stage 2 Operating Time Self-Test Stage 1 Operating Time Self-Test Stage 2 Operating Time Self-Test Stage 3 Operating Time Self-Test Repetitions Programming Mode Entry Window 87 Data Transmission Single Bit Time (PSI5 Low Bit Rate) 88 Modulation Current (20% to 80% of IMOD - IIDLE) Rise Time 89 Position of bit transition (PSI5 Low Baud Rate) * tBittrans_LowBaud 49 50 51 % (7) 90 Asynchronous Response Time * tASYNC -- 912 / fOSC -- s (7) 2.7 * Dynamic Electrical Characteristics - Signal Chain VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified # Characteristic Symbol Min Typ Max Units 91 Internal Oscillator Frequency * fOSC 3.80 4 4.20 MHz (1) 92 93 DSP Low-Pass Filter (Note15) Cutoff frequency LPF0 (referenced to 0 Hz) Filter Order LPF0 * * fC_LPF0 OLPF0 400 3 Hz 1 (7) (7) 94 95 96 97 98 99 100 101 102 103 104 105 DSP Offset Cancellation Low-Pass Filter (Note 15) Offset Cancellation Low-Pass Filter Input Sample Rate Stage 1 Cutoff frequency, Startup Phase 1 Stage 1 Filter Order, Startup Phase 1 Stage 2 Cutoff frequency, Startup Phase 1 Stage 2 Filter Order, Startup Phase 1 Cutoff frequency, Option 0 Filter Order, Option 0 Offset Cancellation Output Update Rate (10-Bit Mode) Offset Cancellation Output Step Size (10-Bit Mode) Offset Monitor Update Frequency Offset Monitor Count Limit Offset Monitor Counter Size tOC_SampleRate fC_OC10 OOC10 fC_OC03 OOC03 fC_OC0 OOC0 tOffRate_10 OFFStep_10 OFFMONOSC OFFMONCNTLIMIT OFFMONCNTSIZE 256 10.0 1 0.300 1 0.100 1 fOSC / 2e6 0.5 fOSC/2000 4096 8192 s Hz 1 Hz 1 Hz 1 s LSB Hz 1 1 (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) 106 107 108 109 Sensing Element Natural Frequency 60g 120g 240g 480g fgcell_X60 fgcell_X120 fgcell_X240 fgcell_X480 12651 12651 26000 26000 13871 13871 28700 28700 Hz Hz Hz Hz (9) (9) (9) (9) 110 111 112 113 Sensing Element Rolloff Frequency (-3 db) 60g 120g 240g 480g fgcell_X60 fgcell_X120 fgcell_X240 fgcell_X480 938 938 3952 3952 2592 2592 14370 14370 Hz Hz Hz Hz (9) (9) (9) (9) 114 115 116 117 Sensing Element Damping Ratio 60g 120g 240g 480g gcell_X60 gcell_X120 gcell_X240 gcell_X480 2.760 2.760 1.260 1.260 6.770 6.770 3.602 3.602 (9) (9) (9) (9) 118 119 120 121 Sensing Element Delay (@100 Hz) 60g 120g 240g 480g fgcell_delay_X60 fgcell_delay_X120 fgcell_delay_X240 fgcell_delay_X480 63 63 13 13 170 170 40 40 s s s s (9) (9) (9) (9) 122 Package Resonance Frequency fPackage 100 kHz (9) MMA52xxAKW Sensors Freescale Semiconductor, Inc. 9 2.8 Dynamic Electrical Characteristics - Supply and SPI VL (VCC - VSS) VH, TL TA TH, T 25 K/min, unless otherwise specified # Characteristic Symbol Min Typ Max Units tSET 5 ms (3) tINT_INIT 16000 / fOSC s (7) tVCC_MICROCUTmin tVCC_MICROCUT tVCC_RESET 30 50 1000 s s s (3) (3) (3) 123 Quiescent Current Settling Time (Power Applied to Iq = IIDLE 2mA) 124 Reset Recovery Internal Delay (After internal POR) 125 126 127 VCC Micro-cut (CBUF=CREG=CREGA=1 F) Survival Time (VCC disconnect without Reset, CBUF=CREG=CREGA=700 nF) Survival Time (VCC disconnect without Reset, CBUF=CREG=CREGA=1 F) Reset Time (VCC disconnect above which Reset is guaranteed) 128 129 VBUF, Capacitor Monitor Disconnect Time (Figure 9) POR to first Capacitor Test Disconnect Disconnect Delay, Asynchronous Mode (Figure 9) tPOR_CAPTEST tCAPTEST_ADLY 12000 / fOSC 688 / fOSC s s (7) (7) 130 131 VREG, VREGA Capacitor Monitor POR to first Capacitor Test Disconnect Disconnect Rate tPOR_CAPTEST tCAPTEST_RATE 12000 / fOSC 256 / fOSC s s (7) (7) 132 133 134 135 136 137 138 139 140 141 142 143 144 145 Serial Interface Timing (See Figure 6, CDOUT 80 pF, RDOUT 10 k) Clock (SCLK) period (10% of VCC to 10% of VCC) Clock (SCLK) high time (90% of VCC to 90% of VCC) Clock (SCLK) low time (10% of VCC to 10% of VCC) Clock (SCLK) rise time (10% of VCC to 90% of VCC) Clock (SCLK) fall time (90% of VCC to 10% of VCC) CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC) CS asserted to DOUT valid (CS = 10% of VCC to DOUT = 10/90% of VCC) Data setup time (DIN = 10/90% of VCC to SCLK = 10% of VCC) DIN Data hold time (SCLK = 90% of VCC to DIN = 10/90% of VCC) DOUT Data hold time (SCLK = 90% of VCC to DOUT = 10/90% of VCC) SCLK low to data valid (SCLK = 10% of VCC to DOUT = 10/90% of VCC) SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC) CS high to DOUT disable (CS = 90% of VCC to DOUT = Hi Z) CS high to CS low (CS = 90% of VCC to CS = 90% of VCC) tSCLK tSCLKH tSCLKL tSCLKR tSCLKF tLEAD 320 120 120 60 20 10 0 60 1000 15 15 40 28 60 50 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) tACCESS tSETUP tHOLD_IN tHOLD_OUT tVALID tLAG tDISABLE tCSN 1. Parameters tested 100% at final test. 2. Parameters tested 100% at wafer probe. 3. Verified by characterization 4. * Indicates critical characteristic. 5. Verified by qualification testing. 6. Parameters verified by pass/fail testing in production. 7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing is determined by internal system clock frequency. 8. N/A. 9. Verified by simulation. 10. N/A. 11. Measured at VCC pin; VSYNC guaranteed across full VIDLE range. 12. Self-Test repeats on failure up to a ST_RPTMAX times before transmitting Sensor Error Message. 13. N/A. 14. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad. 15. Filter cutoff frequencies are directly dependent upon the internal oscillator frequency. MMA52xxAKW 10 Sensors Freescale Semiconductor, Inc. VCC_UV_f + VCC_HYST VCC_UV_f Response Terminated if in process VCC VBUF_UV_f + VBUF_HYST VBUF_UV_f VBUF VREG_UV_f + VREG_HYST VREG_UV_f VREG VREGA_UV_f+VREGA_HYST VREGA_UV_f VREG POR Time Figure 5. Powerup Timing CS tLEAD tSCLKR tSCLK tSCLKF tCSN tSCLKH SCLK tSCLKL tLAG tACCESS tVALID tHOLD_OUT tDISABLE DOUT tHOLD_IN tSETUP DIN Figure 6. Serial Interface Timing MMA52xxAKW Sensors Freescale Semiconductor, Inc. 11 3 Functional Description 3.1 User Accessible Data Array A user accessible data array allows for each device to be customized. The array consists of an OTP factory programmable block, an OTP user programmable block, and read-only registers for device status. The OTP blocks incorporate independent error detection circuitry for fault detection (reference Section 3.2). Portions of the factory programmable array are reserved for factory-programmed trim values. The user accessible data is shown in Table 2. Table 2. User Accessible Data Byte Addr (XLong Msg) Register $00 SN0 $01 $02 Bit Function Nibble Addr (Long Msg) Bit Function Nibble Addr (Long Msg) Type 7 6 5 4 3 2 1 0 $01 SN[7] SN[6] SN[5] SN[4] $00 SN[3] SN[2] SN[1] SN[0] SN1 $03 SN[15] SN[14] SN[13] SN[12] $02 SN[11] SN[10] SN[9] SN[8] SN2 $05 SN[23] SN[22] SN[21] SN[20] $04 SN[19] SN[18] SN[17] SN[16] $03 SN3 $07 SN[31] SN[30] SN[29] SN[28] $06 SN[27] SN[26] SN[25] SN[24] $04 DEVCFG1 $09 0 0 1 0 $08 0 RNG[2] RNG[1] RNG[0] $05 DEVCFG2 $0B 0 0 0 0 $0A 0 0 0 0 $06 DEVCFG3 $0D 0 0 0 0 $0C 0 0 0 0 $07 DEVCFG4 $0F 0 0 0 0 $0E 0 0 0 0 $08 DEVCFG5 $11 0 0 0 0 $10 0 0 0 0 R $09 DEVCFG6 $13 0 1 0 0 $12 0 0 0 0 $0A DEVCFG7 $15 0 0 0 0 $14 0 0 0 0 $0B DEVCFG8 $17 1 0 1 0 $16 0 0 0 0 $0C SC $19 0 TM_B RESERVED IDEN_B $18 OC_INIT_B IDEF_B OFF_B 0 $0D MFG_ID $1B 0 0 0 0 $1A 0 0 0 0 Type codes R: Readable register via PSI5 3.1.1 Device Serial Number Registers A unique serial number is programmed into the serial number registers of each device during manufacturing. The serial number is composed of the following information: Bit Range Content SN[12:0] Serial Number SN[31:13] Lot Number Serial numbers begin at 1 for all produced devices in each lot and are sequentially assigned. Lot numbers begin at 1 and are sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. The serial number registers are included in the factory programmed OTP CRC verification. Reference Section 3.2 for details regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or performance, and are only used for traceability purposes. MMA52xxAKW 12 Sensors Freescale Semiconductor, Inc. 3.1.2 Factory Configuration Register (DEVCFG1) The factory configuration register is a factory programmed, read-only register which contains user specific device configuration information. The factory configuration register is included in the factory programmed OTP CRC verification. Location Bit Address Register $04 DEVCFG1 7 Factory Default 3.1.2.1 6 5 4 3 2 1 0 0 0 1 0 0 RNG[2] RNG[1] RNG[0] 0 0 1 0 0 0 0 0 Range Indication Bits (RNG[2:0]) The range indication bits are factory programmed and indicate the full-scale range of the device as shown below. 3.1.3 RNG[2] RNG[1] RNG[0] Full-Scale Acceleration Range g-Cell Design PSI5 Init Data Transmission (D9) Reference Table 9 0 0 0 Reserved N/A 0001 0 0 1 60g Medium-g 0111 0 1 0 Reserved N/A 0010 0 1 1 120 g Medium-g 1000 1 0 0 Reserved N/A 0011 1 0 1 240 g High-g 1001 1 1 0 Reserved N/A 0100 1 1 1 480 g High-g 1010 Status Check Register (SC) The status check register is a read-only register containing device status information. Location Bit Address Register 7 6 5 4 3 2 1 0 $0C SC 0 TM_B RESERVED IDEN_B OC_INIT_B IDEF_B OFF_B 0 3.1.3.1 Test Mode Flag (TM_B) The test mode bit is cleared if the device is in test mode. 3.1.3.2 TM_B Operating Mode 0 Test Mode is active 1 Test Mode is not active Internal Data Error Flag (IDEN_B) The internal data error bit is cleared if a register data error detection mismatch is detected in the user accessible OTP array. A device reset is required to clear the error. IDEN_B Error Condition 0 Error detection mismatch in user programmable OTP array 1 No error detected MMA52xxAKW Sensors Freescale Semiconductor, Inc. 13 3.1.3.3 Offset Cancellation Init Status Flag (OC_INIT_B) The offset cancellation initialization status bit is set once the offset cancellation initialization process is complete, and the filter has switched to normal mode. 3.1.3.4 OC_INIT_B Error Condition 0 Offset Cancellation in initialization 1 Offset Cancellation initialization complete (tOC1 and tOC2 expired) Internal Factory Data Error Flag (IDEF_B) The internal factory data error bit is cleared if a register data CRC fault is detected in the factory programmable OTP array. A device reset is required to clear the error. 3.1.3.5 IDEF_B Error Condition 0 CRC error in factory programmable OTP array 1 No error detected Offset Error Flag (OFF_B) The offset error flag is cleared if the acceleration signal reaches the offset limit. 3.2 OFF_B Error Condition 0 Offset error detected 1 No error detected OTP Array Error Detection The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the factory programmed array is locked. The CRC verification uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = `111'. The CRC is continuously calculated on the factory programmable array with the exception of the factory lock bits. Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The calculated CRC is then compared against the stored 3 bit CRC. If a CRC error is detected in the OTP array, the IDEF_B bit is cleared in the SC register. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values. MMA52xxAKW 14 Sensors Freescale Semiconductor, Inc. 3.3 Voltage Regulators The device derives its internal supply voltage from the VCC and VSS pins. Separate internal voltage regulators are used for the analog (VREGA) and digital circuitry (VREG). The analog and digital regulators are supplied by a buffer regulator (VBUF) to provide immunity from EMC and supply dropouts on VCC. External filter capacitors are required, as shown in Figure 1. The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the internal voltages have increased above the undervoltage detection thresholds. The voltage monitor asserts internal reset when the external supply or internally regulated voltages fall below the undervoltage detection thresholds. A reference generator provides a reference voltage for the converter. VCC VREF VBUF VOLTAGE REGULATOR VBUF VREGA = 2.50 V VOLTAGE REGULATOR VREGA TRIM BANDGAP REFERENCE BIAS GENERATOR VREF TRIM TRIM REFERENCE VREF_MOD = 1.250 V GENERATOR VBUF VREF VREGA OSCILLATOR TRIM CONVERTER OTP ARRAY VOLTAGE REGULATOR VREG = 2.50 V VREG DIGITAL LOGIC DSP VCC COMPARATOR Micro-cut VBUF COMPARATOR POR VREG VREGA VREF COMPARATOR COMPARATOR Figure 7. Voltage Regulation and Monitoring MMA52xxAKW Sensors Freescale Semiconductor, Inc. 15 3.3.1 VBUF, VREG, and VREGA Regulator Capacitor The internal regulators require an external capacitor between each of the regulator pins (VBUF, VREG, or VREGA) and the associated the VSS / VSSA pin for stability. Figure 1 shows the recommended types and values for each of these capacitors. 3.3.2 VCC, VBUF, VREG, and VREGA Undervoltage Monitor A circuit is incorporated to monitor the supply voltage (VCC) and all internally regulated voltages (VBUF, VREG, and VREGA). If any of internal regulator voltages fall below the specified undervoltage thresholds in Section 2, the device will be reset. If VCC falls below the specified threshold, PSI5 transmissions are terminated for the present response. Once the supply returns above the threshold, the device will respond to the next detected sync pulse. Reference Figure 8. VCC micro-cut occurs VCC VBUF VCC undervoltage detected VREG VREGA Response Terminated IDATA POR Time Figure 8. VCC Micro-Cut Response MMA52xxAKW 16 Sensors Freescale Semiconductor, Inc. 3.3.3 VBUF, VREG, and VREGA Capacitance Monitor A monitor circuit is incorporated to ensure predictable operation if the connection to the external VBUF, VREG, or VREGA, capacitor becomes open. The VBUF regulator is disabled tCAPTEST_ADLY seconds after each data transmission for a duration of tCAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold, forcing a device reset. The VREG and VREGA regulators are disabled at a continuous rate (tCAPTEST_RATE), for a duration of tCAPTEST_TIME seconds. If either external capacitor is not present, the associated regulator voltage will fall below the internal reset threshold, forcing a device reset. IDATA tCAPTEST_TIME tCAPTEST_ADLY Capacitor Present Capacitor Open CAP_Test VBUF VBUF_UV_f POR Time Figure 9. VBUF Capacitor Monitor - Asynchronous Mode tCAPTEST_RATE tCAPTEST_TIME CAP_Test VREG Capacitor Present Capacitor Open VPORVREG_f POR Time Figure 10. VREG Capacitor Monitor MMA52xxAKW Sensors Freescale Semiconductor, Inc. 17 tCAPTEST_RATE tCAPTEST_TIME CAP_Test VREGA Capacitor Present Capacitor Open VPORREGA_f POR Time Figure 11. VREGA Capacitor Monitor 3.4 Internal Oscillator A factory trimmed oscillator is included as specified in Section 2. 3.5 Acceleration Signal Path 3.5.1 Transducer The transducer is an overdamped mass-spring-damper system defined by the following transfer function: where: 2 n H ( s ) = --------------------------------------------------------2 2 s + 2 n s + n = Damping Ratio n = Natural Frequency = 2 fn Reference Section 2.7 for transducer parameters. 3.5.2 Converter A sigma delta modulator converts the differential capacitance of the transducer to a 1 MHz data stream that is input to the DSP block. g-CELL 1= CTOP VX FIRST INTEGRATOR CINT1 z-1 1-z CBOT SECOND INTEGRATOR 2 1-BIT QUANTIZER z-1 -1 _OUT 1 - z-1 ADC C = CTOP - CBOT V = C x VX / CINT1 1 2 DAC V = 2 x VREF Figure 12. Converter Block Diagram MMA52xxAKW 18 Sensors Freescale Semiconductor, Inc. 3.5.3 Digital Signal Processing Block A Digital Signal Processing (DSP) block is used to perform signal filtering and compensation. A diagram illustrating the signal processing flow within the DSP block is shown in Figure 13. B A _OUT DOWNSAMPLING D C LOW-PASS FILTER SINC FILTER COMPENSATION OFFSET OFFSET CANCELLATION CANCELLATION LOW-PASS FILTER OUTPUT RATE LIMITING E F OUTPUT H G SCALING INTERPOLATION OUTPUT Figure 13. Signal Chain Diagram Table 3. Signal Chain Characteristics A Description Sample Time (s) Data Width (Bits) SD 1 1 Over Range (Bits Signal Width (Bits) Signal Noise (Bits) Signal Margin (Bits) Typical Block Latency 1 Reference Section 3.5.2 203/fosc B SINC Filter 16 20 13 C Low-Pass Filter 16 26 4 10 3 9 D Compensation 16 26 4 10 3 9 E Down Sampling 16 26 4 10 3 9 F High-Pass Filter 16 26 4 10 3 9 Reference Section 3.5.3.2 Section 3.5.3.2 Section 3.5.3.2 68/fosc Reference Section 3.5.3.3 Section 3.5.3.3 DSP Sampling G 16 10 4/fosc Section 3.5.3.5 1 10 64/fosc Section 3.5.3.5 10-Bit Output Scaling H 3.5.3.1 Interpolation Decimation Sinc Filter The serial data stream produced by the converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 16. 3 1 - z -16 H ( z ) = ------------------------------------16 x ( 1 - z - 1 ) MMA52xxAKW Sensors Freescale Semiconductor, Inc. 19 Figure 14. Sinc Filter Response, tS = 16 s MMA52xxAKW 20 Sensors Freescale Semiconductor, Inc. 3.5.3.2 Low-Pass Filter Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter. ( n 11 z 0 ) + ( n 12 z - 1 ) + ( n 13 z - 2 ) ( n 21 z 0 ) + ( n 22 z - 1 ) + ( n 23 z - 2 ) H ( z ) = a 0 ------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------( d 11 z 0 ) + ( d 12 z - 1 ) + ( d 13 z - 2 ) ( d 11 z 0 ) + ( d 22 z - 1 ) + ( d 23 z - 2 ) Table 4. Low-Pass Filter Coefficients Description Filter Coefficients Group Delay a0 5.189235225042199e-02 n11 1.629077582099646e-03 d11 1.0 n12 1.630351547919014e-03 d12 -9.481076477495780e-01 0 d13 0 n21 2.500977520825902e-01 d21 1.0 n22 4.999999235890745e-01 d22 -1.915847097557409e+00 n23 2.499023243303036e-01 d23 9.191065266874253e-01 400 Hz, 3-Pole LPF n13 2816/fosc Note: Low-Pass Filter values do not include g-cell frequency response. MMA52xxAKW Sensors Freescale Semiconductor, Inc. 21 Figure 15. Low-Pass Filter Characteristics: fC = 400 Hz, 3-Pole, tS = 16 s MMA52xxAKW 22 Sensors Freescale Semiconductor, Inc. 3.5.3.3 Offset Cancellation The device provides an offset cancellation circuit to remove internal offset error. A block diagram of the offset cancellation is shown in Figure 16. INPUT DATA INC/DEC OFFSET CANCELLATION LOW-PASS FILTER n + ( n z-1 ) 1 2 a ------------------------------------0 d + ( d z-1 ) 1 2 TO_OUTPUT SCALING OUT COUNTER 0.5 Hz (Derived from fOSC) Input Data downsampled to 256s CLK OFFMONNEG INC/DEC OUT OFF_ERR UP/DOWN COUNTER OFFMONPOS 2 kHz (Derived from fOSC) OFFMONCNTLIMIT CLK Figure 16. Offset Cancellation Block Diagram The transfer function for the offset LPF is: no 1 + ( no 2 z - 1 ) H ( z ) = ao 0 ---------------------------------------------do 1 + ( do 2 z - 1 ) Response parameters are specified in Section 2 and the offset LPF coefficients are specified in Table 6. During startup, two phases of the offset LPF are used to allow for fast convergence of the internal offset error during initialization. The timing and characteristics of each phase are shown in Table 5 and Table 6 and specified in Section 2. For more information regarding the startup timing, reference the PSI5 initialization information in Section 4.4. The offset low-pass filter used in normal operation is selected by the OC_FILT bit as shown in Table 5. During the Initialization Self-Test phase, the offset cancellation circuit output value is frozen. During normal operation, output rate limiting is applied to the output of the high-pass filter. Rate limiting updates the offset cancellation output by OFFStep_xx LSB every tOffRate_xx seconds. Table 5. Offset Cancellation Startup Characteristics and Timing Offset Cancellation Startup Phase Offset LPF Output Rate Limiting Total Time for Phase 1 10 Hz Bypassed 80 ms 2 0.3 Hz Bypassed 70 ms Self-Test 0.3 Hz Bypassed (Frozen during ST2) 96 ms per Self-Test Sequence (up to 6 repeats) Complete 0.1 Hz Enabled N/A MMA52xxAKW Sensors Freescale Semiconductor, Inc. 23 Table 6. High-Pass Filter Coefficients Description 10 Hz HPF 0.3 Hz HPF 0.1 Hz HPF Coefficients Group Delay ao0 0.015956938266754 no1 0.499998132328277 do1 1.0 no2 0.499998132328277 do2 -0.984043061733246 ao0 0.000482380390167 no1 0.499938218213271 do1 1.0 no2 0.499938218213271 do2 -0.999517619609833 ao0 0.0001608133316040 no1 0.4999999403953552 do1 1.0 no2 0.4999999403953552 do2 -0.9998391270637512 16.384 ms 537.6 ms 1591ms Figure 17. 10 Hz Offset Cancellation Low-Pass Filter Characteristics Figure 18. 0.1 Hz Offset Cancellation Low-Pass Filter Characteristics MMA52xxAKW 24 Sensors Freescale Semiconductor, Inc. 3.5.3.4 Offset Monitor The device includes an offset monitor circuit. The output of the single pole low-pass filter in the offset cancellation block is continuously monitored against the offset limits specified in Section 2.4. An up/down counter is employed to count up If the output exceeds the limits, and to count down if the output is within the limits. The output of the counter is compared against the count limit OFFMONCNTLIMIT. If the counter exceeds the limit, the OFF_B flag in the SC register is cleared. The counter rails once the max counter value is reached (OFFMONCNTSIZE). The offset monitor is disabled during Initialization Phase 1, Phase 2, and Phase 3. 3.5.3.5 Data Interpolation The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital signal processing chain is delayed one sample time. 3.5.3.6 Output Scaling The 26-bit digital output from the DSP is clipped and scaled to a 10-bit word which spans the acceleration range of the device. Figure 19 shows the method used to establish the output acceleration data word from the 26-bit DSP output. Over Range D25 D24 D23 10-bit Data Word Signal D22 Noise D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 Margin D9 D8 ... D2 D1 D0 Using Rounding Figure 19. 10-Bit Output Scaling Diagram MMA52xxAKW Sensors Freescale Semiconductor, Inc. 25 3.6 Overload Response 3.6.1 Overload Performance The device is designed to operate within a specified range. Acceleration beyond that range (overload) impacts the output of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the device that is dependent upon the overload frequency and amplitude. The g-cell is overdamped, providing the optimal design for overload performance. However, the performance of the device during an overload condition is affected by many other parameters, including: * g-cell damping * Non-linearity * Clipping limits * Symmetry Figure 20 shows the g-cell, ADC and output clipping of the device over frequency. The relevant parameters are specified in Section 2. g-cellRolloff Acceleration (g) Region Clipped by Output LPFRolloff R eg ion pe Clip d by g-ce ll Determined by g-cell roll-off and ADC clipping e to n du arity o i t r e to in e l Dis on-L lipp igna and N nC S o i f g o Re etr y ion Reg Asymm gg-cell_Clip A d by gADC_Clip DC Determined by g-cell roll-off and full-scale range gRange_Norm Region of Interest fLPF Region of No Signal Distortion Beyond Specification fg-Cell 5kHz 10kHz Frequency (kHz) Figure 20. Output Clipping vs. Frequency 3.6.2 Sigma Delta Modulator Over Range Response Over Range conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits of the DSP. The converter can saturate at levels above those specified in Section 2 (GADC_CLIP). The DSP operates predictably under all cases of over range, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. MMA52xxAKW 26 Sensors Freescale Semiconductor, Inc. 4 PSI5 Layer and Protocol 4.1 Communication Interface Overview The communication interface between a master device and the MMA52xx is established via a PSI5 compatible 2-wire interface. Figure 21 shows the PSI5 master to slave connections. SATELLITE MODULE #1 MASTER DEVICE MMA51xx VCC VSS Discrete Components VCC IData VSS Figure 21. PSI5 Satellite Interface Diagram 4.2 Data Transmission Physical Layer The device uses a two wire interface for both its power supply (VCC), and data transmission. Data transmissions from the device to the PSI5 master are accomplished via modulation of the current on the power supply line. 4.3 Data Transmission Data Link Layer 4.3.1 Bit Encoding The device outputs data by modulation of the VCC current using Manchester 2 Encoding. Data is stored in a transition occurring in the middle of the bit time. The signal idles at the normal quiescent supply current. A logic low is defined as an increase in current at the middle of a bit time. A logic high is defined as a decrease in current at the middle of a bit time. There is always a transition in the middle of the bit time. If consecutive "1" or "0" data are transmitted, There will also be a transition at the start of a bit time. IMOD CURRENT IDLE CURRENT `0' BIT tBIT `1' BIT SENSED HIGH SENSED LOW CONSECUTIVE `0' DATA BITS CONSECUTIVE `1' DATA BITS Figure 22. Manchester 2 Data Bit Encoding MMA52xxAKW Sensors Freescale Semiconductor, Inc. 27 4.3.2 Data Transmission Transmission frames are composed of two start bits, a 10-bit data word, and error detection bit(s). Data words are transmitted least-significant bit (LSB) first. A typical Manchester-encoded transmission frame is illustrated in Figure 23. Data Bit SB1 SB0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 PAR `0' `0' `1' `1' `1' `0' `0' `1' `1' `1' `1' `0' `1' SB1 IMOD Bit Value tBIT tTRAN = tBIT * 13 tFRAME Figure 23. Example Manchester Encoded Data Transfer - PSI5-x10P 4.3.3 Error Detection Error detection of the transmitted data is accomplished via a parity bit. Even parity is employed. The number of logic "1" bits in the transmitted message must be an even number. MMA52xxAKW 28 Sensors Freescale Semiconductor, Inc. 4.3.4 Data Range Values Table 8 shows the details for each data range. Table 7. PSI5 Data Values 10-Bit Data Value Decimal Hex +511 $1FF * * * * * * +502 $1F6 +501 $1F5 +500 $1F4 +499 $1F3 * * * * * * Description Reserved Sensor Defect Error Message Reserved +489 $1E9 +488 $1E8 Sensor Busy +487 $1E7 Sensor Ready +486 $1E6 Sensor Ready, but Unlocked +485 $1E5 * * * * * * +481 $1E1 +480 $1E0 * * * * * * +3 $03 +2 $02 +1 $01 0 0 -1 $3FF -2 $3FE -3 $3FD * * * * * * -480 $220 -481 $21F * * * * -496 $210 -497 $20F * * * * -512 $200 Reserved Maximum positive acceleration value Positive acceleration values 0g level Negative acceleration values Maximum negative acceleration value Initialization Data Codes 10-Bit Status Data Nibble 1 - 16 (0000 - 1111) (Dx) Initialization Data IDs Block ID 1 - 16 (10-bit Mode) (IDx) MMA52xxAKW Sensors Freescale Semiconductor, Inc. 29 4.4 Initialization Following powerup, the device proceeds through an initialization process which is divided into 3 phases: * Initialization Phase 1: No Data transmissions occur * Initialization Phase 2: Sensor self-test and transmission of configuration information * Initialization Phase 3: Transmission of "Sensor Busy", and "Sensor Ready" / "Sensor Defect" message Once initialization is completed the device begins normal mode operation, which continues as long as the supply voltage remains within the specified limits. IIDLE + IMOD IIDLE POR INIT 1 NORMAL MODE INIT 3 INIT 2 Figure 24. PSI5 Sensor 10-Bit Initialization During PSI5 initialization, the device completes an internal initialization process consisting of the following: * Power-on Reset * Device Initialization * Program Mode Entry Verification * Offset Cancellation Initialization (2 Stages) * Self-Test Figure 25 shows the timing for internal and external initialization. POR Internal Delay tINT_INIT PSI5 Initialization Phase 1 PSI5 Initialization Phase 2 tPSI5_INIT1 tPSI5_INIT2 Self-Test Offset Cancellation Offset Cancellation Raw Offset Stage 1 Stage 2 Calculation tOC1 tOC2 tST1 PSI5 PSI5 Initialization Normal Mode Phase 3 tPSI5_INIT3 Self-Test Self-Test Deflection Normal Data Verification Calculation tST2 tST3 Self-Test Repeat (If Necessary) ST_RPT * tST Figure 25. Initialization Timing MMA52xxAKW 30 Sensors Freescale Semiconductor, Inc. 4.4.1 PSI5 Initialization Phase 1 During PSI5 initialization phase 1, the device begins internal initialization and self checks, but transmits no data. Initialization begins with the sequence below and shown in Figure 25: * Internal Delay to ensure analog circuitry has stabilized (tINT_INIT) * Offset Cancellation phase 1 Initialization (tOC1) * Offset Cancellation phase 2 Initialization (tOC2) 4.4.2 PSI5 Initialization Phase 2 During PSI5 initialization phase 2, the device continues its internal self checks and transmits the PSI5 initialization phase 2 data. Initialization is transmitted using the initialization data codes and IDs specified in Table 9, and in the order shown in Figure 26. D1 ID11 D11 ID12 D12 D2 ... ID1k Repeat k times D1k ID21 D21 ID22 D22 ... ID2k D2k Repeat k times ... D32 ... ID321 D321 ID322 D322 ... ... ID32k D32k Repeat k times Figure 26. PSI5 Initialization Phase 2 Data Transmission Order (10-bit Mode) The Initialization phase 2 time is calculated with the following equation: t PHASE2 = TRANS NIBBLE x k x ( DataFields ) x t ASYNC where: * TRANSNIBBLE * k * Data Fields * tS-S = # of Transmissions per Data Nibble 2 for 10-bit Data: 1 for ID, and 1 for Data = the repetition rate for the data fields = 32 data fields for 10-bit data = Sync Pulse Period MMA52xxAKW Sensors Freescale Semiconductor, Inc. 31 4.4.2.1 PSI5 Initialization Phase 2 In PSI5 initialization phase 2, 10-bit mode, the device transmits a sequence of sensor specific configuration and serial number information. The transmission data is in conformance with the PSI5 specification, Revision 1.3, Revision 1.10. The data content and transmission format is shown in Table 8 and Table 9. Times are calculated using the equation in Section 4.4.2. Table 8. Initialization Phase 2 Time Operating Mode Repetition Rate (k) # of Transmissions Nominal Phase 2 Time Asynchronous Mode (228 s) 8 512 116.7 ms Table 9. PSI5 Initialization Phase 2 Data PSI5 V1.2 PSI5 V1.2 Field ID # Nibble ID # Page Address PSI5 Nibble Address Register Address Description Value F1 D1 0000 Hard-coded Protocol Revision = V1.3 0100 F2 D2, D3 0001, 0010 Hard-coded Number of Data Blocks = 32 0010 0000 F3 D4, D5 0100, 0110 MFG_ID[7:0] Manufacturer ID 0100 0110 F4 D6, D7 0101, 0110 Hard-coded Sensor Type = Acceleration (high-g) 0000 0001 D8 0111 Factory Programmed Axis 0000 1000 60g: 0111 120g: 1000 240g: 1001 480g: 1010 Range Varies F5 D9 0 F6 F7 F8 D10 1001 DEVCFG2[7:4] Sensor Specific Information 0000 D11 1010 DEVCFG2[3:0] Sensor Specific Information 0000 D12 1011 Hard-coded Product Revision Factory D13 1100 Hard-coded Product Revision Factory D14 1101 DEVCFG6[3:0] Product Revision 0000 D15 1110 0001 D16 1111 0010 D17 0000 D18 0001 D19 0010 SN0 (High Nibble) MMA52xx Serial Number D20 0011 SN0 (Low Nibble) MMA52xx Serial Number Factory D21 0100 SN1 (High Nibble) MMA52xx Serial Number Factory D22 0101 SN1 (Low Nibble) MMA52xx Serial Number Factory D23 0110 SN2 (High Nibble) MMA52xx Serial Number Factory D24 F9 Factory Programmed 0000 0000 Factory 0111 SN2 (Low Nibble) MMA52xx Serial Number Factory 1000 SN3 (High Nibble) MMA52xx Serial Number Factory D26 1001 SN3 (Low Nibble) MMA52xx Serial Number Factory D27 1010 0000 D28 1011 0000 D29 1100 D25 1 Factory Programmed 0000 D30 1101 D31 1110 0000 0000 D32 1111 0000 MMA52xxAKW 32 Sensors Freescale Semiconductor, Inc. 4.4.3 Internal Self-Test During PSI5 Initialization Phase 2 and Phase 3, the device completes it's internal self-test as described below and shown in Figure 25. * Self-Test Phase 1 - Raw Offset Calculation - The average offset is calculated for tST1 (Self-Test Disabled). * Self-Test Phase 2 - Self-Test Deflection Verification - - - - - The offset cancellation value is frozen for tST2 + 2ms Self-Test is enabled After tST2/2, the acceleration output value is averaged for tST2/2 to determine the self-test value The self-test value is compared against the limits specified in Section 2.5 Self-Test is disabled * Self-Test Phase 3 - Self-Test Normal Data Calculation - The average offset is calculated for tST3 - If Self-Test passed, the device advances to normal mode - If Self-Test failed, the device repeats Self-Test Phases 1 through 3 up to ST_RPT times. 4.4.4 Initialization Phase 3 During PSI5 initialization phase 3, the device completes it's internal self checks, and transmits a combination of "Sensor Busy", "Sensor Ready", or "Sensor Defect" messages as defined in Table 7. Self-Test is repeated on failure up to ST_RPT times to provide immunity to misuse inputs during initialization. Self-Test terminates successfully after one successful self-test sequence. Table 10 shows the nominal Initialization Phase 3 times for self-test repeats. Times are calculated using the following equation. ( t INTINIT + t OC1 + t OC2 + ( t ST1 + t ST2 + t ST3 ) x ( STRPT + 1 ) ) - ( t PSI5INIT1 + t PSI5INIT2xx ) t PSI5INIT3 = ROUNDUP --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 2 x t ASYNC t ASYNC Table 10. Initialization Phase 3 Time Operating Mode 10-Bit Asynchronous Mode 0 (228 s) 4.5 Error Handling 4.5.1 Sensor Defect Message Self-Test Repetitions # of Sensor Busy Messages # of Sensor Ready or Sensor Defect Messages Nominal Phase 3 Time (ms) 0 2 0.91 1 423 96.90 2 844 3 1265 2 192.89 288.88 4 1686 384.86 5 2107 480.85 The following failures will cause the device to transmit a "Sensor Defect" error message: 4.5.2 Error Condition Error Type Offset Error Temporary (Normal transmissions continue once offset returns within limits) Self-Test Failure Latched until reset IDEN_B, IDEF_B flag cleared Latched until reset No Response Error The following failures will cause the device to stop transmitting: Error Condition Error Type Undervoltage Failure (VCC) Temporary: Normal transmissions continue once voltage returns above failure limit) MMA52xxAKW Sensors Freescale Semiconductor, Inc. 33 5 Package 5.1 Case Outline Drawing Reference Freescale Case Outline Drawing # 98ASA00090D http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf 5.2 Recommended Footprint Reference Freescale Application Note AN3111, latest revision: http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf Table 11. Revision History Revision number Revision date 0 09/2012 Description of changes * Initial release. MMA52xxAKW 34 Sensors Freescale Semiconductor, Inc. How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits based on the Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm. Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) 2012 Freescale Semiconductor, Inc. Document Number: MMA52xxAKW Rev. 0 09/2012