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© 2005 Fairchild Semiconductor Corporation DS500442 www.fairchildsemi.com
Februa ry 200 1
Revised May 2005
74LCX162374 Low Volt age 16-Bit D-Type Flip-Flop wit h 5V Tolerant Inputs and Outputs and 26: Series Resistors
74LCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 5V Tolerant Input s and Outputs
and 26: Series Resistor s
General Descript ion
The LCX162374 contains sixteen non-inverting D-type
flip-flops with 3- STATE outp uts and is intende d for bus ori -
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The LCX16 2374 i s designed for low vol tage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment. The 26
:
series resistor in the output helps
reduce output overshoot and undershoot.
The LCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
■5V tolerant inputs and outputs
■2.3V–3.6V VCC specifications provided
■Equivalent 26
:
series resistor on outputs
■7.0 ns tPD max (VCC
3.3V), 20
P
A ICC max
■Power down high impedance inputs and outputs
■Supports live insertion/withdrawal (Note 1)
■
r
12 mA output drive (VCC
3.0V)
■Latch-up per for man c e exce eds 500 mA
■ESD performa nce :
Human body model
!
2000V
Machine model
!
200V
■Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC t hrough a p ull-up re sistor: th e minimu m value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Note 2: BGA package av ailable in Tape and Ree l only.
Note 3: Devices al so av ailable in Tape and Reel. Specify by appending t he suffix letter “X” to th e ordering co de.
Logic Symbol
Order Number Package Number Package Description
74LCX162374GX
(Note 2) BGA54A
(Preliminary) 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LCX162374MEA
(Note 3) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX162374MTD
(Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
■Implements proprietary noise/EMI reduction circuitry
www.fairchildsemi.com 2
74LCX162374
Connection Diagrams
Pin Assignment for SSO P and TSSOP
Pin Assignment for FB GA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
HIGH Volt age Level
L
LOW Voltage Le ve l
X
Immaterial
Z
High Impedance
O0
Previ ous O0 bef ore HIGH-to-LOW of CP
Pin Names Description
OEnOutput Enable Input (Active LOW)
CPnClock Pulse Input
I0–I15 Inputs
O0–O15 Outputs
NC No Connect
123456
AO0NC OE1CP1NC I0
BO2O1NC NC I1I2
CO4O3VCC VCC I3I4
DO6O5GND GND I5I6
EO8O7GND GND I7I8
FO10 O9GND GND I9I10
GO12 O11 VCC VCC I11 I12
HO14 O13 NC NC I13 I14
JO15 NC OE2CP2NC I15
Inputs Outputs
CP1OE1I0–I7O0–O7
LH H
LL L
LL X O
0
XH X Z
Inputs Outputs
CP2OE2I8–I15 O8–O15
LH H
LL L
LL X O
0
XH X Z
3 www.fairchildsemi.com
74LCX162374
Functional Description
The LCX162374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The dev ice is byte con trolled wi th each byte fun c-
tioning identically, but independent of the other. The control
pins can b e sho rte d t oge the r to obtain ful l 1 6-b i t o per atio n.
Eac h by t e h a s a bu ffered cl oc k a nd bu ffered O ut p ut En ab le
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the con-
tents of the flip-flops are available at the outputs. When
OEn is HIG H, the outputs go to the high imped ance state.
Operation of the OEn input d oes not affect the stat e of the
flip-flops.
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagatio n delays.
www.fairchildsemi.com 4
74LCX162374
Absolute Maximum Ratings(No t e 4)
Recommended Operating Conditions (Note 6)
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ra tings. The “Recom-
mend ed Operat ing Conditions” table will def ine the condit ions for actual device op eration.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
Symbol Parameter Value Conditions Units
VCC Supply Vo ltag e
0.5 to
7.0 V
VIDC Input Voltage
0.5 to
7.0 V
VODC Output Voltage
0.5 to
7.0 3-STATE V
0.5 to VCC
0.5 Output in HIGH or LOW State (Note 5)
IIK DC Input Diode Current
50 VI
GND mA
IOK DC Output Diode Current
50 VO
GND mA
50 VO
!
VCC
IODC Output Source/Sink Current
r
50 mA
ICC DC Supply Current per Supply Pin
r
100 mA
IGND DC Ground Current per Gr ound Pin
r
100 mA
TSTG Storage Tem per atu re
65 to
150
q
C
Symbol Parameter Min Max Units
VCC Supply Voltage Operating 2.0 3.6 V
Data Retention 1.5 3.6
VIInput Vo l tage 05.5 V
VOOutput Voltage HIGH or LOW State 0 VCC V
3-STATE 0 5.5
IOH/IOL Output Current VCC
3.0V
3.6V
r
12 mAVCC
2.7V
3.0V
r
8
VCC
2.3V
2.7V
r
4
TAFree-Air Operating Temperature
40 85
q
C
'
t/
'
V Input Edge Rate, VIN
0.8V–2.0V, VCC
3.0V 0 10 ns/V
Symbol Parameter Conditions VCC TA
40
q
C to
85
q
CUnits
(V) Min Max
VIH HIGH Level Input Vo ltage 2.3
2.7 1.7 V
2.7
3.6 2.0
VIL LOW Level Inpu t Voltage 2.3
2.7 0.7 V
2.7
3.6 0.8
VOH HIGH Level Output Voltage IOH
100
P
A2.3
3.6 VCC
0.2
V
IOH
4 mA 2.3 1.8
IOH
4 mA 2.7 2.2
IOH
6 mA 3.0 2.4
IOH
8 mA 2.7 2.0
IOH
12 mA 3.0 2.0
VOL LOW Level Output Voltage IOL
100
P
A2.3
3.6 0.2
V
IOL
4 mA 2.3 0.6
IOL
4 mA 2.7 0.4
IOL
6 mA 3.0 0.55
IOL
8 mA 2.7 0.6
IOL
12 mA 3.0 0.8
IIInput Leakage Current 0
d
VI
d
5.5V 2.3
3.6
r
5.0
P
A
IOZ 3-STATE Output Leakage 0
d
VO
d
5.5V 2.3
3.6
r
5.0
P
A
VI
VIH or VIL
5 www.fairchildsemi.com
74LCX162374
DC Electrical Characteristics (Continued)
Note 7: Outputs disabled or 3-STAT E only.
AC Electrical Characteristics
Note 8: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (t OSLH). Pa r am eter guar anteed by de s ign.
Dynamic Switching Characteristics
Capacitance
Symbol Parameter Conditions VCC TA
40
q
C to
85
q
CUnits
(V) Min Max
IOFF Power-Off Leakage Current VI or VO
5.5V 0 10
P
A
ICC Quiescent Supply Current VI
VCC or GND 2.3
3.6 20
P
A
3.6V
d
VI, VO
d
5.5V (Note 7) 2.3
3.6
r
20
'
ICC Increase in ICC per Input VIH
VCC
0.6V 2.3
3.6 500
P
A
Symbol Parameter
TA
40
q
to
85
q
C, RL
500
:
Units
VCC
3.3V
r
0.3V VCC
2.7V VCC
2.5V
r
0.2V
CL
50 pF CL
50 pF CL
30 pF
Min Max Min Max Min Max
fMAX Maximum Clock Frequency 170 MHz
tPHL Propagation Delay 1.5 7.0 1.5 7.3 1 .5 8.4 ns
tPLH CP to On1.5 7.0 1.5 7.3 1.5 8.4
tPZL Output Enable time 1.5 6.9 1.5 7.1 1.5 9.0 ns
tPZH 1.5 6.9 1.5 7.1 1.5 9.0
tPLZ Output Disable Time 1.5 6.0 1.5 6.2 1.5 7.2 ns
tPHZ 1.5 6.0 1.5 6.2 1.5 7.2
tSSetup Time 2.5 2.5 3.0 ns
tHHold Time 1.5 1.5 2.0 ns
tWPulse Width 3.0 3.0 3.5 ns
tOSHL Output to Output Skew (Note 8) 1.0 ns
tOSLH 1.0
Symbol Parameter Conditions VCC TA
25
q
CUnits
(V) Typical
VOLP Quiet Output Dynamic Peak VOL CL
50 pF, VIH
3.3V, VIL
0V 3.3 0.35 V
CL
30 pF, VIH
2.5V, VIL
0V 2.5 0.25
VOLV Quiet Output Dynamic Valley VOL CL
50 pF, VIH
3.3V, VIL
0V 3.3
0.35 V
CL
30 pF, VIH
2.5V, VIL
0V 2.5
0.25
Symbol Parameter Conditions Typical Units
CIN Input Capacitance VCC
Open, VI
0V or VCC 7pF
COUT Output Capacitance VCC
3.3V, VI
0V or VCC 8pF
CPD Power Dissipation Capacitance VCC
3.3V, VI
0V or VCC, f
10 M Hz 20 pF
www.fairchildsemi.com 6
74LCX162374
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig cap acitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and trec Waveforms
3-STA TE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3n s)
Test Switch
tPLH, tPHL Open
tPZL, tPLZ 6V at VCC
3.3
r
0.3V, and 2.7V
VCC x 2 at VCC
2.5
r
0.2V
tPZH, tPHZ GND
Symbol VCC
3.3V
r
0.3V 2.7V 2.5V
r
0.2V
Vmi 1.5V 1.5V VCC/2
Vmo 1.5V 1.5V VCC/2
VxVOL
0.3V VOL
0.3V VOL
0.15V
VyVOH
0.3V VOH
0.3V VOH
0.15V
7 www.fairchildsemi.com
74LCX162374
Schematic Diagram Ge neric for LCX Family
www.fairchildsemi.com 8
74LCX162374
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Packag e Num b er BGA5 4A
Preliminary
9 www.fairchildsemi.com
74LCX162374
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
www.fairchildsemi.com 10
74LCX162374 Low Volt age 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26: Series Resistors
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent i n any compon ent of a lif e supp ort
device or system whose failure to perform can be rea-
sonabl y ex pect ed to cause the fa ilu re of the lif e su pp ort
device or system, or to affect it s safety or effectiveness.
www.fairchildsemi.com
www.onsemi.com
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regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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