LT8316
1
Rev. 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
600VIN Micropower No-Opto
Isolated Flyback Controller
The LT
®
8316 is a micropower, high voltage flyback con-
troller. No opto-isolator is needed for regulation. The
device samples the output voltage from the isolated fly-
back waveform appearing across a third winding on the
transformer. Quasi-resonant boundary mode operation
improves load regulation, reduces transformer size, and
maintains high efficiency.
At start-up, the LT8316 charges its INTVCC capacitor via
a high voltage current source. During normal operation,
the current source turns off and the device draws its
power from a third winding on the transformer minimiz-
ing standby power dissipation.
The LT8316 operates from a wide range of input supply
voltages and can deliver up to 100W of power. It is avail-
able in a thermally enhanced 20-pin TSSOP package with
four pins removed for high-voltage spacing.
16VIN to 600VIN Isolated 12VOUT Supply
APPLICATIONS
n Wide Input Voltage Range: 16V to 600V
n No Opto-Isolator Required for Regulation
n Quasi-Resonant Boundary Mode Operation
n Constant-Current and Constant-Voltage Regulation
n Low-Ripple Light Load Burst Mode
®
Operation
n Low Quiescent Current: 75μA
n Programmable Current Limit and Soft-Start
n TSSOP Package with High-Voltage Spacing
n Isolated Telecom, Automotive, Industrial, Medical
Power Supplies
n Isolated Off-Line Housekeeping Power Supplies
n Electric Vehicles and Battery Stacks
n Multioutput Isolated Power Supplies for Inverter Gate
Drives
All registered trademarks and trademarks are the property of their respective owners.
Efficiency
4.7µF
100nF
47pF
4.7µF
1300µF
540µH
8.44µH
8.44µH
44.2k
4.99k
108k
20k
40mΩ
61.9k
M1
DCM
V
IN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SENSE
TC
V
C
BIAS
GATE
LT8316
V
IN
16V TO 600V
V
OUT
+
V
OUT
–
8:1:1
12V
30mA TO 800mA (V
IN
= 20V)
30mA TO 3A (V
IN
= 80V)
50mA TO 4A (V
IN
= 160V TO 600V)
8316 TA01a
VIN = 20V
VIN = 80V
VIN = 160V
VIN = 320V
VIN = 600V
LOAD CURRENT (A)
0
1
2
3
4
5
6
70
75
80
85
90
95
EFFICIENCY (%)
8316 TA01b
LT8316
2
Rev. 0
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN ..........................................................................600V
BIAS, EN/UVLO .........................................................40V
INTVCC ......................................................................15V
SMODE, GATE ..................................................... INTVCC
SENSE, TC, FB, VC, IREG/SS .......................................4V
DCM ...................................................................±100mA
Operating Junction Temperature (Note 2)
LT8316E, LT8316I .............................. −40°C to 125°C
Storage Temperature Range .................. −65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................... 300°C
(Note 1)
FE PACKAGE
20(16)-LEAD PLASTIC TSSOP
θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
20 GND
19 GATE
18 SENSE
17 EN/UVLO
16 SMODE
15 GND
14 IREG/SS
13 VC
12 FB
11 TC
VIN 1
VIN 2
VIN 3
INTVCC 8
BIAS 9
DCM 10
21
GND
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8316EFE#PBF LT8316EFE#TRPBF LT8316FE 20-Lead Plastic TSSOP –40°C to 125°C
LT8316IFE#PBF LT8316IFE#TRPBF LT8316FE 20-Lead Plastic TSSOP –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LT8316
3
Rev. 0
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. BIAS = 30V, VEN/UVLO = 30V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
BIAS Chip Bias Voltage Supply Range After Startup 9.5 V
IQBIAS Quiescent Current Burst Mode Operation
Active
75
470
150
700
μA
ICLAMP(MAX) BIAS Clamp Maximum Current 15 mA
VCLAMP BIAS Clamping Voltage ICLAMP = 200µA
ICLAMP = 15mA
34
35
38
39
V
V
ISHDN VIN Shutdown Current VEN/UVLO < 0.3V, BIAS = Floating 12 20 μA
VIN(MIN) Minimum Input Voltage for Startup BIAS = Floating l16 V
ISTARTUP Startup Current Out of INTVCC VIN = 16V, BIAS = Floating l100 300 μA
VUVLO EN/UVLO Threshold
EN/UVLO Hysteresis
VEN/UVLO Falling
VEN/UVLO Rising
1.18
30
1.22
65
1.26
120
V
mV
INTVCC UVLO Rising Threshold Startup Current through Depletion FET 11.1 12 13.1 V
INTVCC UVLO Falling Threshold 7.6 8.1 8.6 V
INTVCC Regulation Voltage Drawing 20mA from INTVCC 9.5 10 10.5 V
INTVCC LDO Dropout Voltage Drawing 20mA from INTVCC 1 V
Gate Driver Rise Time CGATE = 3.3nF, 10% to 90% 30 ns
Gate Driver Fall Time CGATE = 3.3nF, 90% to 10% 8 ns
VREG FB Regulation Voltage l1.18 1.22 1.25 V
GMVoltage Error Amplifier Transconductance VFB = 1.22V ± 5mV 245 350 455 μS
VTC TC Voltage
TC Voltage Temperature Coefficient
TA = 25°C 1.22
+4.1
V
mV/°C
ITC TC Sinking/Sourcing Current ±100 μA
IIREG/SS IREG/SS Current Current Out-of-Pin 9.7 10 10.3 μA
IDCM Flyback Collapse Detection Threshold
Resonant Valley Detection Threshold
IDCM Rising
IDCM Falling
−170
−85
μA
μA
VSENSE(MIN) Minimum Current Voltage Threshold 14 20 26 mV
VSENSE(MAX) Maximum Current Voltage Threshold 90 100 110 mV
SENSE Input Bias Current Current Out-of-Pin 35 µA
FSW(MIN) Minimum Switching Frequency Burst Mode
Standby Mode
3
187
3.5
220
4
250
kHz
Hz
FSW(MAX) Maximum Switching Frequency 138 140 142 kHz
Note 2: The LT8316E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the −40°C
to 125°C operating junction temperature range are assured by design
characterization and correlation with statistical process controls. The
LT8316I is guaranteed over the full −40°C to 125°C operating junction
temperature range. High junction temperatures degrade operating
lifetimes. Operating lifetime is derated at junction temperatures greater
than 125°C.
LT8316
4
Rev. 0
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TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency Boundary Mode Waveforms
Discontinuous Mode Waveforms Burst Mode Waveforms
Load and Line Regulation Output Voltage vs Temperature CV/CC Operation
TA = 25°C, unless otherwise noted.
FRONT PAGE APPLICATION
LOAD CURRENT (A)
0
1
2
3
4
5
6
11.4
11.6
11.8
12.0
12.2
12.4
12.6
OUTPUT VOLTAGE (V)
8316 G01
VIN = 20V
VIN = 80V
VIN = 160V
VIN = 320V
VIN = 600V
FRONT PAGE APPLICATION
V
IN
= 320V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
11.8
11.9
12.0
12.1
12.2
OUTPUT VOLTAGE (V)
8316 G02
IOUT = 100mA
IOUT = 1A
IOUT = 4A
V
IN
= 320V
R
IREG/SS
= 61.9kΩ
FRONT PAGE APPLICATION
LOAD CURRENT (A)
0
1
2
3
4
5
6
0
3
6
9
12
15
OUTPUT VOLTAGE (V)
8316 G03
FRONT PAGE APPLICATION
VIN = 20V
VIN = 80V
VIN = 160V
VIN = 320V
VIN = 600V
LOAD CURRENT (A)
0
1
2
3
4
5
6
0
20
40
60
80
100
FREQUENCY (kHz)
8316 G04
FRONT PAGE APPLICATION
V
IN
= 320V, I
OUT
= 4A
5µs/DIV
V
SENSE
100mV/DIV
V
OUT
AC COUPLED
50mV/DIV
V
SW
200V/DIV
8316 G05
FRONT PAGE APPLICATION
V
IN
= 320V, I
OUT
= 2A
5µs/DIV
V
SENSE
100mV/DIV
V
OUT
AC COUPLED
50mV/DIV
V
SW
200V/DIV
8316 G06
FRONT PAGE APPLICATION
V
IN
= 320V, I
OUT
= 30mA
100µs/DIV
V
SENSE
100mV/DIV
V
OUT
AC COUPLED
50mV/DIV
V
SW
200V/DIV
8316 G07
LT8316
5
Rev. 0
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TYPICAL PERFORMANCE CHARACTERISTICS
ULVO Threshold FB Regulation Voltage TC Pin Voltage
VIN Pin Shutdown Current BIAS Pin Quiescent Current Depletion Startup Current
Load Transient Response Startup Waveforms
TA = 25°C, unless otherwise noted.
EN/UVLO Rising
EN/UVLO Falling
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.15
1.20
1.25
1.30
1.35
ENABLE THRESHOLD (V)
8316 G13
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
1.200
1.205
1.210
1.215
1.220
1.225
1.230
1.235
1.240
FB REGULATION VOLTAGE (V)
8316 G14
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.80
1.00
1.20
1.40
1.60
1.80
TC VOLTAGE (V)
8316 G15
10ms/DIV
I
OUT
2A/DIV
V
OUT
AC COUPLED
200mV/DIV
8316 G08
FRONT PAGE APPLICATION
V
IN
= 320V, R
OUT
= 3Ω
50ms/DIV
V
IN
320V/DIV
V
INTVCC
10V/DIV
V
BIAS
10V/DIV
V
OUT
10V/DIV
8316 G09
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
15
30
45
60
SHUTDOWN CURRENT (μA)
8316 G10
VIN = 100V
VIN = 600V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
40
80
120
160
QUIESCENT CURRENT (μA)
8316 G11
V
INTVCC
(V)
0
3
6
9
12
15
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
I
INTVCC
(mA)
8316 G12
150°C
25°C
–55°C
LT8316
6
Rev. 0
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TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Switch-On Time Minimum Switch-Off Time DCM Pin Threshold
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
50
100
150
200
250
300
350
400
MINIMUM ON TIME (ns)
8316 G19
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
500
550
600
650
700
750
800
850
900
OFF TIME (ns)
8316 G20
RESONANT VALLEY DETECT
FLYBACK COLLAPSE DETECT
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
–220
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
DCM CURRENT (µA)
8315 G21
IREG/SS Pin Current Switching Frequency Limit Switch Current Limit
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
9.5
9.6
9.7
9.8
9.9
10.0
10.1
10.2
10.3
10.4
10.5
IREG/SS CURRENT (μA)
8316 G16
MAXIMUM SWITCHING FREQUENCY
MINIMUM SWITCHING FREQUENCY
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
1
2
3
4
5
125
130
135
140
145
150
FREQUENCY (kHz)
8316 G17
MAXIMUM CURRENT LIMIT
MINIMUM CURRENT LIMIT
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0
5
10
15
20
25
85
90
95
100
105
110
SENSE VOLTAGE (mV)
8316 G18
LT8316
7
Rev. 0
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PIN FUNCTIONS
VIN (Pins 1, 2, 3): Drain of the 600V Internal Startup
FET. During startup, an internal depletion MOSFET draws
power from this pin to charge the INTVCC capacitor.
INTVCC (Pin 8): Internal Gate Driver Bias Voltage. During
start-up, current from the VIN pin charges this pin to 12V.
During operation, a linear regulator from BIAS maintains
this voltage at 10V. Bypass locally with a ≥2.2μF ceramic
≥15V rated capacitor.
BIAS (Pin 9): Unregulated Input Voltage for the IC. This
pin derives power from a third winding on the trans-
former to provide power to INTVCC. Bypass locally with
a ≥100nFcapacitor.
DCM (Pin 10): Discontinuous Conduction Mode Detector.
This pin detects the dV/dt of the switching waveform,
ensuring accurate output voltage sampling and quasi-
resonant boundary-mode switching. Connect a capacitor
with series resistance from this pin to the third winding.
See Boundary Mode Detection section.
TC (Pin 11): Temperature Compensation Pin. This pin
presents a proportional-to-absolute-temperature (PTAT)
voltage, which is equal to the internal 1.22V reference
voltage at 25°C and rises with temperature by 4.1mV/°C,
to compensate for the output rectifier diode. Connect an
appropriate resistor from this pin to FB.
FB (Pin 12): Feedback Pin. The voltage appearing on this
pin is sampled and regulated to equal the internal 1.22V
reference voltage. Connect this pin to a resistor divider
from the third winding to regulate the output voltage.
VC (Pin 13): Loop Compensation Pin. An internal GM
transconductance amplifier feeds this pin with an error
current depending on the sampled FB voltage. The
resulting voltage determines the switching frequency
and peak current limit for power delivery. Connect a
series R-C network to stabilize the regulator. See Loop
Compensationsection.
IREG/SS (Pin 14): Current Regulation/Soft-Start Pin. A
10μA current flows out of this pin. The resulting voltage
sets the output current regulation point, as determined by
an internal current regulation loop. Program the current
with a resistor to GND, or connect a capacitor to imple-
ment soft-start.
SMODE (Pin 16): Standby Mode Pin. Connect this pin to
INTVCC to enable Standby Mode, which reduces the mini-
mum switching frequency to 220Hz for ultralow quiescent
power consumption. Connect to GND to disable.
EN/UVLO (Pin 17): Enable/Undervoltage Lockout Pin. The
chip will operate only if the voltage on this pin is greater
than the internal 1.22V reference voltage. Connect to a
resistor divider as desired, or connect to BIAS or INTVCC
if UVLO functionality is not desired.
SENSE (Pin 18): Current Sense Pin. The voltage appear-
ing on this pin is used for peak current-mode control and
current limiting. Connect a current-sensing resistor from
the main power MOSFET to GND to program the current
limit. Utilize a compact layout with the transformer and
input capacitor to reduce EMI and voltage spikes.
GATE (Pin 19): Gate Driver Output. Connect this pin to the
gate of the main power MOSFET for the flyback converter.
GND (Pins 15, 20, 21): Ground. Solder the exposed pad
(Pin 21) to a ground plane for heat sinking.
LT8316
8
Rev. 0
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BLOCK DIAGRAM
8316 BD
–
+
+
–10V
LDO
BIAS/REF
CONTROL
TSD
INTVCC
BIAS
EN/UVLO
SMODE
9
8
17
16
DCM
10
FB
12
RDCM
RFB2
CDCM
CDRV
CBIAS 36V
DBIAS
BOUNDARY
DETECT
S&H
×1
TC
11 ×1
•
RFB1
LTER
:N
TS
RTC
+
–
GM
VOLTAGE
ERROR AMP
+4.1mV/°C
1.22V
VOLTAGE
CONTROLLED
OSCILLATOR
–
+
S
Q
R
DRIVER
MASTER
LATCH
600V
DEPLETION
FET
CURRENT
COMPARATOR
+
–
CURRENT
ERROR AMP
×10
13 14
10µA
1.25×(1–D)
RIREG
IREG/SSVC
RC
CC
M2
VIN
1, 2, 3
M1
RSNS
15, 20, 21
GND
SENSE 18
GATE 19
•
•
ZSNUB
LSEC
LPRI COUT
NPS :1
D
OUT
VOUT
+
VOUT
–
DSNUB
CIN
VIN
VUVLO
LT8316
9
Rev. 0
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OPERATION
The LT8316 is a high-voltage current-mode switching
controller designed for the isolated flyback topology. The
problem normally encountered in such circuits is that
information relating to the output voltage on the isolated
secondary side of the transformer must be communicated
to the primary side in order to achieve regulation. This is
often performed by opto-isolator circuits, which waste
output power, require extra components that increase the
cost and physical size of the power supply, and exhibit
trouble due to limited dynamic response, nonlinearity,
unit-to-unit variation, and aging over their life.
The LT8316 does not need an opto-isolator because it
derives information about the isolated output voltage by
examining the flyback pulse waveform appearing on a
tertiary winding on the transformer. The output voltage is
easily programmed with two resistors.
The LT8316 features a boundary mode control method
(also called critical conduction mode), where the part
operates at the boundary between continuous conduc-
tion mode and discontinuous conduction mode. Due
to boundary mode operation, the output voltage can be
determined from the tertiary winding’s voltage when the
secondary current is almost zero. This method improves
load regulation without extra resistors and capacitors.
The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in traditional
switching regulators, including a current comparator,
internal reference, LDO, logic, timers and a MOSFET gate
driver. The novel sections include a special sampling error
amplifier, a temperature compensation circuit, an output
current regulator, and a depletion-mode startup FET.
Depletion Startup FET
The LT8316 features an internal depletion mode MOSFET.
At startup, this transistor charges the INTVCC capacitor
so that the LT8316 has power to begin switching. This
removes the need for an external bleeder resistor or other
components.
Boundary Mode Operation
Boundary mode is a variable frequency, current-mode
switching scheme. The external N-channel MOSFET turns
on and the inductor current increases until it reaches the
limit determined by the voltage on the VC pin and the
sense resistor’s value. After the MOSFET turns off, the
voltage on the tertiary winding rises to the output voltage
multiplied by the transformer tertiary-to-secondary turns
ratio. After the current through the output diode falls to
zero, the voltage on the tertiary winding falls. A boundary
mode detection comparator on the DCM pin detects the
negative dV/dt associated with the falling voltage and trig-
gers the sample-and-hold circuit to sample the FB voltage.
When the tertiary voltage reaches its minimum and stops
falling, the boundary mode comparator turns the internal
MOSFET back on for minimal switching energy loss.
Boundary mode operation returns the secondary current
to zero every cycle, so parasitic resistive voltage drops
do not cause load regulation errors. Boundary mode also
allows the use of a smaller transformer compared to con-
tinuous conduction mode and does not exhibit subhar-
monic oscillation.
Discontinuous Conduction Mode Operation
As the load gets lighter, the peak switch current decreases.
Maintaining boundary mode requires the switching fre-
quency to increase. An excessive switching frequency
increases switching and gate charge losses. To limit these
losses, the LT8316 features an internal oscillator which
limits the maximum switching frequency to 140kHz. Once
the switching frequency hits this limit, the part starts to
reduce its switching frequency and operates in discon-
tinuous conduction mode.
Low Ripple Burst Mode Operation
Unlike traditional flyback converters, the MOSFET has
to turn on and off to generate a flyback pulse in order
to update the sampled output voltage. The duration of a
well-formed flyback pulse must exceed the minimum-off
time for proper sampling. To this end, a minimum switch
turn-off current is necessary to ensure a flyback pulse of
sufficient duration.
LT8316
10
Rev. 0
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APPLICATIONS INFORMATION
OPERATION
As the load gets very light, the LT8316 reduces switching
frequency while maintaining the minimum current limit in
order to reduce current delivery while still properly sam-
pling the output voltage. Because flyback pulses must be
generated to regulate the output, a minimum switching
frequency of 3.5kHz is enforced. The minimum switch-
ing frequency determines how often the output voltage is
sampled and introduces a minimum load requirement of
approximately 1% of the maximum load power.
Tying the SMODE pin to INTVCC enables Standby Mode,
which reduces the minimum switching frequency to
220Hz, reducing the minimum load requirement at the
expense of a longer period between samples.
CV/CC Regulation
Like a traditional voltage regulator, the LT8316 implements
a G
M
transconductance amplifier that regulates the output
voltage. In addition, the LT8316 includes a current
regulation loop which regulates the estimated output
current to a point set by the voltage on the IREG/SS pin.
Below the current setpoint, the output voltage is regulated
for constant-voltage (CV) regulation. Below the voltage
setpoint, the the output current is regulated for constant-
current (CC) regulation.
The LT8316 is designed to be an easy-to-use, yet fully-
featured flyback controller. With proper technique, it is
simple to build an efficient and robust power solution.
However, the voltage and power levels involved can be
lethal. Milliamperes from a high voltage power supply
can cause heart fibrillation and death. Never touch con-
ductive nodes while the circuit is active, and keep one
hand behind your back while probing.
Depletion Startup FET
The LT8316 features an internal depletion-mode FET,
which has a negative threshold voltage and is therefore
normally on. At startup, this FET charges the INTVCC
capacitor to 12V so that the LT8316 has power to begin
switching. This removes the need for an external bleeder
resistor or other startup components. Once INTVCC is
charged, the depletion-mode FET turns off.
The depletion FET is current-limited to avoid destructive
power levels. To ensure start-up, do not load INTVCC or
BIAS with excessive current while the chip is starting.
ENABLE and Undervoltage Lockout (UVLO)
A resistive divider from VIN to the EN/UVLO pin imple-
ments undervoltage lockout (UVLO). The EN/UVLO pin
threshold is set at 1.22V. Upon startup, the EN/UVLO
pin exhibits a ~65mV hysteresis voltage to prevent
oscillations.
The EN/UVLO pin can also be driven with logic levels and
set by the output pin of a digital controller. Otherwise,
EN/UVLO can also be tied to BIAS or INTVCC to keep the
chip enabled.
Output Voltage
The output voltage is programmed by the RFB1 and RFB2
resistors depicted in the Block Diagram. The LT8316
operates similarly to traditional current-mode switchers,
except in its use of a unique sample-and-hold error ampli-
fier, which regulates the isolated output voltage from the
sampled flyback pulse.
Operation is as follows: when the power switch M1 turns
off, the voltage across the tertiary winding rises. The
amplitude of the flyback pulse is given as:
VFLBK = (VOUT + VF + ISEC • ESR) • NTS,
LT8316
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APPLICATIONS INFORMATION
where
VF = Output diode (DOUT) forward-biased voltage
ISEC = Transformer secondary current
ESR = Parasitic resistance of secondary circuit
NTS = Transformer tertiary-to-secondary turns ratio
The voltage divider formed by RFB1 and RFB2 feeds a
scaled version of the flyback pulse to the FB pin, where
it is sampled and fed to the error amplifier. Because the
sample-and-hold circuit samples the voltage when the
secondary current is nearly zero, the (ISEC • ESR) term in
the VFLBK equation can be ignored.
The internal 1.22V reference voltage feeds the non-invert-
ing input of the error amplifier. The high gain of the overall
loop causes the FB voltage to be nearly equal to the refer-
ence voltage. The resulting flyback voltage VFLBK can be
expressed as:
VFLBK =1+RFB2
R
FB1
⎛
⎝
⎜
⎞
⎠
⎟• 1.22V
Combining with the previous VFLBK equation and solving
for VOUT yields:
VOUT =1+RFB2
R
FB1
⎛
⎝
⎜
⎞
⎠
⎟•1.22V
N
TS
−VF
Due to the fast nature of the flyback pulse, it is recom-
mended to keep RFB1 between 1kΩ and 10kΩ in order to
preserve the resistor divider’s dynamic response.
Selecting the RFB2 Resistor Value
The LT8316 uses a unique sampling scheme to regulate
the isolated output voltage. Due to its sampling nature,
the scheme exhibits repeatable delays and error sources,
which will affect the output voltage and force a re-evalu-
ation of the resistor values.
With a fixed value for RFB1 (such as 10kΩ) chosen, rear-
rangement of the expression for VOUT yields the starting
value for RFB2:
RFB2 =RFB1 •VOUT +VF
1.22V • NTS −1
⎛
⎝
⎜⎞
⎠
⎟
where
VOUT = Desired output voltage
VF = Output diode (DOUT) forward voltage ≈ 300mV
NTS = Transformer tertiary-to-secondary turns ratio
Power up the application with the final power components
installed and the starting RFB2 value, and measure the
regulated output voltage, V
OUT(MEAS)
. The final R
FB2
value
can be adjusted to:
RFB2(FINAL) ≈RFB2 +RFB1
( )
•VOUT
VOUT(MEAS)
−RFB
1
Once the final RFB2 value is selected, the regulation accu-
racy from board to board for a given application will be
very consistent, typically within ±5% when including
device variation of all the components in the system
(assuming resistor tolerances and transformer windings
matching within ±1%). However, if the transformer or
the output diode is changed, or the layout is dramatically
altered, there may be some change in VOUT.
Example: Consider a 12V output supply with an output
diode whose forward voltage at nearly zero current is
300mV at room temperature. If the tertiary-to-secondary
ratio NTS is 1 and RFB1 is 10kΩ, then RFB2 is calculated
as 90.9kΩ. The application is powered up and the output
is slightly high at 12.2V, so RFB2 is adjusted to 88.7kΩ.
Output Diode Temperature Compensation
Reiterating the equation for VOUT,
VOUT =1+RFB2
R
FB2
⎛
⎝
⎜
⎞
⎠
⎟•1.22V
N
TS
−VF
The first term in the VOUT equation is insensitive to tem-
perature, but the output diode forward voltage VF has
a significant negative temperature coefficient (from
−1mV/°C to −2mV/°C). Such a temperature coefficient
produces approximately 200mV to 400mV output voltage
variation across operating temperature.
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At higher output voltages, the resulting variation may
be unimportant as it represents a small fraction of the
total output. However, for lower output voltages, the
diode temperature coefficient accounts for a large output
voltageerror.
To correct this error, the TC pin provides a buffered
proportional-to-absolute-temperature (PTAT) voltage. At
room temperature, this voltage is equal to the internal
1.22V reference, and it has a +4.1mV/°C temperature
coefficient.
The output diode’s temperature coefficient TCF can easily
be found experimentally by applying a uniform tempera-
ture to both the output diode and the LT8316. First, RFB1
and RFB2 are adjusted to give the desired output voltage
at room temperature. The temperature is then raised or
lowered by a known amount to a new temperature, and
the diode temperature coefficient is found as:
TCF=VOUT(25°C) −VOUT(TNEW)
T
NEW
−25°C
where
VOUT(25°C) = VOUT measured at room temperature
VOUT(TNEW) = VOUT measured at new temperature
TNEW = New temperature in Celsius
Alternatively, TCF can be found more accurately by
measuring VOUT at two extremes of temperature and
computing:
TCF=–ΔVOUT
ΔT
It should be noted that for this measurement, it is critical
that the entire board be heated or cooled uniformly, for
example by an oven. A heat gun or freeze spray will not
suffice, since the heating and cooling will not be uniform,
and dramatic temperature mismatch between the LT8316
and the output diode will cause significant error.
If no method is available to apply uniform heat or cooling,
extrapolating data from the diode’s data sheet or assum-
ing a nominal TCF value (such as −1.5mV/°C) may yield
a satisfactory result.
With the output diode’s temperature coefficient known,
a resistor RTC is then attached from the TC pin to the FB
pin. Its value can be calculated as:
RTC =−RFB2 • 4.1mV / °C
TC
F
• N
TS
Example: If the output diode’s temperature coefficient TCF
is found experimentally to be –1.9mV/°C, then with RFB2
= 88.7kΩ, a RTC value of 191kΩ will yield a temperature-
invariant output voltage.
Sense Resistor Selection
The resistor RSNS between the power MOSFET and GND
should be selected to provide an adequate switch current
to drive the application without exceeding the current limit
threshold.
At maximum current delivery, current limit occurs when
the SENSE pin voltage is 100mV. In boundary mode, the
maximum output current will depend on the duty cycle D
and is given by:
IOUT(MAX) ≈100mV
2 • R
SNS
• 1−D
( )
• NPS
where
NPS = Transformer primary-to-secondary turns ratio
D≈VOUT +VF
( )
• NPS
V
OUT
+V
F
( )
• N
PS
+V
IN
VIN = Power supply voltage.
It should be noted that the worst-case occurs at minimum
VIN, so DVIN(MIN) should be calculated assuming VIN =
VIN(MIN). Solving for the sense resistor value:
RSNS =1−DVIN(MIN)
I
OUT(MAX)
• 50mV • NPS • 80%
A factor of 80% is introduced to compensate for system
delays and tolerances, but it may need adjustment for the
final application.
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Example: A 12V output voltage is generated from a
VIN=400V input that can drop as low as VIN(MIN)=250V.
If a transformer with primary-to-secondary turns ratio
NPS=10 is selected to supply a maximum output current
I
OUT(MAX)
=2A, then the duty cycle is D
VIN(MIN)
≈33% and
the sense resistor is calculated R
SNS
=133mΩ. A 120mΩ
resistor is selected.
A more accurate value for R
SNS
can be obtained by finding
D experimentally with an oscilloscope and electronic load.
Output Power
Compared with a buck or a boost converter, a flyback con-
verter has a complicated relationship between the input
and output currents. Boost converters have relatively con-
stant maximum input current regardless of input voltage,
while buck converters have relatively constant maximum
output current regardless of input voltage, owing to the
fact that they have continuous input and output currents
respectively. A flyback converter, however, has both dis-
continuous input and output currents. The duty cycle
affects both input and output currents, making it hard to
predict maximum output power.
The following equation calculates output power:
POUT = 0.5 • η • VIN • D • ISW(MAX)
where
η = Efficiency ≈ 80%
D≈VOUT +VF
( )
• NPS
V
OUT
+V
F
( )
• N
PS
+V
IN
ISW(MAX) = Max. switch current limit = 100mV/RSNS
The calculated power is approximate, and does not take
into account timing variations caused by circuit parasitics.
The actual output power must be evaluated on the bench.
Example: Consider a 12V output converter with a VIN(MIN)
of 250V and a VIN(MAX) of 500V. With a ten-to-one primary-
to-secondary winding ratio (NPS=10) and a sense resis-
tor RSNS=120mΩ, the maximum power output is 33W
at VIN(MAX)=500V but lowers to 28W at VIN(MIN)=250V.
Selecting a Transformer
Transformer specification and design is possibly the
most critical part of successfully applying the LT8316. In
addition to the usual list of guidelines dealing with high-
frequency isolated power supply transformer design, the
following information should be carefully considered.
Analog Devices has worked with several leading magnetic
component manufacturers to produce pre-designed fly-
back transformers for use with the LT8316. Table1 shows
the details of these transformers.
Table1. Predesigned Transformers — Typical Specifications
TRANSFORMER PART
NUMBER
LPRI
(µH) NP:NS:NTISOLATION VENDOR TARGET APPLICATIONS
11328-T078 670 8:1:1 Reinforced Sumida 100V–600V to 12V/3A
11328-T080 670 4:1:0.5 Reinforced Sumida 100V–600V to 24V/1.5A
11328-T073 670 2:1:0.25 Reinforced Sumida 100V–600V to 54V/0.7A
11328-T061 600 5:1:1 Basic Sumida 200V–450V to 15V/2A
11338-T195 1000 14:1:1.7 Basic Sumida 100V–400V to 7V/2A
11328-T074 500 8:1:1 Reinforced Sumida 100V–450V to 12V/3A
15364-T008 1500 20:1:2.4 Reinforced Sumida 25V–450V to 5V/1A
11328-T086 70 4:1:0.5 Reinforced Sumida 30V–260V to 24V/3A
00399-T239 2800 6:1:0.7 Functional Sumida 90V–500V to 16.8V/0.4A
750317463 440 8:1:1 Reinforced Wurth Elektronik 100V–600V to 12V/4A
750317589 670 8:1:1 Reinforced Wurth Elektronik 100V–600V to 12V/3A
750317464 440 4:1:0.5 Reinforced Wurth Elektronik 100V–600V to 24V/2A
11328-T060 800 18:1:3 Reinforced Sumida 140V–450V to 5V/7A
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Flyback Transformer Modeling
A flyback transformer can be thought of as an ideal trans-
former with a parallel magnetizing inductance and series
leakage inductances, as shown in Figure1.
The magnetizing inductance, which is the mutual induc-
tance shared by both primary and secondary windings,
is essential for absorbing energy and delivering it to the
load. It stores energy in magnetic flux lines that pass
through both primary and secondary windings.
If the leakage inductances are small, the magnetizing
inductance can be measured by leaving the secondary
open-circuited and measuring the inductance of the pri-
mary, resulting in an inductance L
PRI
. The magnetizing
inductance can also be measured from the secondary by
leaving the primary open-circuited and measuring the
secondary inductance LSEC. The relationship between the
primary-referred magnetizing inductance and secondary-
referred magnetizing inductance is given by the primary-
to-secondary turns ratio NPS as:
LPRI = LSEC • NPS2
The transformer also has leakage inductances, which
are parasitic inductances associated with each winding.
These inductances store energy in magnetic flux lines
which “leak” out of the magnetic core and do not pass
through both windings, and therefore represent self-
inductances whose energy cannot be transferred through
the transformer. As such, they contribute to energy loss
and reduced converter efficiency.
If the leakage inductances are small, the combined leak-
age inductance can be measured by short-circuiting the
secondary and measuring the primary inductance. This
results in a primary-referred inductance,
LLEAK = LLEAK(PRI) + LLEAK(SEC) • NPS2
Figure1. Transformer Model
8316 F01
LPRI
L
LEAK(PRI)
L
LEAK(SEC)
NPS:1
IDEAL
The leakage inductance and magnetizing inductance are
related by the coupling coefficient k according to the
relation:
k=LPRI
L
PRI
+L
LEAK
/ 2
Coupling coefficients of k=99% are common, and are
a function of transformer construction and materials.
Increased voltage isolation between primary and sec-
ondary is often desired for safety purposes, but gener-
ally reduces the coupling coefficient and increases leak-
age inductance. Bifilar windings maximize the coupling
coefficient, but are often undesirable because of their
minimal isolation and increased primary-to-secondary
capacitance. In the end, a reasonable trade-off between
isolation and coupling coefficient must be made.
Magnetizing Inductance Requirement
The appropriate magnetizing inductance depends on the
LT8316’s minimum switch-on time, its minimum switch-
off time, and output power.
The conduction of secondary current reflects the output
voltage onto the tertiary winding during the flyback pulse.
The LT8316 obtains output voltage information from the
reflected output voltage on the FB pin. The sample-and-
hold error amplifier needs a minimum of 800ns to set-
tle and sample the reflected output voltage. In order to
ensure proper sampling, the secondary winding needs to
conduct current for at least 800ns.
The minimum value for primary-side magnetizing induc-
tance is given by:
LPRI ≥tOFF(MIN) • NPS • VOUT +VF
( )
ISW(MIN)
where
tOFF(MIN) = Minimum switch-off time = 800ns
I
SW(MIN)
= Minimum switch current limit = 20mV/R
SNS
The LT8316 has a minimum switch-on time that prevents
the chip from turning on the power switch for a period
shorter than 300ns in order to blank the initial switch
LT8316
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turn-on current spike. If the inductor current exceeds the
minimum switch current limit during that time, the mini-
mum load current will increase. Therefore, the following
equation must also be observed:
LPRI ≥tON(MIN) • VIN(MAX)
ISW(MIN)
where
tON(MIN) = Minimum Switch-On Time = 300ns
Additionally, the magnetizing inductance must be large
enough to provide sufficient power to the output when the
LT8316 operates at maximum frequency. This creates a
third requirement for magnetizing inductance:
LPRI ≥2 • (VOUT +VF) • IOUT(MAX)
η• ISW(MAX)2• fSW(MAX)
where
ISW(MAX) = Maximum switch current = 100mV/RSNS
IOUT(MAX) = Maximum load current
fSW(MAX) = Maximum switching frequency = 140kHz
η = Efficiency ≈ 80%
In general, choose a transformer with its primary mag-
netizing inductance about 20% to 50% larger than the
minimum values calculated above.
In addition to these minimum values, the magnetizing
inductance has a maximum value. To avoid a stuck out-
put-low state, the LT8316 has a 50μs backup timer that
turns the switch on if the secondary diode turn-off has
not been detected. As a result, the magnetizing inductance
must not be so large as to cause secondary diode conduc-
tion to exceed this time. This creates a final requirement
for maximum magnetizing inductance:
LPRI <
0.8 • V
OUT
+V
F
( )
•N
PS
• t
BU
ISW MAX
( )
where
tBU = Backup time = 50μs
Example: For a 12V/2A output converter with
VIN(MAX)=500V, VF=300mV, NPS = 10, and
RSNS=120mΩ, the first equation requires LPRI ≥ 590μH,
the second equation requires LPRI ≥ 900μH, and the third
equation requires LPRI ≥ 633μH. A reasonable standard
value for primary inductance is LPRI=1.2mH. If a larger
minimum load at high VIN can be tolerated, 820μH is
acceptable. The fourth equation dictates that LPRI must
be less than 5.9mH; this requirement is easily satisfied
by both options.
Saturation Current
The current in the transformer windings should not
exceed its rated saturation current. Beyond its saturation
value, the inductance drops and the current rises to an
uncontrolled value, causing extra power dissipation and
possible failure. Choose a transformer whose primary
saturation current is at least 30% greater than ISW(MAX),
which is 100mV/RSNS.
Turns Ratios
Typically, choose the transformer primary-to-secondary
turns ratio NPS to maximize available output power. For
low output voltages, a larger N
PS
ratio can be used to
maximize the transformer’s current gain. However,
remember that the MOSFET’s drain sees a voltage that
is equal to VIN plus the output voltage multiplied by NPS.
Additionally, leakage inductance will cause a voltage spike
(VLEAKAGE) that adds to this reflected voltage. This total
quantity needs to remain below the absolute maximum
rating of the MOSFET’s drain to prevent breakdown.
Together these conditions place an upper limit on the
turns ratio N
PS
for a given application. Choose a turns
ratio low enough to ensure:
NPS <VBR −VIN(MAX) −VLEAKAGE
V
OUT
+V
F
where
VBR = MOSFET breakdown voltage.
For producing high output voltages, a low ratio NPS may
be used. However, the multiplied capacitance presented to
the transformer primary may cause ringing that exceeds
LT8316
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the 300ns tON(MIN), causing light-load instability. Fully
evaluate these applications before use with the LT8316.
During operation, the LT8316 derives its power from a
tertiary winding through its BIAS pin. BIAS must be main-
tained between 10V and 30V for proper operation. This
dictates a tertiary-to-secondary turns ratio NTS of:
10V
V
OUT
<NTS <30V
V
OUT
Example: For VOUT = 12V, NTS must lie between 0.83
and 2.5, or a 5:6 and 5:2 tertiary-to-secondary ratio
respectively.
Due to leakage inductance ringing on the tertiary winding,
BIAS will rise above its nominal value. To prevent BIAS pin
breakdown, an internal clamp circuit activates at 36V and
shunts the excess current to ground. This current must
not exceed 15mA; evaluate at maximum load current and
minimum VIN to verify proper operation.
Because the output voltage is measured through the volt-
age appearing on the third winding, NTS directly affects
the output voltage regulation accuracy. For best results,
make sure the transformer is manufactured with a precise
turns ratio specified within ±1%.
Leakage Inductance and Snubbers
Any leakage inductance on either the primary or secondary
windings causes a voltage spike to appear on the primary
after the power switch turns off. This spike is increasingly
prominent at higher load currents where more energy is
stored in the leakage inductance. This energy cannot be
delivered to the load, and must be dissipated as heat. It
is thus very important to minimize transformer leakage
inductance.
When designing an application, adequate margin should
be kept for the worst-case leakage voltage spikes even
under overload conditions. In most cases, the reflected
output voltage on the primary plus VIN should be kept
below 80% of VBR, as shown in Figure2. This leaves 20%
margin for the leakage spike across line and load condi-
tions. A larger voltage margin will be required for poorly
wound transformers with excessive leakage inductance.
In addition to the voltage spikes, the leakage inductance
also causes the switching node to ring for a while after
the power switch turns off. To prevent the voltage ring-
ing from falsely triggering the boundary mode detector,
the LT8316 internally blanks the boundary mode detector
for 800ns. Any ringing after 800ns may trigger the power
switch to turn back on again before the secondary current
falls to zero, so the leakage inductance spike and associ-
ated ringing should be limited to less than 800ns.
Figure2. Maximum Voltages for SW Pin Flyback Waveform
8316 F02
V
SW
tOFF > 800ns
VLEAKAGE
V
SW
V
SW
TIME
No Snubber with DZ Snubber with RC Snubber
tOFF > 800ns
VLEAKAGE
TIME
tOFF > 800ns
VLEAKAGE
TIME
<VBR
<0.8
VBR
<VBR
<0.8VBR
<VBR
<0.8VBR
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Figure3. Snubber Circuits
A snubber circuit is recommended for most applications.
Figure3 shows two types of snubber circuits that can
protect the internal power switch: the DZ (diode-Zener)
snubber and the RC (resistor-capacitor) snubber. The DZ
snubber ensures a well-defined and consistent clamping
voltage and has slightly higher power efficiency, while
the RC snubber quickly damps the voltage spike ringing
and provides better load regulation and EMI performance.
Figure2 shows the flyback waveforms with the DZ and
RC snubbers.
For the DZ snubber, proper care must be taken when
choosing both the diode and the Zener diode. Choose
a fast-recovery diode that has a reverse-voltage rating
higher than the maximum DRAIN pin voltage.
The Zener diode breakdown voltage should be chosen to
balance power loss and switch voltage protection. The
best compromise is to choose the largest voltage break-
down. Use the following equation to make the proper
choice:
VZENER(MAX) ≤ VBR – VIN(MAX)
Multiple Zener diodes may be placed in series to attain
the required voltage and power dissipation.
The Zener diode must be rated to absorb the power loss
in the clamp, which is due to energy storage in the leak-
age inductance and the primary-to-secondary commuta-
tion time, which decreases with higher clamp voltage.
A 500mW Zener is typically recommended. Design the
metal of the VIN trace for sufficient heat removal.
For the RC snubber, the recommended design approach
is to power up at low voltage to avoid overvoltage stress,
measure the period of the ringing on the MOSFET’s drain
when the power switch turns off without the snubber
(TRING), and then add capacitance CSNUBBER (starting with
100pF) until the period of the ringing is 1.5 to 2 times lon-
ger (T
RING(SNUBBED)
). The change in period will determine
the value of the parasitic capacitance CSW, from which
the parasitic inductance LLEAK can also be determined,
according to the equations:
CSW =
C
SNUBBER
T
RING(SNUBBED)
T
RING
⎛
⎝
⎜⎞
⎠
⎟
2
−1
LLEAK =T
RING
2π
⎛
⎝
⎜⎞
⎠
⎟
2
•1
C
SW
With the value of the switching node capacitance and leak-
age inductance known, a resistor can be added in series
with the snubber capacitor to dissipate power and criti-
cally dampen the ringing. The equation for deriving the
optimal series resistance is:
RSNUBBER =LLEAK
CSW
Energy absorbed by the RC snubber will be converted to
heat and will not be delivered to the load. In high power
applications, the snubber resistor may need to be sized
for thermal dissipation.
8316 F03
DZ Snubber RC Snubber
L
ℓ
Z
D
C
R
•
•
L
ℓ
•
•
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Note that the switching node capacitance is sometimes
dominated by transformer interwinding capacitance. Also
note that oscilloscope probes present considerable load-
ing capacitance. Use of low-capacitance, high-voltage
100× probes is recommended.
Leakage Inductance and Output Diode Stress
The output diode may also see increased reverse voltage
stresses from leakage inductance. While it nominally sees
a reverse voltage of the input voltage divided by NPS plus
the output voltage when the MOSFET power switch turns
on, the capacitance on the output diode and the leakage
inductance form an LC tank which may ring beyond that
expected reverse voltage. A snubber or clamp may be
implemented to reduce the voltage spike if it is desired
to use a lower reverse voltage diode.
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider that effectively reduces the size of the tertiary-
referred flyback pulse used for voltage feedback. This
will increase the output voltage by a similar percentage.
Note that, unlike leakage spike behavior, this phenom-
enon is load independent. To the extent that the secondary
leakage inductance is a constant percentage of mutual
inductance (over manufacturing variations), this can be
accommodated by adjusting the RFB2/RFB1 resistor ratio.
Winding Resistance
Resistance in either the primary or secondary will reduce
conversion efficiency. Good output voltage regulation
will be maintained despite winding resistance due to the
boundary/discontinuous conduction mode operation of
the LT8316.
Boundary Mode Detection
Boundary mode is a variable frequency switching scheme
that always returns the secondary current to zero with
every cycle.
The DCM pin uses a fast, current-input comparator in
combination with a small capacitor CDCM to detect when
the flyback waveform’s dV/dt is negative, indicating that
the secondary diode has turned off and the flyback pulse
on the tertiary winding is falling. To avoid false tripping
due to leakage inductance ringing, a blanking time of
800ns is applied after the switch turns off. The detector
triggers when CDCM draws 170μA of current out of the
DCM pin. This information is used to set the timing of
the FB sample-and-hold and estimate the output current.
This is not the best time to turn the switch on because the
MOSFET’s drain voltage is still nearly VIN + (VOUT•NPS),
and turning the switch on would waste all the energy
stored in the parasitic capacitance on the switching node.
When the secondary current reaches zero, discontinuous
ringing begins and the energy in the parasitic capacitance
on the switch node resonates with the transformer’s mag-
netizing inductance, delivering this energy back to VIN.
The minimum voltage of the switching node during this
discontinuous ring is VIN – (VOUT • NPS). This is the opti-
mal moment to turn the switch back on, and the LT8316
does this by sensing when current drawn out of DCM falls
to 85μA. This switching technique increases efficiency by
up to 5%.
Typical CDCM values range from 10pF to 100pF. A good
starting value is 47pF. If the LT8316 is observed not to
run in boundary mode, then increasing this capacitor will
help. An unnecessarily large CDCM value can cause pre-
mature switch turn-on and increased power loss.
Excessive current delivered to the DCM pin can cause
erratic behavior. To avoid this, a resistor RDCM can be
added in series with CDCM to limit the current. Typical
values range from 5kΩ to 50kΩ.
Output Capacitor Selection
The output capacitor should be chosen to minimize the
output voltage ripple while considering the increase in
size and cost of a larger capacitor. The following equa-
tion provides an estimate of the maximum output voltage
ripple at steady-state:
VRIPPLE ≈LPRI •ILIM2
2 •C
OUT
• V
OUT
where
ILIM=Maximum primary current = 100mV/RSNS
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This is a simplified equation; the actual ripple will depend
on load current, duty cycle and capacitor ESR.
The LT8316 samples the output voltage only when
switching. As a result, when it is operating at its minimum
frequency, a load transient may discharge the output
capacitor before the device can respond. The output
capacitor must be sufficient to prevent the load from
brown-out in this event. Additional bulk capacitance may
be desirable for this purpose.
Operation Under Light Output Loads
The LT8316 detects the output voltage from the flyback
pulse appearing on the tertiary winding, which requires
delivering power to the output. Thus, the LT8316 deliv-
ers a minimum amount of energy even during light load
conditions to ensure accurate output voltage information.
The minimum operating frequency at minimum load is
approximately 3.5kHz. The minimum delivery of energy
creates a minimum load requirement on the output of
approximately 1% of the maximum load power.
A Zener diode sufficiently rated to handle the minimum
load power can be used to provide a minimum load with-
out decreasing efficiency in normal operation. In selecting
a Zener diode for this purpose, the Zener voltage should
be high enough that the diode does not become the load
path during transient conditions but the voltage must still
be low enough that the MOSFET and output voltage rat-
ings are not exceeded when the Zener functions as the
minimum load.
Standby Mode Operation
For extremely low no-load power dissipation, the LT8316
features a standby mode which is enabled by tying the
SMODE pin to INTVCC. When the load current has dropped
to zero, the LT8316 reduces its minimum switching fre-
quency by a factor of 16 from 3.5kHz to 220Hz.
This reduces the minimum load current by a factor of16,
at the cost of slower transient response. Because the
output voltage is sampled only once every 4.6ms, the
LT8316 will be unable to respond to load steps for up to
this period.
Output Current Regulation and Soft-Start
Using duty cycle information and the current limit set by
the VC pin, the LT8316 estimates the output current and
regulates it to a setpoint determined by the voltage on the
IREG/SS pin. The output current is regulated according
to the equation:
IOUT =NPS • VIREG/SS
25 • R
SNS
where
VIREG/SS = Voltage on IREG/SS pin.
A trimmed 10μA current flows out of the IREG/SS pin,
so that a resistor tied from this pin to GND programs the
output current according to the equation:
RIREG/SS =2.5MΩ• IOUT • RSNS
N
PS
Example: For an application with RSNS=120mΩ, NPS=10,
and a desired regulated output current IOUT=2A, an
IREG/SS resistor is selected RIREG/SS=60.4kΩ.
Circuit parasitics, especially transformer capacitance, will
influence the accuracy of output current regulation due to
energy delivery to the parasitics. Although this effect is
usually small, some iteration may be necessary if accu-
racy better than 5% is required. In this case, R
IREG/SS
can be implemented with a rheostat and adjusted until
the desired output current is realized, and then replaced
with a fixed-value resistor for production. When the
rheostat is present, a small bypass capacitor is helpful to
attenuate switching interference pickup by the rheostat.
Additionally, an RC snubber placed across the secondary
rectifier can improve current regulation accuracy.
Soft-start functionality can also be implemented by con-
necting a capacitor from the IREG/SS pin to GND. The
10μA current will act to charge the external soft-start
capacitor. At startup, the regulated output current will rise
monotonically until reaching voltage regulation. The soft-
start capacitor then charges entirely and the output current
regulation loop will not interfere with voltageregulation.
LT8316
20
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
In order to avoid an undervoltage condition which causes
the chip to shut down, the combined capacitance on the
INTV
CC
and BIAS pins must be sufficient to power the
LT8316 until the output achieves regulation.
If power at VIN is removed, over-temperature protection
is engaged, undervoltage lockout trips, or overcurrent in
the sense resistor is detected, a 20Ω pull-down switch to
GND discharges any capacitance on the IREG/SS pin for
the duration of the fault plus 640μs.
Protection from Shorted Output Conditions
During a shorted output condition, the LT8316 operates
at the minimum operating frequency. In normal operation,
the tertiary winding provides power to the IC, but the
tertiary winding voltage collapses during a shorted condi-
tion. This causes the part’s INTV
CC
UVLO of 8.1V (typical)
to shutdown switching and charge through the depletion
startup current source. The part starts switching again
when INTVCC has reached its turn-on voltage of 12V.
To protect the output diode from excessive power dis-
sipation during overload conditions, it is advised to
program the regulated output current with a resistor
RIREG/SS. For voltage regulators, the programmed cur-
rent should be 120% to 150% of the maximum load cur-
rent to ensure current regulation does not interfere with
voltageregulation.
Loop Compensation
The LT8316 is compensated using an external resistor-
capacitor network on the VC pin. Typical values are in the
range of RC = 20kΩ and CC = 220nF. If too large an RC
value is used, the part will be more susceptible to high fre-
quency noise and jitter. If too small of an RC value is used,
the transient performance will suffer. The value choice for
C
C
is somewhat the inverse of the R
C
choice: if too small a
CC value is used, the loop may be unstable and if too large
a CC value is used, the transient performance will suffer.
Transient response may be evaluated with a load step box
and adjusted with an adjustable RC compensation net-
work. Stability should be confirmed over the full range of
load current and input voltage.
Extending Supply Voltage
The LT8316 is rated to operate from a VIN up to 600V.
Operation from a higher supply voltage is made possible
by placing a Zener diode in series with the VIN pin, as
shown in Figure4. The voltage dropped across the Zener
diode reduces the voltage applied to the chip, allowing the
supply voltage to exceed 600V.
For example, a 600V Zener diode will, in principle, allow
a supply voltage ranging from 616V to 1200V. It should
be noted that 616V is needed only during start-up; after
start-up, the LT8316 will continue to operate through
transient dips in supply voltage. In practice, the input
voltage range must be adjusted according to the Zener
diode’s voltage tolerance.
Figure4.
V
IN
LT8316
8316 F04
VSUPPLY
Increased Supply Voltage with a Zener Diode
LT8316
21
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure5. 94% Efficient Isolated 54V Supply
D1
D2
D4
D3
4.7µF
100nF
47pF
4.7µF
1µF
22µF
63V
670µH
10.5µH
168µH
10k
49.9k
4.99k
549k
10k
50mΩ
56.2k
STD6N90K5
DCM
V
IN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SENSE
TC
V
C
BIAS
GATE
LT8316
100Ω
1nF
10Ω
20Ω
V
IN
20V TO 600V
V
OUT
+
V
OUT
–
T1
54V
3mA TO 200mA (VIN = 20V)
4mA TO 400mA (VIN = 50V)
8mA TO 700mA (VIN = 100V TO 600V)
8316 F05
T1: SUMIDA 11328-T073
D1: BAV20WS-7-F
D2: PDU340
D3: SMBJ188A
D4: US1MFA
8:4:1
4.7µF
100V
X7S
LT8316
22
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure6. 91% Efficient Isolated 5V/7A Synchronous Flyback Converter
D1
D5
D4
4.7µF
330nF
47pF
4.7µF
4.7µF
1500µF
6.3V
810µH
22.5µH
2.5µH
10k
61.9k
4.99k
42.2k
10k
62mΩ
68.1k
M2
DCM
V
IN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SENSE
TC
V
C
BIAS
GATE
LT8316
100Ω
1nF
M1
3.32k
120pF
4.7µF
3Ω
1µF
INTV
CC
GATE
DRAIN
GND
V
CC
LT8309
D2
D3
100Ω
10Ω
729k
6.98k
D6
V
IN
140V TO
450V
V
OUT
+
V
OUT
–
18:1:3
5V
70mA TO 7A
T1
T1: SUMIDA 11328-T060
M1: BSC052N08NS5
M2: IPD80R450P7
D1, D2: BAV21WS-7-F
D3: IN4148
D4: SMAJ200A
D5: CMMR1U-08
D6: CMHZ5258B
8316 F06
100µF
10V
X5R/X7R
x3
LT8316
23
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure7. Ultra-Wide Input Range Non-Isolated 12V Buck Converter
Figure8. Non-Isolated 16.8V Gate Drive Supply
D3
10µF
100nF
10pF
0.1µF
47µF
16V
X5R/X7R
x3
10k
21.5k
2.49k
22.1k
220mΩ
M1
L1
1mH
D2
100nF
D1
DCM
V
IN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SENSE
TC
V
C
BIAS
GATE
LT8316
V
IN
19V TO 600V
V
OUT
12V
10mA TO 200mA
8316 F07
M1: TK3P80E
L1: SUMIDA RPT129NP-102MB
D1, D3: US1KFA
D2: CMDSH2-3
D2
D1
4.7µF
330nF
47pF
4.7µF
1\0µF
50V
X5R/X7R
x4
2.8mH
77.8µH
10k
4.99k
10k
220mΩ
48.7k
M1
DCM
V
IN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SENSE
TC
V
C
BIAS
GATE
LT8316
100Ω
1nF
130k
V
IN
20V TO 500V
V
OUT
6:1
16.8V/0.42A
T1
8316 F08
D3
100Ω
M1: IPD80R4K5P7
T1: SUMIDA 00399-T239
D1: PDS4150H
D2: BAV20WS-7-F
D3: CMZ5932
0.47µF
0.12A (VIN = 20V)
0.25A (VIN = 50V)
0.42A (VIN = 100V TO 500V)
LT8316
24
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure9. Nonisolated 24V Buck Converter with Optional Undervoltage Lockout
D4
10µF
100nF
10pF
10k
46.4k
R4
2.49k
22.1k
220mΩ
M1
L1
1.5mH
D2
100nF
D1
DCM
V
IN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SENSE
TC
V
C
BIAS
GATE
LT8316
10µF
42.2k
1M
10nF
D3
0.1µF
V
IN
36V TO 600V
V
OUT
24V
10mA TO 200mA
8316 F09
M1: TK3P80E
L1: SUMIDA RPT129NP-152MB
D1, D3, D4: US1KFA
D2: CMDSH2-3
Optional UVLO Circuit
10µF
50V
X5R
x3
LT8316
25
Rev. 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
FE20(16) (BB) TSSOP REV Ø 1014
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 8 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
1.78
(.070)
1.78
(.070)
REF
20 19
0.2
18 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
1.78
(.070)
4.83
(.1902)
0.48
(.019)
REF
0.42
(.016)
REF
0.45 ±0.05
0.65 BSC
5.00
±0.10
6.60
±0.10
0.80 ±0.10
0.42
5.68
(.224)
REF
5.68
(.224)
REF
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
Variation: FE20(16)
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1990 Rev Ø)
Exposed Pad Variation BB
0.22
LT8316
26
Rev. 0
For more information www.analog.com
ANALOG DEVICES, INC. 2019
03/19
www.analog.com
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D1
D2
D4
D3
4.7µF
220nF
47pF
4.7µF
670µH
10.5µH
42µH
10k
44.2k
4.99k
249k
10k
50mΩ
56.2k
DCM
V
IN
EN/UVLO
FB
GND
INTV
CC
IREG/SS
SMODE
SENSE
TC
V
C
BIAS
GATE
LT8316
100Ω
1nF
10Ω
20Ω
STD6N90K5
1µF
100µF
35V
V
IN
20V TO 600V
V
OUT
+
V
OUT
–
T1
24V/1.5A
8316 TA03
6mA TO 400mA (VIN = 20V)
7mA TO 900mA (VIN = 50V)
20mA TO 1.5A (VIN = 100V TO 600V)
T1: SUMIDA 11328-T080
D1: BAV20WS-7-F0
D2: PDS4200H-13
D3: SMBJ188A
D4: US1MFA
8:2:1
10µF
50V
X5R/X7R
x2