Advanced Communication Devices Corp ADVANCE INFORMATION Data Sheet: ACD82224 ACD82224 24 Ports 10/100 Fast Ethernet Switch Last Update: September 19, 2000 Please check ACD' s website for update information before starting a design Web site: http://www.acdcorp.com or Contact ACD at: Email: support@acdcorp.com Tel: 510-354-6810 Fax:510-354-6834 ACD Confidential Material Use under Non-Disclosure Agreement only. No reproduction or redistribution without ACD's prior permission. CONTENT LIST 1. GENERAL DESCRIPTION ............................................................................................................. 3 2. MAJOR FEATURES........................................................................................................................ 5 3. SYSTEM BLOCK DIAGRAM......................................................................................................... 5 4. SYSTEM DESCRIPTION................................................................................................................ 6 MACs, RMII & MII Interfaces ......................................................................................................... 6 Queue Manager ................................................................................................................................ 6 Built-in ARL & External-ARL Interface.......................................................................................... 6 Register & UART Interface .............................................................................................................. 7 External-MIB & External-MIB Interface .......................................................................................... 7 5. FUNCTIONAL DESCRIPTION....................................................................................................... 8 Frame Format................................................................................................................................... 8 Start of Frame Detection................................................................................................................... 8 Frame Reception............................................................................................................................... 8 Preamble Bit Processing ................................................................................................................... 9 Destination Address Processing ........................................................................................................ 9 Source Address Processing ............................................................................................................... 9 Frame Data....................................................................................................................................... 9 FCS Calculation ............................................................................................................................... 9 Illegal Frame Length & Extra-long Frame...................................................................................... 10 Frame Filtering............................................................................................................................... 10 Jabber Lockup Protection................................................................................................................ 10 Excessive Collision......................................................................................................................... 10 Frame Forwarding.......................................................................................................................... 11 Frame Transmission ....................................................................................................................... 11 Shared Buffer ................................................................................................................................. 11 Starvation Control Scheme ............................................................................................................. 12 Flow Control Scheme ..................................................................................................................... 13 Port-based VLAN Support (Registers 23 & 24).............................................................................. 13 Port Trunking................................................................................................................................. 14 Dumping Port................................................................................................................................. 14 Spanning Tree Support ................................................................................................................... 15 Queue Management........................................................................................................................ 15 PHY Management .......................................................................................................................... 15 PHY Interface................................................................................................................................. 15 SRAM Interface.............................................................................................................................. 16 CPU Interface................................................................................................................................. 16 ARL Interface................................................................................................................................. 16 MIB Interface ................................................................................................................................. 16 LED Interface................................................................................................................................. 16 Life Pulse ....................................................................................................................................... 17 6. INTERFACE DESCRIPTION ........................................................................................................ 18 RMII Interface (RMII).................................................................................................................... 19 PHY Management Interface............................................................................................................ 19 CPU Interface................................................................................................................................. 20 SRAM Interface.............................................................................................................................. 21 ARL & MIB Interfaces ................................................................................................................... 22 LED Interface................................................................................................................................. 23 Configuration Interface................................................................................................................... 25 Other Interface ............................................................................................................................... 26 7. REGISTER DESCRIPTION........................................................................................................... 27 INTSRC register (register 1)........................................................................................................... 28 Page 1 of 77 Confidential Page 1 SYSERR register (register 2) .......................................................................................................... 29 PAR register (register 3)................................................................................................................. 29 PMERR register (register 4) ........................................................................................................... 29 ACT register (register 5)................................................................................................................. 29 SAL & SAH register (register 8,9).................................................................................................. 30 UTH register (register 10)............................................................................................................... 30 BTH register (register 11)............................................................................................................... 31 MINL & MINH register (register 12,13)......................................................................................... 31 MAXL & MAXH register (register 14,15) ...................................................................................... 31 SYSCFG register (register 16) ........................................................................................................ 32 INTMSK register (register 17)........................................................................................................ 33 SPEED register (register 18)........................................................................................................... 33 LINK register (register 19) ............................................................................................................. 33 nFWD register (register 20)............................................................................................................ 34 nBP register (register 21)................................................................................................................ 34 nPORT register (register 22)........................................................................................................... 34 PVID register (register 23) ............................................................................................................. 35 VPID register (register 24) ............................................................................................................. 35 POSCFG register (register 25) ........................................................................................................ 35 PAUSE register (register 26) .......................................................................................................... 37 DPLX register (register 27) ............................................................................................................ 37 nPM register (register 29)............................................................................................................... 37 ERRMSK register (register 30)....................................................................................................... 37 CLKADJ register (register 31)........................................................................................................ 37 PHYREG register (register 32-63) .................................................................................................. 38 8. PIN DESCRIPTIONS..................................................................................................................... 39 RMII Clock Interface...................................................................................................................... 40 9. TIMING DESCRIPTION ............................................................................................................... 54 10. ELECTRICAL SPECIFICATION ................................................................................................ 60 11. PACKAGING .............................................................................................................................. 61 Appendix-A1 ......................................................................................................................................... 62 Built-in ARL with 2048 MAC Addresses........................................................................................ 62 Page 2 of 77 Confidential Page 2 1. GENERAL DESCRIPTION The ACD82224 is a single chip implementation of 24-port 10/100 Ethernet switch system intended for IEEE 802.3 and 802.3u compatible networks. The device includes 24 independent 10/100 MACs. Each MAC interfaces with an external PMD/PHY device through a Reduced MII (RMII) interface. The last port is RMII and MII selectable. When in MII mode, this port becomes a shared port with the in-band management CPU. Link, Speed, and Duplex can be automatically configured through the MDIO port. Each port can operate at either 10Mbps or 100Mbps. The core logic of the ACD82224, implemented with patent pending BASIQ (Bandwidth Assured Switching with Intelligent Queuing) technology, can simultaneously process 24 asynchronous 10/100Mbps port traffic. The Queue Manager inside the ACD82224 provides the capability of routing traffic with the same order of sequence, without any packet loss. A complete 24-port 10/100 switch can be built with the addition of 10/100 RMII PHY and SRAM TM 1 (ZBT or compatible). An additional 11K MAC addresses can be supported with the use of ACD's Address Resolution Logic (ARL) chip, the ACD80800. Advanced network management features can be supported with the use of ACD's Management Information Base (MIB) chip, the ACD80900. The single universal 388-pin PBGA package for all 3 controllers makes One-PCBFor-ALL three systems very easy to implement, which significantly reduce the cost and time associated with multiple system product development. Figure-1.1: ACD82224 Based 24 Ports Single Chip Un-managed 10/100 Switch System PHYs, Transformers & RJ45 Not Populated for ACD82216 16-port System MAG 23-20 MAG 19-16 MAG 15-12 MAG 11-8 MAG 7-4 MAG 3-0 Quad RMII PHY Quad RMII PHY Quad RMII PHY Quad RMII PHY Quad RMII PHY Quad RMII PHY 4 RMII Bus 4 RMII Bus 4 RMII Bus 4 RMII Bus 4 RMII Bus 4 RMII Bus LED Connector ZBT SRAM SRAM BUS ACD822xx 100 MHz OSC 1 ZBT is the trade mark of IDT. Page 3 of 77 Confidential Page 3 Figure-1.2: ACD82224 Based 24 Ports 3-Chip Managed 10/100 Switch System PHYs & Transformers & RJ45 Not Populated for ACD82216 16-port System MAG 22-20 MAG 19-16 MAG 15-12 MAG 11-8 MAG 7-4 MAG 3-0 Quad RMII PHYs Quad RMII PHYs Quad RMII PHYs Quad RMII PHYs Quad RMII PHYs Quad RMII PHYs 4 RMII Bus RMII Bus 3 RMII Bus 4 RMII Bus 4 RMII Bus 4 RMII Bus 4 RMII Bus RMII Bus LED Connector ACD80900 Flash LOCAL BUS DRAM ACD80800 Optional ARL Bus ACD82224 Bus Drivers SRAM BUS Crystal CPU text text ZBT SRAM 100 MHz OSC RS-232 Transceiver Serial Interface Page 4 of 77 Confidential Page 4 2. MAJOR FEATURES * * * * * * * * * * * * * * * * * * * * 24 ports 10/100 Fast Ethernet Switch (auto-sensing or manual selection) Reduced MII interface, with selectable MII for the last port Capable of Trunking for up to 800 Mbps link Full & half duplex operation Speed auto negotiation through MDIO 4.8 Gbps aggregated throughput, true non-blocking switch architecture, full wire speed forwarding Built-in storage of 2,048 MAC address Supports up to 11K MAC addresses with the ACD80800 Shared frame buffer with starvation control TM Memory interface with ZBT or compatible SRAM at 100MHz Automatic source address learning Zero-Packet Loss back-pressure flow control under half duplex mode 802.3x pause frame flow control under full duplex mode Store-and-forward switch mode Port based V-LAN support for up to 4 VLANs UART type CPU management interface RMON and SNMP support with ACD80900 Status LEDs: Link, Speed, Full Duplex, Transmit, Receive, Collision, and Frame Error 388-pin PBGA package Power: core 2.5V, I/O 3.3V with 5V tolerance 3. SYSTEM BLOCK DIAGRAM ACD822xx PMD/ PHY-0 PMD/ PHY-1 FIFO Buffer MAC-0 FIFO Lookup Engine (2K MAC Addr.) Buffer FIFO BIST Handler LED Controller Buffer MAC-1 FIFO Buffer MX Queue Manager DMX PMD/ PHY(xx-2) FIFO PMD/ PHY(xx-1) FIFO FIFO FIFO MAC(xx-2) MAC(xx-1) Buffer Buffer Buffer ARL Interface SRAM Interface MIB Interface ARL ACD80800 (11K MAC Addr.) (optional) ZBT or The Compatible SRAM MIB ACD80900 (optional) Buffer xx=16 for ACD82216 24 for ACD82224 Page 5 of 77 Confidential Page 5 4. SYSTEM DESCRIPTION The ACD82224 is a single chip implementation of a 24-port Fast Ethernet switch. Together with external SRAM devices and transceiver devices, it can be used to build a complete 10/100 Mbps Fast Ethernet switch. Each port can be either auto-sensing or manually selected to run at 10 Mbps or 100 Mbps speed rates and under Full or Half-duplex mode. There are four (4) major functional blocks inside the ACD82224: (a) The Media Access Controller (MAC) (b) The Queue Manager (c) The Lookup Engine (d) The Register file (e) The MIB Engine interface There are five (5) types of interfaces: (a) RMII interfaces (b) RMII/MII selectable interface (c) Memory interface (d) External-ARL interface (e) External-MIB interface MACs, RMII & MII Interfaces There are 24 independent MACs within the ACD82224. The MAC controls the receiving, transmitting, and deferring process of each individual port, in accordance to the IEEE 802.3 and 802.3u standards. The MAC logic also provides framing, FCS checking, error handling, status indication and flow control functions (backpressure & pause-frame). Each MAC interfaces with an external transceiver through a RMII (Reduced MII) interface. The last MAC has a selectable RMII/MII interface. The MII mode allows direct connection with the ACD80900 (MIB), which also acts as a three-port switch for the management CPU to share the regular switch port for in-band management. Queue Manager The device utilizes ACD's proprietary BASIQ (Bandwidth Assured Switching with Intelligent Queuing) technology. It efficiently enforces the first-in-first-out rule of Ethernet Bridge-type devices. It also enables a true non-blocking frame switching operation at wire speeds for high throughput and high port density Ethernet switch design. Built-in ARL & External-ARL Interface The on-chip Lookup Engine implements a 2,048 entries MAC address lookup table. It maps each destination address with a corresponding port ID. Each MAC address is automatically learned by the LOOKUP ENGINE after an error-free frame is received. The address entries can also be managed for aging, locking, and forced filtering. Through the serial CPU interface of the ACD82224 switch, a management CPU can learn the address change in the lookup table. Hence, the ACD82224 alone can be used to build a complete Fast Ethernet switch with up to 2,048 host connections. (See Appendix-A for detail) For workgroup or backbone switches, the ACD82224 can support more MAC addresses per port through the use of an external ARL chip, the ACD80800. The ACD82224 has a glueless ARL interface that allows a supporting chip (ACD80800) to provide up to 11K MAC addresses per Page 6 of 77 Confidential Page 6 switch. System designers can also use this ARL interface to implement a vendor-specific address resolution algorithm. Register & UART Interface A System CPU can access various registers inside the ACD82224 through a serial CPU management interface (UART). The CPU can configure the switch by writing into the appropriate registers, or retrieve the status of the switch by reading the corresponding registers within the ACD82224 switch. The CPU can also access the registers of external transceiver (PHY) devices through the CPU management interface as well. External-MIB & External-MIB Interface The ACD82224 provides management support through the use of the ACD80900 (Management Information Base). The MIB interface can be used to monitor all traffic activities of the switch system. The supporting chip (the ACD80900) provides a full set of statistics counters to support both SNMP and RMON network management functions. In addition to the statistics counters, the ACD80900 also support all groups of RMON management, including Host, HostN, Matrix, Filtering and Capturing groups. System designers can also use the MIB interface to implement vendor-specific network management functionality. Page 7 of 77 Confidential Page 7 5. FUNCTIONAL DESCRIPTION The MAC controller performs transmitting, receiving, and deferring functions, in accordance to the 802.3 and 802.3u specification. The MAC logic also handles frame detection, frame generation, error detection, error handling, status indication and flow control functions. Under full-duplex mode, the flow control is implemented in compliance with IEEE 802.3x standard. Frame Format The ACD82224 assumes that the received data packet will have the following format: Preamble SFD DA SA Type/Len Data FCS Where, * Preamble is a repetitive pattern of `1010....' of any length with nibble alignment. * SFD (Start Frame Delimiter) is defined as an octet pattern of 10101011. * DA (Destination Address) is a 48-bit field that specifies the MAC address of the destined DTE. For any frame with "1" in the first bit of the DA, with the exception of the BPDU address (the reserved group address described in table 3-5 of IEEE 802.1d), the ACD82224 will treat it as a broadcast/multicast frame. It will forward the frame to all ports within the source port's VLAN, except the source port itself. * SA (Source Address) is a 48-bit field that contains the MAC address of the source DTE that is transmitting the frame to the ACD82224. After a frame is received with no error, the SA is learned as the port's MAC address. * Type/Len field is a 2-byte field that specifies the type (DIX Ethernet frame) or length (IEEE 802.3 frame) of the frame. The ACD82224 does not process this information, unless it is a Pause-Frame * Data is the encapsulated information within the Ethernet Packet. The ACD82224 does not process any of the data information in this field. * FCS (Frame Check Sequence) is a 32-bit field of CRC (Cyclic Redundancy Check) value based on the destination address, the source address, the type/length and the data field. The ACD82224 will verify the FCS field for each frame. The procedure for computing FCS is described in the section "FCS Calculation." Start of Frame Detection When a port's MAC logic detects the assertion of the CRS_DV signal in the RMII interface, it will start a receiving process. The received data will come through a 2-bit wide data bus, clocked by the 50 MHz receiving-clock from the ACD82224. It will then pass a frame alignment circuit, which will convert the 2-bit signal into a single bit stream and detect the occurrence of the SFD pattern (10101011). All signals before the SFD are filtered out and the rest of the data frame will be stored into the frame buffer of the switch. Frame Reception Page 8 of 77 Confidential Page 8 Under normal operating conditions, the ACD82224 expects a received frame to have a minimum inter frame gap (IFG). The minimum IFG required by the ACD82224 is 64 BT. If a packet comes with an IFG less than 64 BT, the ACD82224 will not guarantee the reception of that frame. The packet may be dropped if it is not properly received. The ACD82224 will check all received frames for errors such as symbol error, FCS error, short event, runt, long event, jabber, etc. Frames with any kind of error will not be forwarded to any port. Preamble Bit Processing The preamble bit in the header of each frame will be used to synchronize the MAC logic with the incoming bit stream. There is no limit on the minimum length or the maximum length of preamble bits. After the receive-signal CRS_DV is asserted by the external PHY device, the MAC will wait for the SFD pattern (10101011) to trigger a frame receiving process. Destination Address Processing As a frame comes in, the embedded Destination Address (DA) is passed to the Address Resolution Logic (ARL). The ARL will compare it with the MAC address entries stored in the address lookup table. A destination port is identified if a match of address is found. If external ARL is used, the ACD82224 will indicate the present of 48-bit DA through the ARL interface. The external ARL will use the value of DA for address comparison and return a result to the ACD82224. Source Address Processing As a frame comes in, the embedded Source Address (SA) will be passed to the ARL. At the end of the frame, if no error is detected, the SA will be used to update the address lookup table. If an external ARL is used, the ACD82224 will indicate the presence of a SA on the ARL interface, so that the external ARL can learn the address. The address table will be cleared after a HardwareReset, but a Software-Reset will not clear the address table. Frame Data Frame data are transparent to the ACD82224. The ACD82224 will forward the data to destination port(s) without interpreting the content of the frame data field. FCS Calculation Each port of the ACD82224 has a CRC checking logic to verify if the received frame has the correct FCS value. An incorrect FCS value is an indication of a fragmented frame or a frame with frame bit error. The method of calculating the CRC value is by using the following polynomial, G(x) = x 32 +x 26 +x 23 +x 22 +x 16 +x 12 +x 11 +x 10 8 7 5 4 2 +x +x +x +x +x +x+1 as a divider to divide the bit sequence of the incoming frame, beginning with the first bit of the destination address field, to the end of the data field. The result of the calculation, which is the Page 9 of 77 Confidential Page 9 residue after the polynomial division, is the value of the frame check sequence. This value should be equal to the FCS field appended at the end of the frame. If the value does not match the FCS field of the frame, the Frame Bit Error LED of the port will be turned on once and the packet will be dropped. Illegal Frame Length & Extra-long Frame During the receiving process, the MAC will monitor the length of the received frame. Legal Ethernet frames should have a length of not less than 64 bytes and no more than 1518 bytes. If the carrier-sense signal (CRS_DV) of a frame is asserted for less than 84 BT, the frame is flagged with short event error. If the length of a frame is less than 512 BT, the frame is flagged with runt error. In order to support an application where extra byte length is required, an Extra long frame option is provided. When the Extra long frame option is enabled (bit-11 of Register 25), only frames longer than 1530 bytes are marked with a long event error. Frame length is measured from the first byte of DA to the last byte of FCS. Frame Filtering Frames with any kind of error will be filtered. Error types include CRC, alignment, false carrier sense, short event, runt, long event and jabber. An error frame will still be displayed on the MIB interface, along with the error status indication. Any frame heading to its own source port will be filtered. When external ARL is used, the filtering decision will be made by the ARL. The ACD82224 will act in accordance with the ARL's decision. If the Spanning Tree Support option (Bit 1 of Register 16) is set, a frame with DA equal to 01-80C2-00-00-00 will be forwarded to port-23 (the default CPU port) as a BPDU frame. If Spanning Tree Support is not enabled, a frame with reserved group address specified in Table-3.5 of the IEEE802.1d will be treated as a broadcast frame and will be forwarded to all the ports in the same VLAN of the source port. Jabber Lockup Protection If a receiving port is active continuously for more than 50,000 bit times, the port is considered to be jabbering. A jabbering port will automatically be partitioned from the switch system in order to prevent it from impairing the performance of the network. The partitioned port will be re-activated as soon as the offending signal discontinues. Excessive Collision In the event that there are more than 16 consecutive collisions, the ACD82224 will reset the counter to zero and re-transmit the packet. This implementation insures there is no packet loss even under channel capture situation. However, the ACD82224 has an option to drop the packet on excessive collisions. When this option is enabled (bit-15 of Register 25), the frame will be dropped after 16 consecutive collisions. Page 10 of 77 Confidential Page 10 Frame Forwarding If the first bit (bit-40) of the destination address is 0, the frame is handled as a unicast frame. The destination address is passed to the Address Resolution Logic; which returns a destination port number to identify which port the frame should be forwarded to. If the Address Resolution Logic cannot find any match for the destination address, the frame will be treated as a frame with unknown DA. The frame will be processed in one of two ways upon bit-12of Register 25. 1. If the option flood-to-all-port is set, the switch will forward the frame to all ports within the same VLAN of the source port, except the source port itself. 2. If the option is not set, the frame will be forwarded to the `dumping port' of the source port VLAN only. The dumping port is determined by the VLAN ID of the source port. If the source port belongs to multiple VLANs, a frame with unknown DA will then be forwarded to multiple dumping ports of the VLANs. If the first bit of the destination address is a 1, the frame is handled as a multicast or broadcast frame. The ACD82224 does not differentiate a multicast packet from a broadcast packet except for the reserved bridge management group address, as specified in Table-3.5 of IEEE 802.1d standard. The destination ports of a broadcast frame are all ports within the same VLAN except the source port itself. The order of all broadcast frames with respect to the unicast frames is strictly enforced by the ACD82224. Frame Transmission The ACD82224 transmits all frames in accordance to IEEE 802.3 standard. The ACD82224 will send the frames with a guaranteed minimum inter frame gap of 96 BT, even if the received frames have an IFG less than the minimum requirement. Before the transmitting process is started, the MAC logic will check if the channel has been silent for more than 64 BT. Within the 64 BT silent window, the transmission process will defer on any receiving process. If the channel has been silent for more than 64 BT, the MAC will wait an additional 32 BT before starting the transmitting process. In the event that the carrier sense signal is asserted by the RMII during the wait period, the MAC logic will generate a JAM signal to cause a forced collision. The MAC logic will abort the transmitting process if a collision is detected. Re-transmission of the frame is scheduled in accordance to the IEEE 802.3's truncated binary exponential back-off algorithm. If the transmitting process has encountered 16 consecutive collisions, an excessive collision error is reported, and the ACD82224 will try to re-transmit the frame, unless the drop-onexcessive-collision option of the port is enabled. It will first reset the number of collisions to zero and then start the transmission after a 96 BT of inter frame gap. If drop-on-excessive-collision is enabled, the ACD82224 will not try to re-transmit the frame after 16 consecutive collisions. If collision is detected after 512 BT of the transmission, a late collision error will be reported and the frame may or may not be retransmitted. Shared Buffer All ports of the ACD82224 work in Store-And-Forward mode so that all ports can support both 10Mbps and 100Mbps data speeds. The ACD82224 utilizes a global memory buffer pool, which is shared by all ports. The device has a unique architecture that inherits the advantages of both output buffer-based and input buffer-based switches: short latency of an output-buffer based switch which only store the received data once into the memory and efficient flow control of an input-buffer based switch. Page 11 of 77 Confidential Page 11 Starvation Control Scheme All frames received by the ACD82224 will be stored into a common physical frame buffer pool. In order to make sure all ports have fair access to the network, a buffer allocation scheme (starvation control) is used to prevent active ports from occupying all the buffers and starving off the less active ports. The frame buffer pool is divided into 3 portions: the reserved pool, the common pool and the extra pool, as shown in Figure-5.1: Figure-5.1: Buffer Partition Extra Pool (shared by all full duplex ports with flow control capability) ~80% Common Pool (shared by all the ports) ~50% Reserved Pool (dedicated to each port) The reserved pool guarantees each port will have a fair network access possibility, even under the worst traffic congestion situation. It takes about 50% of the total buffer and is evenly allocated to each port as its dedicated buffer slot. The dedicated slot is not shared with other ports. Page 12 of 77 Confidential Page 12 The common pool provides a deep buffer for the busy ports (e.g. server port) to serve multiple low speed ports (e.g. client port) simultaneously. It helps to avoid head-of-line blocking. It takes about 30% of the total buffer and is shared by all ports. It stores the congested traffics before the flow control mechanism is triggered. The extra pool is reserved only for ports with pause frame based flow control capacity. It takes the remaining 20% of the total buffer. It is used to minimize the chance of frame dropping by buffering for the latency of the pause frame based flow control scheme. It is used only after a flow control mechanism is triggered. Flow Control Scheme Flow control activity is triggered when the buffer utilization exceeds certain thresholds specified by the dedicated registers. Register-10 is used to specify the Upper and the Lower Thresholds of the reserved buffer slot for each port. Register-11 is used to specify the Upper and the Lower thresholds of the broadcast queue. For full duplex with pause frame capability operation: (1) If the buffer utilization of the reserved buffer slot for the source port has exceeded the "Upper Threshold", and the common pool has been used up. (2) Then a max-pause-frame (a pause frame with a maximum time interval of FFFFh) will be sent to the sending port to stop it from sending any new frames. If pause-frame based flow control is not enabled at that port, the frame will be dropped. (3) Once a Max-Pause-Frame is sent, if the utilization of the reserved buffer slot of the port drops below the lower threshold, a Mini-Pause-Frame (a pause frame with minimum time interval of 0) will be sent to the sending port to enable new frame transmission. But if the utilization of the reserved buffer slot of the port does not drop below the lower threshold for the maximum time interval, ACD82224 will not send another Max-Pause-Frame to the sending port to prevent the Buffer Capturing by other ports. For half duplex operation: (1) If the buffer utilization of a port has exceeded the upper threshold of the reserved buffer slot, and the common pool has been used up. (2) The port will execute backpressure based flow control by sending a jam pattern on each incoming frame. If backpressure flow control of the port is not enabled, the frame will be dropped. If the broadcast flow control is enabled (when bit-17 of register-25 is cleared), flow control will be triggered when the broadcast queue is larger than the "Upper Threshold" in Register-11. All full duplex ports with pause-frame capability will send a Max-Pause-Frame to its linking party. All half-duplex ports with backpressure capability will jam incoming frames. After a Max-PauseFrame is sent, and if the broadcast queue is below the "Lower Threshold" in Register-11, a MiniPause-Frame will be sent to release the hold on transmission. Port-based VLAN Support (Registers 23 & 24) The ACD82224 can support up to 4 port-based security VLANs. Each port of the ACD82224 can be assigned to up to four VLAN. On power up, every port is assigned to VLAN-I as the default Page 13 of 77 Confidential Page 13 VLAN. Frames from the source port will only be forwarded to destination ports within the same VLAN domain. A broadcast/multicast frame will be forwarded to all ports within the VLAN(s) of the source port. A unicast frame will be forwarded to the destination port only if the destination port is in the same VLAN as the source port. Otherwise, the frame will be treated as a frame with unknown DA. Each VLAN can be assigned with a dedicated dumping port. Multiple VLANs can also share a dumping port. Unicast frames with unknown destination addresses will be forwarded to the dumping port of the source port VLAN. A Leaky VLAN can be enabled by setting the corresponding bit in the system configuration register (bit-8 of register-16). A VLAN becomes a broadcast domain. Each broadcast domain VLAN can still be assigned with a dedicated dumping port. Port Trunking Security VLAN can be disabled by setting the corresponding bit in the system configuration register (bit 8 of Register 16, see Table 7.15). When security VLAN is disabled, each VLAN becomes a Leaky VLAN and is equivalent to a broadcast domain. Four dumping ports of four different Leaky VLANs can be grouped together to form a fat pipe uplink (for example, port 0, port 1, port 2, and port 3 can be grouped to form an 800 Mbps uplink port). When multiple dumping ports are grouped as a single pipe, each port has to be assigned to one and only one VLAN. A unicast frame with a matched DA will be forwarded to any destination port, even if the VLAN ID is different. All unmatched DA packets will be forwarded to the designated dumping port of the source port VLAN. The broadcast and multicast packets will only be forwarded to the ports in the same VLAN of the source port. Therefore, a 200 to 800 Mbps pipe can be established by carefully grouping the dumping ports, and directly connecting with any segmentation switches. Dumping Port Each VLAN can be assigned with a dedicated dumping port. Multiple VLANs can share a single dumping port. Each dumping port can be used for an up-link connection or for a DTE connection. That is, the dumping port can be used to connect the switch with a computer repeater hub, a workgroup switch, a router, or any type of interconnection device compliant with IEEE 802.3 standard. ACD82224 will direct the following frames to the dumping port: (1) A frame with unknown unicast destination address. (2) A frame with a unicast destination address that does not match with any port's source address within the VLAN of the source port. (3) A frame with a broadcast/multicast destination address (See Spanning Tree Support). If the device is configured to work under Flood-to-All-Port mode (Register 25, bit 12), the frames with unknown DA will be forwarded to all the ports in the VLAN(s) of the source port except the source port itself. Mode of Operation Each port can be configured or auto-sensed to work under either half-duplex or full-duplex mode. Under half duplex mode, the CSMA/CD will be enforced, and the flow control is achieved through backpressure. Under full duplex mode, the receiving process and the transmitting process of the port are independent, and the flow control is done by pause-frame based flow control scheme specified by the IEEE 802.3x. Page 14 of 77 Confidential Page 14 Spanning Tree Support The ACD82224 supports the Spanning Tree protocol. When Spanning Tree Support is enabled (Register-16 bit-1, see Table 7.15), frames from the CPU port (port-23) having a DA value equal to the reserved Bridge Management Group Address for BPDU will be forwarded to the port specified by the CPU. Frames from all other ports with a DA value equal to the Reserved Group Address for BPDU will be forwarded to the CPU port if the port is in the same VLAN of the CPU port. Port 23 is designed as the default CPU port. When Spanning Tree Support is disabled (Register-22 nPORT Register), all reserved group addresses for Bridge Management is treated as broadcast addresses, with the exception of the reserved multicast addresses for pause frame specified by IEEE802.3x. Every port of the ACD82224 can be set to block-and-listen mode (Register-21 nBP Register) through the CPU interface. In this mode, incoming frames with a DA value equal to the reserved Group Address for BPDU will be forwarded to the CPU port. Incoming frames with all other DA values will be dropped. Outgoing frames with a DA value equal to the Group Address for BPDU will be forwarded to the attached PHY device; all other outgoing frames will be filtered. Queue Management Each port of the ACD82224 has its own individual transmission queue. All frames coming into the ACD82224 are stored into the shared memory buffer, and are lined up in the transmission queues of the corresponding destination port. The order of all frames, unicast or broadcast, is strictly enforced by the ACD82224. The ACD82224 is designed with a non-blocking switching architecture. It is capable of achieving wire speed forwarding rates and can handle maximum traffic loads. PHY Management The ACD82224 supports PHY device management through the serial MDIO and MDC signal lines. The ACD82224 can continuously poll the status of the PHY devices through the serial management interface if Register-25 bit-16 is cleared. The ACD82224 will also configure the PHY capability field like Link, Speed, and Duplex status to ensure proper operation of the link. The ACD82224 also enables the CPU to access any registers in the PHY devices through the CPU interface (See Register-32 example). The ID of the PHY device can start from either "0" or "1", depending on the setting of bit-14 of register-25. There are two ways to disable Automatic PHY Management as follows: (1) Set Register-25 bit-16 to disable Automatic PHY Management for all ports. (2) Set the specific port in Register-29 to disable the port from Automatic PHY Management. PHY Interface The PHY interface for port-0 through port-22 can only be RMII. The RMII CLK (50MHz clock) will be used as the RXCLK and TXCLK. There are three wires on the receiving side (RXD[1:0] and CRS_DV), and three wires on the transmitting side (TXD[1:0] and TXEN). Port-23 can be configured as either RMII or MII (Register-16 bit-15). The MII option is used for direct connection with the ACD80900 only supporting MII interface. ACD82224 supports PHY management through the MDIO and MDC signal lines. ACD82224 can continuously poll the status of the PHY devices through the serial management interface, without Page 15 of 77 Confidential Page 15 using a CPU. ACD82224 also allows the CPU to access any registers in the PHY devices through the CPU interface. SRAM Interface TM The ACD82224 uses pipeline ZBT (zero-bus- turn-around) or compatible types of SRAM. The speed should be 100MHz or faster. Each read or write cycle should take no more than 10 ns. The SRAM interface contains a 52-bit data bus (48-bit data and 4-bit status), a 19-bit address bus, and 2 control signals. CPU Interface The ACD82224 does not require any microprocessor for operation. Initialization and most configurations can be done with pull-up or pull-down of designated hardware pins. A CPU interface is provided for a microprocessor to access the internal control registers and status registers. The microprocessor can send a read command to retrieve the status of the switch, or send a write command to configure the switch through the interface. The interface is a commonly used UART type interface. The CPU interface can also be used to access the registers inside each PHY device connected to the ACD82224. ARL Interface The ACD82224 has a built-in MAC address storage for up to 2,048 source addresses. If more than 2,048 addresses are needed, an external ARL (e.g. ACD80800) can be used to expand the address space to 11K entries. The external ARL is connected through the ARL interface (Table-6.9). It can tap the value if DA out of the memory interface bus, and execute a lookup process to map the value of the DA into a port number. It can also learn the SA values embedded in the received frames. The value of SA is used to build the address lookup table inside the ACD80800. If the new addressed are over the maximum number of look-up table, ARL will not learn the newer address until there is any available entry again (i.e. the learned address aged). MIB Interface Traffic activities on all ports of the ACD82224 can be monitored through the MIB interface. Through the MIB interface, a MIB device can view the frames transmitted from or received by any port. Therefore, the MIB device can maintain a record of traffic statistics for each port to support network management. Since all received data are stored into the memory buffer, and all transmitted data are retrieved from the memory buffer, the data of the activities can also be captured from the memory interface data bus. The status of each data transaction between the ACD82224 and SRAM is displayed by dedicated status signals of the ACD82224 interface (Table-6.9). LED Interface The ACD82224 provides a wide variety of LED indicators for simple system management. The update of the LED is completely autonomous and merely requires low speed TTL or CMOS Page 16 of 77 Confidential Page 16 devices as LED drivers. The status display is designed to be flexible to allow the system designer to choose those indicators appropriate for the specification of the end equipment. There are two LED control signals, LEDVLD0 and LEDVLD1. They are used to indicate the start and end of the LED data signal presented on nLED0-nLED3. The LEDCLK signal is a 2.5 MHz clock signal. The rising edge of LEDCLK should be used to latch the LED data signal into the LED driver circuitry. The LED data signals contain Lnk, Xmt, Rcv, Col, Err, Fdx and Spd, which represent Link status, Transmit status, Receive status, Collision indication, Frame error indication, Full duplex operation and Operational Speed status respectively. These status signals are sent out sequentially from port 23 to port 0, once every 50 ms. For details about the timing diagrams of the LED signals, refer to the chapter of "Timing Description " Life Pulse The ACD82224 will generate Life Pulses at WCHDOG pin once every 800 nsec to indicate normal operation status. Absence of the Life Pulses is an indication that, the ACD82224 has encountered some fatal error and needs to be reset. The life pulses are used to reset a watchdog counter, such that, if the watchdog counter is not reset and has reached a predetermined value, a system reset signal can be generated to reset the ACD82224. Page 17 of 77 Confidential Page 17 6. INTERFACE DESCRIPTION Figure-6.1 shows all the interfaces of the ACD82224 controller and their relations to other modules in a typical switch system. Table-6.1 list all function pins grouped by types. Figure-6.1 Major Interface Group ADDR[0:18] nWE nCS DATA[0:47] BE[0:2] EOF P(a) RMII P(a+1) RMII RMII PHY .... * a=8 for 82216 0 for 82224 ZBT SRAM TM P23 RMII RMIICLK[0:5] LED Logic System Logic LED[0:3] LEDCLK LEDVLD[0:1] ACD822xx SWDIR[0:1] SWSYNC SWSTAT[0:3] ARLDI[0:3] ARLDIV SWRXCLK ACD80800 Optional CLK100 nRESET WCHDOG TESTEN SYSERR ACD80900 Optional SWTXCLK P23 RMII Table-6.1 Interface Group Interface RMII Port[0:22] Pin Name PxCRS_DV, PxRXD0, PxRXD1, PxTXEN, PxTXD0, and PxTXD1 P23CRS*, P23RXDV*, P23RXCLK, P23RXERR, P23RXD0*, P23RXD1*, P23RXD2, P23RXD3, P23COL,P23TXEN, P23TXD0*, P23TXD1*, P23TXD2, P23TXD3, and P23TXCLK (*: shared with RMII signals in Port23) RMIICLK[5:0] RMII Clock PHY Management MDC, and MDIO Memory Address ADDR[0:18] DATA[47:0], BE[2:0], and EOF Memory Data Memory Control nWE, and nCS SWDIR[1:0], SWPID[4:0], SWSYNC, SWSTAT[4:0], SWRXCLK, ARL and MIB SWTXCLK, ARLDI[3:0], and ARLDIV MII Port-23 LED CPU System Control LEDVLD[1:0], LEDCLK, and nLED[3:0] CPUDI, CPUDO, and CPUIRQ CLK100, nRESET, WCHDOG, and SYSERROR Factory Test 2.5V 3.3V Ground EN16P, CLKSEL, TESTEN, and ZBTCLK VDD (for Core) VDDQ (for I/O) VSS (including 36 center thermal ground) Total Number of pins Page 18 of 77 Confidential 82224 138 15 6 2 19 52 2 19 7 3 4 4 17 33 67 388 Page 18 RMII Interface (RMII) The ACD82224 communicates with the external 10/100 Ethernet transceivers through standard RMII interface. The signals of RMII interface are described in Table-6.2a: Table-6.2a: RMII Interface Name PxCRSDV PxRXD0 PxRXD1 PxTXEN PxTXD0 PxTXD1 RMIICLK[5:0] Type I I I O O O O Description Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit enable Transmit data bit 0 Transmit data bit 1 Reduced MII clock (50 MHz) For RMII interface, signal PxRXDV, PxRXD0, and PxRXD1 are sampled by the rising edge of RMIICLK. Signal PxTXEN, PxTXD0, and PxTXD1 are clocked out by the falling edge of RMIICLK. The detailed timing requirement is described in the chapter of "Timing Description" MII Interface (MII) The last port (e.g. Port-23 on the ACD82224) can be selected to act in MII mode. The MII mode is used to connect the ACD80900 for in-band management function. The ACD80900 acts as a three-way switch to allow the management CPU to share the regular port. The signals of MII interface are described in Table-6.2b: Table-6.2b: MII Interface MII Mode P23CRS P23RXDV P23RXCLK P23RXERR P23RXD0 P23RXD1 P23RXD2 P23RXD3 P23COL P23TXEN P23TXCLK P23TXD0 P23TXD1 P23TXD2 P23TXD3 RMII Mode P23CRSDV NC NC NC P23RXD0 P23RXD1 NC NC NC P23TXEN NC P23TXD0 P23TXD1 NC NC Type I I I I I I I I I O I O O O O Description Carrier sense Receive data valid Receive clock (25/2.5 MHz) Receive error Receive data bit 0 Receive data bit 1 Receive data bit 2 Receive data bit 3 Collision indication Transmit data valid Transmit clock (25/2.5 MHz) Transmit data bit 0 Transmit data bit 1 Transmit data bit 2 Transmit data bit 3 Under the MII mode, signal P23RXDV, P23RXER and P23RXD0 through P23RXD3 are sampled by the rising edge of P23RXCLK. Signal P23TXEN, and P23TXD0 through P23TXD3 are clocked out by the falling edge of P23TXCLK. The detailed timing requirement is described in the chapter of "Timing Description" PHY Management Interface All control and status registers of the PHY devices are accessible through the PHY management interface. The interface consists of two signals: MDC and MDIO, which are described in table-6.3. Page 19 of 77 Confidential Page 19 Table-6.3: PHY Management Interface Signals Name MDC MDIO Type O I/O Description PHY management clock (1.25MHz) PHY management data Frames transmitted on MDIO has the following format (Table-6.4): Table-6.4: MDIO Format Operation Write Read PRE 1...1 1...1 ST 01 01 OP 01 10 PHY-ID A[4:0] A[4:0] REG-AD R[4:0] R[4:0] TA 10 Z0 DATA D[15:0] D[15:0] IDLE Z Z Prior to any transaction, the ACD82224 will output thirty-two bits of `1' as preamble signal. After the preamble, a 01 signal is used to indicate the start of the frame. For a write operation, the device will send a `01' to signal a write operation. Following the `01' write signal will be the 5 bit ID address of the PHY device and the 5 bit register address. A `10' turn around signal is then follows the "write" signal. After the turn around, the 16 bit of data will be written into the register. After the completion of the write transaction, the line will be left in a high impedance state. For a read operation, the ACD82224 will output a `10' to indicate read operation after the start of frame indicator. Following the `10' read signal will be the 5-bit ID address of the PHY device and the 5-bit register address. Then, the ACD82224 will cease driving the MDIO line, and wait for one bit time. During this time, the MDIO should be in a high impedance state. The ACD82224 will then synchronize with the next bit of `0" driven by the PHY device, and continue on to read 16 bits of data from the PHY device. The system designer can set the ID of the PHY devices as 0 for port-0, 1 for port-1, ... and 23 for port-23, when the PHYID option (Bit-14 of Register-25) is set to "0". If the PHYID option is set to "1", the corresponding PHY ID should set to 1 through 24. The detailed timing requirements on PHY management signals are described in the chapter of "Timing Description." CPU Interface The ACD82224 includes a CPU UART interface to enable an external CPU to access the internal registers of the ACD82224. The baud rate of the UART can be from 19200 to 38400 bps. The ACD82224 automatically detects the baud rate for each command, and returns the result at the same baud rate. The signals in the CPU interface are described in Table-6.5. Table-6.5: CPU Interface Signals Name CPUDI CPUDO CPUIRQ Type I Tri-state O Description CPU data input CPU data output CPU interrupt request A command sent by the CPU through the CPUDI line consists of 7 octets. Command frames transmitted on CPUDI have the format shown in Table-6.6: Table-6.6: CPUDI Format Operation Write Page 20 of 77 Command 0010XX11 Address A[7:0] Index I[7:0] Confidential Data D[23:0] Checksum C[7:0] Page 20 Read 0010XX01 A[7:0] I[7:0] D[23:0] C[7:0] The byte order of data in all fields follows the big-endian convention, i.e. most significant octet first. The bit order is the least significant order first. The Command octet specifies the type of the operation. The Bit-7, bit-6, and bit-5 of the command octet are specified the Device Type. (1) Switch Controller, the device type is 001. (2) ARL Controller, the device type is 010. (3) Management Controller, the device type is 100. The Bit-2 and bit-3 of the command octet are used to specify the device ID of the chip. They are set by bit 20 and bit 21 of the Register 25 at power on strobe. The address octet specifies the number of the register. The index octet specifies the index of the register in a register array. For write operation, the Data field is a 3-octet value to specify what to write into the register. For read operation, the Data field is a 3-octet 0 as padded data. If the data of register is less than 24bit, it is aligned to bit-0 of Data field. The checksum value is an 8-bit value of exclusive-OR of all octets in the frame, starting from the Command octet. For each valid command received, the ACD82224 will always send a response. Response from the ACD82224 is sent through the CPUDO line. Response frames sent by the ACD82224 have the following format (Table-6.7): Table-6.7: Switch Response Format Response Write Read Command 00000011 00000001 Result R[7:0] R[7:0] Data D[23:0] D[23:0] Checksum C[7:0] C[7:0] The command octet specifies the type of the response. The result octet specifies the result of the execution. The Result field in a response frame is defined as: * "0" for no error * "1" for Access Violation Error For response to a read operation, the Data field is a 3-octet value to indicate the content of the register. For response to a write operation, the Data field is 32 bits of 0. If the data of register is less than 24-bit, it is align to bit-0 of Data field. The checksum value is an 8-bit value of exclusive-OR of all octets in the response frame, starting from the Command octet. CPUIRQ is high active and used to notify the CPU that some special status has been encountered by the ACD82224, like port partition, and fatal system error, etc. By clearing the appropriate bit in the interrupt mask register, the specific source interrupt can be stop. Reading the interrupt source register retrieves the source of the interrupt request and clears the interrupt source register. CPUIRQ keeps high if the interrupt source is still existed. SRAM Interface All received frames are stored into the shared frame buffer through the memory interface. When the destination port is ready to transmit the frame, data is read from the shared memory buffer through the memory interface. The memory interface signals are described in the following table: Page 21 of 77 Confidential Page 21 Table-6.8: ZBT SRAM Interface Name DATA[47:0] BE[2:0] EOF ADDR[18:0] Type I/O I/O I/O O Description Memory data bus Byte enable End of frame Memory address bus nWE O nCE O Write enable: 0=Write 1=Read Chip enable, low active The synchronous clock input of the External SRAM's should connect to 100 MHz system clock. Data is written into the SRAM or read from the SRAM in 52-bit wide words. ADDRx specifies the address of each word. * * * * * * DATA[47:0] are used to transfer up to 6 octets of data each time. BE[2:0] indicate the valid bytes in 6 octet of data in DATA[47:0]. EOF indicates the last word of a frame. ADDR[18:0] specifies up to 512K word addresses. nWE specifies the type of operation for each clock cycle. nCE selects the SRAM chip associated with the word address. The timing requirement for SRAM access is described in the chapter of "Timing Description." ARL & MIB Interfaces The ARL interface provides a communication path between the ACD82224 and an external ARL device such as the ACD80800, which can provide up to 11K of address lookup. The MIB interface provides a communication path between the ACD82224 and an external MIB device such as the ACD80900 for management function implementation. Both the ACD80800 and the ACD80900 collect traffic information by monitoring the data bus of the buffer memory. The two interfaces share many common pins, as shown in Figure-6.1and Table-6.9. When the ACD82224 receives a frame, it will store it into the frame buffer memory through data bus DATA[47:0]. The external ARL extracts the destination address and source address of the frame posted on the Data [0:47] while it is written into the memory. It then finds the corresponding destination port and returns the result through the ARLDI[3:0] lines to the ACD82224. The timing requirement on ARL signals is described in Chapter 9, "Timing Description". At the same time, the external MIB also grabs the frame into its internal buffer for further management processing. Please see the ACD80800 and the ACD80900 Data Sheets for details. Page 22 of 77 Confidential Page 22 Table-6.9: ARL & MIB Interfaces Signals Name DATA[47:0] BE[2:0] EOF SWDIR[1:0] Type O O O O SWSYNC SWSTAT[3:0] O O SWRXCLK SWTXCLK P-23 MII O O ARLDI[3:0] I ARLDIV I ARL Interface MIB Interface Frame Data Byte Enable: BE[0:2] End of Frame: EOF Data Direction Indicator : 00 = idle, 01 = receive, 10 = transmit, 11 = control Port synchronization: indicating when Port-0 is driving DAT[0:47] Data state indicator: 0000 - Idle 0001 - First word (DA) 0010 - Second word (SA) 0011 - Third through last word 0100 - Filter Event 0101 - Drop Event 0110 - Jabber 0111 - False Carrier (receive) - Deferred Transmission (transmit) 1000 - Alignment error (receive) - Single Collision (transmit) 1001 - Flow Control (receive) - Multiple Collision (transmit) 1010 - Short Event (receive) - Excessive Collision (transmit) 1011 - Runt (receive) - Late Collision (transmit) 1100 - Symbol Error 1101 - FCS Error 1110 - Long Event 1111 - Reserved Receive Clock NA Transmit Clock NA The default CPU port, share with regular Port-23 traffic ARL Data Input: NA Returns 12-bit (3-cycles) ARL look-up result to the switch: *Bit[11:7] - Source Port ID (0 - 23) *Bit[6:5] - Look-up Result: 00 - reserved 01 - matched 10 - not matched 11 - forced discard *Bit[4:0] - Destination Port ID (0 - 23) ARL Data Input Valid: Assertion to indicate start NA of a new result on ARLDI[0:3] LED Interface The status of each port is displayed on the LED interface for every 50ms. LEDVLD0 and LEDVLD1 are used to indicate the start and end of the LED data. LED data is clocked out by the Page 23 of 77 Confidential Page 23 falling edge of LEDCLK, and should be sampled by the rising edge of LEDCLK. LED data of port-23 are clocked out first, followed by port-22 down to port-0. All LED signals are low active. The signals in the LED interface is described in Table-6.10: Table-6.10: LED Interface Signals Name LEDVLD0 LEDVLD1 LEDCLK nLED0 nLED1 nLED2 nLED3 Page 24 of 77 Type O O O O O O Description LED signal valid 0 LED signal valid 1 2.5 MHz LED clock Dual purpose indicator Dual purpose indicator Dual purpose indicator O Dual purpose indicator Group 0 1 0 NA full duplex indication port speed (1=10Mbps,0=100Mbps) Link status Confidential Group 1 0 1 frame error indicator collision indication receiving activity transmit activity Page 24 Configuration Interface The default values of certain register bits are set by internal pull-high/pull-low 75K Ohm resistors. These default values can be overwritten by external pull-high/pull-low with 4.7K Ohm resistors. Table-6.11 lists all the available pins. The meanings of the register bits are described in the chapter of "Register Description." Table-6.11: Configuration Interface POS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name P20TXD0 P20TXD1 P21TXD0 P21TXD1 P17TXD0 P17TXD1 P18TXD0 P18TXD1 P20TXEN P21TXEN P17TXEN P18TXEN LEDCLK LEDVLD0 LEDVLD1 nLED3 nLED2 nLED1 nLED0 P15TXEN P12TXEN, P14TXEN P23TXEN P11TXEN P03TXEN P23TXD0 P23TXD1 P23TXD2 P23TXD3 P05TXEN P06TXEN P08TXEN P09TXEN P00TXD0 P00TXD1 P02TXD0 P02TXD1 P03TXD0 P03TXD1 P05TXD0 P05TXD1 P00TXEN P02TXEN Register Register-25 Register-16 Register-31 Register-30 Register-20 of the built-in ARL Bit# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 15 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 Default Table-7.25 Table-7.16 Table-7.31 Table-7.30 0 0 Note: POS41 and POS42 are belonging to Build-In ARL'S PosCfg Register (ARL Register 20). Page 25 of 77 Confidential Page 25 Other Interface Table-6.12: Other Signals Name CLK100 NRESET WCHDOG SYSERROR ZBTCLK CLKSEL, EN16P, TESTEN VDD VDDC VSS Type I I O O O I I I I Description 100 MHz clock input Hardware reset, low active Watch dog life pulse system error indication Factory use only Factory use only 3.3V power 2.5V power Ground The CLK100 should come from 100MHz clock oscillator, with 3.3Volt or 5Volt, 40/60 Duty Cycle, and 50 ppm accuracy. The nRESET is a low-active hardware reset pin. Assertion of this pin will cause the ACD82224 to go through a power-up initialization process. All registers are set to their default value after reset. The WCHDOG pin is used to handle exceptional cases. A normal working ACD82224 sends out continuous life pulses from the WCHDOG pin, which can be monitored by an external watchdog circuit. If no life pulse is detected, the external watchdog circuit may force reset of the switch system. It is a safeguard against unforeseeable situations. The SYSERROR is System error indication and it's high active. When there is any error occurs in SYSERR Register it's asserted to HIGH until the SYSERR Register been read. The CLKSEL, EN16P, and TESTEN are input pins for factory test use only. These three pins must be connected to ground directly. The ZBTCLK is output pin and also for factory use. Do not connect the ZBTCLK. Page 26 of 77 Confidential Page 26 7. REGISTER DESCRIPTION Registers in the ACD82224 are used to define the operational mode of various function modules of the switch controller and the peripheral devices. Default values at power-on are predefined. The management CPU (optional) can read the content of all registers and modify some of the registers to change the operational mode. Table-7.0.1 lists all the registers inside the switch controller. Table-7.0.1: Register List Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32~63 Name DEVID INTSRC SYSERR PAR PMERR ACT RSVD RSVD SAL SAH UTH BTH MAXL MAXH MINL MINH SYSCFG INTMSK SPEED LINK nFWD nBP nPORT PVID VPID POSCFG PAUSE DPLX RSVD nPM ERRMSK CLKADJ PHYREG Page 27 of 77 Type R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W Size 16 Bit 8 Bit 9 Bit 24 Bit 24 Bit 24 Bit 24 Bit 24 Bit 16 Bit 16 Bit 16 Bit 16 Bit 16 Bit 16 Bit 16 Bit 8 Bit 24 Bit 24 Bit 24 Bit 24 Bit 24 Bit 4 Bit 5 Bit 24 Bit 24 Bit 24 Bit 24 Bit 8 Bit 8 Bit 16 Bit Index 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 24 4 1 1 1 1 1 1 32 Confidential Description Device ID is 0601h Interrupt Source System Error Port Partition Indication PHY Management Error Port Activity Source Address, bit 23:0 Source Address, bit 47:24 Unicast Threshold Broadcast Threshold FCS of Max-Pause-Frame, bit 15:0 FCS of Max-Pause-Frame, bit 31:16 FCS of Mini-Pause-Frame, bit 15:0 FCS of Mini-Pause-Frame, bit 31:16 System Configuration Interrupt Mask Port Speed Port Link Port Forward Disable Port Back Pressure Disable Port Disable Port VLAN ID VLAN Dumping Port Power-On-Strobe Configuration Port Pause Frame Disable Port Duplex Mode Port PHY Management Disable Error Mask ARL Clock Delay Adjustment Registers in PHY device with ID is 0~31 Page 27 Many registers have particular bit designated to a particular port, so that the status of each port can be changed or monitored independently. The mapping of Register-Bit and Port-ID for each controller is listed in Table-7.0.2. Table-7.0.2: Register-Bit/Port-ID Mapping Register -Bit Port -ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Port Number ACD82224 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19 Port 20 Port 21 Port 22 Port 23 INTSRC register (register 1) The INTSRC register indicates the source of the interrupt request. Before the CPU starts to respond to an interrupt request, it should read this register to find out the interrupt source. This register is automatically cleared after each read. Table-7.1 lists all the bits of this register. Table-7.1: INTSRC Register Bit 0 1 2 3 4 5 6 7 Description System initialization completed System error occurred Port partition occurred ARL Interrupt Reserved Default 0 Note: The source interrupt for bit-3 ARL interrupt is referred to ARL Register-13. Page 28 of 77 Confidential Page 28 SYSERR register (register 2) The SYSERR register indicates the presence of system errors. It is automatically cleared after each read. Table-7.2 lists the system error reported. Table-7.2: SYSERR Register Bit 0 1 2 3 4 5 6 7 8 Description BIST failure indication Reserved Default 0 PAR register (register 3) The PAR register indicates the presence of the partitioned ports and the port ID. A port can be automatically partitioned if there is a consecutive false carrier event, an excessive collision or jabber. This register is automatically cleared after each read. Table-7.3 lists the bits of this register. Table-7.3: PAR Register Bit [0:23] Description 0 - Port X is not partitioned. 1 - Port X is partitioned. Default 0 PMERR register (register 4) The PMERR register indicates the presence of PHYs that have failed to respond to the PHY Management command issued through the MDIO line. This register is automatically cleared after each read. Table-7.4 describes the bits of this register. Table-7.4: PMERR Register Bit [0:23] Description 0 - Port X's PHY responded 1 - Port X's PHY failed to respond Default 0 ACT register (register 5) The ACT register indicates the presence of transmitting or receiving activities of each port since the register was last read. This register is automatically cleared after each read. Table-7.5 describes all the bits of this register. Table-7.5: ACT register Bit [0:23] Page 29 of 77 Description 0 - Port X no activity 1 - Port X has activity Confidential Default 0 Page 29 SAL & SAH register (register 8,9) The SAL and SAH registers together contain the complete Source Address for pause frame generation. SAL contains the least significant 24 bit of the MAC address. SAH contains the most significant 24 bit of the MAC address. The default locally managed source address for pause frame generation is FEh-FFh-FFh-FFh-FFh-FFh a. Table-7.8 and table-7.9 describes all the bits of these two registers. Table-7.8: SAL Register Bit 7:0 15:8 23:16 Description Bit 47:40 of the switch's MAC address. Bit 39:32 of the switch's MAC address. Bit 31:24 of the switch's MAC address. Default FEh FFh Table-7.9: SAH Register Bit 7:0 15:8 23:16 Description Bit 23:16 of the switch's MAC address. Bit 15:8 of the switch's MAC address. Bit 7:0 of the switch's MAC address. Default FFh UTH register (register 10) The UTH register contains the unicast buffer thresholds for each port. When the upper threshold is exceeded, the MAC may generate a Max-Pause-Frame. When the lower threshold is crossed, the MAC may generate a Mini-Pause-Frame. Table-7.10 describes each bit in this register. Table-7.10: UTH Register * Bit Description 7:0 Lower threshold of unicast utilization. 15:8 Higher threshold of unicast utilization. Total Frame Buffer Depth (52-bit wide word) 64K 128K 256K 512k 64K 128K 256K 512k Default* 2 4 8 16 4 8 24 64 Note: The value is related to the memory size specified by bit[9:8] of register 25. Page 30 of 77 Confidential Page 30 BTH register (register 11) The BTH register contains the broadcast queue buffer threshold for each port. When the upper threshold is exceeded, the MAC may generate a Max-Pause-Frame. When the lower threshold is crossed, the MAC may generate a Mini-Pause-Frame. Table-7.11 describes each bit in this register. Table-7.11: BTH Register Bit 7:0 15:8 Description Lower threshold of broadcast queue Higher threshold of broadcast queue Default 16 48 MINL & MINH register (register 12,13) The MINL and MINH registers together contain the 32-bit Frame Check Sequence (FCS) of the mini-pause-frame. MINL contains the least significant 16 bit of the FCS. MINH contains the most significant 16 bit of the FCS. The default FCS value assumes the default source address for the Mini-Pause-Frame. Table-7.12 and table-7.13 describe all the bits of these two registers. Table-7.12: MINL Register Bit 7:0 15:8 Description Bit 31:24 of the mini-pause-frame's FCS Bit 23:16 of the mini-pause-frame's FCS Default 89 O3 Description Bit 15:18 of the mini-pause-frame's FCS Bit 7:0 of the mini-pause-frame's FCS Default D7 A9 Table-7.13: MINH Register Bit 7:0 15:8 MAXL & MAXH register (register 14,15) The MAXL and MAXH registers together contain the 32-bit Frame Check Sequence (FCS) of the max-pause-frame. MAXL contains the least significant 16 bit of the FCS. MAXH contains the most significant 16 bit of the FCS. The default FCS value assumes the default source address for the Max-Pause-Frame. Table-7.14 and table-7.15 describe all the bits of these two registers. Table-7.14: MAXL Register Bit 7:0 15:8 Description Bit 31:24 of the max-pause-frame's FCS Bit 23:16 of the max-pause-frame's FCS Default 0D 68 Table-7.15: MAXH Register Bit 7:0 15:8 Page 31 of 77 Description Bit 15:8 of the max-pause-frame's FCS Bit 7:0 of the max-pause-frame's FCS Confidential Default D8 D0 Page 31 SYSCFG register (register 16) The SYSCFG register specifies certain system configurations. The system options are described in the chapter of "Function Description." Table-7.16 describes all the bits of this register. Table-7.16: SYSCFG Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description 0 - BIST enabled; 1 - BIST disabled. 0 - Spanning Tree support disabled; 1 - Spanning Tree support enabled 0 - External ARL result latched by rising edge; 1 - External ARL result latched by falling edge; Reserved. Reserved. 0 - wait for CPU. 1 - system ready to start *This bit is used by the CPU when bit-15 of register-25 is set as "0" (for system with control CPU). The system will wait for CPU to set this bit. Must set this bit before CPU programs any register. 0 - PHY Management not completed 1 - PHY Management completed. *This bit is used by the CPU when bit-15 of register-25 is set as "0" (for system with a control CPU). The MAC will not start until this bit is set by the CPU. 0 - Watchdog function enabled. 1 - Watchdog function disabled. 0 - Secure VLAN checking rule enforced. 1 - Leaky VLAN checking rule enforced. Reserved. 0 - Late Back-Pressure scheme disabled 1 - Late Back-Pressure scheme enabled *When enabled, the MAC will generate back-pressure only after reading the first bit of DA 0 - special handling of broadcast frames disabled 1 - special handling of broadcast frames enabled *When enabled, all broadcast frames from Port0~Port22 are forwarded to the Port23 only, and all broadcast frames from the Port23 are forwarded to all other ports. Default 0 Software Reset: Set "1" to start a system reset to initialize all state machines. It will not re-start PHY's Auto-Negotiation. Hardware Reset: Set "1" to stop the life pulse on the watchdog pin, which in turn will trigger the external watchdog circuitry to reset the whole system. Reserved 0 - Port 23 is MII 1 - Port 23 is RMII (POS shared with P03TXEN) 1 If the bit-19 of Register-25 is set (CPU start mode), ACD82224 will stop the initialized procedures after it is completed with self-test. CPU must set bit-5 of register-16 to enable access internal registers. CPU set bit-6 of register-16 to enable MAC and Queue manager. Then ACD82224 will start switching based on CPU's configuration. Page 32 of 77 Confidential Page 32 INTMSK register (register 17) The INTMSK register defines the valid interrupt sources allowed to assert interrupt request pin. Table-7.17 lists all the bits of this register. Table-7.17: INTMSK Register Bit 0 Description Enable "system initialization completion" to interrupt 1 Enable "internal system error" to interrupt 2 3 4 5 6 7 Enable "port partition event" to interrupt Enable "internal ARL" to interrupt Reserved Default 1 SPEED register (register 18) The SPEED register specifies or indicates the speed rate of each port. Table-7.18 describes all the bits of this register. These two modes are also applied to the SPEED (register-18), LINK (register-19), DPLX (register-27), PAUSE (register-26) register. (1) Automatic PHY management mode (default setting): These four registers controlled by ACD82224's PHY management Hardware update their status. To enable this mode if bit-16 of register-25 is cleared, and the corresponding bit (port) in nPM register (register-29) is cleared. (2) CPU mode: CPU sets these registers through UART interface. To enable this mode if bit-16 of register-25 is set, or the corresponding bit (port) in nPM register (register-29) is set. Table-7.18: SPEED Register Bit [0:23] Description 0 - Port X at 10Mbps 1 - Port X at 100Mbps Default 0 LINK register (register 19) The LINK register specifies or indicates the link status of each port. Table-7.19 describes all the bits of this register. Table-7.19: LINK Register Bit [0:23] Page 33 of 77 Description 0 - Port X link not established 1 - Port X link established Confidential Default 0 Page 33 nFWD register (register 20) The nFWD register defines the forwarding mode of each port. Under forwarding mode, a port can forward all frames. Under block-and-listen mode, a port will not forward regular frames, except BPDU frames. If the spanning tree algorithm discovers redundant links, the control CPU will allow only one link remaining in forwarding mode and force the other links into block-andlisten mode. Setting the associated bit in this register will put the port into block-and-listen mode. Table-7.20 describes all the bits of this register. Table-7.20: nFWD Register Bit [0:23] Description 0 - Port X in forwarding state. 1 - Port X in block-and-listen state. Default 0 nBP register (register 21) The nBP register defines backpressure flow control capability for each port. Table-7.21 describes all the bits of this register. Table-7.21: nBP Register Bit [0:23] Description 0 - Port X back-pressure scheme enabled 1 - Port X back pressure scheme disabled Default 0 nPORT register (register 22) The nPORT register is used to isolate ports from the network. Setting the associated bit in this register will stop a port from either receiving or transmitting any frame. Table-7.22 describes all the bits of this register. But, the source MAC address is still learned by ARL unless ARL nLearnReg is set for the specific port. Table-7.22: nPORT Register Bit [0:23] Page 34 of 77 Description 0 - Port X enabled 1 - Port X disabled Confidential Default 0 Page 34 PVID register (register 23) The PVID registers assign VLAN IDs for each port. There are 24 PVID registers, one for each port. A PVID consists of 4 bits, each corresponding bit mapping to one of the 4 VLANs. A port can belong to more than one VLAN at the same time. Table-7.23 describes all the bits of this register. Table-7.23: PVID Register Bit 0 1 2 3 Description 0- 1- 0- 1- 0- 1- 0- 1- port not in VLAN-I. port in VLAN-I. port not in VLAN-II. port in VLAN-II. port not in VLAN-III. port in VLAN-III. port not in VLAN-IV. port in VLAN-IV. Default Port 1~23 (index = 1~23) 1 Default Port 0 (index = 0) 1 0 1 0 1 0 1 VPID register (register 24) The VPID registers specify the dumping port for each VLAN. There are 4 VPID 5-bit registers, one for each VLAN. A valid VPID's ID is "0" through "23". Table-7.24 describes all the bits of this register. If the multiple VLANs are set, the dumping port for the associated VLAN has to be assigned correctly even bit-12 of register-25 is set (unknown DA forwarded to all ports). Table-7.24: VPID Registers (4 registers) VPID register VPID[0] VPID[1] VPID[2] VPID[3 Index 0 1 2 3 Bit 4:0 4:0 4:0 4:0 Description Dumping port ID for VLAN-1 Dumping port ID for VLAN-2 Dumping port ID for VLAN-3 Dumping port ID for VLAN-4 Default "00000" Port-0 POSCFG register (register 25) The POSCFG register specifies a certain configuration setting for the switch system. The default values of this register can be changed through pull-up/pull-down of specific pins, as described in the "Configuration Interface" section of the "Interface Description" chapter. Table-7.25 describes all the bits of this register. Page 35 of 77 Confidential Page 35 Table-7.25: POSCFG Register Bit 3:0 7:4 9:8 10 11 12 13 14 15 16 17 18 19 21:20 22 23 Description Default Shared Pin 0000 P21TXD1 ZBT SRAM Read Timing Adjustment P21TXD0 (16 levels within a 10 ns clock cycle, each delay unit adds P20TXD1 approximately 0.5-0.7 ns, "inversion" adds 5 ns or one half of P20TXD0 clock cycle to the delay) 0001 - no delay (From Bit3 0000 - inversion plus no delay 0011 - 1 units delay to Bit0) 0010 - inversion plus 1 units delay 0101 - 2 units delay 0100 - inversion plus 2 units delay 0110 - inversion plus 3 units delay 0111 - 3 units delay 1000 - inversion plus 4 units delay 1001 - 4 units delay 1010 - inversion plus 5 units delay 1011 - 5 units delay 1100 - inversion plus 6 units delay 1101 - 6 units delay 1110 - inversion plus 7 units delay 1111 - 7 units delay ZBT SRAM Clock Timing Adjustment 0000 P18TXD1 (16 levels within a 10 ns clock cycle, each delay unit adds P18TXD0 P17TXD1 approximately 0.5-0.7 ns, "inversion" adds 5 ns or one half of P17TXD0 clock cycle to the delay) 0101 - no delay 0100 - inversion plus no delay 0111 - 1 units delay 0110 - inversion plus 1 units delay 0000 - inversion plus 2 units delay 0001 - 2 units delay 0010 - inversion plus 3 units delay 0011 - 3 units delay 1100 - inversion plus 4 units delay 1101 - 4 units delay 1110 - inversion plus 5 units delay 1111 - 5 units delay 1000 - inversion plus 6 units delay 1001 - 6 units delay 1010 - inversion plus 7 units delay 1011 - 7 units delay 01 P21TXEN SRAM size selection: 00 - 64K words P20TXEN 01 - 128K words 10 - 256k words 11 - 512K words 0 - MDC latched by rising edge; 0 P17TXEN 1 - MDC latched by falling edge; 0 - Long Event defined as frame longer than 1518 byte. 1 P18TXEN 1 - Long Event defined as frame longer than 1530 byte. 0 - Frames with unknown DA forwarded to the dumping port. 0 LEDLCK 1 - Frames with unknown DA forwarded to all ports. 0 - Internal ARL selected (2K MAC address entry). 0 LEDVLD0 1 - External ARL selected (11K MAC address entry). 0 - PHY Ids start from 0, range from 1 to 23. 0 LEDCLD1 1 - PHY Ids start from 1, range from 0 to 24 0 - Re-transmit after excessive collision. 0 nLED3 1 - Drop after excessive collision. 0 - Automatic PHY Management enabled 0 nLED2 1 - Automatic PHY Management disabled: CPU need to update SPEED, LINK, DPLX and PAUSE registers 0 - Flow Control on broadcast queue utilization enabled 0 nLED1 1 - Flow control on broadcast queue utilization disabled: broadcast frames dropped if the queue is full 0 - System errors will trigger software reset 0 nLED0 1 - System errors will trigger hardware reset 0 - System will start by itself upon hardware reset 0 P15TXEN 1 - System will not start until bit-5/6 of register-16 is set 2-bit device ID for UART communication. The device responses 0 P14TXEN only to UART commands with matching ID P12TXEN 0- 1- 0- 1- Page 36 of 77 RMII TX's data is driven on falling edge RMII TX's data is driven on rising edge RMII RX's data is latched on rising edge RMII RX's data is latched on falling edge Confidential 1 P23TXEN 1 P11TXEN Page 36 PAUSE register (register 26) The PAUSE register defines the pause-frame based flow control capability of each port. Table7.26 describes all the bits of this register. Table-7.26: PAUSE Register Bit [0:23] Description 0 - Port X Pause-Frame disabled 1 - Port X Pause-Frame enabled Default 0 DPLX register (register 27) The DPLX register specifies or indicates the half/full-duplex mode of each port. Table-7.27 describes all the bits of this register. Table-7.27: DPLX Register Bit [0:23] Description 0 - Port X under half duplex mode 1 - Port X under full duplex mode Default 0 nPM register (register 29) The nPM register indicates the automatic PHY management capability of each port. If a bit is set in this register, the corresponding SPEED, LINK, DPLX, and PAUSE registers of the port will not be updated by Automatic PHY Management. Table-7.29 describes all the bits of this register. Table-7.29: nPM Register Bit [0:23] Description 0 - Port X's status update enabled 1 - Port X's status update disabled Default 0 ERRMSK register (register 30) The ERRMSK register defines certain errors as system errors. It is reserved for factory use only. Table-7.30 lists all the error masks specified by this register. Table-7.30: ERRMSK register Bit 0 1 2 3 4 5 6 7 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 1 1 1 1 1 1 1 1 Shared Pin P00TXD0 P00TXD1 P02TXD0 P02TXD1 P03TXD0 P03TXD1 P05TXD0 P05TXD1 CLKADJ register (register 31) The CLKADJ register defines the delay time of the ARLCLK relative to the transition edge of the data signals. The ARLCLK provides reference timing for supporting chips, such as the Page 37 of 77 Confidential Page 37 ACD80800 and the ACD80900, which need to snoop the data bus for certain activities. Table7.31 describes all the bits of this register. Table-7.31: CLKADJ Register Bit 3:0 5:4 7:6 Description ARL Clock Timing Adjustment: (16 levels within a 10 ns clock cycle, each delay unit adds approximately 0.5-0.7 ns, "inversion" adds 5 ns or one half of clock cycle to the delay) 0001 - no delay 0000 - inversion plus no delay 0011 - 1 units delay 0010 - inversion plus 1 units delay 0100 - inversion plus 2 units delay 0101 - 2 units delay 0110 - inversion plus 3 units delay 0111 - 3 units delay 1000 - inversion plus 4 units delay 1001 - 4 units delay 1010 - inversion plus 5 units delay 1011 - 5 units delay 1100 - inversion plus 6 units delay 1101 - 6 units delay 1110 - inversion plus 7 units delay 1111 - 7 units delay Write Data Window Width Adjustment (Approximately 0.7 ns per increment) 00 - Default 2.5 ns wide 01 - 1 units increment 10 - 2 units increment 11 - 3 units increment Write Data Window Location Adjustment (Approximately 1.25ns per increment) 00 - no delay 01 - 1 unit delay 10 - 2 units delay 11 - 3 units delay Default 0011 Shared Pin P23TXD3 P23TXD2 P23TXD1 P23TXD0 (From Bit3 to Bit0) 00 P06TXEN P05TXEN 00 P09TXEN P08TXEN PHYREG register (register 32-63) The PHYREG refers to the registers residing on the PHY devices. The ACD82224 provides a mirror access path for the control of CPU to access the registers on the PHYs. For detailed information about the PHY registers, please refer to the PHY data sheet. The register index is used by the ACD82224 to specify the PHY's internal registers. For example, register-36 with index-0 would refer to the control register (register-0) in the device of PHY's ID is 4. Table-7.24: PHY Registers PHYREG 32~63 Register 32 Register 33 Register 34 Register 35 .. .. Register 63 Page 38 of 77 Index 0~31 0~31 0~31 0~31 .. .. 0~31 Description PHY Management registers with PHY's ID is 0 PHY Management registers with PHY's ID is 1 PHY Management registers with PHY's ID is 2 PHY Management registers with PHY's ID is 3 .. .. PHY Management registers with PHY's ID is 31 Confidential Default PHY Default Value Page 38 8. PIN DESCRIPTIONS Figure-8.1: Pin Diagram/Bottom View 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AD AF AE Page 39 of 77 AB AC Y W V U T R P N M L K J H G F E D C B A AA Confidential Page 39 RMII Clock Interface Pin Name RMIICLK0 RMIICLK1 RMIICLK2 RMIICLK3 RMIICLK4 RMIICLK5 Location AC07 AF16 AE24 V24 J25 C23 I/O O Description Reduced MII clock (50 MHz) Description Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 ERRMSK REG Bit-0: Reserved (default high) Transmit data bit 1 ERRMSK REG Bit-1: Reserved (default high) Transmit enable ARL's POSCFG REG Bit-1: NOCPU mode (default low). Suggest pull-high with 4.7K resister to set NOCPU enabled. Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable ARL's POSCFG REG Bit-2: Reserved (default low). Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 ERRMSK REG Bit-2: Reserved (default high) Transmit data bit 1 ERRMSK REG Bit-3: Reserved (default high) Transmit enable Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 ERRMSK REG Bit-4: Reserved (default high) Transmit data bit 1 ERRMSK REG Bit-5: in: Reserved (default high) Transmit enable SYSCFG REG Bit-15: Port23 MII/RMII Selection. (default high) Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 RMII Interface (Port 0 ~ Port 22) Pin Name P00CRS_DV P00RXD0 P00RXD1 P00TXD0 Location AE10 AF10 AC10 AC09 I/O I I I I/O* P00TXD1 AD08 I/O* P00TXEN AD07 I/O* P01CRS_DV P01RXD0 P01RXD1 P01TXD0 P01TXD1 P01TXEN AE12 AF12 AD11 AD10 AF11 AE11 I I I O O I/O* P02CRS_DV P02RXD0 P02RXD1 P02TXD0 AD12 AE14 AC14 AC12 I I I I/O* P02TXD1 AF13 I/O* P02TXEN P03CRS_DV P03RXD0 P03RXD1 P03TXD0 AE13 AD14 AE16 AD15 AD13 O I I I I/O* P03TXD1 AE15 I/O* P03TXEN AF14 I/O* P04CRS_DV P04RXD0 P04RXD1 P04TXD0 P04TXD1 P04TXEN P05CRS_DV P05RXD0 P05RXD1 P05TXD0 AC17 AE18 AD17 AD16 AF17 AC15 AD18 AE20 AC19 AE19 I I I O O O I I I I/O* Page 40 of 77 Confidential Page 40 P05TXD1 AF19 I/O* P05TXEN AF18 I/O* P06CRS_DV P06RXD0 P06RXD1 P06TXD0 P06TXD1 P06TXEN AF21 AD20 AE22 AD19 AE21 AF20 I I I O O I/O* P07CRS_DV P07RXD0 P07RXD1 P07TXD0 P07TXD1 P07TXEN P08CRS_DV P08RXD0 P08RXD1 P08TXD0 P08TXD1 P08TXEN AC22 AF23 AD22 AD21 AE23 AF22 AD25 AD26 AC25 AF24 AE26 AD23 I I I O O O I I I O O I/O* P09CRS_DV P09RXD0 P09RXD1 P09TXD0 P09TXD1 P09TXEN AB23 AB24 Y23 AC26 AB25 AC24 I I I O O I/O* P10CRS_DV P10RXD0 P10RXD1 P10TXD0 P10TXD1 P10TXEN P11CRS_DV P11RXD0 P11RXD1 P11TXD0 P11TXD1 P11TXEN Y26 Y24 W25 AA26 Y25 AA24 V25 V26 U25 W26 W24 V23 I I I O O O I I I O O I/O* P12CRS_DV P12RXD0 P12RXD1 P12TXD0 P12TXD1 P12TXEN U24 R25 R26 U23 T25 U26 I I I O O I/O* Page 41 of 77 ERRMSK REG Bit-6 (default high) Transmit data bit 1 ERRMSK REG Bit-7 (default high) Transmit enable (default Low) CLKADJ REG Bit-4: Write Data Window Width Adjustment bit0 Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable (default low) CLKADJ REG Bit-5: Write Data Window Width Adjustment bit1 Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable CLKADJ REG Bit-6: Write Data Window Location Adjustment. bit-0 (default low) Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable CLKADJ REG Bit-7: Write Data Window Location Adjustment. bit-1 (default low) Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable POS REG Bit-23: RMII RX's data is latched on falling edge/rising edge(default high), Suggest pull-low with 4.7K resister. Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable (default low) Confidential Page 41 P13CRS_DV P13RXD0 P13RXD1 P13TXD0 P13TXD1 P13TXEN P14CRS_DV P14RXD0 P14RXD1 P14TXD0 P14TXD1 P14TXEN R24 N23 N26 R23 P26 P25 M26 L25 M24 M25 N24 P24 I I I O O O I I I O O I/O* P15CRS_DV P15RXD0 P15RXD1 P15TXD0 P15TXD1 P15TXEN L24 K26 K23 M23 K25 L26 I I I O O I/O* P16CRS_DV P16RXD0 P16RXD1 P16TXD0 P16TXD1 P16TXEN P17CRS_DV P17RXD0 P17RXD1 P17TXD0 G25 H23 G26 H26 J24 K24 F26 G24 E25 F25 I I I O O O I I I I/O* P17TXD1 G23 I/O* P17TXEN H24 I/O* P18CRS_DV P18RXD0 P18RXD1 P18TXD0 E23 D26 C25 F24 I I I I/O* P18TXD1 D25 I/O* P18TXEN E26 I/O* P19CRS_DV P19RXD0 P19RXD1 P19TXD0 P19TXD1 B24 A24 B23 C26 A25 I I I O O Page 42 of 77 POS REG Bit-20: 2-bit device ID bit-0 for UART communication. ACD82224 responses only to UART commands with matching ID. Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable (default low) POS REG Bit-21: 2-bit device ID bit-1for UART communication. The device responses only to UART commands with matching ID. Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit Enable (default low) POS REG Bit-19: system will start by itself upon hardware reset System will not start until bit-5/6 of register-16 is set . Carrier Sense/Receive Data Valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 (default low) POS REG Bit-4 ZBT SRAM Clock Timing Adjustment Bit-0 Transmit data bit 1 (default low) POS REG Bit-5: ZBT SRAM Clock Timing Adjustment Bit-1 Transmit enable (default low) POS REG Bit-10: Reserved Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 (default low) POS REG Bit-6: ZBT SRAM Clock Timing Adjustment Bit-2 Transmit data bit 1 (default low) POS REG Bit-7: ZBT SRAM Clock Timing Adjustment Bit-3 Transmit enable POS REG Bit-11: Long Event Defined As Frame Longer Than 1518/1530 Byte (default high) Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Confidential Page 42 P19TXEN P20CRS_DV P20RXD0 P20RXD1 P20TXD0 D24 A22 B21 C21 B22 O I I I I/O* P20TXD1 D22 I/O* P20TXEN A23 I/O* P21CRS_DV P21RXD0 P21RXD1 P21TXD0 C20 D18 A19 B20 I I I I/O* P21TXD1 A20 I/O* P21TXEN A21 I/O* P22CRS_DV P22RXD0 P22RXD1 P22TXD0 P22TXD1 P22TXEN B17 C18 A17 B18 A18 C19 I I I O O O Transmit enable Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 (default low) POS REG Bit-0 ZBT SRAM Read Timing Adjustment bit-0 Transmit data bit 1 (default low) POS REG Bit-1: ZBT SRAM Read Timing Adjustment bit-1 Transmit enable (default high) POS REG Bit-8: SRAM size selection bit-0 Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 (default low) POS REG Bit-2 ZBT SRAM Read Timing Adjustment bit-2 Transmit data bit 1 (default low) POS REG Bit-3: ZBT SRAM Read Timing Adjustment bit-3 Transmit enable (default low) POS REG Bit-9: SRAM size selection bit-1 Carrier Sense/Receive data valid Receive data bit 0 Receive data bit 1 Transmit data bit 0 Transmit data bit 1 Transmit enable MII Interface (Port 23) Pin Name P23CRS P23RXDV P23RXCLK P23RXERR P23RXD0 P23RXD1 P23RXD2 P23RXD3 P23COL P23TXEN D08 B15 A15 C16 A16 C17 B16 D17 C10 D13 Location I/O I I I I I I I I I I/O* P23TXCLK P23TXD0 D15 C13 I I/O* P23TXD1 D12 I/O* P23TXD2 C11 I/O* P23TXD3 D10 I/O* Description Carrier sense (Shared with RMII P23CRS_DV) Receive data valid Receive clock (25/2.5 MHz) Receive error Receive data bit 0(Shared with RMII P23RXD0) Receive data bit 1(Shared with RMII P23RXD1) Receive data bit 2 Receive data bit 3 Collision indication Transmit data valid (Shared with RMII P23TXEN) POS REG Bit-22: RMII TX's data is driven on falling edge/rising edge (default high). Suggest pull-low with 4.7K resister. Transmit clock (25/2.5 MHz) Transmit data bit 0 (Shared with RMII P23TXD0) CLKADJ REG Bit-0: ARL Clock Timing Adjustment bit-0 (default low). Transmit data bit 1(Shared with RMII P23TXD1) CLKADJ REG Bit-1: ARL Clock Timing Adjustment bit-1 (default low). Transmit data bit 2 CLKADJ REG Bit-2: ARL Clock Timing Adjustment bit-2 (default high). Transmit data bit 3 CLKADJ REG Bit-3: ARL Clock Timing Adjustment bit-3 (default high). PHY Management Interface Signals Pin Name MDC Page 43 of 77 Location AD04 I/O O Description PHY management clock (1.25MHz) Confidential Page 43 MDIO AC03 I/O PHY management data I O O CPU data input CPU data output CPU interrupt request CPU Interface Signals Name UARTDI UARTDO SWIRQ Type U03 T03 C06 Description ZBT SRAM Interface Pin Name DATA00 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 DATA34 DATA35 DATA36 DATA37 DATA38 DATA39 DATA40 DATA41 DATA42 DATA43 DATA44 DATA45 DATA46 DATA47 Page 44 of 77 Location F01 F02 G01 G02 H01 H02 J01 J02 K01 K02 L01 L02 M01 M02 N01 N02 P01 P02 R01 R02 T01 T02 U01 U02 V01 V02 W01 W02 Y01 Y02 AA01 AA02 AB01 AB02 AC01 AC02 AD01 AD02 AF02 AF03 AE03 AF04 AE04 AF05 AE05 AF06 AE06 I/O I/O Confidential Description Memory data bus Page 44 BE00 BE01 BE02 EOF Page 45 of 77 AF07 AF08 AE08 AF09 AE07 I/O I/O I/O I/O Confidential Byte enable Byte enable Byte enable End of frame Page 45 ADDR00 ADDR01 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 O Memory address bus nWE B03 B01 C02 C01 D02 D01 E01 E02 B07 A07 A03 B04 A04 B05 A05 B06 A06 B08 A08 C04 O nCS D03 O Write enable: 0=Write 1=Read Chip enable, low active ARL & MIB Interfaces Signals Pin Name SWDIR00 SWDIR01 SWSYNC K03 L03 E03 SWSTAT00 SWSTAT01 SWSTAT02 SWSTAT03 A14 A13 B13 A12 O SWRXCLK SWTXCLK ARLDI00 ARLDI01 A09 A11 G04 F03 O O I Page 46 of 77 Location I/O O O Confidential Description Data Direction Indicator : 00 = idle, 01 = receive, 10 = transmit, 11 = control Port synchronization: indicating when Port-0 is driving DAT[47:0] Data state indicator SWSTAT[3:0]: 0000 - Idle 0001 - First word (DA) 0010 - Second word (SA) 0011 - Third through last word 0100 - Filter Event 0101 - Drop Event 0110 - Jabber 0111 - False Carrier (receive) - Deferred Transmission (transmit) 1000 - Alignment error (receive) - Single Collision (transmit) 1001 - Flow Control (receive) - Multiple Collision (transmit) 1010 - Short Event (receive) - Excessive Collision (transmit) 1011 - Runt (receive) - Late Collision (transmit) 1100 - Symbol Error 1101 - FCS Error 1110 - Long Event 1111 - Reserved Receive Clock, used by ACD80800 and ACD80900 Transmit Clock, used by ACD80900 only ARL Data Input used by ACD80800 only: Returns 12-bit ARL look-up result to the switch: Page 46 ARLDI02 ARLDI03 * * H03 K04 * ARLDIV J04 Bit[11:7] - Source Port ID (0 - 23) Bit[6:5] - Look-up Result: 00 - reserved 01 - matched 10 - not matched 11 - forced discard Bit[4:0] - Destination Port ID (0 - 23) I ARL Data Input Valid: Assertion to indicate start of a new result on ARLDI[3:0]. Used by ACD80900 only. Description LED Signal Valid #0 (default low) POS REG Bit-13: Internal ARL Selected (2K MAC Address Entry)/ External ARL Selected (11K MAC Address Entry). LED Signal Valid #1 (default low) POS REG Bit-14: PHY IDs Start From 0 or 1 2.5 MHz LED Clock POS REG Bit-12: Frames With Unknown DA Forwarded To The Dumping Port OR all ports (default low). When LEDVLD1 Is High, It's Frame Error Indicator. POS REG Bit-18: System errors will trigger software/hardware reset. (default low) When LEDVLD1 Is High, It's full duplex Indication. When LEDVLD1 Is High, It's Collision Indication. POS REG Bit-17: Flow Control on broadcast queue utilization enable/disable. (default low) When LEDVLD0 Is High, It's Speed (1:10Mbps, 0: 100Mbps). When LEDVLD1 Is High, It's Receiving Activity. POS REG Bit-16: Automatic PHY Management Enabled/Disabled. (default low) When LEDVLD0 Is High, It's Link Status. When LEDVLD0 Is High, It's Transmit Activity. POS REG Bit-15: Re-Transmit After Excessive Collision/Drop after Excessive Collision. (default low) LED Interface Signals Pin Name LEDVLD0 W03 Location I/O I/O* LEDVLD1 Y04 I/O* LEDCLK V03 I/O* nLED0 R04 I/O* nLED1 R03 I/O* nLED2 N03 I/O* nLED3 P04 I/O* System Control interface Signals Pin Name CLK100 WCHDOG SYSERROR AB04 Y03 M03 I/O I O O nRESET TESTEN CLKSEL EN16P ZBTCLK AB03 D07 D20 AC05 P03 I I I I O Page 47 of 77 Location Description 100 MHz Main Clock input Watch dog life pulse. 2.5Mhz continuous clock. System error indication high active. When there is any error occurs in SYSERR REG, it's asserted to HIGH. Hardware reset, low active Factory used only. Connect to Ground. Factory used only. Connect to Ground. Factory used only. Connect to Ground. Factory used only. Not Connect Confidential Page 47 Table-8.1a: Pin List Sorted by Location ( 1 of 3 ) Location A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 Pin Name VSS VSS ADDR10 ADDR12 ADDR14 ADDR16 ADDR09 ADDR18 SWRXCLK PID2 SWTXCLK STAT3 STAT1 STAT0 P23RXCLK P23RXD0 P22RXD1 P22TXD1 P21RXD1 P21TXD1 P21TXEN P20CRS_DV P20TXEN P19RXD0 P19TXD1 VSS ADDR01 VSS ADDR00 ADDR11 ADDR13 ADDR15 ADDR08 ADDR17 PID4 PID3 PID1 PID0 STAT2 VDDQ P23RXDV P23RXD2 P22CRS_DV P22TXD0 VDD P21TXD0 P20RXD0 P20TXD0 P19RXD1 P19CRS_DV VSS VSS ADDR03 ADDR02 VSS new VDD SWIRQ VDDQ VDDQ VDD P23COL P23TXD2 VDDQ P23TXD0 I/O O O O O O O O O O O O O I I I O I I/O I/O I I/O I O O O O O O O O O O O O O I I I O I/O I I/O I I O O O O I I/O I/O POS Location C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D01 D02 D03 D04 D05 D06 3 D07 9 D08 D09 8 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E01 E02 E03 E04 E23 E24 2 E25 E26 0 F01 F02 F03 F04 F23 F24 F25 F26 G01 G02 G03 G04 G23 G24 G25 27 G26 H01 25 H02 Pin Name VDDQ VDD P23RXER P23RXD1 P22RXD0 P22TXEN P21CRS_DV P20RXD1 VDDQ MIICLK5 VSS P18RXD1 P19TXD0 ADDR05 ADDR04 nCS VSS VDDQ VDDQ TESTEN P23CRS VSS P23TXD3 VDDQ P23TXD1 P23TXEN VSS P23TXCLK VDDQ P23RXD3 P21RXD0 VSS CLKSEL VDDQ P20TXD1 VSS P19TXEN P18TXD1 P18RXD0 ADDR06 ADDR07 SWSYNC VDDQ P18CRS_DV VDD P17RXD1 P18TXEN DATA00 DATA01 ARLDI1 VDDQ VDDQ P18TXD0 P17TXD0 P17CRS_DV DATA02 DATA03 VDD ARLDI0 P17TXD1 P17RXD0 P16CRS_DV P16RXD1 DATA04 DATA05 I/O POS I I I O I I O I O O O O I I I/O 28 I/O I/O 26 22 O I I I I/O O I/O I O O O 1 7 I I I/O I/O I/O I I/O I/O I I/O I/O I I/O I I I I/O I/O 11 6 4 5 Table-8.1b: Pin List Sorted by Location ( 2 of 3 ) Page 48 of 77 Confidential Page 48 Location H03 H04 H23 H24 H25 H26 J01 J02 J03 J04 J23 J24 J25 J26 K01 K02 K03 K04 K23 K24 K25 K26 L01 L02 L03 L04 L11 L12 L13 L14 L15 L16 L23 L24 L25 L26 M01 M02 M03 M04 M11 M12 M13 M14 M15 M16 M23 M24 M25 M26 N01 N02 N03 N04 N11 N12 N13 N14 N15 N16 N23 N24 N25 N26 P01 Pin Name ARLDI2 VSS P16RXD0 P17TXEN VDDQ P16TXD0 DATA06 DATA07 VDDQ ARLDIV VSS P16TXD1 MIICLK4 VDD DATA08 DATA09 SWDIR0 ARLDI3 P15RXD1 P16TXEN P15TXD1 P15RXD0 DATA10 DATA11 SWDIR1 VDDQ VSS VSS VSS VSS VSS VSS VDDQ P15CRS_DV P14RXD0 P15TXEN DATA12 DATA13 SYSERR VDD VSS VSS VSS VSS VSS VSS P15TXD0 P14RXD1 P14TXD0 P14CRS_DV DATA14 DATA15 nLED2 VSS VSS VSS VSS VSS VSS VSS P13RXD0 P14TXD1 VDD P13RXD1 DATA16 Page 49 of 77 I/O I I I/O POS 10 O I/O I/O I O O I/O I/O O I I O O I I/O I/O O I I I/O I/O I/O O O I O I I/O I/O I/O I O I I/O 19 16 Location P02 P03 P04 P11 P12 P13 P14 P15 P16 P23 P24 P25 P26 R01 R02 R03 R04 R11 R12 R13 R14 R15 R16 R23 R24 R25 R26 T01 T02 T03 T04 T11 T12 T13 T14 T15 T16 T23 T24 T25 T26 U01 U02 U03 U04 U23 U24 U25 U26 V01 V02 V03 V04 V23 V24 V25 V26 W01 W02 W03 W04 W23 W24 W25 W26 Pin Name DATA17 ZBTCLK nLED3 VSS VSS VSS VSS VSS VSS VSS P14TXEN P13TXEN P13TXD1 DATA18 DATA19 nLED1 nLED0 VSS VSS VSS VSS VSS VSS P13TXD0 P13CRS_DV P12RXD0 P12RXD1 DATA20 DATA21 UARTDO VDDQ VSS VSS VSS VSS VSS VSS VDDQ VDDQ P12TXD1 VDD DATA22 DATA23 UARTDI VDD P12TXD0 P12CRS_DV P11RXD1 P12TXEN DATA24 DATA25 nLEDCLK VSS P11TXEN MIICLK3 P11CRS_DV P11RXD0 DATA26 DATA27 LEDVLD0 VDDQ VSS P11TXD1 P10RXD1 P11TXD0 Confidential I/O I/O O I/O POS I/O O O I/O I/O I/O I/O 21 15 17 18 O I I I I/O I/O O O I/O I/O I O I I I/O I/O I/O I/O I/O O I I I/O I/O I/O 20 12 23 13 O I O Page 49 Table-8.1c: Pin List Sorted by Location ( 3 of 3 ) Location Y01 Y02 Y03 Y04 Y23 Y24 Y25 Y26 AA01 AA02 AA03 AA04 AA23 AA24 AA25 AA26 AB01 AB02 AB03 AB04 AB23 AB24 AB25 AB26 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 Pin Name DATA28 DATA29 WCHDOG LEDVLD1 P09RXD1 P10RXD0 P10TXD1 P10CRS_DV DATA30 DATA31 VDD VDDQ VDDQ P10TXEN VDD P10TXD0 DATA32 DATA33 nRESET CLK100 P09CRS_DV P09RXD0 P09TXD1 VDDQ DATA34 DATA35 MDIO VSS EN16P VDDQ MIICLK0 VSS P00TXD0 P00RXD1 VDDQ P02TXD0 VSS P02RXD1 P04TXEN VDDQ P04CRS_DV VSS P05RXD1 VDD VDDQ P07CRS_DV VSS P09TXEN P08RXD1 P09TXD0 DATA36 DATA37 VSS MDC VDD VDDQ P00TXEN P00TXD1 VDD P01TXD0 P01RXD1 P02CRS_DV P03TXD0 P03CRS_DV P03RXD1 Page 50 of 77 I/O I/O I/O O I/O I I O I I/O I/O POS 14 O O I/O I/O I I I I O I/O I/O I/O I O I/O I 33 I/O 35 I O I I I I/O I O I/O I/O 32 O I/O I/O O I I I/O I I 41 34 37 Location AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Pin Name P04TXD0 P04RXD1 P05CRS_DV P06TXD0 P06RXD0 P07TXD0 P07RXD1 P08TXEN VSS P08CRS_DV P08RXD0 VSS VSS DATA40 DATA42 DATA44 DATA46 EOF BE1 VDDQ P00CRS_DV P01TXEN P01CRS_DV P02TXEN P02RXD0 P03TXD1 P03RXD0 VDDQ P04RXD0 P05TXD0 P05RXD0 P06TXD1 P06RXD1 P07TXD1 MIICLK2 VSS P08TXD1 VSS DATA38 DATA39 DATA41 DATA43 DATA45 DATA47 BE0 BE2 P00RXD0 P01TXD1 P01RXD0 P02TXD1 P03TXEN VDD MIICLK1 P04TXD1 P05TXEN P05TXD1 P06TXEN P06CRS_DV P07TXEN P07RXD0 P08TXD0 VSS VSS Confidential I/O O I I O I O I I/O POS 31 I I I/O I/O I/O I/O I/O I/O I O I I/O I I/O I I I/O I O I O O 42 38 39 O I/O I/O I/O I/O I/O I/O I/O I/O I O I I/O I/O O O I/O I/O I/O I O I O 36 24 29 40 30 Page 50 Table-8.2a: Pin List Sorted by Name ( 1 of 3 ) Pin Name ADDR00 ADDR01 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ARLDI0 ARLDI1 ARLDI2 ARLDI3 ARLDIV CLKSEL BE0 BE1 BE2 CLK100 DATA00 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 DATA34 DATA35 Page 51 of 77 I/O O O O O O O O O O O O O O O O O O O O I I I I I I I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O POS Location B03 B01 C02 C01 D02 D01 E01 E02 B07 A07 A03 B04 A04 B05 A05 B06 A06 B08 A08 G04 F03 H03 K04 J04 D20 AF08 AE08 AF09 AB04 F01 F02 G01 G02 H01 H02 J01 J02 K01 K02 L01 L02 M01 M02 N01 N02 P01 P02 R01 R02 T01 T02 U01 U02 V01 V02 W01 W02 Y01 Y02 AA01 AA02 AB01 AB02 AC01 AC02 Pin Name DATA36 DATA37 DATA38 DATA39 DATA40 DATA41 DATA42 DATA43 DATA44 DATA45 DATA46 DATA47 EN16P EOF LEDVLD0 LEDVLD1 MDC MDIO MIICLK0 MIICLK1 MIICLK2 MIICLK3 MIICLK4 MIICLK5 nCS nLED0 nLED1 nLED2 nLED3 nLEDCLK nRESET nWE P00CRS_DV P00RXD0 P00RXD1 P00TXD0 P00TXD1 P00TXEN P01CRS_DV P01RXD0 P01RXD1 P01TXD0 P01TXD1 P01TXEN P02CRS_DV P02RXD0 P02RXD1 P02TXD0 P02TXD1 P02TXEN P03CRS_DV P03RXD0 P03RXD1 P03TXD0 P03TXD1 P03TXEN P04CRS_DV P04RXD0 P04RXD1 P04TXD0 P04TXD1 P04TXEN P05CRS_DV P05RXD0 P05RXD1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O O I/O O O O O O O O I/O I/O I/O I/O I/O I O I I I I/O I/O I/O I I I O O O I I I I/O I/O I/O I I I I/O I/O I/O I I I O O O I I I Confidential POS Location AD01 AD02 AF02 AF03 AE03 AF04 AE04 AF05 AE05 AF06 AE06 AF07 AC05 AE07 13 W03 14 Y04 AD04 AC03 AC07 AF16 AE24 V24 J25 C23 D03 18 R04 17 R03 16 N03 15 P04 12 V03 AB03 C04 AE10 AF10 AC10 33 AC09 44 AD08 41 AD07 AE12 AF12 AD11 AD10 AF11 AE11 AD12 AE14 AC14 35 AC12 36 AF13 42 AE13 AD14 AE16 AD15 37 AD13 38 AE15 24 AF14 AC17 AE18 AD17 AD16 AF17 AC15 AD18 AE20 AC19 Page 51 Table-8.2b: Pin List Sorted by Name ( 2 of 3 ) Pin Name P05TXD0 P05TXD1 P05TXEN P06CRS_DV P06RXD0 P06RXD1 P06TXD0 P06TXD1 P06TXEN P07CRS_DV P07RXD0 P07RXD1 P07TXD0 P07TXD1 P07TXEN P08CRS_DV P08RXD0 P08RXD1 P08TXD0 P08TXD1 P08TXEN P09CRS_DV P09RXD0 P09RXD1 P09TXD0 P09TXD1 P09TXEN P10CRS_DV P10RXD0 P10RXD1 P10TXD0 P10TXD1 P10TXEN P11CRS_DV P11RXD0 P11RXD1 P11TXD0 P11TXD1 P11TXEN P12CRS_DV P12RXD0 P12RXD1 I/O I/O I/O I/O I I I O O I/O I I I O O O I I I O O I/O I I I O O I/O I I I O O O I I I O O I/O I I I P12TXD0 P12TXD1 P12TXEN P13CRS_DV P13RXD0 P13RXD1 P13TXD0 P13TXD1 P13TXEN P14CRS_DV P14RXD0 P14RXD1 P14TXD0 P14TXD1 P14TXEN P15CRS_DV P15RXD0 P15RXD1 P15TXD0 P15TXD1 P15TXEN P16CRS_DV P16RXD0 O O I/O I I I O O O I I I O O I/O I I I O O I/O I I Page 52 of 77 POS 39 40 29 30 31 32 23 20 21 19 Location AE19 AF19 AF18 AF21 AD20 AE22 AD19 AE21 AF20 AC22 AF23 AD22 AD21 AE23 AF22 AD25 AD26 AC25 AF24 AE26 AD23 AB23 AB24 Y23 AC26 AB25 AC24 Y26 Y24 W25 AA26 Y25 AA24 V25 V26 U25 W26 W24 V23 U24 R25 R26 U23 T25 U26 R24 N23 N26 R23 P26 P25 M26 L25 M24 M25 N24 P24 L24 K26 K23 M23 K25 L26 G25 H23 Pin Name P16RXD1 P16TXD0 P16TXD1 P16TXEN P17CRS_DV P17RXD0 P17RXD1 P17TXD0 P17TXD1 P17TXEN P18CRS_DV P18RXD0 P18RXD1 P18TXD0 P18TXD1 P18TXEN P19CRS_DV P19RXD0 P19RXD1 P19TXD0 P19TXD1 P19TXEN P20CRS_DV P20RXD0 P20RXD1 P20TXD0 P20TXD1 P20TXEN P21CRS_DV P21RXD0 P21RXD1 P21TXD0 P21TXD1 P21TXEN P22CRS_DV P22RXD0 P22RXD1 P22TXD0 P22TXD1 P22TXEN P23COL P23CRSDV/CRS P23RXCLK P23RXD0 P23RXD1 P23RXD2 P23RXD3 P23RXDV P23RXER P23TXCLK P23TXD0 P23TXD1 P23TXD2 P23TXD3 P23TXEN PID0 PID1 PID2 PID3 PID4 STAT0 STAT1 STAT2 STAT3 SWDIR0 I/O I O O O I I I I/O I/O I/O I I I I/O I/O I/O I I I O O O I I I I/O I/O I/O I I I I/O I/O I/O I I I O O O I I POS Location G26 H26 J24 K24 F26 G24 E25 4 F25 5 G23 10 H24 E23 D26 C25 6 F24 7 D25 11 E26 B24 A24 B23 C26 A25 D24 A22 B21 C21 0 B22 1 D22 8 A23 C20 D18 A19 2 B20 3 A20 9 A21 B17 C18 A17 B18 A18 C19 C10 D08 I I I I I I I O I/O I/O I/O I/O I/O O O O O O O O O O O A15 A16 C17 B16 D17 B15 C16 D15 C13 D12 C11 D10 D13 B12 B11 A10 B10 B09 A14 A13 B13 A12 K03 Confidential 25 26 27 28 22 Page 52 Table-8.2c: Pin List Sorted by Name ( 3 of 3 ) Pin Name SWIRQ SWRXCLK SWSYNC SWTXCLK SYSERR TESTEN UARTDI UARTDO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ ZBTCLK VDDQ VDDQ VDDQ VDDQ VSS VSS VSS VSS VSS VSS Page 53 of 77 I/O O O O O O I I O o POS Location C06 A09 E03 A11 M03 D07 U03 T03 AA03 AA25 AC20 AD05 AD09 AF15 B19 C05 C09 C15 E24 G03 J26 M04 N25 T26 U04 AA04 AA23 AB26 AC06 AC11 AC16 AC21 AD06 AE09 AE17 B14 C07 C08 C12 C14 C22 D05 D06 D11 D16 D21 E04 F04 F23 H25 J03 L04 L23 P03 T04 T23 T24 W04 A01 A02 A26 AC04 AC08 AC13 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS WCHDOG I/O O Confidential POS Location AC23 AD03 AD24 AE01 AE02 AE25 AF01 AF25 AF26 B02 B25 B26 C03 C24 D04 D09 D14 D19 D23 H04 J23 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N04 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 P23 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15 T16 V04 W23 Y03 Page 53 9. TIMING DESCRIPTION RFE_CLK RXD[1:0] t1 T# t1 t2 t2 Description: RXDV, RXD setup time RXDV, RXD hold time MIN 4 2 TYP - MAX - UNIT ns ns Figure-9.1a RMII Receive Timing Figure-9.1b: RMII Transmit Timing REF_CLK t1 t2 TXD[1:0] Page 54 of 77 Confidential T# Desciption t1 TXEN, TXD setup time Min T y p M a x Unit 4 - - ns t2 TXEN, TXD hold time 2 - - ns Page 54 Figure-9.2a MII Receive Timing RXCLK RXDV RXD[3:0] RXER t1 T# t1 t2 t2 Description: RX_DV, RXD, RX_ER setup time RX_DV, RXD, RX_ER hold time MIN 5 5 TYP - MAX - UNIT ns ns Figure-9.2b: MII Transmit Timing TXCLK t1 t2 TXEN TXD[3:0] Page 55 of 77 Confidential T# Desciption t1 TXEN, TXD setup time Min Typ Max 10 - - Unit ns t2 TXEN, TXD hold time 10 - - ns Page 55 Figure-9.3: PHY Management Read Timing t2 MDC MDIO t1 T# t1 t2 Description MDIO setup time MDC cycle MIN TYP MAX UNIT 0 300 ns 800 ns Figure-9.4: PHY Management Write Timing MDC t1 t2 t5 t3 t4 MDIO Page 56 of 77 T# Description MIN TYP MAX UNIT t1 MDC High time 360 - 440 ns t2 MDC Low time 360 - 440 ns t3 MDC period - 800 - ns t4 MDIO set up time 10 - - ns t5 MDIO hold time 10 - - ns Confidential Page 56 Figure-9.5: SRAM (ZBT) Read/Write Timing t1 MCLK t2 t3 t4 t5 nCE t6 nWE t7 A1 A2 A3 A4 ADDRESS t8 t13 t10 t9 Q1 Q2 D3 D4 DATA t11 t14 t12 t15 T# t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Page 57 of 77 Description: MIN Clock cycle time 10 Clock HIGH time 4 Clock LOW time 4 Chip Enable setup time 3 Chip Enable hold time 2 Read/Write setup time 3 Read/Write hold time 2 Address setup time 3 Address hold time 2 Clock to output data in Low-Z 1.5 Clock to output data valid Clock to output data invalid 1.5 Clock to output data in High-Z Input data setup time 3 Input data hold time 1 Confidential MAX 5 4 - UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Page 57 Figure-9.6: CPU Command Timing t4 t1 t2 idle state start stop bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit bit CPUDI stop bit t3 CPUDO bit bit stop 6 7 bit start bit0 bit T# Description t1 CPU idle time t2 C P U c o m m a n d b it time MIN TYP MAX 0 - - U N IT us 10 - 1000 us t3 Response time 0 - 20 ms t4 Command time - - 20 ms Figure-9.7: ARL Result Timing ARLCLK ARLDO DA1 DA2 t1 ARLDI Result2 Result1 t2 T# Page 58 of 77 t3 MIN TYP MAX UNIT t1 time between DAs Description 0 - - ns t2 time for ARL result 0 - 200 ns t3 time between results 0 - - ns Confidential Page 58 Figure-9.8: LED Signal Timing LEDCLK LEDVLD0 LEDVLD1 ER R nLED0 ER ER R R ER R ER R ER R nLED1 FD X FD X FD X FD X FD X FD CO CO CO X L L L CO CO CO L L L nLED2 SP D SP D SP D SP D SP D SP D RC RC RC V V V RC RC V V LNK LNK LNK XM XM XM T T T XM XM XM T T T nLED3 LNK LNK LNK P22 P23 P2 P21 P0 P1 P22 P23 P2 P21 RC V P0 P1 * P[7:0] time slots is not used for 82216 Page 59 of 77 Confidential Page 59 10. ELECTRICAL SPECIFICATION 10. ELECTRICAL SPECIFICATION Figure-10.1: Absolute Maximum Ratings Item DC supply voltage for Core DC supply voltage for I/O Input signal voltage Signal current DC output voltage Symbol VDD VDDQ Vin Ii/o Vo Rating 3.0 V 4.0 V 3.6 V 2.5mA 2.8V Figure-10.2 Recommended Operation Conditions Item DC supply voltage for Core DC supply voltage for I/O Operating temperature Maximum power consumption Page 60 of 77 Symbol VDD VDDQ Ta N/A Confidential Rating 2.5V 3.3V 0 - 70 C TBD Page 60 11. PACKAGING Top View 35 30 Advanced Comm. Devices FLLLLL SMAYYWW ACD822xx Side View 2.33 0.56 0.6 Bottom View 31.75 1.27 0.635 0.75 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 Page 61 of 77 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Confidential 17 18 19 20 21 22 23 24 25 26 Page 61 Appendix-A1 Address Resolution Logic Built-in ARL with 2048 MAC Addresses Page 62 of 77 Confidential Page 62 1. SUMMARY The internal Address Resolution Logic (ARL) of the switch controllers automatically builds up an address table and maps up to 2,048 MAC addresses for the associated ports. CPU intervention is not required in an UN-managed system. For a managed system, the management CPU can configure the operation mode of the ARL, learn all the addresses in the address table, add new addresses into the lookup table, control security or filtering feature of each address entry etc. The ARL high performance design guarantee very low latency and will never slow down the frame switching operation. It helps the switch controllers maintain wire speed forwarding rate under any type of traffic load. The 2K internal addresses space can be expanded to 11K entries by using the external ARL, ACD80800. Figure-1: Built-in ARL Block Diagram Address Learning Engine Address Aging Engine Control Registers Command Registers Data Registers External CPU Interface Address Registers Internal Switch Interface Address Lookup Engine CPU Interface Engine Address Table (2048 Entries) Page 63 of 77 Confidential Page 63 2. FEATURES * * * * * * * * * * * Supports up to 2,048 internal MAC address lookup Provides UART type of interface for management CPU Wire speed address lookup time. Wire speed address learning time. Address can be automatically learned from switch without external CPU intervention Address can be manually added by the CPU through CPU interface Each MAC address can be secured by the CPU from being changed or aged out Each MAC address can be marked by the CPU from receiving any frame Each newly learned MAC address is notified to the CPU Each aged out MAC address is notified to the CPU Automatic address aging control, with configurable aging period 3. FUNCTIONAL DESCRIPTION The internal ARL provides Address Resolution service for the switch controllers. Figure-1 is a block diagram of the ARL. Traffic Snooping All Ethernet frames received by the switch controller have to be stored into memory buffer. As the frame data are written into memory. The status of the data shown on the data bus is displayed by the switch controller through the SWSTAT[3:0] bus. The ARL interface with the Switch Controller contains the signals of the data bus and the state bus. By snoop the data bus and the state bus of the switch controller, the internal ARL can detect destination MAC address and source MAC address embedded inside each frame. Address Learning Each source MAC address extracted from the data bus, along with the ingress port ID, is passed to the Address Learning Engine of the ARL. 1. The Address Learning Engine first determines whether the frame is a valid frame. 2. For a valid frame, it will first try to find the source address from the current address table. 3. If that address is not listed, OR the port ID associated with the listed MAC address does not match the ingress port ID, it will be learned into the address table as a new address. 4. After an address is learned by the address learning engine, the CPU can be notified to read this newly learned address so that it can add it into the CPU's address table. 5. If the Address Table is full, Address Learning Engine will not learn any the new MAC address unless there is new entry available (i.e. Address aging-out). Address Aging After each source address is learned into the address table, it has to be refreshed at least once within each address aging period. Refresh means it is caught again from the switch interface. If it has not occurred for a pre-set aging period, the Address Aging Engine will remove the address from the address table. After an address is removed by the address aging engine, the CPU can be notified through interrupt request that it needs to read this aged out address so that it can remove this address from the CPU's address table. Page 64 of 77 Confidential Page 64 The default aging time is 300 seconds. That means Address Aging Engine checks the timer every 300 seconds from power up. If the new address is learned just after the aging-out checking process finished. The worst case aging time can be about 600 seconds. You can program the timer register through CPU interface (UART). The register is resided in Register18 and 19 of ARL. Address Lookup Each destination address is passed to the Address Lookup Engine of the ARL. The Address Lookup Engine checks if the destination address matches with any existing address in the address table. If it does, the ARL returns the associated Port ID to switch controller. Otherwise, a "no match" result is passed to switch controller. CPU Interface The CPU can access the registers of the ARL by sending commands to the UART data input line. Each command is consists of action (read or write), register type, register index, and data. Each result of command execution is returned to the CPU through the UART data output line. Registers The ARL provides a number of registers for the control CPU. Through these registers, the CPU can read all address entries of the address table, delete particular addresses from the table, add particular addresses into the table, secure an address from being changed, set filtering on some addresses, change the hashing algorithm etc. Through interrupt request signals, the CPU can be notified whenever it needs to retrieve data for a newly-learned address or an aged-out address so that the CPU can build an exact same address table learned by the ARL. CPU Interface Engine The command sent by the control CPU is executed by the CPU Interface Engine. For example, the CPU may send a command to learn the first newly learned address. The CPU Interface Engine is responsible to find the newly learned address from the address table, and passes it to the CPU. The CPU may request to learn next newly learned address. And the CPU Interface Engine starts to search for next newly learned address from the address table. Address Table The address table can hold up to 2,048 MAC addresses, together with the associated port ID, security flag, filtering flag, new flag, aging information etc. The address table resides in the embedded SRAM inside the built-in ARL. Page 65 of 77 Confidential Page 65 4. INTERFACE DESCRIPTION CPU Interface The CPU can communicate with the ARL through the UART interface of the switch controller. The management CPU can send commands to the ARL by writing into associated registers, and retrieve result from the ARL by reading out of the corresponding registers. The registers are described in the section on "Register Description." The CPU interface signals are described by table-1: Table-1: CPU Interface Name UARTDI UARTDO I/O I O Description UART input data line. UART output data line. UARTDI is used by the control CPU to send commands into the ARL. The baud rate will be automatically detected by the ARL. The result is returned through the UARTDO line with the detected baud rate. The format of the command packet is shown as follows: A command sent by the CPU through the CPUDI line consists of 7 octets. Command frames transmitted on CPUDI have the format shown below: ARL CPUDI Format Operation Write Read Command 0100XX11 0100XX01 Address A[7:0] A[7:0] Data D[31:0] D[31:0] Checksum C[7:0] C[7:0] The byte order of data in all fields follows the big-endian convention, i.e. most significant octet first. The bit order is the least significant order first. The Command octet specifies the type of the operation. The Bit-7, bit-6, and bit-5 of the command octet are specified the Device Type. (1) Switch Controller, the device type is 001. (2) ARL Controller, the device type is 010. (3) Management Controller, the device type is 100. The Bit-2, and bit-3 of the command octet are used to specify the device ID of the chip which is shared with ACD82224 device ID (ACD82224 bit 20 and bit 21 of Register 25). The address octet specifies the number of the register. For write operation, the Data field is a 4-octet value to specify what to write into the register. For read operation, the Data field is a 4-octet 0 as padded data. If the data of register is less than 32-bit, it is align to bit-0 of Data field. The checksum value is an 8-bit value of exclusive-OR of all octets in the frame, starting from the Command octet. For each valid command received, the ARL will always send a response. Response from the ARL is sent through the CPUDO line. Response frames sent by the ACD82224 have the following format: ARL UARTDO (Response) Format Response Write Page 66 of 77 Command 0100XX11 Address A[7:0] Confidential Data D[31:0] Checksum C[7:0] Page 66 Read 0100XX01 A[7:0] D[31:0] C[7:0] For response to a read operation, the Data field is a 4-octet value to indicate the content of the register. For response to a write operation, the Data field is 32 bits of 0. If the data of register is less than 24-bit, it is align to bit-0 of Data field. The checksum value is an 8-bit value of exclusive-OR of all octets in the response frame, starting from the Command octet. The ARL will always check the command header to see if both the device type and the device ID matches with its setting. If not, it ignores the command and does not generate any response to this command. 5. REGISTER DESCRIPTION The built-in ARL provides a number of registers for the CPU to access the address table. Commands are sent to ARL by writing into the associated registers. Before the CPU can pass a command to ARL, it must check the Result register (Register-11) for execution status of the previous command. The CPU may need to retrieve the previous result before sending new command. Then the CPU will write the new command parameters into the Data Registers, and the command type into the Command Register. The ARL will then reset the Result Register to 0. The Result register will indicate the completion of the command at the end of the execution. Before the completion of the execution, any command written into the command register is ignored by the ARL. The registers accessible to the CPU are described by table-2: Table-2: Register Description Reg. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Register Name DataReg0 DataReg1 DataReg2 DataReg3 DataReg4 DataReg5 DataReg6 DataReg7 AddrReg0 AddrReg1 CmdReg RsltReg CfgReg IntSrcReg IntMskReg nLearnReg0 nLearnReg1 nLearnReg2 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Size 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 5 Bit 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 8 Bit 18 19 20 AgeTimeReg0 AgeTimeReg1 PosCfg R/W R/W R/W 8 Bit 8 Bit 3 Bit Page 67 of 77 Description Byte 0 of data Byte 1 of data Byte 2 of data Byte 3 of data Byte 4 of data Byte 5 of data Byte 6 of data Byte 7 of data LSB of address value MSB of address value Command register Result register Configuration register Interrupt source register Interrupt mask register Address learning disable register for port 0 - 7 Address learning disable register for port 8 - 15 Address learning disable register for port 16 - 23 LSB of aging period register MSB of aging period register Power On Strobe configuration register Confidential Page 67 DataReg0 ~ DataReg7 (Register 0 ~ Register 7) The DataReg[0:7] are registers used to pass the command parameters to the ARL, and the execution results to the CPU. ARL only stores 47-bit of MAC address, the first bit of the first Byte (MSB) is not stored in ARL table (this bit to indicate broadcast/multicast frame). The data in Data register 0 is shift left one bit compared to the MAC MSB. For example, if the MAC address is "08-00-12-34-56-78", DataReg-0 is stored the value of "04" instead of "08". AddrReg0 and AddrReg1 (Register 8 and Register 9) The AddrReg[0:1] are used to specify the address associated with the command. CmdReg (Register 10) The CmdReg is used to pass the type of command to the ARL. The command types are listed in table-3. The details of each command are described in the chapter of "Command Description." Table-3: Command List Command 0x09 Description Add the specified MAC address into the address table 0x0A Set a lock for the specified MAC address 0x0B Set a filtering flag for the specified MAC address 0x0C Delete the specified MAC address from the address table 0x0D Assign a port ID to the specified MAC address 0x10 0x11 0x20 0x21 0x30 0x31 0x40 0x41 0x50 0x51 0x60 0x61 0x80 0x81 Read the first entry of the address table Read next entry of address book Read first valid entry Read next valid entry Read first new entry Read next new entry Read first aged entry Read next aged entry Read first locked entry Read next locked entry Read first filtered entry Read next filtered entry Read first entry with specified PID Read next entry with specified PID 0xFF ARL reset Page 68 of 77 Confidential Page 68 RstReg (Register 11) The RstReg is used to indicate the status of command execution. The result code is listed as follows: Bit 3:0 4 Description 4-bit error code 0000 - No error 0001 - Cannot find the specified entry Other - Errors Command completed. 0 - Execution has been started but not yet completed 1 - Execution has been completed, Must check Bit[3:0], any error occurring. Default 0000 0 CfgReg (Register 12) The CfgReg is used to configure the ARL functions. The bit definition of CfgReg is described as: Bit 0 1 2 3 7:4 Description Disable address aging Disable address lookup NA NA Hashing algorithm selection Default 0 0 0 0 0000 IntSrcReg (Register 13) The IntSrcReg is used to indicate what can cause interrupt request to CPU. The source of interrupt is listed as: Bit 0 1 2 3 4 5 6 7 Description Aged address exists New address exists Reserved Reserved Bucket overflowed Command is done System initialization is completed Self test failure Default 0 0 0 0 0 1 1 0 IntMskReg (Register 14) The IntMskReg is used to enable an interrupt source to generate an interrupt request. The bit definition is the same as IntSrcReg. A 1 in a bit enables the corresponding interrupt source to generate an interrupt request once it is set. Bit Page 69 of 77 Description Confidential Default Page 69 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 Aged address exists New address exists Reserved Reserved Bucket overflowed Command is done System initialization is completed Self test failure nLearnReg0 ~ nLearnReg2 (Register 15 ~ Register 17) The nLearnReg[2:0] are used to disable address learning activity from a particular port. If the bit corresponding to a port is set, the ARL will not try to learn new addresses from that port. The nLearnReg0/1/2 are bit-to-port mapping registers. The bit[0:7] of nLearnReg0 is represented by port[0:7]. The bit[0:7] of nLearnReg1 is represented by port[8:15]. The bit[0:7] of nLearnReg2 is represented by port[16:23]. AgeTimeReg0 and AgeTimeReg1 (Register 18 and Register 19) The AgeTimeReg[1:0] are used to specify the period of address aging control. The aging period can be from 0 to 65535 units, with each unit counted as 2.684 second. The default age time is 300 seconds. To make the new setting age period effective, CPU must send "ARL Reset" (0xff, see ARL Table-3) command to ARL after configuring the new AgeTimeReg[1:0] and set the bit-0 of Register-20 to one to wake up ARL engine PosCfgReg (Register 20) The PosCfgReg is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin. The bits of PosCfgReg0 is listed as follows: Bit 0 1 2 Description Reserved NOCPU 0 - Wait for CPU 1 -ARL initializes by itself Reserved Default Shared Pin 0 0 NA P00TXEN 0 P02TXEN Note: If NOCPU is set to 0, the ARL will not start the initialization process until Bit-1 of PosCfgReg is set to 1. 6. COMMAND DESCRIPTION Command 09H Description: Add the specified MAC address into the address table. Page 70 of 77 Confidential Page 70 Parameter: Store the MAC address into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the associated port number into DataReg6. Result: the MAC address will be stored into the address table if there is space available. The result is indicated by the Result register. Command 0AH Description: Set the Lock bit for the specified MAC address. Parameter: Store the MAC address into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Result: the state machine will seek for an entry with matched MAC address, and set the Lock bit of the entry. The result is indicated by the Result register. Command 0BH Description: Set the Filter flag for the specified MAC address. Parameter: Store the MAC address into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Result: the state machine will seek for an entry with matched MAC address, and set the Filter bit of the entry. The result is indicated by the Result register. Command 0CH Description: Delete the specified MAC address from the address table. Parameter: Store the MAC address into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Result: the MAC address will be removed from the address table. The result is indicated by the Result register. Command 0DH Description: Assign the associated port number to the specified MAC address. Parameter: Store the MAC address into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the port number into DataReg6. Result: the port ID field of the entry containing the specified MAC address will be changed accordingly. The result is indicated by the Result register. Command 10H Description: Read the first entry of the address table. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of the first entry of the address book will be stored into the Data registers. The MAC Page 71 of 77 Confidential Page 71 address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC * address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7.The Read Pointer will be set to point to second entry of the address book. Note - the Flag bits are defined as: b7 Rsvd Where * * * * * * * b6 Rsvd b5 Filter b4 Lock b3 New b2 Old b1 Age b0 Valid Filter - 1 indicates the frame heading to this address should be dropped. Lock - 1 indicates the entry should never be changed or aged out. New - 1 indicates the entry is a newly learned address. Old - 1 indicates the address has been aged out. Age - 1 indicates the address has not been visited for current age cycle. Valid - 1 indicates the entry is a valid one. Rsvd - Reserved bits. Command 11H Description: Read next entry of address book. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of the address book entry pointed by Read Pointer will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer will be increased by one. Command 20H Description: Read first valid entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first valid entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 21H Description: Read next valid entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next valid entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 Page 72 of 77 Confidential Page 72 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 30H Description: Read first new entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first new entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Page 73 of 77 Confidential Page 73 Command 31H Description: Read next new entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next new entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 40H Description: Read first aged entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first aged entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 41H Description: Read next aged entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next aged entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 50H Description: Read first locked entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first locked entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Page 74 of 77 Confidential Page 74 Command 51H Description: Read next locked entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next locked entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 60H Description: Read first filtered entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first filtered entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 61H Description: Read next valid entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next filtered entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 80H Description: Read first entry with specified port number. Parameter: Store port number into DataReg6. Result: The result is indicated by the Result register. If the command is completed with no error, the content of first entry of the address book with the said port number will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Page 75 of 77 Confidential Page 75 Command 81H Description: Read next valid entry. Parameter: Store port number into DataReg6. Result: The result is indicated by the Result register. If the command is completed with no error, the content of next entry from the Read Pointer of the address book with the said port number will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command FFH Description: ARL reset. Parameter: None Result: This command will reset the ARL. All entries of the address book will be cleared and set the bit-0 of Register-20 to one to wake up ARL engine Page 76 of 77 Confidential Page 76