M 65656MATRA MHS
Rev. C (09/08/95) 1
Description
The M 65656 is a very low power CMOS static RAM
organized as 32768 × 8 bits. It is manufactured using the
MHS high performance CMOS technology named
SCMOS.
W ith this process, MHS is the first to bring the solution for
applications where fast computing is as mandatory as low
consumption, such as aerospace electronics, portable
instruments or embarked systems.
Using an array of six transistors (6T) memory cells, the
M 65656 combines an extremely low standby supply
current (Typical value = 0.1 µA) with a fast access time
at 40 ns. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
Extra protection against heavy ions is given by the use of
an epitaxial layer of a P substrate.
For military/space applications that demand superior
levels of performance and reliability the M 65656 is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
Access time
commercial : 35(*), 40, 45, 55 ns
industrial automotive and military : 40(*), 45, 55 ns
Very low power consumption
active : 50 mW (typ)
standby : 0.5 µW (typ)
data retention : 0.4 µW (typ)
(*) Preliminary. Consult sales.
Wide temperature range : –55 to + 125°C
300 and 600 mils width package
TTL compatible inputs and outputs
Asynchronous
Single 5 volt supply
Equal cycle and access time
Gated inputs : no pull-up/down
resistors are required
Interface
Block Diagram
32 K × 8 Ultimate CMOS SRAM
M 65656 MATRA MHS
Rev. C (09/08/95)2
Pin Configuration
Side Brazed 600/300 mils 28 pins
SOIC/SOJ 300 mils 28 pins
CDIL 600 mils 28 pins
Multilayer Flat Pack 28 pins
(Top View)
Pin Names
A0-A14 : Address inputs CS : Chip-Select
I/O0-I/O7 : Input/Output W : Write Enable
VCC : Power OE : Output Enable
GND : Ground
Truth Table
CS W OE INPUTS/
OUTPUTS MODE
H X X Z Deselect/
POWER-DOWN
L H L DATA OUT Read
L L X DATA IN Write
L H H Z Output Disable
L = low, H = high, X = H or L, Z = high impedance
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : -0.3 V to + 7.0 V. . . . . . . . . . . . . . .
Input or Output voltage applied : (Gnd – 0.3 V) to (Vcc + 0.3 V). . . . .
Storage temperature : –65 oC to + 150 oC. . . . . . . . . . . . . . . . . . . . . . .
Electro static discharge voltage > 2000 V (MIL STD 883,. . . . . . . . . .
METHOD 3015)
Operating Range
OPERATING VOLTAGE OPERATING TEMPERATURE
Military VCC = 5 V ± 10 % – 55 _C to + 125 _C
Automotive VCC = 5 V ± 10 % – 40 _C to + 125 _C
Industrial VCC = 5 V ± 10 % – 40 _C to 85 _C
Commercial VCC = 5 V ± 10 % 0 _C to 70 _C
DC Operating Conditions
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
Vcc Supply voltage 4.5 5.0 5.5 V
Gnd Ground 0.0 0.0 0.0 V
VIL (1) Input low voltage – 0.3 0.0 0.8 V
VIH(1) input high voltage 2.2 – Vcc + 0.3 V
Note : 1. VIH max = Vcc + 0.3 V, VIL min = –0.3 V or –1.0 pulse 50 ns.
M 65656MATRA MHS
Rev. C (09/08/95) 3
Capacitance
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
Cin (2) Input capacitance – – 8 pF
Cout (2) Output capacitance – – 8 pF
Note : 2. TA = 25°C, f = 1 MHz, Vcc = 5.0 V, these parameters are not tested.
DC Parameter
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
IIX (3) Input leakage current – 1.0 – 1.0 µA
IOZ(3) Output leakage current – 1.0 – 1.0 µA
VOL (4) Output low voltage – – 0.4 V
VOH (4) Output high voltage 2.4 – – V
Notes : 3. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output disabled.
4. Vcc min, IOL = 4 mA, IOH = –1.0 mA.
Consumption for Commercial Specification
SYMBOL PARAMETER M 65656
L–35(*) M 65656
V–35(*) M 65656
L – 40 M 65656
V – 40 M 65656
L – 45 M 65656
V – 45 M 65656
L – 55 M 65656
V – 55 UNIT VALUE
ICCSB
(5) Standby supply
current 10 5 10 5 10 5 10 5 mA max
ICCSB1
(6) Standby supply
current 75 5 75 5 75 5 75 5 µA max
ICCOP
(7) Operating supply
current 90 70 90 70 90 70 90 70 mA max
Consumption for Industrial Specification
SYMBOL PARAMETER M 65656
L – 40(*) M 65656
V – 40(*) M 65656
L – 45 M 65656
V – 45 M 65656
L – 55 M 65656
V – 55 UNIT VALUE
ICCSB
(5) Standby supply
current 10 5 10 5 10 5 mA max
ICCSB1
(6) Standby supply
current 100 10 100 10 100 10 µA max
ICCOP
(7) Operating supply
current 90 70 90 70 90 70 mA max
Consumption for Automotive and Military Specification
SYMBOL PARAMETER M 65656
L – 40(*) M 65656
V – 40(*) M 65656
L – 45 M 65656
V – 45 M 65656
L – 55 M 65656
V – 55 UNIT VALUE
ICCSB
(5) Standby supply
current 10 5 10 5 10 5 mA max
ICCSB1
(6) Standby supply
current 500 100 500 100 500 100 µA max
ICCOP
(7) Operating supply
current 90 70 90 70 90 70 mA max
Notes : 5. CS ≥ VIH, Vin ≥ VIH or Vin ≤ VIL.
6. CS ≥ Vcc – 0.3 V, Iout = 0 mA. Vin ≥ Vcc – 0.3 V or Vin ≤ 0.3 V.
7. Vcc max, Iout = 0 mA, Vin = Gnd/Vcc. Duty cycle 100 %, F = 5 MHz, derating = 10 mA/MHz.
(*) Preliminary. Please consult sales.
M 65656 MATRA MHS
Rev. C (09/08/95)4
Data Retention Mode
MHS CMOS RAM’s are designed with battery backup in
mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules insure
data retention :
1. Chip select (CS) must be held high during data
retention ; within Vcc to Vcc – 0.2 V.
2. Output Enable (OE) should be held high to keep the
RAM outputs high impedance, minimizing power
dissipation.
3. CS must be kept between Vcc -0.3 V and 70 % of Vcc
during the power up and power down transitions.
4. The RAM can begIn operation > 45 ns after Vcc
reaches the minimum operating voltage (4.5 V).
Timing
Data Retention Characteristics
PARAMETER DESCRIPTION MINIMUM TYPICAL (8) MAXIMUM UNIT
VCCDR Vcc for data retention 2.0 – – V
TCDR Chip deselect to data retention
time 0.0 – – ns
TR Operation recovery time TAVAV (9) – – ns
ICCDR1 (10) Data retention current COM IND AUTO
and
MIL
@ 2.0 V : M-65656 V
M-65656 L –
–0.1
0.1 3
60 8
80 80
300 µA
µA
ICCDR2 (10) Data retention current
@ 3.0 V : M-65656 V
M-65656 L –
–0.3
0.3 4
70 9
90 90
400 µA
µA
Notes : 8. TA = 25°C.
9. TAVAV = Read cycle time.
10. CS = Vcc, Vin = Gnd/Vcc, this parameter is only tested at Vcc = 2 V.
M 65656MATRA MHS
Rev. C (09/08/95) 5
AC Parameters
AC Conditions
Input pulse levels : Gnd to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input rise : 5 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input timing reference levels : 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output load : See fig. 1a, 1b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Cycle : Commercial Specification (note 12)
SYMBOL PARAMETER M 65656
L/V – 35(*) M 65656
L/V – 40 M 65656
L/V – 45 M 65656
L/V – 55 UNIT VALUE
TAVAV Write cycle time 35 40 45 55 ns min
TAVWL Address set-up time 0 0 0 0 ns min
TAVWH Address valid to end of write 30 30 35 40 ns min
TDVWH Data set-up time 20 22 25 25 ns min
TELWH CS low to write end 30 30 35 40 ns min
TWLQZ (11) Write low to high Z 15 15 15 20 ns max
TWLWH Write pulse width 30 30 35 40 ns min
TWHAX Address hold to end of write 0 0 0 0 ns min
TWHDX Data hold time 0 0 0 0 ns min
TWHQX (11) Write high to low Z 0 0 0 0 ns min
Write Cycle : Industrial Automotive and Military Specification (note 12)
SYMBOL PARAMETER M 65656
L/V – 40(*) M 65656
L/V – 45 M 65656
L/V – 55 UNIT VALUE
TAVAV Read cycle time 40 45 55 ns min
TAVWL Address set-up time 0 0 0 ns min
TAVWH Address valid to end of write 30 35 40 ns min
TDVWH Data set-up time 22 25 25 ns min
TELWH CS low to write end 30 35 40 ns min
TWLQZ (11) Write low to high Z 15 15 20 ns min
TWLWH Write pulse width 30 35 40 ns min
TWHAX Address hold to end of write 0 0 0 ns min
TWHDX Data hold time 0 0 0 ns min
TWHQX (11) Write high to low Z 0 0 0 ns min
Notes : 11. Specified with CL = 5 pF (see figure 1b). Guaranteed. Not tested.
(*) Preliminary. Consult sales.
M 65656 MATRA MHS
Rev. C (09/08/95)6
Write Cycle 1 : W Controlled (note 12)
Write Cycle 2 : CS Controlled (note 12)
Note : 12. The internal write time of the memory is defined by the overlap of CS LOW and W LOW. Both signals must be LOW to initiate a
write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the
rising edge of the signal that terminates the write.
Data out is high impedance if OE = VIH.
AC Test Loads and Waveforms
Figure 1
aFigure 1 b Figure 2
Equivalent to : THEVENIN EQUIVALENT
M 65656MATRA MHS
Rev. C (09/08/95) 7
Read Cycle : Commercial Specification
SYMBOL PARAMETER M 65656
L/V – 35(*) M 65656
L/V – 40 M 65656
L/V – 45 M 65656
L/V – 55 UNIT VALUE
TAVAV Write cycle time 35 40 45 55 ns min
TAVQV Address access time 35 40 45 55 ns max
TAVQX Address valid to low Z 5 5 5 5 ns min
TELQV Chip-select access time 35 40 45 55 ns max
TELQX(13) CS low to low Z 5 5 5 5 ns min
TEHQZ(13) CS high to high Z 15 15 15 15 ns max
TGLQV Output Enable access time 18 20 20 25 ns max
TGLQX(13) OE low to low Z 5 5 5 5 ns min
TGHQZ(13) OE high to high Z 15 15 15 20 ns max
Read Cycle : Industrial Automotive and Military Specification
SYMBOL PARAMETER M 65656
L/V – 40(*) M 65656
L/V – 45 M 65656
L/V – 55 UNIT VALUE
TAVAV Read cycle time 40 45 55 ns min
TAVQV Address access time 40 45 55 ns max
TAVQX Address valid to low Z 5 5 5 ns min
TELQV Chip-select access time 40 45 55 ns max
TELQX(13) CS low to low Z 5 5 5 ns min
TEHQZ(13) CS high to high Z 15 15 15 ns max
TGLQV Output Enable access time 20 20 25 ns max
TGLQX(13) OE low to low Z 5 5 5 ns min
TGHQZ(13) OE high to high Z 15 15 20 ns max
Notes : 13. Specified with CL = 5 pF (see figure 1b). Guaranteed but not tested.
(*) Preliminary. Consult sales.
M 65656 MATRA MHS
Rev. C (09/08/95)8
Read Cycle nb 1 (notes 14, 15)
Read Cycle nb 2 (notes 14, 16)
Notes : 14. W is high for read cycle.
15. Device is continuously selected CS & OE = VIL.
16. Address valid prior to or coincident with CS transition low.
M 65656MATRA MHS
Rev. C (09/08/95) 9
Ordering Information
C = Commercial 0°to +70°C
I = Industrial –40°to +85°C
A = Automotive –40°to +125°C
M = Military –55°to +125°C
S = Space –55 °to +125°C
1I = 28 pins DIL CERAMIC 600 mils
CI = 28 pins DIL SIDE-BRAZED 600 mils
CP = 28 pins DIL SIDE-BRAZED 300 mils
DP = 28 pins Multilayers flat pack
TI = 28 pins SOIC 300 mils
UI = 28 pins SOJ 300 mils
32K × 8
STATIC RAM
blank = MHS standards
/883 = MIL STD 883 Class B or S
P883 = MIL STD 883 + PIND test
SB/SC = SCC 9000 level B/C
SHXXX = Special customer request
FHXXX = Flight models (space)
EHXXX = Engineering models (space)
MHXXX = Mechanical parts (space)
LHXXX = Life test parts (space)
: R = Tape and reel
: RD = Tape and reel dry pack
: D = Dry pack
35 ns
40 ns
45 ns
55 ns
V = Very low power
L = Low power
The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication
and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
