74ALVC373D,112 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74ALVC373 is an octal D-type transparent latch featuring separate D-type inputs for

each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input

and an outputs enable (OE) input are common to all latches.

When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this

condition, the latches are transparent, that is, a latch output will change each time its

corresponding D-input changes. When pin LE is LOW, the latches store the information

that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of

pin LE.

When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins

Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.

Operation of input pin OE does not affect the state of the latches.

The 74ALVC373 is functionally identical to the 74ALVC573, but has a different pin

arrangement.

2. Features

■Wide supply voltage range from 1.65 V to 3.6 V

■3.6 V tolerant inputs/outputs

■CMOS low power consumption

■Direct interface with TTL levels (2.7 V to 3.6 V)

■Power-down mode

■Latch-up performance exceeds 250 mA

■Complies with JEDEC standards:

◆JESD8-7 (1.65 V to 1.95 V)

◆JESD8-5 (2.3 V to 2.7 V)

◆JESD8B/JESD36 (2.7 V to 3.6 V)

■ESD protection:

◆HBM JESD22-A114E exceeds 2000 V

◆MM JESD22-A 115-A exceeds 200 V

74ALVC373

Octal D-type transparent latch; 3-state

Rev. 02 — 18 October 2007 Product data sheet

Product data sheet Rev. 02 — 18 October 2007 2 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74ALVC373D −40 °Cto+85°C SO20 plastic small outline package; 20 leads;

body width 7.5 mm SOT163-1

74ALVC373PW −40 °Cto+85°C TSSOP20 plastic thin shrink small outline package; 20 leads;

body width 4.4 mm SOT360-1

74ALVC373BQ −40 °Cto+85°C DHVQFN20 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 20 terminals;

body 2.5 ×4.5 ×0.85 mm

SOT764-1

Fig 1. Logic symbol Fig 2. IEC logic symbol

mna881

11 1

mna880

1EN

11 C1

1D 2

Fig 3. Functional diagram

mna882

3-STATE

OUTPUTS

LATCH

1 to 8

Q7 19

Product data sheet Rev. 02 — 18 October 2007 3 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

Fig 4. Logic diagram (one latch)

Fig 5. Logic diagram

mna189

mna883

LELELE

LE LE LE LE

Product data sheet Rev. 02 — 18 October 2007 4 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

5. Pinning information

5.1 Pinning

5.2 Pin description

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

a supply pin or input.

Fig 6. Pin conﬁguration SO20 and TSSOP20 Fig 7. Pin conﬁguration DHVQFN20

373A

OE VCC

Q0 Q7

D0 D7

D1 D6

Q1 Q6

Q2 Q5

D2 D5

D3 D4

Q3 Q4

GND LE

001aad090

001aad089

373A

Transparent top view

D2 D5

Q2 Q5

Q1 Q6

D1 D6

D0 D7

Q0 Q7

GND

VCC

912

8 13

7 14

6 15

GND(1)

5 16

4 17

3 18

2 19

terminal 1

index area

Table 2. Pin description

Symbol Pin Description

D[0:7] 3, 4, 7, 8, 13, 14, 17, 18 data input

LE 11 latch enable input (active HIGH)

OE 1 output enable input (active LOW)

Q[0:7] 2, 5, 6, 9, 12, 15, 16, 19 3-state latch output

VCC 20 supply voltage

GND 10 ground (0 V)

Product data sheet Rev. 02 — 18 October 2007 5 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

6. Functional description

[1] H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition

X = don’t care

Z = High-impedance OFF-state

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.

[3] For SO20 packages: above 70 °C derate linearly with 8 mW/K.

For TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.

For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.

Table 3. Functional table[1]

Operating modes Input Internal latch Output

OE LE Dn Qn

Enable and read register

(transparent mode) LHLLL

LHHHH

Latch and read register L L l L L

LLhHH

Latch register and disable

outputs HXXXZ

HLhHZ

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +4.6 V

IIK input clamping current VI<0V −50 - mA

VIinput voltage −0.5 +4.6 V

IOK output clamping current VO>V

CC or VO<0V - ±50 mA

VOoutput voltage output HIGH or LOW state [1] [2] −0.5 VCC + 0.5 V

output 3-state −0.5 +4.6 V

power-down mode, VCC = 0 V [2] −0.5 +4.6 V

IOoutput current VO= 0 V to VCC -±50 mA

ICC supply current - 100 mA

IGND ground current −100 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb =−40 °C to +85 °C[3] - 500 mW

Product data sheet Rev. 02 — 18 October 2007 6 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 1.65 3.6 V

VIinput voltage 0 3.6 V

VOoutput voltage output HIGH or LOW state 0 VCC V

output 3-state 0 3.6 V

power-down mode; VCC = 0 V 0 3.6 V

Tamb ambient temperature in free air −40 +85 °C

∆t/∆V input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V

VCC = 2.7 V to 3.6 V - 10 ns/V

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC --V

VCC = 2.3 V to 2.7 V 1.7 - - V

VCC = 2.7 V to 3.6 V 2.0 - - V

VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V

VCC = 2.3 V to 2.7 V - - 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 V

VOH HIGH-level output voltage VI=V

IH or VIL

IO=−100 µA; VCC = 1.65 V to 3.6 V VCC −0.2 - - V

IO=−6 mA; VCC = 1.65 V 1.25 1.51 - V

IO=−12 mA; VCC = 2.3 V 1.8 2.10 - V

IO=−18 mA; VCC = 2.3 V 1.7 2.01 - V

IO=−12 mA; VCC = 2.7 V 2.2 2.53 - V

IO=−18 mA; VCC = 3.0 V 2.4 2.76 - V

IO=−24 mA; VCC = 3.0 V 2.2 2.68 - V

VOL LOW-level output voltage VI=V

IH or VIL

IO= 100 µA; VCC = 1.65 V to 3.6 V - - 0.2 V

IO= 6 mA; VCC = 1.65 V - 0.11 0.3 V

IO= 12 mA; VCC = 2.3 V - 0.17 0.4 V

IO= 18 mA; VCC = 2.3 V - 0.25 0.6 V

IO= 12 mA; VCC = 2.7 V - 0.16 0.4 V

IO= 18 mA; VCC = 3.0 V - 0.23 0.4 V

IO= 24 mA; VCC = 3.0 V - 0.30 0.55 V

IIinput leakage current VCC = 3.6 V; VI= 3.6 Vor GND - ±0.1 ±5µA

Product data sheet Rev. 02 — 18 October 2007 7 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25°C.

10. Dynamic characteristics

IOZ OFF-state output current VI=V

IH or VIL; VCC = 1.65 V to 3.6 V;

VO= 3.6 Vor GND; -±0.1 ±10 µA

IOFF power-off leakage supply VCC = 0 V; VIor VO= 0 V to 3.6 V - ±0.1 ±10 µA

ICC supply current VCC = 3.6 V; VI=V

CC or GND;

IO=0A - 0.2 10 µA

∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V;

VI=V

CC −0.6 V; IO=0A - 5 750 µA

CIinput capacitance - 3.5 - pF

Table 6. Static characteristics

…continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

tpd propagation delay Dn to Qn; see Figure 8 [2]

VCC = 1.65 V to 1.95 V 1.0 2.5 5.4 ns

VCC = 2.3 V to 2.7 V 1.0 2.0 3.5 ns

VCC = 2.7 V 1.0 2.3 3.6 ns

VCC = 3.0 V to 3.6 V 1.0 2.2 3.3 ns

LE to Qn; see Figure 9

VCC = 1.65 V to 1.95 V 1.0 2.8 6.0 ns

VCC = 2.3 V to 2.7 V 1.0 2.1 3.8 ns

VCC = 2.7 V 1.0 2.4 3.7 ns

VCC = 3.0 V to 3.6 V 1.0 2.3 3.3 ns

ten enable time OE to Qn; see Figure 10 [2]

VCC = 1.65 V to 1.95 V 1.5 3.0 6.4 ns

VCC = 2.3 V to 2.7 V 1.0 2.4 4.5 ns

VCC = 2.7 V 1.5 3.0 4.6 ns

VCC = 3.0 V to 3.6 V 1.0 2.3 4.0 ns

tdis disable time OE to Qn; see Figure 10 [2]

VCC = 1.65 V to 1.95 V 1.5 3.4 7.0 ns

VCC = 2.3 V to 2.7 V 1.0 2.2 4.4 ns

VCC = 2.7 V 1.5 2.8 4.4 ns

VCC = 3.0 V to 3.6 V 1.0 2.7 4.4 ns

Product data sheet Rev. 02 — 18 October 2007 8 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

[1] Typical values are measured at Tamb =25°C

[2] tpd is the same as tPHL and tPLH.

ten is the same as tPZH and tPZL.

tdis is the same as tPHZ and tPLZ.

[3] CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:

fi= input frequency in MHz; fo= output frequency in MHz

CL= output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL×VCC2×fo) = sum of the outputs

tWpulse width LE pulse width HIGH; see Figure 9

VCC = 1.65 V to 1.95 V 3.8 1.0 - ns

VCC = 2.3 V to 2.7 V 3.3 0.8 - ns

VCC = 2.7 V 3.3 2.0 - ns

VCC = 3.0 V to 3.6 V 3.3 2.2 - ns

tsu set-up time Dn to LE; see Figure 11

VCC = 1.65 V to 1.95 V 0.8 0.1 - ns

VCC = 2.3 V to 2.7 V 0.8 0.1 - ns

VCC = 2.7 V 0.8 0.1 - ns

VCC = 3.0 V to 3.6 V 0.8 0.1 - ns

thhold time Dn to LE; see Figure 11

VCC = 1.65 V to 1.95 V 0.8 −0.1 - ns

VCC = 2.3 V to 2.7 V 0.8 −0.2 - ns

VCC = 2.7 V 0.8 −0.3 - ns

VCC = 3.0 V to 3.6 V 0.7 −0.1 - ns

CPD power dissipation

capacitance per latch; VI = GND to VCC; VCC = 3.3 V [3]

outputs HIGH or LOW state - 35 - pF

outputs 3-state - 14 - pF

Table 7. Dynamic characteristics

…continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

Product data sheet Rev. 02 — 18 October 2007 9 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 8. Input Dn to output Qn propagation delay times

mna884

Dn input

Qn output

tPHL tPLH

GND

VOH

VOL

Table 8. Measurement points

Supply voltage VCC VMOutput

VxVy

1.65 V to 1.95 V 0.5VCC VOL + 0.15 V VOH − 0.15 V

2.3 V to 2.7 V 0.5VCC VOL + 0.15 V VOH − 0.15 V

2.7 V 1.5 V VOL + 0.3 V VOH − 0.3 V

3.0 V to 3.6 V 1.5 V VOL + 0.3 V VOH − 0.3 V

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 9. Latch enable (LE) pulse width and latch enable input to output (Qn) propagation delays

mna885

LE input

Qn output

tPHL tPLH

VOH

GND

VOL

Product data sheet Rev. 02 — 18 October 2007 10 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 10. Enable and disable times

mna395

tPLZ

tPHZ

outputs

disabled outputs

enabled

outputs

enabled

Qn output

LOW-to-OFF

OFF-to-LOW

Qn output

HIGH-to-OFF

OFF-to-HIGH

OE input

VOL

VOH

VCC

GND

tPZL

tPZH

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predicable output performance.

Fig 11. The data set-up and hold times for Dn input to LE input

mna887

tsu

GND

LE input

Dn input

Product data sheet Rev. 02 — 18 October 2007 11 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

Test data is given in Table 9.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 12. Test circuitry for switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aae331

VEXT

VCC

VIVO

DUT

Table 9. Test data

Supply voltage Input Load VEXT

VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩopen 2 × VCC GND

2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ωopen 2 × VCC GND

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen 6 V GND

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen 6 V GND

Product data sheet Rev. 02 — 18 October 2007 12 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

12. Package outline

Fig 13. Package outline SOT163-1 (SO20)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 13.0

12.6 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT163-1

detail X

0.25

075E04 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.51

0.49 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

vMA

(A )

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-27

03-02-19

Product data sheet Rev. 02 — 18 October 2007 13 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

Fig 14. Package outline SOT360-1 (TSSOP20)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 6.6

6.4 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.5

0.2 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT360-1 MO-153 99-12-27

03-02-19

0.25

110

20 11

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

max.

1.1

Product data sheet Rev. 02 — 18 October 2007 14 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

Fig 15. Package outline SOT764-1 (DHVQFN20)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.6

4.4

3.15

2.85

2.6

2.4 1.15

0.85

3.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT764-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT764-1

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

19 12

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Product data sheet Rev. 02 — 18 October 2007 15 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74ALVC373_2 20071018 Product data sheet - 74ALVC373_1

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 3: DHVQFN20 package added.

•Section 7: derating values added for DHVQFN20 package.

•Section 12: outline drawing added for DHVQFN20 package.

74ALVC373_1 20020226 Product speciﬁcation - -

Product data sheet Rev. 02 — 18 October 2007 16 of 17

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

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General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

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NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

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grant, conveyance or implication of any license under any copyrights, patents

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15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74ALVC373

Octal D-type transparent latch; 3-state

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 October 2007

Document identifier: 74ALVC373_2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 6

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

15.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

16 Contact information. . . . . . . . . . . . . . . . . . . . . 16

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17