TDC1147 7 INV Monolithic Video A/D Converter 7-Bit, 15Msps The TDC1147 is a 7-bit flash analog-to-digital converter which has no pipeline delay between sampling and valid data. The output data register normally found on flash A/D converters has been bypassed, allowing data to transfer directly to output drivers from the encoding logic section of the circuit. The converter requires only one clock pulse to perform the complete conversion operation. The conversion time is guaranteed to be less than 60 nanoseconds. The TDC1147 is function and pin-compatible with TRW's TDC1047 7-bit flash A/D converter which has an output data register. The TDC1147 will operate accurately at sampling rates up to 15Msps and has an analog band- width of 7MHz. Linearity errors are guaranteed to be less than 0.4% over the operating temperature range. Features No Digital Pipeline Delay e 7-Bit Resolution @ 1/2 LSB Linearity Sample-And-Hold Circuit Not Required TTL Compatible e Selectable Output Format Available In 24 Pin CERDIP Applications Low-Cost Video Digitizing Medical Imaging Data Acquisition High Resolution A/D Converters Telecommunications Systems Radar Data Conversion Functional Block Diagram NMINV }- NLINV conv }_________. ><] Rr > f $ > hg > Y "g < > >1 4 > ~ e e e e ~ e Y R 127707 7 ENCODER d > az $ [> e e > \ Na < ng i Py ns LK > > Ry > Re) . DIFFERENTIAL BY COMPARATORS (127) 241 TRW LSI Products tne. PO. Box 2472 1a Jolla, CA 92038 TRW Inc. 1990 40G01900 Rev. E11/90 Printed in the U.S.A. Phone: (619) 457-1000 FAX: (619) 455-6314 CmTDC1147 arte Pin Assignments Vin 198 24 Vin Rr 2 23 Rp Agnp 3 22 AGND Denn 4 21 Deno NMINV 5 20 CONV (MSB) D, 6 19 D7 (LSB) Do 7 18 Dg D3 8 17 Ds Dy 9 2 1B Vee Vec 10 15 NLINV Veg 11 14 Veg Agap 12 13 Agno 24 Pin CERDIP B7 Package Functional Description General Information The TDC1147 has two functional sections: a comparator array and encoding logic. The comparator array compares the input signal with 127 reference voltages to produce an N-of-127 code (sometimes referred to as a ther- mometer code, as all the comparators referred to voltages more positive than the input signal will be off, and those referred to voltages more negative than the input signal will be on}. The encoding logic converts the N-of-127 code into binary or offset two's complement coding, and can invert either output code. This coding function is controlled by DC signals on pins NMINV and NLINV. Power The TDC1147 operates from two supply voltages, +5.0V and 5.2V. The return path for Iec (the current drawn from the +5.0V supply) is Dayp. The return path for ig (the current drawn fram the 5.2V supply) is AGNp.- All power anc ground pins must be connected. Reference The TDC1147 converts analog signals in the range VRBSViINSVazT into digital form. Vap (the voltage applied to the pin at the bottom of the reference resistor chain} and Vat (the voltage applied to the pin at the top of the reference resistor chain) should be between +0.1V and 1.1V. Vay should be more positive than Vag within that range. The voltage applied across the reference resistor chain (VpT-Vpp) must be between 0.8V 242 and 1.2V. The nominal voltages are VpT=0.00V and Vpp=1.00V. These voltages may be varied dynamically up to 7MHz. Due to slight variations in the reference current with clock and input signals, R7 and Rp should be low-impedance points. For circuits in which the reference is not varied, a bypass capacitor to ground is recommended. If the reference inputs are varied dynamically as in an Automatic Gain Control {AGC) circuit, a low-impedance reference source is recommended. Controls Two function control pins, NMINV and NLINV are provided. These controls are for DC (i.e., steady state} use. They permit the output coding to be either straight binary or offset two's complement, in either true or inverted sense, according to the Output Coding Table. Convert The TDC1147 uses a CONVert (CONV) input signal to initiate the A/D conversion process. Unlike other flash A/D converters which have a one-clock-cycle pipeline delay between sampling and output data, the TDC1147 requires only a single pulse to perform the entire conversion operation. The analog input is sampled {comparators are latched) within the maximum Sampling Time Offset (tsto, see Figure 1} Data from that sample becomes valid after a maximum Output Delay Time (tp) while data from the previous sample is held at the outputs for a minimum Output Hold Time (ty). This allows data from the TDC1147 to be acquired by an external register or other circuitry. Note that there are minimum time requirements for the HIGH and LOW portions (tpyyy. tpyy_! of the CONV waveform and all output timing specifications are measured with respect to the rising edge of CONV. Analog Input The TDC1147 uses latching comparators which cause the input impedance to vary slightly with the signal level. For optimal performance, both Vij pins must be used and the source impedance of the driving circuit must be less than 30 Ohms. The input signal will not damage the TDC1147 if it remains within the range of Ver to +0.5V. If the input signal is between the Vay and VaR references, the output will be a binary number between Q and 127 inclusive. A signal outside this range will indicate either full-scale positive or full-scale negative, depending on whether the signal is off-scale in the positive or negative direction. TRW LSI Products Inc.TDC1147 itv Outputs The outputs of the TDC1147 are TTL compatible, and signal. New data becomes valid after a maximum time capable of driving four low-power Schottky TTL (54/74 {tp) after the rising edge of the CONV signal. The use of LS} unit loads. The outputs hold the previous data a 2.2 kOhm pull-up resistors is recommended. minimum time (tyo) after the rising edge of the CONV Package Interconnections Signal Signal Qu Type Name Function Value B7 Package Pins Power Vec Positive Supply Voltage +5,0V 10, 16 Vee Negative Supply Voltage ~5.2V 11, 14 Deno Digital Ground 0.0V 4,21 AGND Analog Ground 0.0V 3, 12, 13, 22 Reference Ry Reference Resistor (Top) 0.00V 2 Rp Reference Resistor (Bottom) 1.00V 23 Controls NMINV Not Most Significant Bit INVert TTL 5 NLINV Not Least Significant Bit INVert TTL 15 Convert CONV Convert TTL 20 Analog Input VIN Analog Signal Input OV to -1V 1, 24 Outputs Dy MSB Output TTL 6 Dy TTL 7 D3 TTL 8 Dy TTL 9 Ds TTL 17 Dg TTL 18 D7 LSB Output TTL 19 TRW LSI Products Inc. 243TDC1147 arte Figure 1. Timing Diagram _ , | SAMPLE | SAMPLE N ANALOG INPUT | - sto N+1 | DATA \ / DATA DATA DATA tho a-] | er tp Figure 2. Simplified Analog Input Equivalent Circuit Vin o I VIN 1-OF-127 Pin C I COMPARATORS IN CB | v I y RB REFERENCE FEA RESISTOR VEE CHAIN 3 Ciy IS A NONLINEAR JUNCTION CAPACITANCE Vap IS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN Rg Figure 3. Digital Input Equivalent Circuit Vcc > 22K INPUT 15K t}-Hdee-4ne 244 Figure 4. Output Circuits +Vec Vec j 8100 TO 4 -- OUTPUT ) PIN zx QUTPUT A0pe =. 13062 x OUTPUT EQUIVALENT LOAD 1 = CIRCUIT TEST LOAD FOR DELAY + MEASUREMENTS TRW LSI Products Inc.TDC1147 WAC 7 IXVY Absolute maximum ratings (beyond which the device may be damaged) | i Supply Voltages Vcc ( d to Deno! -05 to +7.0V Veg (measured to Agyp) +05 to -7.0V Agno (measured to Ogyp} -0.5 to +0.6V Input Voltages CONV, NMINV, NLINV (measured to Dgnp) -0.5 to +5.5V Vine rt: Vp (measured to Agyp) +0.5 to Ver Vpt (measured to Vpp) +22 to -2.2V Output Applied vottage ( d to Deno) -05 to 55V2 Applied current, externally forced -1.0 to 6.0mA34 Short circuit duration (single output in high state to ground} 1 sec Temperature Operating, case -55 to +126C junction +175C Lead, soldering (10 seconds) +300C Storage -65 to +150C Notes: 1. Absolute maximum ratings are limiting values applied individually while all ather parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied veltage must be current limited to specified range. 3. Forcing valtage must be limited to specified range. 4. Current is specified as positive when flowing into the device. Operating conditions ee ee Temperature Range Standard Extended Parameter Test Conditions Min Nom Max Min Nom Max Units Voc Positive Supply Voltage (measured to Dep! 475 5.0 5.25 45 5.0 55 V Ver Negative Supply Voltage (measured to Agyn) -49 -62 -55 -49 -2 -5 V VaGND Analog Ground Voltage (measured to Ogyp) -0.1 0.0 0.1 -0.1 0.0 01 V tpwe CONV Pulse Width, LOW 22 22 ns tpwH CONV Pulse Width, HIGH 18 18 ns Vit Input Voltage, Logic LOW 08 08 v Vin Input Voltage, Logic HIGH 2.0 2.0 v lor Output Current, Logic LOW 40 2.0 mA lou Output Current, Logic HIGH -04 -04 mA Vat Most Positive Reference Input ~O1 0.0 0.1 -0.1 0.0 0.1 v Veg Most Negative Reference Input ! -09 -10 1 -09 -10 11 v Vat-Vap Voltage Reference Differential 08 10 12 08 1.0 12 v Vin Input Voltage Vee Vat Vep Vat Vv Ty Ambient Temperature, Still Air 0 70 Te Case Temperature -55 126 c Note: 1. Vpy must be more positive than Vag, and voltage reference differential must be within specified range. TRW LSI Products Inc. 245TDC1147 7ItWY IXY Electrical characteristics within specified operating conditions ee a Temperature Range Standard Extended Parameter Test Conditions Min Max Min Max Units log Positive Supply Current Voc = Max, static | 25 30 mA lee Negative Supply Current Veg = Max, static | Ty = OC to 70C -170 mA Ty = 70C ~135 mA Te = -55C to 125C ~220 mA Te = 126C ~ 130 mA Ipeg Reference Current Vet. Vag = Nom 35 50 mA Rrer Total Reference Resistance 34 20 Ohms Rin Input Equivalent Resistance Vet. Vap = Nom, Vin = Vpp 100 40 kOhms Cin Input Capacitance 60 60 pF lep Input Constant Bias Current Veg = Max 160 300 uA WL Input Current, Logic LOW Veo = Max, Vj) = 0.5V CONV -04 -0.6 mA NMINV, NLINV -0.6 -08 mA ly input Current, Logic HIGH Voc = Max, V, = 24V 50 50 uA y Input Current, Max Input Voltage Vec = Max, V) = 5.5V 1.0 1.0 mA Von Output Voltage, Logic LOW Voc = Min, Ip, = Max 05 05 V Vou Gutput Voltage, Logic HIGH Veco = Min, Igy = Max 24 24 V los Short Circuit Output Current Veg = Max, one pin to ground, -30 ~30 mA one second duration. C Digital Input Capacitance Ty = 26C, F = IMHz 15 15 pF Note 1. Worst case, all digital inputs and outputs LOW Switching characteristics within specified operating conditions ceennneeee eee eee ere Temperature Range Standard Extended Parameter Test Conditions Min Max Min Max Units Fs Maximum Conversion Rate Vec = Min, Veg = Min 15 15 MSPS isto Sampling Time Offset Veco = Min, Veg = Min 7 10 ns tp Output Delay Veco = Min, Veg = Min, Load 1 60 70 ns tuo Output Hold Time Voc = Max, Veg = Max, Load 1 15 15 ns 246 TRW LSI Products Inc.TDC1147 System performance characteristics within specified operating conditions IXvy ss ee emperature Range Standard Extended Parameter Test Conditions Min Max Min Max Units Ey Linearity Error, Integral independent Vet. YRp = Nom 0.4 04 % Eig _ Linearity Error, Differential o4 04 h i) Code Size Vet. Vap = Nom 30 170 30 170 % Nominal VoT _ Offset Voltage, Top Vin = Yer +80 +50 mV Vop Offset Voltage, Bottom Vin = Vee -30 -30 mV Teo Temperature Coefficient +20 +20 BVPC BW Bandwidth, Full Power Input 7 7 MHz ttr Transient Response, Full Scale 10 10 ns SNR Signal-to-Noise Ratio 7MHz Bandwidth, 20MSPS Conversion Rate Peak SignaliRMS Noise 1MHZz Input 45 46 dB 7MHz Input 43 4 dB RMS Signal/RMS Noise 1MHz Input 36 37 dB 7MuHz Input 34 35 dB Eap Aperture Error 50 50 ps DP Differential Phase Error! Fo = 4 x NTSC 16 15 Degree 0G Differential Gain Error! Fo = 4x NTSC 25 25 % Note: Output Coding 1. In excess of quantization Binary Offset Two's Complement Range True Inverted True Inverted -1,00V FS NMINV = 1 0 0 1 NLINV = 1 0 1 0 0.0000V 0000000 W111 000000 O11 -0.0078V 0000001 1191110 1000001 0111110 e e e e e e e e e e e e e -0.4960V ani 1000000 nin oooooee -0.5039V 100000 oti oooo000 nin e e J e e e e e ee e e e e -0.9921V 1111110 (000001 0111110 1000001 ~ 1.0000 1111111 000000 0111111 1000000 Note: TRW LSI Products Inc. 1. Voltages are code midpoints. 247 QuTDC1147 7 IXvy Calibration To calibrate the TDC1147, adjust Vpq and Vap to set the 1st and 127th thresholds to the desired voltages. Assuming a OV to 1V input range, continuously strobe the converter with 0.0039V (1/2 LSB from OV) on the analog input, and adjust VpT for output toggling between codes 00 and 01. Then apply 0.996V (1/2 LSB from 1V) and adjust Vpp for toggling between codes 126 and 127. The degree of required adjustment is indicated by the offset voltages, Vogt and Vop. Offset voltages are generated by the inherent parasitic resistance between the package pin and the actual resistor chain on the integrated circuit. These parasitic resistors are shown as Ry and Ra in the Functional Block Diagram. Calibration will cancel all offset voltages, eliminating offset and gain errors. The above method for calibration requires that both ends of the resistor chain, Rt and Rp, are driven by variable voltage sources. Instead of adjusting Vat, Ry can be connected to analog ground and the OV end of the range calibrated with an input amplifier offset control. The offset error at the bottom of the resistor chain causes a slight gain error, which can be compensated for by varying the voltage applied to Rp. The bottom 248 reference is a convenient point for gain adjust that is not in the analog signal path. Typical Interface Circuit Figure 5 shows an example of a typical interface circuit for the TDC1147. The analog input amplifier is a bipolar wideband operational amplifier, which is used to directly drive the A/D converter. Bipolar inputs may be accommodated by adjusting the offset control. A zener diode provides a stable reference for both the offset and gain control. The amplifier has a gain of 1 providing the recommended 1Vp-p input for the A/D converter. Proper decoupling is recommended for all supplies, although the degree of decoupling shown may not be needed. A variable capacitor permits either step response or frequency response optimization. This may be replaced with a fixed capacitor, whose value depends upon the circuit board layout and desired optimization. The bottom reference voltage, Vap, is supplied by an inverting amplifier, followed with a PNP transistor. The transistar provides a low-impedance source and is neces- sary to sink the current flowing through the reference resistor chain. The bottom reference voltage can be adjusted to cancel the gain error introduced by the offset voltage, Vqp, as discussed in the Calibration section. TRW LSI Products Inc.TDC1147 are = aes Figure 5. Typical Interface Circuit \N *. 2 +5V > ul 4c {3 16 FAIR- RITE 10uF 7 ats gnc 7743001111 2 rh ce , 16pF VARIABLE 8 mu at? ye Dy (SB) viveo 374.0 ay VIDEO WV AM MWA au 2! KO KO ve 39.2 2 . ] P RT b 1KQ co AIS OFFSET oe Toc1047 2K 4 RB u4 "GAIN" MULTITURN POT R6 eh p, 8 ci iMa13 Aa L 2K ae tent & 3 uF. MULTITURN POT S~q- oa0w. S10 ' mV xO L og R12 Vin Al gt 4 G U2 Sa | 72 | " 2.2K HA~2539-$ AM VIN OP - AMP {2 . 4 sv t > KO Ly. 3 3, 12, 13, 2 Fk Awa a7 cio gt 2 22K , B 0.1 F Rr ln 1 Far-are| 50 p, [7 R 2743001111 10K 2 tte" ts cA L cit , uF O1uF yt y Sov 0, L2 | Qi 4,21 Rig 2N2907 rh | Ognp 2.2K 19 D; (LSB) 5 NMINV -} 2 15 cLK > CONV NLINV F- Vee qt a, _| -5.24 > 4 ce 70 uF 25V Notes: 1. Unless otherwise specified, all resistors are W4W, 2%. 1000 R2 2 Al = Zy -| 1000 + R2 1 3. Re (= }-san Veer Zin TRW LSI Products Inc. 249A/D Converters 7rtrwe 252 TRW LSI Products Inc.