TECHNICAL NOTE High-performance Regulator IC Series for PCs Ultra Low Dropout Linear Regulators for PC Chipsets BD3508EKN Description The BD3508EKN ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to minimize the input-to-output voltage differential to the ON resistance (RON=65m) level. By lowering the dropout voltage in this way, the regulator realizes high current output (Iomax=3.0A) with reduced conversion loss, and thereby obviates the switching regulator and its power transistor, choke coil, and rectifier diode. Thus, the BD3508EKN is designed to enable significant package profile downsizing and cost reduction. An external resistor allows the entire range of output voltage configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power supply sequence is required. Features 1) Internal high-precision reference voltage circuit(0.65V1%) 2) Built-in VCC under voltage lock out circuit (VCC=3.80V) 3) NRCS (soft start) function reduces the magnitude of in-rush current 4) Internal Nch MOSFET driver offers low ON resistance (65m typ) 5) Built-in current limit circuit(3.0A min) 6) Built-in thermal shutdown (TSD) circuit 7) Variable output (0.652.7V) 8) Incorporates high-power HQFN20V package: 4.2x4.2x0.9(mm) Applications Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances Model Lineup Oct. 2008 Absolute Maximum Ratings BD3508EKN Absolute Maximum Ratings(Ta=100) PARAMETER Input Voltage 1 Input Voltage 2 Enable Input Voltage Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature SYMBOL VCC VIN Ven Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax RATING 6.0 *1 6.0 *1 6.0 0.5 *2 0.75 *3 1.75 *4 2.0 *5 -10+100 -55+125 +150 UNIT V V V W W W W *1 Should not exceed Pd. *2 Reduced by 4mW/ for each increase in Ta25(no heat sink) *3 Reduced by 6mW/ for each increase in Ta25 (when mounted on a 70mmx70mmx1.6mm glass-epoxy board, with no copper foil on the bottom surface) *4 Reduced by 14mW/ for each increase in Ta25 (when mounted on a 70mmx70mmx1.6mm glass-epoxy board, with 60mm X 60 mm copper foil on the bottom surface...1-layer) *5 Reduced by 16mW/ for each increase in Ta25 (when mounted on a 70mmx70mmx1.6mm glass-epoxy board, with 60mm X 60 mm copper foil on the bottom surface...2-layer) Operating Conditions Operating Voltage(Ta=25) PARAMETER Input Voltage 1 Input Voltage 2 Output Voltage Setting Range Enable Input Voltage NRCS Capacity SYMBOL VCC VIN Vo Ven CNRCS *6 VCC and VIN do not have to be implemented in the order listed. This product is not designed for use in radioactive environments. MIN. 4.3 0.75 VFB -0.3 0.001 MAX. 5.5 VCC-1 *6 2.7 5.5 1 UNIT V V V V uF Electrical Characteristics (Unless otherwise specified, Ta=25 VCC=5V Ven=3V VIN=1.8V R1=3.9K R2=3.3K) Parameter Symbol Limit Typ. 0.7 0 1.200 - Max. 1.4 10 - Unit Condition Bias Current VCC Shutdown Mode Current Output Voltage Maximum Output Current Output Short Circuit Current Output Voltage Temperature Coefficient Feedback Voltage 1 ICC IST VOUT Io Iost Min. 3.0 3.0 Tcvo - 0.01 - %/ VFB1 0.643 0.650 0.657 V Feedback Voltage 2 VFB2 0.630 0.650 0.670 V Line Regulation 1 Line Regulation 2 Load Regulation Minimum Input-Output Voltage Differential Standby Discharge Current [ENABLE] Enable Pin Input Voltage High Enable Pin Input Voltage Low Enable Input Bias Current [FEEDBACK] Feedback Pin Bias Current [NRCS] NRCS Charge Current NRCS Standby Voltage [UVLO] VCC Under voltage Lock out Threshold Voltage VCC Under voltage Lock out Hysteresis Voltage [AMP] Reg.l1 Reg.l2 Reg.L - 0.1 0.1 0.5 0.5 0.5 10 %/V %/V mV dVo - 65 100 mV Iden 1 - - mA Enhi 2 - - V Enlow -0.2 - 0.8 V Ien - 7 10 uA IFB -100 0 100 nA Inrcs VSTB 14 - 20 0 26 50 uA mV VccUVLO 3.5 3.8 4.1 V Vcchys 100 160 220 mV VCC:Sweep-down Gate Source Current IGSO - 1.6 - mA VFB=0, VGATE=2.5V Gate Sink Current IGSI - 4.7 - mA VFB=VCC, VGATE=2.5V *7 Design targets mA uA V A A Ven=0V Vo=0V Io=0 to 3A 7 Ta=-10 to 100 * VCC=4.3V to 5.5V VIN=1.2V to 3.3V Io=0 to 3A Io=1A,VIN=1.2V 7 Ta=-10 to 100 * Ven=0V, Vo=1V Ven=3V Vnrcs=0.5V Ven=0V VCC:Sweep-up Reference Data Vo 50mV/div Vo 50mV/div 45mV Io 2A/div Io 2A/div 3.0A Io=0A3A/3sec Vo 50mV/div Io=3A0A/3sec Io=3A0A/3sec t(5sec/div) Fig.4 Transient response (30A) Co=150Fx2 t(5sec/div) Ven 2V/div VNRCS 2V/div VNRCS 2V/div 87mV 3.0A Io=3A0A/3sec Fig.5 Transient response (30A) Co=150F Ven 2V/div t(5sec/div) Fig.3 Transient response (03A) Co=47F Io 2A/div 3.0A 3.0A Io=0A3A/3sec Vo 100mV/div 79mV Io 2A/div 3.0A t(5sec/div) Fig.2 Transient response (03A) Co=150F Vo 50mV/div 55mV Io 2A/div Io=0A3A/3sec 91mV Io 2A/div 3.0A t(5sec/div) Fig.1 Transient response (03A) Co=150Fx2 Vo 100mV/div 64mV t(5sec/div) Fig.6 Transient response (30A) Co=47F VCC Ven VIN Vo 1V/div Vo 1V/div t(200sec/div) Vo t(2msec/div) Fig.7 Waveform at output start VCCVINVen Fig.8 Waveform at output OFF Fig.9 Input sequence VCC VCC VCC Ven Ven Ven VIN VIN VIN Vo Vo Vo VINVCCVen Fig.10 Input sequence VenVCCVIN Fig.11 Input sequence VCCVenVIN Fig.12 Input sequence 1.25 VCC Ven Ven VIN VIN Vo Vo 1.23 Vo(V) VCC 1.21 1.19 1.17 1.15 VINVenVCC VenVINVCC -10 1.00 1 0.85 90 100 1.8 1.7 0.75 0.70 IIN(mA) 0.8 0.80 ICC(uA) ICC(mA) 70 1.9 0.90 0.6 0.4 0.65 0.60 1.6 1.5 1.4 1.3 1.2 0.2 1.1 0.55 1 0 0.50 -10 10 30 50 Ta() 70 -60 90 100 Fig.16 Ta-ICC -30 0 30 60 Ta() 90 -10 120 150 25 20 24 15 10 21 20 19 30 60 Ta() 90 120 150 -10 10 30 50 Ta() 70 90 -10 100 9 8 7 60 60 50 55 4 RON(m) RON(m) 5 30 20 3 2 10 30 50 Ta() 70 Fig.22 Ta-Ien 90 100 0 -10 2.5V 1.8V 45 40 1.2V 30 1 -10 50 Ta() 35 10 0 30 50 40 6 10 Fig.21 Ta-IFB Fig.20 Ta-INRCS Fig.19 Ta-IINSTB 10 90 100 -20 15 0 70 -15 16 -30 0 -10 17 0 90 100 -5 18 5 70 5 IFB(nA) INRCS(uA) 15 50 Ta() 10 22 20 30 Fig.18 Ta-IIN 23 25 -60 10 Fig.17 Ta-ISTB 30 IIN(uA) 50 Ta() 2 1.2 0.95 Ien(uA) 30 Fig.15 Ta-Vo (Io=0mA) Fig.14 Input sequence Fig.13 Input sequence 10 25 10 30 50 Ta( ) 70 Fig.23 Ta-RON (VCC=5V/Vo=1.2V) 90 100 2 4 6 Vcc(V) Fig.24 VCC-RON 8 Block Diagram VCC VCC 6 VIN1 VCC Enable EN UVLO Reference 7 8 Current CL Limit Block VCC 9 VIN2 10 16 17 18 CL UVLO TSD Thermal Vo1 Vo2 Vo3 Vo EN R2 FB 19 Shutdown GATE NRCS 11 TSD 1 20 NRCS Pin Function Table R1 2 GND Pin Layout N.C N.C N.C 15 14 13 N.C GATE 12 11 Vo1 16 10 VIN3 Vo2 17 9 VIN2 8 VIN1 FB 19 7 EN NRCS 20 6 VCC FIN Vo3 18 1 VIN VIN3 2 3 GND1 GND2 N.C 4 5 N.C N.C PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PIN Name GND1 GND2 N.C. N.C. N.C. VCC EN VIN1 VIN2 VIN3 GATE N.C. N.C. N.C. N.C. Vo1 Vo2 Vo3 FB 20 NRCS reverse FIN PIN Function Ground pin 1 Ground pin 2 No connection (empty) pin No connection (empty) pin No connection (empty) pin Power supply pin Enable input pin Input pin 1 Input pin 2 Input pin 3 Gate pin No connection (empty) pin No connection (empty) pin No connection (empty) pin No connection (empty) pin Output voltage pin 1 Output voltage pin 2 Output voltage pin 3 Reference voltage feedback pin In-rush current protection (NRCS) capacitor connection pin Connected to heatsink and GND * Please short N.C to the GND Operation of Each Block AMP This is an error amp that functions by comparing the reference voltage (0.65V) with Vo to drive the output Nch FET (Ron=65m). Frequency optimization helps to realize rapid transit response, and to support the use of functional polymer output capacitors. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is active, output goes LOW and the output NchFET switches OFF. EN The EN block controls the regulator ON/OFF pin by means of the logic input pin. In OFF position, circuit voltage is maintained at 0A, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the NRCS pin Vo, thereby draining the excess charge and preventing the load IC from malfunctioning. Since no electrical connection is required (such as between the VCC pin and the ESD prevention Di), module operation is independent of the input sequence. UVLO To prevent malfunctions that can occur when there is a momentary decrease in VCC supply voltage, the UVLO circuit switches output OFF, and, like the EN block, discharges the NRCS Vo. Once the UVLO threshold voltage (TYP3.80V) is exceeded, the power-on reset is triggered and output begins. CURRENT LIMIT With output ON, the current limit function monitors internal IC output current against the parameter value (3.0A). When current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent state is eliminated, output voltage is restored at the parameter value. NRCS The soft start function is realized by connecting an NRCS pin external capacitor to the target ground. Output ramp-up can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as the 20A (TYP) constant current source and charges the externally connected capacitor. TSD (Thermal Shut Down) The shutdown (TSD) circuit automatically switches output OFF when the chip temperature gets too high, thus serving to protect the IC against "thermal runaway" and heat damage. Because the TSD circuit is provided to shut down the IC in the presence of extreme heat, in order to avoid potential problems with the TSD, it is crucial that the Tj (max) parameter not be exceeded in the thermal design. VIN The VIN line is the major current supply line, and is connected to the output NchFET drain. Since no electrical connection (such as between the VCC pin and an ESD protective Di) is necessary, VIN operates independent of the input sequence. However, since there is an output NchFET body Di between VIN and Vo, a VIN-Vo electric (Di) connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to the VIN from Vo. Timing Chart EN ON/OFF VIN VCC Ven 0.65V(typ) NRCS Startup Vo t VCC ON/OFF VIN UVLO Hysteresis VCC Ven 0.65V(typ) NRCS Startup Vo t Evaluation Board BD3508EKN Evaluation Board Schematic BD3508EKN Evaluation Board Standard Component List Component Rating Manufacturer Product Name Component Rating Manufacturer Product Name U1 - ROHM BD3508EKN C5 47uF ROHM MCH318CN476K C1 1uF ROHM MCH184CN105K C4 10uF ROHM MCH218CN106K C10 0.01uF ROHM MCH185CN103K R1 3.9k ROHM MCR03EZPF3301 R8 0 - Jumper R2 3.3k ROHM MCR03EZPF3901 BD3508EKN Evaluation Board Layout Silkscreen TOP Layer Bottom Layer Recommended Circuit Example Option R3 C5 15 14 13 12 11 Vo (1.2V/3A) C3 16 10 17 9 18 8 19 7 20 6 C2 VIN R2 R1 C4 R1/R2 Recommended Value 3.9k/3.3k C3 47F C1 1F C2 10F C4 0.01F R3/C5 - Component 1 2 3 4 5 VEN C1 VCC Programming Notes and Precautions IC output voltage can be set with a configuration formula using the values for the internal reference output voltage (VFB)and the output voltage resistors (R1, R2). Select resistance values that will avoid the impact of the VFB current (100nA). The recommended total resistance value is 10K. To assure output voltage stability, please be certain the Vo1, Vo2, and Vo3 pins and the GND pins are connected. Output capacitors play a role in loop gain phase compensation and in mitigating output fluctuation during rapid changes in load level. Insufficient capacitance may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate output voltage fluctuation under rapid load change conditions. While a 47F ceramic capacitor is recomended, actual stability is highly dependent on temperature and load conditions. Also, note that connecting different types of capacitors in series may result in insufficient total phase compensation, thus causing oscillation. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VCC) input pins. If the impedance of this power supply were to increase, input voltage (VCC) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 1F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VCC) input pins. If the impedance of this power supply were to increase, input voltage (VCC) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 10F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush current from going through the load (VIN to Vo) and impacting output capacitors at power supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the UVLO function is deactivated. The temporary reference voltage is proportionate to time, due to the current charge of the NRCS pin capacitor, and output voltage start-up is proportionate to this reference voltage. Capacitors with low susceptibility to temperature are recommended, in order to assure a stable soft-start time. This component is employed when the C3 capacitor causes, or may cause, oscillation. It provides more precise internal phase correction. Heat Loss Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed temperature limits, and thermal design should allow sufficient margin from the limits. 1. Ambient temperature Ta can be no higher than 100 . 2. Chip junction temperature (Tj) can be no higher than 150. Chip junction temperature can be determined as follows: Calculation based on ambient temperature (Ta) Tj=Ta+j-axW Reference values j-a:HQFN20V 250.0/W Bare (unmounted) IC 166.7/W 1-layer substrate (top layer copper foil less than 3%) 2 71.4/W 1-layer substrate (bottom layer surface copper foil area 60x60mm ) 2 62.5/W 2-layer substrate (top layer copper foil area 60x60mm ) 3 Substrate size: 70x70x1.6mm (substrate with thermal via) It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in the inner layer (in using multiplayer substrate). This package is so small (size: 4.2mmx4.2mm) that it is not available to layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below). enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the number is designed suitable for the actual situation.). Most of the heat loss that occurs in the BD3508EKN is generated from the output Nch FET. Power loss is determined by the total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the BD3508EKN) make certain to factor conditions such as substrate size into the thermal design. Power consumption (W) = Input voltage (VIN)- output voltage (Vo) Example) VIN=1.5V, Vo=1.2V, Io(Ave) = 3A Power consumption (W) = 1.5(V)-1.2(V) = 0.9(W) x3.0(A) xIo (Ave) Input-Output Equivalent Circuit Diagram VCC VCC 1k NRCS 1k 1k 1k 1k VIN1 VIN2 VIN3 10k 10k 1k VCC VCC 1k FB 1k EN VO1 VO2 350k 100k 1k 50k 100k VO3 10k 20pF Reference landing pattern thermal via MID D3 e b2 L2 b2 E3 e MIE L2 (Unit : mm) Lead pitch landing pitch landing length landing pitch e 0.50 central pad length MIE 2.60 central pad pitch l2 1.10 thermal via b2 0.25 D3 1.60 E3 1.60 Diameter 0.30 *It is recommended to design suitable for the actual application. Operation Notes 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Output pin In the event that load containing a large inductance component is connected to the output terminal, and generation of back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode. (Example) OUTPUT PIN 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 9. Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. TSD on temperature [C] (typ.) Hysteresis temperature [C] (typ.) BD3508EKN 175 15 10. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 11. Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. Resistor Transistor (NPN) Pin A Pin B C Pin B B E Pin A N P+ N P+ P N Parasitic element N P+ P P substrate N C E Parasitic element P substrate GND Parasitic element B N P+ Parasitic element GND GND GND Other adjacent elements 12. Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. Heat Dissipation Characteristics HQFN20V [W] 2.5 Power Dissipation [Pd] 2.0 (1) IC unit j-a=250/W (2) Substrate (Bottom surface copper foil area: none) j-a=166.7/W (3) Substrate (Bottom surface copper foil area: 60mmx 60mm...1 layer) j-a=71.4/W (4) Substrate (Bottom surface copper foil area: 60mmx 60mm...2 layers) j-a=62.5/W (4) 2.0W (3) 1.75W 1.5 1.0 (2) 0.75W 0.5 (1) 0.5W 0 0 25 50 75 100 Ambient Temperature [Ta] 125 150 [] Type Designations (Ordering Information) B D 3 Product Name 5 0 8 E K Package Type BD3508 N - E 2 E2 Emboss tape reel opposite draw-out side: 1 pin EKN : HQFN20V Package specification HQFN20V Packing Specs External View 11 6 5 Unreeling Direction 2500pcs E2 (With reel in left hand, unreeling with the right, the index [number 1] pin is at the top left) 5) .3 (0 3- 1 0.220.05 (2.1) 10 20 .2 16 (0 4.00.1 0.05 0.1 0.6 -+0.3 1234 1234 1234 1234 1234 1234 0.220.05 ) .5 (0 0.03 0.02 -+0.02 0.95MAX 4.20.1 2) 15 Pieces/Reel 0.5 (1.1) Embossed tape (moisture-proof packing) Packing (2.1) 4.20.1 4.00.1 0.05 (Unit: mm) Reel #1 Pin Draw-out side Note: Please order by the number of reels desired Catalog No.08T431A '08.10 ROHM (c) Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. 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If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright (c) 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev3.0