M16C/26A Group (M16C/26A, M16C/26T)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0071-0040Z
Rev.0.40
2004.07.30
Rev.0.40 2004.07.30 page 1 of 24
REJ03B0071-0040Z
1. Overview
The M16C/26A group (M16C/26A, M16C/26T) of single-chip microcomputers is built using the high-perfor-
mance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 42-pin and 48-
pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featur-
ing a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing
instructions at high speed. In addition, this microcomputer contains a multiplier and a DMAC which com-
bined with fast instruction processing capability, makes it suitable for control of various OA, communication,
and industrial equipment which requires high-speed arithmetic/logic operations.
There is a Normal-ver. for M16C/26A and T-ver. and v-ver. for M16C/26T.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment,
home appliances (inverter solution), auotmotives, etc
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
------Table of Contents------
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 2 of 24
REJ03B0071-0040Z
Item Performance
CPU Number of basic instructions 91 instructions
Shortest instruction
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V) (M16C/26A, M16C/26T(T-ver.))
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V) (M16C/26A)
50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105°C) (M16C/26T(V-ver.))
62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125°C) (M16C/26T(V-ver.))
Operation mode Single chip mode
Address space 1M byte
Memory capacity ROM/RAM : See the product list
Peripheral Port Input/Output : 39 lines
function Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
Serial I/O 2 channels (UART, clock synchronous serial I/O)
1 channel (UART, clock synchronous, I2C bus1 , or IEBus2)
A/D converter 10 bit A/D Converter : 1 circuit, 12 channels
DMAC 2 channels
CRC calcuration circuit
2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable
Watchdog timer 15 bits x 1 channel (with prescaler)
Interrupt
20 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit 4 circuits
Main clock(*), Sub-clock(*)
On-chip oscillator, PLL frequency synthesizer
(*)These circuit contain a built-in feedback resister.
Oscillation stop detection Main clock oscillation stop, re-oscillation detection function
Low voltage detection circuit Available (M16C/26A) Not available (M16C/26T)
Electrical
Power supply voltage VCC=3.0V to 5.5V (
f(BCLK)=20MHZ) (M16C/26A)
Characteristics
VCC=
2.7V to 5.5V (
f(BCLK)=10MHZ)
VCC=3.0V to 5.5V
(M16C/26T(T-ver.))
VCC=4.2V to 5.5V
(M16C/26T(V-ver.))
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz, in wait mode)
0.7 µA
(Vcc=3V, when stop mode)
Flash memory Program/erase voltage
2.7V to 5.5V (M16C/26A)
3.0V to 5.5V (M16C/26T(T-ver.)) 4.2V to 5.5V (M16C/26T(V-ver.))
Number of program/erase 100 times ( Block A ,Block B : 10,000 times
(option3) )
Operating ambient temperature -20 to 85°C / -40 to 85°C 4 (M16C/26A)
-40 to 85°C (M16C/26T(T-ver.))
-40 to 105°C / -40 to 125°C (M16C/26T(V-ver.))
Package 48-pin plastic molded QFP
Notes:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. If you desire this option, please so specify.
4. See Table 1.6 for the operating ambient temperature.
Table 1.1. Performance outline of M16C/26A group (48-pin device)(M16C/26A, M16C/26T)
1.2 Performance Outline
Table 1.1 lists performance outline of M16C/26A group (M16C/26A, M16C/26T) 48-pin device.
Table 1.2 lists performance outline of M16C/26A 42-pin device.
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 3 of 24
REJ03B0071-0040Z
Table 1.2. Performance outline of M16C/26A group (42-pin device) (M16C/26A)
Item Performance
CPU Number of basic instructions 91 instructions
Shortest instruction
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
Operation mode Single chip mode
Address space 1M byte
Memory capacity ROM/RAM : See the product list
Peripheral Port Input/Output : 33 lines
function Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
Serial I/O 1 channel (UART, clock synchronous serial I/O)
1 channel (UART, clock synchronous, I2C bus1 , or IEBus2)
A/D converter 10 bit A/D Converter : 1 circuit, 10 channels
DMAC 2 channels
CRC calcuration circuit
2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable
Watchdog timer 15 bits x 1 channel (with prescaler)
Interrupt
18 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit 4 circuits
Main clock(*), Sub-clock(*)
On-chip oscillator, PLL frequency synthesizer
(*)These circuit contain a built-in feedback resister.
Oscillation stop detection Main clock oscillation stop, re-oscillation detection function
Low voltage detection circuit Available
Electrical
Power supply voltage VCC=3.0V to 5.5V (
f(BCLK)=20MHZ)
Characteristics
VCC=
2.7V to 5.5V (
f(BCLK)=10MHZ)
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz, in wait mode)
0.7 µA
(Vcc=3V, when stop mode)
Flash memory Program/erase voltage
2.7V to 5.5V
Number of program/erase
100 times(all area) or 1,000 times(program ara)/10,000 times(data area)3
Operating ambient temperature -20 to 85°C / -40 to 85°C 3
Package 42-pin plastic molded SSOP
Notes:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. See Table 1.6 for the number of program/erase and the operating ambient temperature.
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 4 of 24
REJ03B0071-0040Z
I/O
Ports
Internal Peripheral Functions
Timer
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
Watchdog Timer
(15bits)
A/D converter
(10bits x 12 channels) U(S)ART/SIO (channel 0)
Serial Ports System Clock Generator
X
IN
-X
OUT
X
CIN
-X
COUT
On-chip Oscillator
M16C/60 series 16-bit CPU Core
R0LR0H
R1LR1H
R2
R3
A0
A1
FR
R0LR0H
R1LR1H
R2
R3
A0
A1
FB
Registers
SB
PC
ISP
USP
Program Counter
Stack Pointers
INTB
V ector Table
FLG
Flag Register
Memory
Multiplier
Flash ROM
RAM
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I
2
C/IEbus
(channel 2)
3-phase PWM
Port P1
3
Port P6
8
Port P7
8
Port P8
8
Port P9
4
Port P10
8
Flash ROM
(Data Flash)
DMAC (2 channels) PLL frequency synthesizer
CRC calculation circuit
(CCITT, CRC-16)
1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/26A group, 48-pin device.
Figure 1.1. M16C/26A Group, 48-pin Block Diagram
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 5 of 24
REJ03B0071-0040Z
Figure 1.2 is a block diagram of the M16C/26A group, 42-pin device.
Figure 1.2. M16C/26A Group, 42-pin Block Diagram
I/O
Ports
Internal Peripheral Functions
Timer
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
Watchdog Timer
(15bits)
A/D converter
(10bits x 10 channels) U(S)ART/SIO (channel 0)
Serial Ports System Clock Generator
X
IN
-X
OUT
X
CIN
-X
COUT
On-chip Oscillator
M16C/60 series 16-bit CPU Core
R0LR0H
R1LR1H
R2
R3
A0
A1
FR
R0LR0H
R1LR1H
R2
R3
A0
A1
FB
Registers
SB
PC
ISP
USP
Program Counter
Stack Pointers
INTB
V ector Table
FLG
Flag Register
Memory
Multiplier
Flash ROM
RAM
U(S)ART/SIO/I
2
C/IEbus
(channel 2)
3-phase PWM
Port P1
3
Port P6
4
Port P7
8
Port P8
8
Port P9
2
Port P10
8
Flash ROM
(Data Flash)
DMAC (2 channels) PLL frequency synthesizer
CRC calculation circuit
(CCITT, CRC-16)
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 6 of 24
REJ03B0071-0040Z
1.4 Product List
Tables 1.3 to 1.5 list the M16C/28 group products and Figure 1.3 shows the type numbers, memory sizes
and packages.
Table 1.3. Product List (1) -M16C/26A As of Jun 2004
Type No. ROM capacity RAM capacity Package type Remarks
M30260M3A-XXXGP (D) 24K byte 1K byte
M30260M4A-XXXGP (D) 32K byte 1K byte
M30260M6A-XXXGP (D) 48K byte 2K byte
M30260M8A-XXXGP (D) 64K byte 2K byte
M30263M3A-XXXFP (D) 24K byte 1K byte
M30263M4A-XXXFP (D) 32K byte 1K byte
M30263M6A-XXXFP (D) 48K byte 2K byte
M30263M8A-XXXFP (D) 64K byte 2K byte
M30260F3AGP (D) 24K + 4K byte 1K byte
M30260F4AGP (D) 32K + 4K byte 1K byte
M30260F6AGP (D) 48K + 4K byte 2K byte
M30260F8AGP (D) 64K + 4K byte 2K byte
M30263F3AFP (D) 24K + 4K byte 1K byte
M30263F4AFP (D) 32K + 4K byte 1K byte
M30263F6AFP (D) 48K + 4K byte 2K byte
M30263F8AFP (D) 64K + 4K byte 2K byte
(P) : under planning (D) : under development
Table 1.4. Product List (2) -M16C/26T T-ver. As of Jun 2004
(P) : under planning (D) : under development
NOTES: Specification of M16C/26T partly varies from the one of M16C/26A
Table 1.5. Product List (3) -M16C/26T V-ver. As of Jun 2004
(P) : under planning (D) : under development
NOTES: Specification of M16C/26T partly varies from the one of M16C/26A
48P6Q
Mask ROM Version
42P2R
48P6Q
42P2R
Flash ROM Version
Type No. ROM capacity RAM capacity Package type Remarks
M30260M3T-XXXGP (P) 24K byte 1K byte
M30260M4T-XXXGP (P) 32K byte 1K byte
M30260M6T-XXXGP (P) 48K byte 2K byte
M30260M8T-XXXGP (P) 64K byte 2K byte
M30260F3TGP (D) 24K + 4K byte 1K byte
M30260F4TGP (D) 32K + 4K byte 1K byte
M30260F6TGP (D) 48K + 4K byte 2K byte
M30260F8TGP (D) 64K + 4K byte 2K byte
48P6Q Mask ROM Version
48P6Q Flash ROM Version
Type No. ROM capacity RAM capacity Package type Remarks
M30260M3V-XXXGP (P) 24K byte 1K byte
M30260M4V-XXXGP (P) 32K byte 1K byte
M30260M6V-XXXGP (P) 48K byte 2K byte
M30260M8V-XXXGP (P) 64K byte 2K byte
M30260F3VGP (D) 24K + 4K byte 1K byte
M30260F4VGP (D) 32K + 4K byte 1K byte
M30260F6VGP (D) 48K + 4K byte 2K byte
M30260F8VGP (D) 64K + 4K byte 2K byte
48P6Q Mask ROM Version
48P6Q Flash ROM Version
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 7 of 24
REJ03B0071-0040Z
Product
Code Package
Internal ROM
(Program area)
Program and
Erase Endurance Temperature
Range
Internal ROM
(Data area) Operating Ambient
Temperature
Temperature
Range
Lead-free
Lead-included
D3
D5
D7
D9
U3
U5
U7
U9
100
1,000
100
1,000
0°C to 60°C
100
10,000
100
10,000
0°C to 60°C
0°C to 60°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
Program and
Erase Endurance
Table 1.6. Product code (Flash memory version, M16C/26A)
Package type:
GP : Package 48P6Q (M16C/26A, M16C/26T)
FP : Package 42P2R (M16C/26A)
Version:
A : M16C/26A
T : M16C/26T T-ver.
V : M16C/26T V-ver.
ROM / RAM capacity:
3: (24K+4K) bytes
(Note 1)
/ 1K bytes
4: (32K+4K) bytes
(Note 1)
/ 1K bytes
6: (48K+4K) bytes
(Note 1)
/ 2K bytes
8: (64K+4K) bytes
(Note 1)
/ 2K bytes
Note 1: Only flash memory version exists in "+4K bytes"
Memory type:
M: Mask ROM version
F: Flash memory version
Type No. M 3 0 2 6 0 M 8 A - XXX G P - D3
M16C/26A Group
M16C Family
Shows pin count,
(The value itself has no specific meaning)
Product code:
See Table 1.6 Product code
ROM number:
ROM number is omitted in flash memory version
Figure 1.3. Type No., Memory Size, and Package
Product
Code Package Operating Ambient
Temperature
Lead-free
Lead-included
D3
D5
U3
U5
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
(MASK ROM version, M16C/26A)
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 8 of 24
REJ03B0071-0040Z
Figure 1.4.
Marking Diagram of Flash Memory versionfor M16C/26A (Top View)
0260F8A
A D3
XXXXX
(1) Flash memory version, 48P6Q, M16C/26A
M30263F8AFP
A D3
XXXXXXX
(2) Flash memory version, 42P2R, M16C/26A
0260M8A
001A D3
XXXXX
(3) MASK ROM version, 48P6Q, M16C/26A
M30263M8A-001FP
A D3
XXXXXXX
(4) MASK ROM version, 42P2R, M16C/26A
Product Name : indicates M30260F8AGP
Chip Version and Product Code:
A ⇒ Indicates chip version
The first edition is shown to be blank and continues
with A and B.
D3 ⇒ Indicates Product code (see Table 1.6 Product Code)
Date Code (5 digits) ⇒ indicates manufacturing management code
Product Name : indicates M30260M8AGP
ROM number, Chip Version and Product Code:
001⇒ Indicates ROM Number
A ⇒ Indicates chip version
The first edition is shown to be blank and continues
with A and B.
D3 ⇒ Indicates Product code (see Table 1.6 Product Code)
Date Code (5 digits) ⇒ indicates manufacturing management code
Product Name : indicates M30263F8AFP
Chip Version and Product Code:
A ⇒ Indicates chip version
The first edition is shown to be blank and continues
with A and B.
D3 ⇒ Indicates Product code (see Table 1.6 Product Code)
Date Code (7 digits) ⇒ indicates manufacturing management code
Product Name and ROM number
M30263M8A and FP are indicated of Produnct name
001 is indicated of ROM number
Chip Version and Product Code:
A ⇒ Indicates chip version
The first edition is shown to be blank and continues
with A and B.
D3 ⇒ Indicates Product code (see Table 1.6 Product Code)
Date Code (7 digits) ⇒ indicates manufacturing management code
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 9 of 24
REJ03B0071-0040Z
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
P9
2
/TB2
IN
/AN
32
P9
1
/TB1
IN
/AN
31
CNV
SS
P1
7
/INT
5
/IDU
P1
6
/INT
4
/IDW
P1
5
/INT
3
/AD
TRG
/IDV
P10
7
/AN
7
/KI
3
P7
0
/TxD
2
/TA
0OUT
/SDA/CTS
1
/RTS
1
/CTS
0
/CLKS
1
X
OUT
V
SS
X
IN
P8
5
/NMI/SD
V
CC
P6
7
/TxD
1
P6
6
/RxD
1
P6
5
/CLK
1
RESET
P7
1
/RxD
2
/TA0
IN
/SCL/CLK
1
P7
2
/CLK
2
/TA1
OUT
/V/RxD
1
P7
3
/CTS
2
/RTS
2
/TA1
IN
/V/TxD
1
P7
4
/TA2
OUT
/W
P7
5
/TA2
IN
/W
P7
6
/TA3
OUT
P7
7
/TA3
IN
P8
0
/TA4
OUT
/U
P8
1
/TA4
IN
/U
P8
2
/INT
0
P8
3
/INT
1
P6
4
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
P6
3
/TxD
0
P6
2
/RxD
0
P6
1
/CLK
0
P6
0
/CTS
0
/RTS
0
P9
0
/TB0
IN
/AN
30
/CLK
OUT
P8
7
/X
CIN
P8
6
/X
COUT
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4
/KI
0
P10
3
/AN
3
P10
2
/AN
2
P10
1
/AN
1
AV
ss
P10
0
/AN
0
V
REF
AV
cc
P9
3
/AN
24
P8
4
/INT
2
/ZP
Note. Set PACR2 to PACR0 bit in the PACR register
to "100
2
" before you input and output it after
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the
p
ins are disabled.
Package: 48P6Q
Figure 1.5. Pin Configuration (Top View) of M16C/26A Group, 48-pin Package
PIN CONFIGURATION (top view)(Note)
1.5 Pin Configuration
Figures 1.5 and 1.6 show the pin configurations (top view).
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 10 of 24
REJ03B0071-0040Z
Figure 1.6. Pin Configuration (Top View) of M16C/26A Group, 42-pin Package
PIN CONFIGURATION (top view)(Note)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RESET
AVSS
P100/AN0
VREF
XIN
XOUT
VSS
VCC
P86/XCOUT
P65/CLK1
P83/INT1
P82/INT0
P81/TA4IN/U
P80/TA4OUT/U
P77/TA3IN P76/TA3OUT
P75/TA2IN/W
P74/TA2OUT/W
P64/CTS1/RTS1/CTS0/CLKS1
P70/TxD2/SDA/TA0OUT/CTS1/RTS1/CTS0/CLKS1
P71/RxD2/SCL/TA0IN/CLK1
P72/CLK2/TA1OUT/V/RxD1
P73/CTS2/RTS2/TA1IN/V/TxD1
AVCC
P91/TB1IN/AN31
P90/TB0IN/AN30/CLKout
CNVSS
P87/XCIN
P66/RxD1
P67/TxD1
P85/NMI/SD
P84/INT2/ZP
P17/INT5/IDU
P16/INT4/IDW
P15/INT3/ADTRG/IDV
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
Note. Set PACR2 to PACR0 bit in the PACR register
to "001
2
" before you input and output it after
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the
p
ins are disabled.
Package: 42P2R
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 11 of 24
REJ03B0071-0040Z
Table 1.6. Pin Description(1)
1.6 Pin Description
Table 1.6 and 1.7 describes the available pins.
Pin name Signal name I/O type Function
VCC,VSS Power supply Apply 0V to the Vss pin, and the following voltage to the Vcc pin.
input 2.7 to 5.5V (M16C/26A)
3.0 to 5.5V (M16C/26T T-ver.)
4.2 to 5.5V (M16C/26T V-ver.)
CNVSS CNVSS Input Connect this pin to Vss.
____________
RESET Reset input Input "L" on this input resets the microcomputer.
XIN Clock input Input These pins are provided for the main clock generating circuit input/output.
XOUT Clock output Output Connect a ceramic resonator or crystal between the XIN and the XOUT pins.
To use an externally derived clock, input it to the XIN pin and leave the XOUT
pin open. If XIN is not used (for external oscillator or external clock)
connect XIN pin to VCC and leave XOUT pin open.
AVCC Analog power This pin is a power supply input for the A/D converter. Connect this
supply input pin to VCC.
AVSS Analog power This pin is a power supply input for the A/D converter. Connect this
supply input pin to VSS.
VREF Reference Input This pin is a reference voltage input for the A/D converter.
Voltage input
P15~P17I/O port P1 Input/ This is an 3-bit CMOS I/O port. It has an input/output port direction
output register that allows the user to set each pin for input or output individually.
When used for input, a pull-up resister option can be selected for the
entire group of three pins. Additional software selectable secondary
______
functions are: 1) P15 to P17 can be configured as external INT interrupt
pins; 2) P15 to P17 can be configured as position-data-retain function
input pins,and; 3) P15 can input a trigger for the A/D converter.
P60~P67I/O port P6 Input/ This is an 8-bit CMOS I/O port. It has an input/output port direction
output register that allows the user to set each pin for input or output individually.
When used for input, a pull-up resister option can be selected for the
entire group of four pins. Pins in this port also function as UART0 and
UART1 I/O, as selected by software.P60 to P63 are not available in the 42
pin version.
P70~P77I/O port P7 Input/ This is an 8-bit I/O port equivalent to P6. P7 can also function as I/O for
output timer A0 to A3, as selected by software. Additional programming options
are: P70 to P73 can assume UART1 I/O or UART2 I/O capabilities, and
P72 to P75 can function as output pins for the three-phase motor control
timer.
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Rev.0.40 2004.07.30 page 12 of 24
REJ03B0071-0040Z
Table 1.7. Pin Description(2)
Pin name Signal name I/O type Function
P80~P87I/O port P8 Input/ This is an 8-bit I/O port equivalent to P6. Additional software-selectable
output secondary functions are: 1) P80 and P81 can act as either I/O for Timer
A4, or as output pins for the three-phase motor control timer; 2) P82 to
______
P84 can be configured as external INT interrupt pins. P84 can be used for
_______ _____
Timer A Zphase function; 3) P85 can be used as NMI/SD. P85 can not be
used as I/O port while the three-phase motor control is enabled. Apply a
stable "H" to P85 after setting the direction register for P85 to "0" when
the three-phase motor control is enabled, and; 4) P86 and P87 can serve
as I/O pins for the sub-clock generation circuit. In this latter case, a quartz
oscillator must be connented between P86 (XCOUT pin) and P87 (XCIN pin).
P90~P93I/O port P9 Input/ This is an 4-bit I/O port equivalent to P6. Additional software-selectable
output secondary functions are: 1) P90 to P92 can act as Timer B0~B2 input
pins, and; 2) P90 to P93 can act as A/D converter input pins.
P90 outputs a no-divide, divide-by-8 or divide-by-32 clock of XIN or a
clock of the same frequency as XCIN as selected by program. P92 to P93
are not available in the 42 pin version.
P100~P107I/O port P10 Input/ This is an 8-bit I/O port equivalent to P6. This port can also function as
output A/D converter input pins, as selected by software. Furthermore, P104 to
P107 can also function as input pins for the key input interrupt function.
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit(CPU)
Rev.0.40 2004.07.30 page 13 of 24
REJ03B0071-0040Z
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Data registers (Note)
Address registers (Note)
Frame base registers (Note)
Program counter
Interrupt table register
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Note: These registers comprise a register bank. There are two register banks.
R0H(R0's high bits)
b15 b8 b7 b0
R3
INTBH
USP
ISP
SB
AA
AA
A
A
AA
AA
AA
AA
AAAAAA
AAAAAA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
CDZSBOIU
IPL
R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
R2
b31
R3
R2
A1
A0
FB
b19
INTBL
b15 b0
PC
b19 b0
b15 b0
FLG
b15 b0
b15 b0
b7 b8
Reserved area
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit(CPU)
Rev.0.40 2004.07.30 page 14 of 24
REJ03B0071-0040Z
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to
“1”
when an arithmetic operation resulted in a negative value; otherwise, it is
“0”
.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
3. Memory
Rev.0.40 2004.07.30 page 15 of 24
REJ03B0071-0040Z
3. Memory
Figure 3.1 is a memory map. The linear address space of 1M bytes extends from address 0000016 to
FFFFF16. The internal ROM is allocated in a lower address directiom beginning with address FFFFF16 . For
example, a 64-Kbyte internal ROM is allocated to the address from F000016 to FFFFF16.
The fixed interrupt vector table is allocated to the address from FFFDC16 to FFFFF16. Therefore store the
start address of each interrupt routine here. For details, refer to the "Interrupt".
These devices also contain two blocks of Flash ROM as Data Flash memory to store data. These two
blocks of 2K bytes are located from 0F00016 to 0FFFF16 on all versions.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 1-Kbyte internal RAM is allocated to the address from 0040016 to 007FF16. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR is allocated to the address from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used
by the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software
Manual".
Figure 3.1. Memory Map
SFR
Internal RAM
Reserved area
Internal ROM
(Program area)
(Note 2)
Reset
Watchdog timer
Single step
Address match
BRK instruction
Overflow
Undefined Instruction
Special page
vector table
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
FFFFF
16
FFFDC
16
FFE00
16
DBC
NMI
Internal ROM
(Data area)
(Note 1)
0F000
16
0FFFF
16
Reserved area
Note 1: Shown here is a Block A (2K bytes) and Block B (2K bytes).
(in the flash memory version)
Note 1: When using the masked ROM version, write nothing to
internal ROM area.
Size Address YYYYY
16
Size Address XXXXX
16
Internal RAM Intrnal ROM
2K byte 00BFF
16
48K byte F4000
16
64K byte F0000
16
32K byte F8000
16
1K byte 007FF
16
24K byte FA000
16
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR) MAP
Rev.0.40 2004.07.30 page 16 of 24
REJ03B0071-0040Z
Processor mode register 0 PM0 0016
Processor mode register 1 PM1 000010002
System clock control register 0 CM0 010010002
System clock control register 1 CM1 001000002
Address match interrupt enable register AIER XXXXXX002
Protect register PBCR XX0000002
Oscillation stop detection register (Note 2) CM2 0X0000102
Watchdog timer start register WDTS ??16
Watchdog timer control register WDC 00??????2(Note3)
Address match interrupt register 0 RMAD0 0016
0016
X016
Address match interrupt register 1 RMAD1 0016
0016
X016
Voltage detection register 1 (Note 4,5) VCR1 000010002
Voltage detection register 2 (Note 4,5) VCR2 0016
PLL control register 0 PLC0 0001X0102
Processor mode register 2 PM2 XXX000002
Power supply down detection interrupt register (Note 5) D4INT 0016
DMA0 source pointer SAR0 ??16
??16
X?16
DMA0 destination pointer DAR0 ??16
??16
X?16
DMA0 transfer counter TCR0 ??16
??16
DMA0 control register DM0CON 00000?002
DMA1 source pointer SAR1 ??16
??16
X?16
DMA1 destination pointer DAR1 ??16
??16
X?16
DMA1 transfer counter TCR1 ??16
??16
DMA1 control register DM1CON 00000?002
Note 1: The blank areas are reserved and cannot be used by users.
Note 2: The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset..
Note 3: The WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program.
It is set to "0" when the input voltage at the VCC pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is
set to "1" (2V detection circuit enable).
Note 4: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 5: This register can not use for M16C/26T
X : Nothing is mapped to this bit
? : Undefined
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Address Register Symbol After reset
4. Special Function Register (SFR) Map
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR) MAP
Rev.0.40 2004.07.30 page 17 of 24
REJ03B0071-0040Z
Note 1: The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Address Register Symbol After reset
INT3 interrupt control register INT3IC XX00?0002
INT5 interrupt control register INT5IC XX00?0002
INT4 interrupt control register INT4IC XX00?0002
UART2 Bus collision detection interrupt control register BCNIC XXXX?0002
DMA0 interrupt control register DM0IC XXXX?0002
DMA1 interrupt control register DM1IC XXXX?0002
Key input interrupt control register KUPIC XXXX?0002
A/D conversion interrupt control register ADIC XXXX?0002
UART2 transmit interrupt control register S2TIC XXXX?0002
UART2 receive interrupt control register S2RIC XXXX?0002
UART0 transmit interrupt control register S0TIC XXXX?0002
UART0 receive interrupt control register S0RIC XXXX?0002
UART1 transmit interrupt control register S1TIC XXXX?0002
UART1 receive interrupt control register S1RIC XXXX?0002
TimerA0 interrupt control register TA0IC XXXX?0002
TimerA1 interrupt control register TA1IC XXXX?0002
TimerA2 interrupt control register TA2IC XXXX?0002
TimerA3 interrupt control register TA3IC XXXX?0002
TimerA4 interrupt control register TA4IC XXXX?0002
TimerB0 interrupt control register TB0IC XXXX?0002
TimerB1 interrupt control register TB1IC XXXX?0002
TimerB2 interrupt control register TB2IC XXXX?0002
INT0 interrupt control register INT0IC XX00?0002
INT1 interrupt control register INT1IC XX00?0002
INT2 interrupt control register INT2IC XX00?0002
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR) MAP
Rev.0.40 2004.07.30 page 18 of 24
REJ03B0071-0040Z
0080
16
0081
16
0082
16
0083
16
0084
16
0085
16
0086
16
01B0
16
01B1
16
01B2
16
01B3
16
01B4
16
01B5
16
01B6
16
01B7
16
01B8
16
01B9
16
01BA
16
01BB
16
01BC
16
01BD
16
01BE
16
01BF
16
0250
16
0251
16
0252
16
0253
16
0254
16
0255
16
0256
16
0257
16
0258
16
0259
16
025A
16
025B
16
025C
16
025D
16
025E
16
025F
16
0330
16
0331
16
0332
16
0333
16
0334
16
0335
16
0336
16
0337
16
0338
16
0339
16
033A
16
033B
16
033C
16
033D
16
033E
16
033F
16
Note 1: The blank areas are reserved and cannot be used by users.
Note 2: This register is included in the flash memory version.
X :Nothing is mapped to this bit
? : Undefined
Address Register Symbol After reset
Flash memory control register 4 (Note 2) FMR4 01000000
2
Flash memory control register 1 (Note 2) FMR1 000???0?
2
Flash memory control register 0 (Note 2) FMR0 01
16
Three phase protect control register TPRC 00
16
On-chip oscillator control register ROCR 00000101
2
Pin assignment control register PACR 00
16
Peripheral clock select register PCLKR 00000011
2
NMI digital debounce register NDDR FF
16
Port1
7
digital debounce register P17DDR FF
16
~
~
~
~
~
~
~
~
~
~
~
~
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR) MAP
Rev.0.40 2004.07.30 page 19 of 24
REJ03B0071-0040Z
Address Register Symbol After reset
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Note 1 :The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
Timer A1-1 register TA11 ??
16
??
16
Timer A2-1 register TA21 ??
16
??
16
Timer A4-1 register TA41 ??
16
??
16
Three phase PWM control register 0 INVC0 00
16
Three phase PWM control register 1 INVC1 00
16
Three phase output buffer register 0 IDB0 00
16
Three phase output buffer register 1 IDB1 00
16
Dead time timer DTT ??
16
Timer B2 Interrupt occurrence frequency set counter ICTB2 X?
16
Position-data-retain function control register PDRF XXXX0000
2
Port function control register PFCR 00111111
2
Interrupt request cause select register 2 IFSR2A XXXXXXX0
2
Interrupt request cause select register IFSR 00
16
UART2 special mode register 4 U2SMR4 00
16
UART2 special mode register 3 U2SMR3 000X0X0X
2
UART2 special mode register 2 U2SMR2 X0000000
2
UART2 special mode register U2SMR X0000000
2
UART2 transmit/receive mode register U2MR 00
16
UART2 bit rate register U2BRG ??
16
UART2 transmit buffer register U2TB ????????
2
XXXXXXX?
2
UART2 transmit/receive control register 0 U2C0 00001000
2
UART2 transmit/receive control register 1 U2C1 00000010
2
UART2 receive buffer register U2RB ????????
2
?????XX?
2
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR) MAP
Rev.0.40 2004.07.30 page 20 of 24
REJ03B0071-0040Z
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Note 1 :The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
Address Register Symbol After reset
Count start flag TABSR 0016
Clock prescaler reset flag CPSRF 0XXXXXXX2
One-shot start flag ONSF 0016
Trigger select register TRGSR 0016
Up-dowm flag UDF 0016
Timer A0 register TA0 ??16
??16
Timer A1 register TA1 ??16
??16
Timer A2 register TA2 ??16
??16
Timer A3 register TA3 ??16
??16
Timer A4 register TA4 ??16
??16
Timer B0 register TB0 ??16
??16
Timer B1 register TB1 ??16
??16
Timer B2 register TB2 ??16
??16
Timer A0 mode register TA0MR 0016
Timer A1 mode register TA1MR 0016
Timer A2 mode register TA2MR 0016
Timer A3 mode register TA3MR 0016
Timer A4 mode register TA4MR 0016
Timer B0 mode register TB0MR 00??00002
Timer B1 mode register TB1MR 00?X00002
Timer B2 mode register TB2MR 00?X00002
Timer B2 special mode register TB2SC X00000002
UART0 transmit/receive mode register U0MR 0016
UART0 bit rate register U0BRG ??16
UART0 transmit buffer register U0TB ????????2
XXXXXXX?2
UART0 transmit/receive control register 0 U0C0 000010002
UART0 transmit/receive control register 1 U0C1 000000102
UART0 receive buffer register U0RB ????????2
?????XX?2
UART1 transmit/receive mode register U1MR 0016
UART1 bit rate register U1BRG ??16
UART1 transmit buffer register U1TB ????????2
XXXXXXX?2
UART1 transmit/receive control register 0 U1C0 000010002
UART1 transmit/receive control register 1 U1C1 000000102
UART1 receive buffer register U1RB ????????2
?????XX?2
UART transmit/receive control register 2 UCON X00000002
CRC snoop address register CRCSAR ??16
00XXXX??2
CRC mode register CRCMR 0XXXXXX02
DMA0 request cause select register DM0SL 0016
DMA1 request cause select register DM1SL 0016
CRC data register CRCD ??16
??16
CRC input register CRCIN ??16
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
4. Special Function Register (SFR) MAP
Rev.0.40 2004.07.30 page 21 of 24
REJ03B0071-0040Z
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
Note 1 :The blank areas are reserved and cannot be used by users.
X : Nothing is mapped to this bit
? : Undefined
Register Symbol After reset
A/D register 0 AD0 ????????
2
XXXXXX??
2
A/D register 1 AD1 ????????2
XXXXXX??
2
A/D register 2 AD2 ????????
2
XXXXXX??
2
A/D register 3 AD3 ????????
2
XXXXXX??
2
A/D register 4 AD4 ????????
2
XXXXXX??
2
A/D register 5 AD5 ????????
2
XXXXXX??
2
A/D register 6 AD6 ????????
2
XXXXXX??
2
A/D register 7 AD7 ????????
2
XXXXXX??
2
A/D trigger control register ADTRGCON XXXX0000
2
A/D status register 0 ADSTAT0 00000X00
2
A/D control register 2 ADCON2 00
16
A/D control register 0 ADCON0 00000???
2
A/D control register 1 ADCON1 00
16
Port P1 register P1 ??
16
Port P1 direction register PD1 00
16
Port P6 register P6 ??
16
Port P7 register P7 ??
16
Port P6 direction register PD6 00
16
Port P7 direction register PD7 00
16
Port P8 register P8 ??
16
Port P9 register P9 ???X????
2
Port P8 direction register PD8 00
16
Port P9 direction register PD9 000X0000
2
Port P10 register P10 ??
16
Port P10 direction register PD10 00
16
Pull-up control register 0 PUR0 00
16
Pull-up control register 1 PUR1 00
16
Pull-up control register 2 PUR2 00
16
Port control register PCR 00
16
Address
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
5. Package
Rev.0.40 2004.07.30 page 22 of 24
REJ03B0071-0040Z
5. Package
LQFP48-P-77-0.50 –
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
48P6Q-A
Plastic 48pin 7✕7mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
1.0 ––
M
D
7.4 ––
M
E
7.4
8°0°0.1
1.0 0.650.50.35 9.29.08.8 9.29.08.8 0.5 7.17.06.9 7.17.06.9 0.1750.1250.105 0.270.220.17 1.4
01.7
e
e
E
H
E
1
48 37
24
25
36
12
13
H
D
D
MD
ME
A
F
y
b2
I2
Recommended Mount Pad
A
1
A
2
L
1
L
Detail F
Lp
A3
c
Lp 0.45
–
–
0.6
0.25
–
0.75
–
0.08
x
A3
e
b
x
M
Recommended
SSOP42-P-450-0.80 Weight(g)
––
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy+42 Alloy
42P2R-E Plastic 42pin 450mil SSOP
Symbol Min Nom Max
A
A
2
b
c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
–
–
.250
.050
.130.317.28–
.6311.30–
–
–
.271
–
–
.02.30.150.517.48.80.9311.50.7651
–
.4311–
.42
–
–
.40.20.717.68–
.2312.70–
.150
–
b
2
–.50–
–
0°–10°
e
e
1
eb
2
e
1
I
2
Recommended Mount Pad
–
–
Z
1
0.75
––
0.9
z
Recommended
42 22
21
1
H
E
E
ey
F
A
A
2
A
1
L
1
L
c
Detail F
G
b
D
Detail G
z
Z
1
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Functional differences
Rev.0.40 2004.07.30 page 23 of 24
REJ03B0071-0040Z
6. Functional differences
6.1 Functional differences between M16C/26A and M16C/26T
Item M16C/26A M16C/26T
Main Clock During Oscillating Not oscillating
and After Reset (Initial value of CM05 bit is set to “0”(Initial value of CM05 bit is set to “1”
during and after reset) during and after reset)
Voltage Detection Available Not available
Circuit
(Power supply detection register 1,
(Reserved register)
(Function of 001916,
Power supply detection register 2,
001A16, 001F16
)
Power supply down detection interrupt register)
Package 48P6Q, 42P2R 48P6Q
Note. Since the emulator between the M16C/26A and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/26A group, do not access to the SFR which is not
built in M16C/26A group.
Refer to Hardware Manual about detail and electrical characteristics.
M16C/26A Group (M16C/26A, M16C/26T)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Functional differences
Rev.0.40 2004.07.30 page 24 of 24
REJ03B0071-0040Z
Item M16C/26A M16C/26
Clock Generation 4 circuits (Main clock oscillation circuit, 3 circuits (Main clock oscillation circuit,
Circuit Sub clock oscillation circuit, Sub clock oscillation circuit,
On-chip oscillator, On-chip oscillator)
PLL frequency synthesizer)
System Clock On-chip oscillator Main clock
Source After Reset (Initial value "1" of CM21 bit) (Initial value "0" of CM21 bit)
(Initial value of the CM21
bit in the CM2 register)
Internal RAM Retention
Available Not available
limit Detection Circuit
(VC25 bit) (Reserved bit)
(The b5 bit in the VCR2 register)
On-chip Oscillator Clock
Selectable (8MHz/1MHz/500KHz) Fixed (1MHz)
PACR2 to PACR0 in Necessary to set after reset No PACR register
the PACR Register 48pin:"1002", 42pin:"0012"
IFSR20 Bit in the Necessary to set to "1" after reset No IFSR2A register
IFSR2A Register
External Interrupt 8 causes (INT2 added) 7 causes
13 pin
(48-pin version)
________ _____
INT2/ZP IVCC
Function
P70, P71N-ch open drain output and CMOS N-ch open drain output
output are selectable by S/W
A/D Input Pin 12 channels 8 channels
(48-pin version)
A/D Operation Mode 8 modes (single, repeat, single sweep, 5 modes (single, repeat, single sweep,
repeat sweep mode 0, repeat sweep repeat sweep mode 0, repeat sweep
mode 1, simultaneous sampling, mode 1)
delayed trigger mode 0, delayed
trigger mode 1)
1 shunt current measurement function
is available
Timer B Operation 5 modes (timer, event counter, pulse 4 modes (timer, event counter, pulse
Mode periods measurement, pulse width periods measurement, pulse width
measurment, A/D trigger) measurment)
1 shunt current measurement function
is available
CRC Calculation Available (compatible to CRC-CCITT Not available
and CRC-16 methods)
Three-Phase Motor •Waveform output/Switching port output •Waveform output/Switching port output
Control by software is enabled by software is disabled
•Position-data-retain function •No position-data-retain function
Digital Debounce _______ _____
This function is in the NMI/SD pin and Not available
Function ________
INT5 pin
3 pin
(48-pin version)
P90/CLKOUT/TB0IN/AN30P90/TB0IN
Function (CLKOUT: f1, f8, f32, and fC output)
UART1 Compatible Switching to P64 to P67 or P70 to P73P64 to P67
Pin is enabled
Flash Memory Protection to blocks 0, 1 by FMR02 bit Protection to blocks 0,1 by FMR02 bit
Protect Function Protection to the blocks 0 to 3 by
FMR16 bit
Package 48P6Q, 42P2R 48P6Q
6.2 Functional differences between M16C/26A and M16C/26
Note. Since the emulator between the M16C/26A and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/26A group, do not access to the SFR which is not
built in M16C/26A group.
Refer to Hardware Manual about detail and electrical characteristics.
REVISION HISTORY
M16C/26A Group (M16C/26A, M16C/26T) Short Sheet
Rev. Date Description
Page Summary
A-1
0.20 Dec/ 01/ 03 First edition
0.30 Jun/15/04 All Descriptions about M16C/26A and M16C/26AT are added.
1 The section “1. Overview” is partly revised.
2,3 Table 1.1 and 1.2 are partly revised. Note 2 in Table 1.1 and 1.2 are revised.
4,5 Figure 1.1 and 1.2 integrate descriptions.
6 The section “1.4 Product List” is partly revised.
7 Table 1.6 “Porduct code” is added.
8 Figure 1.4 “
Marking Diagram of Flash Memory versionfor M16C/26A (Top View)
” is added.
9,10 Figure 1.5 to 1.6 are partly revised.
11 Table 1.6 is revised.
12 Table 1.7 is partly revised.
15 The Chapter ”3. Memory” is partly revised. Note 2 in Figure 3.1 is added.
16 The Chapter “4. Special Function Register” is partly revised.
23, 24 The Chaplte “6. Functional differences” is added.
0.40 Sep/30/04 All M16C/26AT is changed to M16C/26T.
M16C/26A Group
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