July 1998 Revision 5
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Technical Data Sheet SSC P485 PL Transceiver IC
Features
• Enables low-cost networking products
• Spread Spectrum Carrier communication technology
• 9600 baud data rate
• Simple interface
• Single +5 Volt power supply requirement
• 20 pin SOIC package
Introduction
The Intellon SSC P485 PL Trans ceiver IC is a highly integrated spread spec trum com munic ation transceiver for
implementing low-cost networking products. The SSC P485 contains a Spread Spectrum Carrier (SSC)
transceiver , signal conditioning c ircuitry, and a simple host inter face. A m inimum of external circuitr y is requir ed
to connect the SSC P485 to the DC power line, twisted pair cable, or other communication medium.
The inherent reliability of SSC signaling technology provides substantial improvement in network and
communication performance over other low-cost communication methods. The SSC P485 is the ideal basic
communications element for a wide variety of low-cost networking applications.
SSC P485 Block Diagram
Clock Circuit
XOUT
XIN
4 MHz
Binary Shift
Register
Summation
Encoder
Tracking & Data
Extraction Logic
Data Decod e
Logic
RX Interf ace Logic
Comp Amp
RST*
ILD
RO
C2
C1
SI
TS Contro l
Waveform
Generator
TX Interf a ce Logic DAC Buf
SO
TS*
DI
WL
SO
C2 VDDD
VSSD
XIN
XOUT
NC
VDDA
TP0
4MHZ
C1
18
17
16
15
14
3
4
5
6
7
SI
VSSD
VSSA
DI
RO
219
201
WL
ILD P485
TS*
8
9
10
13
12
11
RST*
SSC
SSC P485 PL Transceiver IC
July 1998 2 Revision 5
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ADVANCE INFORMATION
Absolute Maximum Ratings (1)
Symbol Parameter Value Unit
VDDMAX DC Supply Voltage -0.3 to 7. 0 V
VIN Input Vol tage at any Pin VSS-0.3 to VDD+0.3 V
TSTG Storage Tem perature -65 to +150 °C
TLLead Temperat ure (S ol deri ng, 10 seconds) 300 °C
Notes:
1. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Recommended Operating Conditions
Symbol Parameter Min Typical Max Unit
VDD DC Supply Vol tage 4.5 5.0 5.5 V
FOSC Oscillator Frequency 12 ± 0.05% MHz
TAOperating Temperature -40 +25 +85 °C
Humidi ty (non-condensing) 95 %
Electrical Characteristics
Conditions: VDD = 4.5 to 5.5 V T= -40 to +85°C
Symbol Parameter Min Typical Max Units
VOH Minimum High-level Output Voltage 2.4 V
VOL Maximum Low-level Output Voltage (1) 0.4 V
VIH Minimum High-level Input Voltage 2.0 V
VIL Maximum Low-level Input Voltage 0.8 V
IIL Maximum I nput Leakage Current ±10 µA
vSO SSC Signal Output Voltage (2) 4 VP-P
IDD Total Power Supply Current 15 mA
Notes:
1. TS* pin IOL = 4 mA, all other outputs IOL = 2 mA
2. ZL = 2K Ω || 10 pF
SSC P485 PL Transceiver IC
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SSC P485 Pin Assignments
Pin Mnemonic Name Description
1 4MHZ 4 MHz Clock Out 4 MHz clock output available for host microcontroller.
2 NC No Connect
3 VSSDDigital Ground Digital ground reference.
4 XIN Crystal Input Connected to external crystal to excite the IC’s internal
oscillator and digital clock.
5 XOUT Crystal Output Connected to external crystal to excite the IC’s internal
oscillator and digital clock.
6VDD
DDigital Supply 5.0 VDC ± 10% digital supply voltage with respect to
VSSD.
7 ILD Idle Line Detect Digital output, active high. Logic 1 state indicates 10 bit
times of idle line, logic 0 indicates detection of carrier or
non-idle line.
8 DI Driver Input Digital input. After the preamble, a low on DI (SPACE)
transmits a superior2 state on SO, a high on DI (MARK)
transmits a superior1 state on SO.
9 RO Receiver Output Digital output. After the preamble and assuming
standard polarity: if superior1 state is detected on SI,
RO will be high (MARK), if superior2 state is detected
on SI, RO will be low (SPACE).
10 WL Word Length Digital input. Logic 1 (default, internal pullup) selects
10-bit frame (START, eight data bits, STOP), logic 0
selects 11-bit frame (START, nine data bits, STOP).
11 TS* Tristate Active low digital output. Enables the external output
amplifier when driven high. Tri-states the external
output amplifier when driven low.
12 RST* Reset Active low digital input. RST* asynchronously forces
RO and ILD outputs to a high state and TS* to a low
state. RST* can be asserted anytime during normal
operation to force the reset state. RST* must be active
(low) for 1 µsec after VD DD and VDDA stabiliz e and the
crystal oscillator stabilizes to guarantee the internal
reset state. See Figure 10.
13 VSSAAnalog Ground Analog ground reference.
14 SO Signal Output Analog signal output. Tri-state enabled with internal
signal.
15 C2 Capacitor 2 Connection for 680pF capacitor to ground.
16 C1 Capacitor 1 Connection for 680pF capacitor to ground.
17 SI Signal Input Analog signal input.
18 VDDAAnalog Supply 5.0 VDC ± 10% analog supply voltage with respect to
VSSA.
19 TP0 Test Point 0 Reserved pin for testing.
20 VSSDDigital Ground Digital ground reference.
SSC P485 PL Transceiver IC
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SSC P485 Application Examples
The SSC P485 m ay be used in a wide variety of applications . A typical node connecting to the m edium is shown
in Figure 1. A gateway between an RS485 twisted pair network and a DC power line network is shown in Figure
2. A multi-point network application with gateways using the SSC P485 is illustrated in Figure 3. Figure 4
presents a host interface flow diagram showing the major steps necessary to transmit and receive messages
using the P485 IC.
Microprocessor
based Control
Logic
Single
Wire
ILD
WR
RD SSC P485 PL
Transceiver
SSC P111
Power Line Media
Interface
SO
TS*
SI
DI
RO
input
filter
output
filter medium
coupler
Figure 1. SSC P485 Typical Node
Microprocessor
based Control
Logic
UART
UART
+
-
D
DE
R
RE*
A
B
RS-4 85 Tra nsceiver
Twisted
Pair Single
Wire
Transmit Enable #1
RXD # 1
RXD #1
TXD # 1
ILD
RXD #2
TXD #2
RXRDY #2
TXRDY #2
DATA 0-7
RXRDY #1
TXRDY #1
TXD # 1
RD #1
RD #2
WR #1
WR #2 SSC P485 PL
Transceiver
SSC P111
Power Line Media
Interface
SO
TS*
SI
ILD
DI
RO input
filter
output
filter medium
coupler
Figure 2. SSC P485 Gateway
SSC P485 PL Transceiver IC
July 1998 5 Revision 5
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ADVANCE INFORMATION
host
micro P485
IC host
micro
P485
IC
gate
way
micro
RS485
IC P485
IC
gate
way
micro
RS485
IC
P485
IC
RS485
device RS485
device RS485
device RS485
device RS485
device RS485
device
gateway gateway
DC power line
P111
IC
P111
IC
P111
IC P111
IC
Figure 3. SSC P485 Multi-point Network Application
SSC P485 PL Transceiver IC
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1-1/2 char times
of quie t since last
character?
message to
transmit?
UART indica tes
receive character
available?
No
Entry
No read character from
UART
Yes
No
store character in
message
process messa ge Yes
ILD
==logic 1?Yes Yes
No
m essage has been
transmitted
UART indica t es
transmit buffer
available?
transmitted last
character?
write next character to
UART
UART indicates
receive character
available?
character
transmitted==character
received?
Yes
write 1st character to
UART
ILD
==logic 1?
No
Yes
Yes
No
No
No
Yes
read character from
UART
Yes
No
UART indicates
receive character
available?
Yes
No
Figure 4. Host Interface Flow Diagram
SSC P485 PL Transceiver IC
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ADVANCE INFORMATION
SSC P485 Power Line Interface
Analog data is transferred between the communication medium and the SSC P485 over the Signal In (SI) and
Signal Out (SO) pins (ref er to Figure 5) . When transm itting, SSC “chirps ” f rom the SSC P485 SO pin ar e f iltered
by the output filter to remove harmonic energy (distortion) from the transmit signal and then amplified by the SSC
P111 Power Line Media Interfac e IC. The SSC P111 is a high-ef fic iency amplifier and tri-s tate switch specif ically
designed for use in power line network systems. The amplifier is powered down and its output set to a high
impedanc e condition when the SSC P485 T S* signal is logic low, isolating the am plifier fr om the receive circ uitry
and reducing node power consumption during receive operation. W hen the SSC P485 TS* signal is logic high,
the communication signal is routed to the communication medium through the coupling circuit (capacitor or
transf ormer). When receiving, the c ommunic ation s ignal pass es through the c oupling c irc uit and is f iltered by the
bandpass input filter. The resulting signal is then applied to the SSC P485 SI pin for processing. Refer to the
application reference shown in Figure 14.
Host micro with
internal UART
ILD
RXD
TXD P485
IC
P111
IC
SO
TS*
SI
ILD
DI
RO
Single
Wire
input
filter
output
filter medium
coupler
Figure 5. SSC P485 Medium Coupling
SSC P485 Message Format
The P485 requires the following message formatting:
Start bits 1, logic low
Data bits 8 or 9 (default 8)
Stop bits 1, logic high
Character gap 0-4 bit times
Message gap 12 bit times minimum
Message length 1 character minimum
SSC P485 PL Transceiver IC
July 1998 8 Revision 5
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ADVANCE INFORMATION
Transmit/Receive Timing
The SSC P485 tim ing with contention res olution is shown below. The P485 generates a pream ble based on the
first character of the message. Contention resolution requires that the f irst character of the message be unique
among all pos sible transm itters in the network . If the channel is available and the transm itter wins contention, a
tracking sync sequence followed by a retransmission of the first character occurs. The P485 also echoes the
first character back to the host allowing the host to determine that the channel was available and to continue
transmitting the message. If the channel was unavailable (the transmitter lost contention), the SO line is tri-
stated and the first character of the received message is passed to the host. The host determines that the
channel was not available (transmitted first character does not match received first character), and the host
enters the receive mess age m ode. Once the end of mess age is detected, the P485 drives ILD high after 10 bit
times to allow all nodes to arbitrate properly. The end of packet condition is true when 5 consecutive ones are
detected on DI following a stop bit. Figure 6 shows a contention resolution example for two contending
transm itters, and Figure 7 shows the end of message s equence and the assertion of ILD. Refer to Figure 9 f or
preamble and data encoding.
SSC P485 PL Transceiver IC
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S1 S1
3407St Sp12 56
DI
RO
T ransmitter #1
charact er 1 character 2
charact er 1 echoed charact er 2 recei ved
SI
SO
preamble character 1 character 2
ILD
sync stuff
Network Bit Time Tracking
S
201 7St Sp5634
S1 S1 S1 S1 S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1 S1 S1
3407St Sp12 56
S2 S2 S2 S1 S1 S1 S2 S1 S2 S1
stuff
S2
201 7St Sp5634
DI
RO
T ransmitter #2 (Receiver)
character 1 received
SI
SO
ILD
3407St Sp12 56
S2 S2 S2 S2 S2
S1 S1
preamble character 1 character 2sync stuff
SS1 S1 S1 S1 S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1 S1 S1 S2 S2 S2 S1 S1 S1 S2 S1 S2 S1
stuff
S2S2 S2 S2 S2 S2
preamble character 1 character 2sync stuff
SS1 S1 S1 S1 S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1 S1 S1 S2 S2 S2 S1 S1 S1 S2 S1 S2 S1S2 S2 S2 S2 S2
2 bit
times
2 bit
times
S1
S1
S2
S2
01
St
St
2.5 bit
times
charact er 2 received
201 7St Sp5634 St
2.5 bit
times
S1 S1
stuff
S2S1 S2
3407St Sp12 56
character 1
preamble
SS2 S2
Figure 6. Contention Resolution Timing
SSC P485 PL Transceiver IC
July 1998 10 Revision 5
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ADVANCE INFORMATION
3407St Sp12 56
DI
RO
Transmitter
character n-1
SI
SO
ILD
3407St Sp12 56
DI
RO
Receiver
SI
SO
ILD
(tri-state)
(MARK hold)
S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1S1
34
07St Sp12 56
S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1
character n
3407St Sp12 56
S1 S1 S1 S1 S1 S1
stuff (end of msg)character n-1 character n
character n receivedcharacter n-1 received
10 bit times
S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1S1 S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1 S1 S1 S1 S1 S1 S1
stuff (end of msg)character n-1 character n
3407St Sp12 56 3407St Sp12 56
character n receivedcharacter n-1 received
10 bit times
S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1S1 S1 S2 S2 S1 S2 S1 S1 S2 S1 S2 S1 S1 S1 S1 S1 S1 S1
stuff (end of msg)character n-1 character n
Figure 7. End of Message Timing
SSC P485 PL Transceiver IC
July 1998 11 Revision 5
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ADVANCE INFORMATION
Spread Spectrum CarrierTM Technology
Spread Spectrum CarrierTM (SSC) T ec hnology is a method of s pread s pec trum comm unications s uitable f or both
point-to-point or carrier sense multiple access (CSMA) networks. Historically, spread spectrum communication
systems have been used for secure communications and/or to overcome narrow-band impairments in the
communications medium. Spread spectrum receivers generally require an initial period of time to synchronize
with the carrier , so they have not been appropriate for CSMA network s. Spread Spec trum Carr ier T ec hnology is
a method by which a series of short, self-synchronizing, frequency swept "chirps" act as a carrier. The chirps are
always of the same known pattern and detectable by all of the nodes on the network. The chirp ranges in
frequency from 100 to 400 kHz over a duration of 100 µs. The chirp is swept from approximately 200 kHz to
400 kHz and then from 100 kHz to 200 kHz. Figure 8 illustrates the SSC power line chirp.
Figure 8. Spread Spectrum Carrier Chirp
Preamble Encoding
Two modulation sc hemes are used f or symbol transm iss ion by the physical layer. Am plitude Shift Keying (ASK)
is used in the preamble of the message packet. ASK modulation uses SUPERIOR and INFERIOR states to
encode symbols. A SUPERIOR state is represented by the presence of a chirp and an inferior state by the
absence of a chirp. Because the transmitter is quiet during inferior states, superior states transmitted by other
devices contending for the channel can be detected during the preamble of the packet. An example of ASK
modulation is s hown in Figure 9. Note that in the preamble, the duration of a symbol is s lightly longer than in the
body of the pack et. A preamble symbol is 114 µs in length. Symbols in the s ync sequence and the Packet Body
are 100 µs in length. Please note the “Chirp” is ALWAYS 100µ s in length and is f ollowed by 14 µ s of quiet tim e
during the preamble.
Data Encoding
Phase Reversal Keying (PRK) utilizes two phases of the SUPERIOR s tate, SUPERIOR S1 and SUPERIOR S2,
which are 180° out of phase with one another, to modulate the encoded data. This modulation technique is more
robust than the ASK technique, because it allows the P485 to correlate and track each symbol rather than just
those encoded as SUPERIOR states. Figure 9 shows an example of PRK.
SSC P485 PL Transceiver IC
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ADVANCE INFORMATION
Preamble Phase
100 usec Phase 2 Chirp
(S2)
114 usec Superior ASK 100 usec Phase 2 Chirp
(S2: 180 degree reve rsal)
100 usec Phase 1 Chirp
(S1)
114 usec Inferior ASK
Message Body Phase
Figure 9. ASK and PRK Data Patterns
SSC P485 PL Transceiver IC
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Timing Diagrams
All timing values are referenced from the 50% mid-point between VDD and VSS. All output timings assume 50
pF load at the pin.
t
rst
RST_N
TS
t
dis
t
dis
t
dis
ILD
RO
Figure 10. Reset Timing
Table 1. Reset Timing Parameters
Symbol Parameter Min Typ Max Units Notes
trst Reset Pulse Width 300 - - ns
tdis Output Disable Time 3 - 20 ns 1
Notes: 1. Signals are forced asynchronously to their inactive state on reset.
SSC P485 PL Transceiver IC
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ADVANCE INFORMATION
t
d
t
d
t
ck12
t
pwh
t
pwl
XIN
4MHZ
t
ck4
Figure 11. 4 MHz Clock Output Timing
Table 2. 4 MHz Clock Timing Parameters
Symbol Parameter Min Typ Max Units Notes
tdOutput Delay 3 - 20 ns
tck12 Input Clock Period 83.288 83.333 83.375 ns 1
tck4 Output Clock Period 249.75 250 250. 25 ns 2
tpwh Pulse Width High - 125 - ns 3
tpwl Pulse Width Low - 125 - ns 3
Notes: 1. Oscillator frequency is 12 MHz ± 0.05%.
2. Clock frequency is 4 MHz ± 0.1%. Assumes XIN is 12 MHz ± 0.05%.
3. Actual pulse width is determined by duty cycle of the oscillator.
SSC P485 PL Transceiver IC
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ADVANCE INFORMATION
Start
DI
D0 Stop
D1 D2 D3 D7 / D8
t
bit
t
bit
t
gap
t
byte
t
char
Figure 12. DI Input Timing
Table 3. DI Input Timing Parameters
Symbol Parameter Min Typ Max Units Notes
tbit Bit Pulse Width 101.01 104.16 107.52 us 1
Baud Rate 9300 9600 9900 baud 1
tgap Inter-Character Gap 0 - 430.08 us
Inter-Character Bits 0 < 1 4 bits
tbyte Byte Length 8 - 9 bits
tchar Character Length 10 - 11 bits
Notes: 1. Corresponds to one bit width.
SSC P485 PL Transceiver IC
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RO
Start D0 StopD1 D2 D3 D7 / D8
t
bit
t
bit
t
gap
t
byte
t
char
Figure 13. RO Output Timing
Table 4. RO Input Timing Parameters
Symbol Parameter Min Typ Max Units Notes
tbit Bit Pulse Width 100.00 104.16 104.42 us 1
Baud Rate 9576 9600 10000 baud 1
tgap Inter-Character Gap 0 - 469.89 us 2
Inter-Character Bits 0 - 4.5 bits 2
tbyte Byte Length 8 - 9 bits
tchar Character Length 10 - 11 bits
Notes: 1. Corresponds to one bit width. RO output is nominally 9600 baud. If the
received baud rate exceeds 9600 baud, the receiver will adjust RO’s output
baud rate to prevent internal buffer overflow.
2. Inter-character gap on RO’s output is a function of the received character
rate and transmitted inter-character gap. Transmitted baud rates of less
than 9600 baud increases the inter-character gap on RO’s output.
Transmitted baud rates of greater than 9600 baud decreases the inter-
character gap on RO’s output.
SSC P485 PL Transceiver IC
July 1998 17 Revision 5
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ADVANCE INFORMATION
L1
1.8UH NLC
L2
180UH
C1
1.0UFX
C2
0.1UFZ
C3
220PFC
Y1
12 MHz
C4
0.1UFZ
C5
0.1UFZ
R1
510
R2
13K
R3
1K
C6 33PFC
C7 33PFC
+5V
C8
680PFX
C9
680PFX
C10
1.0UF, 63V
R4
1M
R5
10K
VAA
TXI 9
VDD 10
BIAS 11
NC 12
CEXT 13
NC 14
VSS 15
NC 16
VSS
1VDD
2VSS
3TXO
4VSS
5VDD
6
TP0
7TS
8
U2 SSC_P111
C11
0.1UFZ
C12
1500PFX
C13
3300PFX
R7
75K, 1%
C14
0.1UFZ
Q1
MMBT3904
R6
10K
VAA
R8
180
C15
.01UFX
C16
3300PFX L3
180UH
L4
120UH
C17
3300PFX
C18
1500PFX
C19
22UF,25V
R9
1K
VAA
R11
100
A
D
K
D1
BAV99
R12
33
R13
10
D2
1N5819
D3
1N5819 D4
P6KE10A
D5
P6KE10A
VAA
TS 11
RST* 12
VSSA 13
SO 14
C2 15
C1 16
SI 17
VDDA 18
TP0 19
VSSD 20
RO
10 WL
9DI
8NC
7VDDD
6XOUT
5XIN
4VSSD
3ILD
24MHZ
1
U1 SSC_P485
R10
1.2K
VAA
+5V
P2
HOST ILD
P3
HOST DI
P4
HOST RO P7 HOST +5V
P8 HOST VAA
P9 HOST GND
P11 HOST GND
P10 HOST DC BUS
P6
HOST RST*
INPUT FILTER
OUTPUT FILTER / TRANSIENT PROTECTION
TRANSMIT P REFILTER
HOST INTERFACE
DC BUS INTERFACE
C20
33UF,25V
C21
22UF,25V
Q2
MMBT3904
R14
47
R15
24K
Q3
MMBT3904
1 2
3 4
TX1
12:12
C22
1.0UF, 63V D6
P6KE24C
P1
HOST 4MHz
P5
HOST WL
POWER SUPPLY
PREAMP
BUFFER
LINE COUPLING
60882 REV.1
Figure 14. P485 Reference Application
SSC P485 PL Transceiver IC
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ADVANCE INFORMATION
SSC P485 Mechanical Specifications
Figure 15. 20-Pin SOIC Package Outline
Dimensions in Inches
SSC P485 PL Transceiver IC
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ADVANCE INFORMATION
Ordering Information
SSC P485 PL Transceiver IC
5100 West Silver Springs Boulevard
Ocala, Florida 34482
Phone: (352) 237-7416
Fax: (352) 237-7616
Internet
http://www.intellon.com
ftp://ftp.intellon.com
Intell on Corporat i on, 1998. Intell on Corporation reserves the ri ght to mak e c hanges to this data sheet without not i ce. Intellon Corporati on
makes no warranty, representation or guarantee regarding t he s uitability of its produc t s for any particular purpose. Intellon Corporation
assum es no liability arising out of the applicat ion or use of any product or circ uit . Intellon Corporation specific ally dis claims any and all
liability, including without limitation consequential or incidental dam ages .
