STK12C68-M
4-53
STK12C68-M
CMOS nvSRAM
8K x 8
AutoStore™
Nonvolatile Static RAM
MIL-STD-883 / SMD # 5962-94599
PIN CONFIGURATIONSLOGIC BLOCK DIAGRAM
A
A
A
A
A
A
4
5
6
7
8
EEPROM ARRAY
256 x 256
STORE
RECALL
STATIC RAM
ARRAY
256 x 256
ROW DECODER
STORE/
RECALL
CONTROL
AAAAA
0
1210
12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
1
2
3
4
5
6
7
G
E
W
COLUMN I/O
COLUMN DECODER
INPUT BUFFERS
AA
011
A
3
A
9
12
HSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
A
A
A
A
A
A
A
A
DQ
DQ
DQ DQ
DQ
DQ
DQ
DQ
V
V
W
HSB
A
A
A
G
A
E
SS
7
6
5
4
3
2
1
0
0
1
2
8
9
10
7
6
5
4
3
CAP
A
12
11
CCX
28 - LCC 28 - 300 C-DIP
PIN NAMES
A0 - A12 Address Inputs
W Write Enable
DQ0 - DQ7Data In/Out
E Chip Enable
G Output Enable
VCCX Power (+5V)
VSS Ground
VCAP Capacitor
HSB Hardware Store/Busy
FEATURES
• 40, 45 and 55ns Access Times
• 15 mA ICC at 200ns Access Speed
• Automatic
STORE
to EEPROM on Power Down
• Hardware or Software initiated
STORE
to
EEPROM
• Automatic
STORE
Timing
• 100,000
STORE
cycles to EEPROM
• 10 year data retention in EEPROM
• Automatic
RECALL
on Power Up
• Software initiated
RECALL
from EEPROM
• Unlimited
RECALL
cycles from EEPROM
• Single 5V±10% Operation
• Available in multiple standard packages
A
A
A
A
A
A
A
A
A
A
A
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
G
A
E
DQ
Vss
V
W
HSB
7
12
6
5
4
3
2
1
0
0
1
8
9
11
10
7
6
2
3
4
5
TOP VIEW
4
5
6
7
8
9
10
11
12
32128 2726
25
24
23
22
21
20
19
18
1716151413
V
CAP
CCX
DESCRIPTION
The Simtek STK12C68-M is a fast static RAM (40, 45
and 55ns), with a nonvolatile EEPROM element incor-
porated in each static memory cell. The SRAM can be
read and written an unlimited number of times, while
independent nonvolatile data resides in EEPROM.
Data transfers from the SRAM to the EEPROM (the
STORE
operation) take place automatically upon power
down using charge stored in an external 100 µF
capacitor. Transfers from the EEPROM to the SRAM
(the
RECALL
operation) take place automatically on
power up. Software sequences may also be used to
initiate both
STORE
and
RECALL
operations. A
STORE
can also be initiated via a single pin.
The STK12C68-M is available in the following pack-
ages: a 28-pin 300 mil ceramic DIP and 28-pad LCC.
STK12C68-M
4-54
ICC bAverage VCC Current 85 mA tAVAV = 40ns
80 mA tAVAV = 45ns
75 mA tAVAV = 55ns
ICC Average VCC Current During
STORE
8 mA All inputs ≤ 0.2V or ≥ (VCC – 0.2V)
ICC bAverage VCC Current 15 mA E ≤ 0.2V, W ≥ (VCC – 0.2V)
at tAVAV = 200ns others ≤ 0.2V or ≥ (VCC – 0.2V)
ICC Average VCC current during AutoStore™ cycle 4 mA All inputs ≤ 0.2V or ≥ (VCC - 0.2V)
ISB cAverage VCC Current 35 mA tAVAV = 40ns
(Standby, Cycling TTL Input Levels) 32 mA tAVAV = 45ns
28 mA tAVAV = 55ns
E ≥ VIH; all others cycling
ICC bAverage VCC Current 4 mA E ≥ (VCC – 0.2V)
(Standby, Stable CMOS Input Levels)
IILK Input Leakage Current (Any Input) ±1µAV
CC = max
VIN = VSS to VCC
IOLK Off State Output Leakage Current ±5µAV
CC = max
VOUT = VSS to VCC
VIH Input Logic "1" Voltage 2.2 VCC+.5 V All Inputs
VIL Input Logic "0" Voltage VSS–.5 0.8 V All Inputs
VOH Output Logic "1" Voltage 2.4 V IOUT = –4mA except HSB
VOL Output Logic "0" Voltage 0.4 V IOUT = 8mA except HSB
TAOperating Temperature –55 125 °C
ABSOLUTE MAXIMUM RATINGSa
Figure 1: AC Output Loading
Voltage on typical input relative to VSS. . . . . . . . . . . . . –0.6V to 7.0V
Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
Note a: Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(One output at a time, one second duration)
5.0V
Output
480 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
255 Ohms
AC TEST CONDITIONS
CAPACITANCE (TA=25°C, f=1.0MHz)
DC CHARACTERISTICS (VCC = 5.0V ± 10%)d
SYMBOL PARAMETER MIN MAX UNITS NOTES
CIN Input Capacitance 8 pF ∆V = 0 to 3V
COUT Output Capacitance 7 pF ∆V = 0 to 3V
SYMBOL PARAMETER MAX UNITS CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground.
13
1
2
3
4
1
2
STK12C68-M
4-55
NO. PARAMETER UNITS
1t
ELQV tACS Chip Enable Access Time 40 45 55 ns
2t
AVAV tRC Read Cycle Time 40 45 55 ns
3t
AVQVgtAA Address Access Time 40 45 55 ns
4t
GLQV tOE Output Enable to Data Valid 20 25 35 ns
5t
AXQX tOH Output Hold After Address Change 5 5 5 ns
6t
ELQX tLZ Chip Enable to Output Active 5 5 5 ns
7t
EHQZhtHZ Chip Disable to Output Inactive 17 20 25 ns
8t
GLQX tOLZ Output Enable to Output Active 0 0 0 ns
9t
GHQZhtOHZ Output Disable to Output Inactive 17 20 25 ns
10 tELICCHetPA Chip Enable to Power Active 0 0 0 ns
11 tEHICCLc,e tPS Chip Disable to Power Standby 35 45 55 ns
READ CYCLES #1 & #2
READ CYCLE #1 f,g
DQ (Data Out)
ADDRESS
DATA VALID
2
t
AVAV
3
t
AVQV
5
t
AXQX
SRAM MEMORY OPERATION
ADDRESS
E
G
DQ (Data Out)
DATA VALID
2
t
AVAV
1
t
ELQV
6
t
ELQX
4
t
GLQV
8
t
GLQX
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
I
CC
ACTIVE
STANDBY
READ CYCLE #2 f
#1, #2 Alt. MIN MAX MIN MAX MIN MAX
SYMBOLS STK12C68-40M STK12C68-45M STK12C68-55M
Note c: Bringing E ≥VIH will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: For READ CYCLE #1 and #2, W is high for entire cycle.
Note g: Device is continuously selected with E low and G low.
Note h: Measured ± 200mV from steady state output voltage.
(VCC = 5.0V ± 10%)d
STK12C68-M
4-56
#1 #2 Alt. MIN MAX MIN MAX MIN MAX
12 tAVAV tAVAV tWC Write Cycle Time 35 45 55 ns
13 tWLWH tWLEH tWP Write Pulse Width 30 35 45 ns
14 tELWH tELEH tCW Chip Enable to End of Write 30 35 45 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 18 20 25 ns
16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns
17 tAVWH tAVEH tAW Address Set-up to End of Write 30 35 45 ns
18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns
19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns
20 tWLQZh,j tWZ Write Enable to Output Disable 17 20 25 ns
21 tWHQX tOW Output Active After End of Write 5 5 5 ns
WRITE CYCLE #1: W CONTROLLED i
WRITE CYCLE #2: E CONTROLLED i
WRITE CYCLES #1 & #2
PREVIOUS DATA
ADDRESS
E
W
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
12
t
AVAV
14
t
ELWH
19
t
WHAX
17
t
AVWH
18
t
AVWL
13
t
WLWH
15
t
DVWH
16
t
WHDX
20
t
WLQZ
21
t
WHQX
ADDRESS
E
W
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
12
t
AVAV
18
t
AVEL
14
t
ELEH
19
t
EHAX
17
t
AVEH
13
t
WLEH
15
t
DVEH
16
t
EHDX
SYMBOLS STK12C68-40M STK12C68-45M STK12C68-55M
NO. PARAMETER UNITS
Note h: Measured ±200mV from steady state output voltage.
Note i: E or W must be ≥ VIH during address transitions.
Note j: If W is low when E goes low, the outputs remain in the high impedance state.
(VCC = 5.0V ± 10%)d
STK12C68-M
4-57
Note e: These parameters guaranteed but not tested.
Note n: HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-Ms to be ganged together for
simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68-M HSB pins.
Note o: A RECALL cycle is initiated automatically at power up when VCC exceeds VSWITCH. tRECALL is measured from the point at which VCC exceeds 4.5V.
22 t
RECALL
RECALL
Cycle Duration 20 µs Note o
23 t
STORE
tHLHH
STORE
Cycle Duration 10 ms VCC ≥ 4.5V
24 tDELAY tHLQZ HSB Low to Inhibit On 1 µs
25 tRECOVER tHHQX HSB High to Inhibit Off 300 ns Note e
26 tASSERT tHLHX External
STORE
Pulse Width 250 ns Note e
VSWITCH Low Voltage Trigger Level 4.0 4.5 V
IHSB_OL HSB Output Low Current 3 mA HSB = VOL, Note e, n
IHSB_OH HSB Output High Current 5 60 µA HSB = VIL, Note e, n
NONVOLATILE MEMORY OPERATION
MODE SELECTION
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active l
L L H X Write SRAM Input Data Active
L H H 0000 Read SRAM Output Data Active k,l
1555 Read SRAM Output Data k,l
0AAA Read SRAM Output Data k,l
1FFF Read SRAM Output Data k,l
10F0 Read SRAM Output Data k,l
0F0F Nonvolatile
STORE
Output High Z k
L H H 0000 Read SRAM Output Data Active k,l
1555 Read SRAM Output Data k,l
0AAA Read SRAM Output Data k,l
1FFF Read SRAM Output Data k,l
10F0 Read SRAM Output Data k,l
0F0E Nonvolatile
RECALL
Output High Z k
XXL X
STORE
/Inhibit Output High Z ICC /Standby m
E W HSB A12 - A0(hex) MODE I/O POWER NOTES
Note k: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a
STORE
cycle or (0000, 1555, 0AAA, 1FFF, 10F0,
0F0E) for a
RECALL
cycle
.
W must be high during all six consecutive cycles. See
STORE
cycle and
RECALL
cycle tables and diagrams for further details.
Note l: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
Note m: HSB initiated
STORE
operation actually occurs only if a WRITE has been done since last
STORE
operation. After the
STORE
(if any) completes, the
part will go into standby mode inhibiting all operation until HSB rises.
HARDWARE
STORE
/
RECALL
SYMBOLS
NO. PARAMETER MIN MAX UNITS NOTES
2
HSB
W
RECALL
STORE
SRAM
Inhibit
Software STOREHSB Initiated STOREPower Down STOREBrown Out RECALLPower Up RECALL
V
SWITCH
V
CAP
24
t
DELAY
26
t
ASSERT
22
t
RECALL
24
t
DELAY
25
t
RECOVER
23
t
STORE
23
t
STORE
23
t
STORE
HARDWARE
STORE
/
RECALL
STK12C68-M
4-58
28 tAVAV tRC
STORE/RECALL
Initiation Cycle Time 35 45 55 ns
29 tELQZpChip Enable to Output Inactive 85 85 85 ns
30 tAVELN tAE Address Set-up to Chip Enable 0 0 0 ns
31 tELEHNq,r tEP Chip Enable Pulse Width 25 35 45 ns
32 tEHAXN tEA Chip Disable to Address Change 0 0 0 ns
SOFTWARE STORE/RECALL CYCLE q,r,t
ADDRESS
E
DQ(Data Out)
VALID
ADDRESS #6ADDRESS #1
VALID HIGH IMPEDANCE
28
t
AVAV
28
t
AVAV
30
t
AVELN
31
t
ELEHN
32
t
EHAXN
23
t
STORE
22
t
RECALL
29
t
ELQZ
ADDRESS #2
Std. Alt. MIN MAX MIN MAX MIN MAX
NO. PARAMETER UNITS
SYMBOLS STK12C68-40M STK12C68-45M STK12C68-55M
Note p: Once the software
STORE
or
RECALL
cycle is initiated, it completes automatically, ignoring all inputs.
Note q: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence.
Note r: If the Chip Enable Pulse Width is less than tELQV (see READ CYCLE #2) but greater than or equal to tELEHN, then the data may not be valid at the end
of the low pulse, however the
STORE
or
RECALL
will still be initiated.
Note s: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout.
Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK12C68-M performs a
STORE
or
RECALL
.
Note t: E must be used to clock in the address sequence for the Software
STORE
and
RECALL
cycles.
SOFTWARE STORE/RECALL CYCLE (VCC = 5.0V ± 10%)d
STK12C68-M
4-59
address locations. By relying on READ cycles only, the
STK12C68-M implements nonvolatile operation while
remaining compatible with standard 8Kx8 SRAMs.
During the
STORE
cycle, an erase of the previous
nonvolatile data is first performed, followed by a pro-
gram of the nonvolatile elements. The program opera-
tion copies the SRAM data into the nonvolatile ele-
ments. Once a
STORE
cycle is initiated, further input
and output are disabled until the cycle is completed.
Because a sequence of addresses is used for
STORE
initiation, it is critical that no other read or write ac-
cesses intervene in the sequence or the sequence will
be aborted.
To initiate the
STORE
cycle the following READ se-
quence must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate
STORE
Cycle
Once the sixth address in the sequence has been
entered, the
STORE
cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
SOFTWARE RECALL
A
RECALL
cycle of the EEPROM data into the SRAM is
initiated with a sequence of READ operations in a
manner similar to the
STORE
initiation. To initiate the
RECALL
cycle the following sequence of READ opera-
tions must be performed:
1. Read address 0000(hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA (hex) Valid READ
4. Read address 1FFF (hex) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Initiate
RECALL
Cycle
Internally,
RECALL
is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL
operation in no way alters the data in the
DEVICE OPERATION
The STK12C68-M has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast static
RAM. In nonvolatile mode, data is transferred from
SRAM to EEPROM (the
STORE
operation) or from
EEPROM to SRAM (the
RECALL
operation). In this mode
SRAM functions are disabled.
STORE
cycles may be initiated under user control via a
software sequence or HSB assertion and are also
automatically initiated when the power supply voltage
level of the chip falls below VSWITCH.
RECALL
opera-
tions are automatically initiated upon power-up and
whenever the power supply voltage level rises above
VSWITCH.
RECALL
cycles may also be initiated by a
software sequence.
SRAM READ
The STK12C68-M performs a READ cycle whenever E
and G are LOW and HSB and W are HIGH. The address
specified on pins A0-12 determines which of the 8192
data bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid after
a delay of tAVQV. If the READ is initiated by E or G, the
outputs will be valid at tELQV or at tGLQV, whichever is
later. The data outputs will repeatedly respond to
address changes within the tAVQV access time without
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought HIGH or W or HSB is brought LOW.
SRAM WRITE
A write cycle is performed whenever E and W are LOW
and HSB is high. The address inputs must be stable prior
to entering the WRITE cycle and must remain stable
until either E or W go HIGH at the end of the cycle. The
data on pins DQ0-7 will be written into the memory if it
is valid tDVWH before the end of a W controlled WRITE
or tDVEH before the end of an E controlled WRITE.
It is recommended that G be kept HIGH during the entire
WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tWLQZ after W goes LOW.
SOFTWARE
STORE
The STK12C68-M software
STORE
cycle is initiated by
executing sequential READ cycles from six specific
STK12C68-M
4-60
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
AUTOMATIC RECALL
During power up, or after any low power condition
(VCAP < VSWITCH), when VCAP exceeds the sense
voltage of VSWITCH, a
RECALL
cycle will automatically
be initiated. After the initiation of this automatic
RE-
CALL
, if VCAP falls below VSWITCH, then another
RE-
CALL
operation will be performed whenever VCAP
again rises above VSWITCH.
If the STK12C68-M is in a WRITE state at the end of
power-up
RECALL
, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor should
be connected between W and system VCC.
HARDWARE PROTECT
The STK12C68-M offers hardware protection against
inadvertent
STORE
operation during low voltage
conditions. When VCAP < VSWITCH, all externally
initiated
STORE
operations will be inhibited.
HSB OPERATION
The Hardware Store Busy pin (HSB) is an open drain
circuit acting as both input and output to perform two
different functions. When driven low by the internal
chip circuitry it indicates that a
STORE
operation (initi-
ated via any means) is in progress within the chip.
When driven low by external circuitry for longer than
tASSERT, the chip will conditionally initiate a
STORE
operation after tDELAY.
READ and WRITE operations that are in progress when
HSB is driven low (either by internal or external cir-
cuitry) will be allowed to complete before the
STORE
operation is performed, in the following manner. After
HSB goes low, the part will continue normal SRAM
operations for tDELAY. During tDELAY, a transition on
any address or control signal will terminate SRAM
operation and cause the
STORE
to commence. Note
that if an SRAM write is attempted after HSB has been
forced low, the write will not occur and the
STORE
operation will begin immediately.
Hardware-Store-Busy (HSB) is a high speed, low drive
capability bi-directional control line. In order to allow a
bank of STK12C68-Ms to perform synchronized
STORE
functions, the HSB pin from a number of chips may be
connected together. Each chip contains a small inter-
nal current source to pull HSB HIGH when it is not being
driven low. To decrease the sensitivity of this signal to
noise generated on the PC board, it may optionally be
pulled to VCCX via an external resistor with a value
such that the combined load of the resistor and all
parallel chip connections does not exceed IHSB_OL at
VOL. Do not connect this or any other pull-up to the
VCAP node.
If HSB is to be connected to external circuits other than
other STK12C68-Ms, an external pull-up resistor should
be used.
During any
STORE
operation, regardless of how it was
initiated, the STK12C68-M will continue to drive the
HSB pin low, releasing it only when the
STORE
is
complete. Upon completion of a
STORE
operation, the
part will be disabled until HSB actually goes HIGH.
AUTOMATIC
STORE
OPERATION
During normal operation, the STK12C68-M will draw
current from VCCX to charge up a capacitor connected
to the VCAP pin. This stored charge will be used by the
chip to perform a single
STORE
operation. After power
up, when the voltage on the VCAP pin drops below
VSWITCH, the part will automatically disconnect the
VCAP pin from VCCX and initiate a
STORE
operation.
Figure 1
shows the proper connection of capacitors for
automatic store operation. The charge storage capaci-
tor should have a capacity of at least 100µF (± 20%) at
6V. Each STK12C68-M must have its own 100µF
capacitor. Each STK12C68-M
must
have a high
quality, high frequency bypass capacitor of 0.1µF
connected between VCAP and VSS, using leads and
traces that are as short as possible.
If the
AutoStore
™ function is not required, then VCAP
should be tied directly to the power supply and VCCX
should be tied to ground. In this mode,
STORE
opera-
tions may be triggered through software control or the
HSB pin. In either event, VCAP (Pin 1)
must
always
have a proper bypass capacitor connected to it.
In order to prevent unneeded
STORE
operations, auto-
matic
STOREs
as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
STK12C68-M
4-61
access cycle time is longer than 55ns.
Figure 2
below
shows the relationship between ICC and access times
for READ cycles. All remaining inputs are assumed to
cycle, and current consumption is given for all inputs at
CMOS or TTL levels.
Figure 3
shows the same relation-
ship for WRITE cycles. When E is HIGH, the chip
consumes only standby currents, and these plots do
not apply.
The cycle time used in
Figure 2
corresponds to the
length of time from the later of the last address transi-
tion or E going LOW to the earlier of E going HIGH or the
next address transition. W is assumed to be HIGH,
while the state of G does not matter. Additional current
is consumed when the address lines change state
while E is asserted. The cycle time used in
Figure 3
corresponds to the length of time from the later of W or
E going LOW to the earlier of W or E going HIGH.
The overall average current drawn by the part depends
on the following items: 1) CMOS or TTL input levels; 2)
the time during which the chip is disabled (E HIGH); 3)
the cycle time for accesses (E LOW); 4) the ratio of
reads to writes; 5) the operating temperature; 6) the
VCC level; and 7) output load.
WRITE operation has taken place since the most recent
STORE
cycle. Note that if HSB is driven low via external
circuitry and no WRITEs have taken place, the part will
still be disabled until HSB is allowed to return HIGH.
Software initiated
STORE
cycles are performed regard-
less of whether or not a WRITE operation has taken
place.
PREVENTING AUTOMATIC STORES
The
AutoStore
™ function can be disabled on the fly by
holding HSB HIGH with a driver capable of sourcing
15mA at a VOH of at least 2.2V as it will have to
overpower the internal pull-down device that drives
HSB low for 50ns at the onset of an
AutoStore
™.
When the STK12C68-M is connected for
AutoStore
™operation (system VCC connected to VCCX
and a 100uF capacitor on VCAP) and VCC crosses
VSWITCH on the way down, the STK12C68 will attempt
to pull HSB LOW ; if HSB doesn't actually get below VIL,
the part will stop trying to pull HSB LOW and abort the
AutoStore
™attempt.
LOW AVERAGE ACTIVE POWER
The STK12C68-M has been designed to draw signifi-
cantly less power when E is LOW (chip enabled) but the
100
80
60
40
20
50 100 150 200
Average Active Current (ma)
0
TTL
CMOS
Cycle Time (ns)
100
80
60
40
20
50 100 150 200
Average Active Current (ma)
0
TTL
CMOS
Cycle Time (ns)
128
26
VV
HSB
CAP CCX
V
SS 14
0.1uF
Bypass
100uF
± 20% +
Power
Supply
10K Ohms
(optional)
nvSRAM
Note: Typical at 25° C
Figure 1
Schematic Diagram
Figure 2
I
CC
(Max) Reads Figure 3
I
CC
(Max) Writes
STK12C68-M
4-62
Temperature Range
M = Military (-55 to 125 degrees C)
Access Time
40 = 40ns
45 = 45ns
55 = 55ns
Package
C = Ceramic 28 pin 300-mil DIP with gold lead finish
K = Ceramic 28 pin 300-mil DIP with solder DIP finish
L = Ceramic 28 pin LCC
Retention / Endurance
10 years / 100,000 cycles
STK12C68 - 5 C 40 M
Lead Finish
A =Solder DIP lead finish
C =Gold lead DIP finish
X =lead finish "A" or "C" is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
01 = 55ns
02 = 45ns
5962-94599 01 MX X
ORDERING INFORMATION
