ISP1505A; ISP1505C ULPI Hi-Speed Universal Serial Bus host and peripheral transceiver Rev. 01 -- 19 October 2006 Product data sheet 1. General description The ISP1505 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. The ISP1505 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer front-end attachment to USB host, peripheral and OTG devices. It is ideal for use in portable electronic devices, such as mobile phones, digital still cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs) and any system chip set to interface with the physical layer of the USB through a 12-pin interface. The ISP1505 can interface to the link with digital I/O voltages in the range of 1.65 V to 3.6 V. The ISP1505 is available in HVQFN24 package. 2. Features n Fully complies with: u Universal Serial Bus Specification Rev. 2.0 u UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 n Interfaces to host and peripheral cores; optimized for stand-alone and embedded host applications with an external VBUS supply; stand-alone peripheral cores, and Session Request Protocol (SRP)-capable peripheral cores n Complete Hi-Speed USB physical front-end solution that supports high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) u Integrated 45 10 % high-speed termination resistors, 1.5 k 5 % full-speed device pull-up resistor, and 15 k 5 % host termination resistors u Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive u USB clock and data recovery to receive USB data at 500 ppm u Insertion of stuff bits during transmit and discarding of stuff bits during receive u Non-Return-to-Zero Inverted (NRZI) encoding and decoding u Supports bus reset, suspend, resume and high-speed detection handshake (chirp) n Supports SRP for reduced power consumption u Complete control over bus resistors u Data line and VBUS pulsing session request methods ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver n n n n n u Integrated VBUS voltage comparators Highly optimized ULPI-compliant interface u 60 MHz, 8-bit interface between the core and the transceiver u Supports both 60 MHz input clock and 60 MHz output clock configurations u Integrated Phase-Locked Loop (PLL) with auto-configuring support for 60 MHz input clock, or one crystal or clock frequency: 19.2 MHz (ISP1505ABS), 26 MHz (ISP1505CBS) u Fully programmable ULPI-compliant register set u Internal Power-On Reset (POR) circuit Flexible system integration and very low current consumption, optimized for portable devices u Power-supply input range is 3.0 V to 3.6 V u Internal voltage regulator supplies 3.3 V and 1.8 V u Supports external VBUS charge pump u External VBUS source is controlled using the PSW_N pin; open-drain PSW_N allows per-port or ganged power control u FAULT input pin to monitor the external VBUS supply status u Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage pins minimize crosstalk u Typical operating current of 10 mA to 48 mA, depending on the USB speed and bus utilization u Typical suspend current of 35 A Full industrial grade operating temperature range from -40 C to +85 C 4 kV ElectroStatic Discharge (ESD) protection on pins DP, DM, VBUS and GND Available in a small HVQFN24 (4 mm x 4 mm) Restriction of Hazardous Substances (RoHS) compliant, halogen-free and lead-free package 3. Applications n n n n n n n n n n n Digital still camera Digital TV Digital Video Disc (DVD) recorder External storage device, for example: u Zip drive u Magneto-Optical (MO) drive u Optical drive: CD-ROM, CD-RW, DVD Mobile phone MP3 player PDA Printer Scanner Set-Top Box (STB) Video camera ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 2 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 4. Ordering information Table 1. Ordering information Part Package Type number Marking Crystal or Name clock frequency Description ISP1505ABS 05A[1] 19.2 MHz HVQFN24 plastic thermal enhanced very thin quad flat package; SOT616-1 no leads; 24 terminals; body 4 x 4 x 0.85 mm ISP1505CBS 05C[1] 26 MHz HVQFN24 plastic thermal enhanced very thin quad flat package; SOT616-1 no leads; 24 terminals; body 4 x 4 x 0.85 mm [1] Version The package marking is the first line of text on the IC package and can be used for IC identification. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 3 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 5. Block diagram 21 CLOCK 16 NXT 8 1, 2, 17 to 20, 22, 24 DATA [7:0] RESET_N/ PSW_N ULPI INTERFACE CONTROLLER REGISTER MAP 6 DP 5 DM HIGH-SPEED USB ATX 14 DIR ULPI INTERFACE USB DATA SERIALIZER 15 STP TERMINATION RESISTORS USB DATA DESERIALIZER VBUS VALID EXTERNAL USB CABLE DRIVE VBUS EXTERNAL 12 POWER-ON RESET GLOBAL RESET VBUS COMPARATORS 8 PLL GLOBAL CLOCKS XTAL1 XTAL2 VCC(I/O) SRP CHARGE AND DISCHARGE RESISTORS 10 11 3, 23 CRYSTAL OSCILLATOR interface voltage ISP1505 internal power REG3V3 REG1V8 VCC 9 VREF 13 7 VBUS/ FAULT BAND GAP REFERENCE VOLTAGE 4 RREF VOLTAGE REGULATOR 004aaa587 Fig 1. Block diagram ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 4 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 6. Pinning information 19 DATA5 20 DATA4 21 CLOCK 22 DATA3 terminal 1 index area 23 VCC(I/O) 24 DATA2 6.1 Pinning DATA1 1 18 DATA6 DATA0 2 17 DATA7 VCC(I/O) 3 RREF 4 DM 5 14 DIR DP 6 13 REG1V8 16 NXT RESET_N/ 12 PSW_N 9 REG3V3 15 STP XTAL2 11 8 XTAL1 10 7 VCC VBUS/FAULT ISP1505 004aaa689 Transparent top view Fig 2. Pin configuration HVQFN24; top view 6.2 Pin description Table 2. Pin description Symbol[1][2] Pin Type[3] Description[4] DATA1 1 I/O pin 1 of the bidirectional ULPI data bus slew-rate controlled output (1 ns); plain input; programmable pull down DATA0 2 I/O pin 0 of the bidirectional ULPI data bus slew-rate controlled output (1 ns); plain input; programmable pull down VCC(I/O) 3 P I/O supply rail RREF 4 AI/O resistor reference DM 5 AI/O data minus (D-) pin of the USB cable DP 6 AI/O data plus (D+) pin of the USB cable VCC 7 P input supply voltage or battery source VBUS/FAULT 8 AI/O This pin has two possible functions: VBUS (analog input and output) -- VBUS pin of the USB cable. FAULT (input) -- Input pin for the external VBUS digital overcurrent or fault detector signal. If this pin is not used as either VBUS or FAULT, it must be tied to ground. 5 V tolerant REG3V3 9 P 3.3 V regulator output XTAL1 10 AI crystal oscillator or clock input XTAL2 11 AO crystal oscillator output ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 5 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 2. Pin description ...continued Symbol[1][2] Pin Type[3] Description[4] RESET_N/ PSW_N 12 I/O This pin has two possible functions: RESET_N (input) -- Active LOW, asynchronous reset input. 3.3 V tolerant; plain input PSW_N (output) -- Active LOW external VBUS power switch or external charge pump enable. open-drain; 3.3 V tolerant If not used, this pin must be connected to VCC(I/O). REG1V8 13 P 1.8 V regulator output DIR 14 O ULPI direction signal STP 15 I ULPI stop signal slew-rate controlled output (1 ns) plain input; programmable pull up NXT 16 O ULPI next signal slew-rate controlled output (1 ns) DATA7 17 I/O pin 7 of the bidirectional ULPI data bus slew-rate controlled output (1 ns); plain input; programmable pull down DATA6 18 I/O pin 6 of the bidirectional ULPI data bus DATA5 19 I/O pin 5 of the bidirectional ULPI data bus slew-rate controlled output (1 ns); plain input; programmable pull down slew-rate controlled output (1 ns); plain input; programmable pull down DATA4 20 I/O pin 4 of the bidirectional ULPI data bus slew-rate controlled output (1 ns); plain input; programmable pull down CLOCK 21 I/O 60 MHz clock output when a crystal is attached; requires 60 MHz clock input when the crystal is not attached slew-rate controlled output (1 ns); plain input DATA3 22 I/O pin 3 of the bidirectional ULPI data bus slew-rate controlled output (1 ns); plain input; programmable pull down VCC(I/O) 23 P I/O supply rail DATA2 24 I/O pin 2 of the bidirectional ULPI data bus slew-rate controlled output (1 ns); plain input; programmable pull down GND die pad P ground supply; down bonded to the exposed die pad (heat sink); to be connected to the PCB ground [1] Symbol names ending with underscore N, for example, NAME_N, indicate active LOW signals. [2] For details on external components required on each pin, see bill of materials and application diagrams in Section 16. [3] I = input; O = output; I/O = digital input/output; AI = analog input; AO = analog output; AI/O = analog input/output; P = power or ground pin. [4] A detailed description of these pins can be found in Section 7.10. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 6 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 7. Functional description 7.1 ULPI interface controller The ISP1505 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface (UPLI) Specification Rev. 1.1. This interface must be connected to the USB link. The ULPI interface controller provides the following functions: * * * * * * * * * * ULPI-compliant interface and register set Allows full control over the USB peripheral, host and SRP functionality Parses the USB transmit and receive data Prioritizes the USB receive data, USB transmit data, interrupts and register operations Low-power mode External VBUS source control VBUS monitoring, charging and discharging 6-pin serial mode and 3-pin serial mode Generates RXCMDs; status updates Maskable interrupts For more information on the ULPI protocol, see Section 9. 7.2 USB serializer and deserializer The USB data serializer prepares data to transmit on the USB bus. To transmit data, the USB link sends a transmit command and data on the ULPI bus. The serializer performs parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end of the packet. When the serializer is busy and cannot accept any more data, the ULPI interface controller de-asserts NXT. The USB data deserializer decodes data received from the USB bus. When data is received, the deserializer strips the SYNC and EOP patterns, and then performs serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data payload. The ULPI interface controller sends data to the USB link by asserting DIR, and then asserting NXT whenever a byte is ready. The deserializer also detects various receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and byte-alignment errors. 7.3 Hi-Speed USB (USB 2.0) ATX The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for USB peripheral, host and OTG implementations. The following circuitry is included: * Differential drivers to transmit data at high-speed, full-speed and low-speed * Differential receiver and single-ended receivers to receive data at high-speed, full-speed and low-speed * Squelch circuit to detect high-speed bus activity ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 7 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver * * * * High-speed disconnect detector 45 high-speed bus terminations on DP and DM for peripheral and host modes 1.5 k pull-up resistor on DP for full-speed peripheral mode 15 k bus terminations on DP and DM for host and OTG modes For details on controlling resistor settings, see Table 7. 7.4 Voltage regulator The ISP1505 contains a built-in voltage regulator that conditions the VCC supply for use inside the ISP1505. The voltage regulator: * Supports input supply range 3.0 V < VCC < 3.6 V. * Supplies internal circuitry with 1.8 V and 3.3 V. Remark: The REG1V8 and REG3V3 pins require external decoupling capacitors. For details, see Section 16. 7.5 Crystal oscillator and PLL The ISP1505 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock generation. The crystal oscillator takes a sine-wave input from an external crystal, on the XTAL1 pin, and converts it to a square wave clock for internal use. Alternatively, a square wave clock of the same frequency can also be directly driven into the XTAL1 pin. Using an existing square wave clock can save the cost of the crystal and also reduce the board size. The PLL takes the square wave clock from the crystal oscillator and multiplies or divides it into various frequencies for internal use. The PLL can also take a 60 MHz input from the CLOCK pin. This eliminates the need for an external crystal or clock on XTAL1. The PLL produces the following frequencies, irrespective of the clock source: * * * * * 60 MHz clock for the ULPI interface controller 1.5 MHz for the low-speed USB data 12 MHz for the full-speed USB data 480 MHz for the high-speed USB data Other internal frequencies for data conversion and data recovery 7.6 VBUS comparators The ISP1505 provides three comparators, VBUS valid comparator, session valid comparator and session end comparator, to detect the VBUS voltage level. 7.6.1 VBUS valid comparator This comparator is used by hosts and A-devices to determine whether the voltage on VBUS is at a valid level for operation. The ISP1505 minimum threshold for the VBUS valid comparator is VA_VBUS_VLD. Any voltage on VBUS below VA_VBUS_VLD is considered a fault. During power-up, it is expected that the comparator output will be ignored. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 8 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver While it is possible for the external 5 V supply to use the ISP1505 internal A_VBUS_VLD comparator, typical 5 V supplies must provide their own power fault indicator that can be connected as an input to the ISP1505 FAULT pin. 7.6.2 Session valid comparator The session valid comparator is a TTL-level input that determines when VBUS is high enough for a session to start. Peripherals, A-devices and B-devices use this comparator to detect when a session is started. The A-device also uses this comparator to determine when a session is completed. The session valid threshold of the ISP1505 is VB_SESS_VLD, with a hysteresis of Vhys(B_SESS_VLD). 7.6.3 Session end comparator The ISP1505 session end comparator determines when VBUS is below the B-device session end threshold. The B-device uses this threshold to determine when a session has ended. The session end threshold of the ISP1505 is VB_SESS_END. 7.7 SRP charge and discharge resistors The ISP1505 provides on-chip resistors for short-term charging and discharging of VBUS. These are used by the B-device to request a session, prompting the A-device to restore the VBUS power. First, the B-device makes sure that VBUS is fully discharged from the previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS register bit to logic 1. The A-device sees that VBUS is charged above the session valid threshold and starts a session by turning on the VBUS power. 7.8 Band gap reference voltage The band gap circuit provides a stable internal voltage reference to bias analog circuitry. The band gap requires an accurate external reference resistor, RRREF, connected between the RREF and GND pins. For details, see Section 16. 7.9 Power-on reset The ISP1505 has an internal power-on reset circuit that resets all internal logic on power-up. The ULPI interface is also reset at power-up. Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset command over the ULPI bus to ensure correct operation of the ISP1505. 7.10 Detailed description of pins 7.10.1 DATA[7:0] Bidirectional data bus. The USB link must drive DATA[7:0] to LOW when the ULPI bus is idle. When the link has data to transmit to the PHY, it drives a nonzero value. Weak pull-down resistors are incorporated into the DATA[7:0] pins as part of the interface protect feature. For details, see Section 9.3.1. The data bus can be reconfigured to carry various data types, as given in Section 8 and Section 9. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 9 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 7.10.2 VCC(I/O) The input power pin that sets the I/O voltage level. For details, see Section 12, Section 13 and Section 16. VCC(I/O) provides power to on-chip pads of the following pins: * * * * * * CLOCK DATA[7:0] DIR NXT RESET_N STP If the ISP1505 CLOCK pin is configured as an input, the VCC(I/O) power must be provided at the same time as the VCC power. If the VCC(I/O) power input is delayed with respect to VCC, input clock mode stability cannot be guaranteed. 7.10.3 RREF Resistor reference analog I/O pin. A resistor, RRREF, must be connected between RREF and GND, as shown in Section 16. This provides an accurate voltage reference that biases internal analog circuitry. Less accurate resistors cannot be used and will render the ISP1505 unusable. 7.10.4 DP and DM The DP (data plus) and DM (data minus) are USB differential data pins. These must be connected to the D+ and D- pins of the USB receptacle. 7.10.5 VCC VCC is the main input supply voltage for the ISP1505. Decoupling capacitors are recommended. For details, see Section 16. 7.10.6 VBUS/FAULT This pin provides two options for VBUS driving and monitoring. If neither function is used, this pin must be connected to ground. 7.10.6.1 VBUS By default, this pin acts as an input to VBUS comparators, and also charges and discharges VBUS for SRP. The VBUS pin requires a capacitive load as shown in Section 16. To prevent electrical overstress, it is strongly recommended that you attach a series resistor on the VBUS pin (RVBUS). RVBUS must not be attached when using the ISP1505 internal charge pump. For details, see Section 16. 7.10.6.2 FAULT (external overcurrent or fault detector) If an external VBUS overcurrent or fault circuit is used, the output fault indicator of that circuit can be connected to the ISP1505 FAULT input pin. The ISP1505 will inform the link of VBUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link must: ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 10 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver * Set the USE_EXT_VBUS_IND register bit to logic 1. * Set the polarity of the external fault signal using the IND_COMPL register bit. * Set the IND_PASSTHRU register bit to logic 1. 7.10.7 REG3V3 and REG1V8 Regulator output voltage. These supplies are used to power the ISP1505 internal digital and analog circuits, and must not be used to power external circuits. For correct operation of the regulator, it is recommended that you connect REG3V3 and REG1V8 to decoupling capacitors. For an example, see Section 16. 7.10.8 XTAL1 and XTAL2 XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the XTAL1 pin depends on the ISP1505 product version. If the link requires a 60 MHz clock from the ISP1505, then either a crystal must be attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left floating. If the link drives a 60 MHz clock into the CLOCK pin, then XTAL1 must be connected to REG1V8, and XTAL2 must be left floating. If a crystal is attached, it requires external load capacitors to GND on each terminal of the crystal. For details, see Section 16. If at any time the system wants to stop the clock on XTAL1, the link must first put the ISP1505 into low-power mode. The clock on XTAL1 must be restarted before low-power mode is exited. 7.10.9 RESET_N/PSW_N This pin provides two optional functions. If neither function is used, this pin must be connected to VCC(I/O). 7.10.9.1 RESET_N An active LOW asynchronous reset pin that resets all circuits in the ISP1505. The ISP1505 contains an internal power-on reset circuit, and therefore using the RESET_N pin is optional. If RESET_N is not used, it must be connected to VCC(I/O). For details on using RESET_N, see Section 9.3.2. 7.10.9.2 PSW_N PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active LOW, external VBUS switch or charge pump enable circuit to control the external VBUS power source. An external pull-up resistor, Rpullup, is required when PSW_N is used. This pin is open-drain, allowing ganged-mode power control for multiple USB ports. For application details, see Section 16. To use the PSW_N pin, the link must disable the reset input by setting the IGNORE_RESET bit in the Power Control register to logic 1. This will ensure that PSW_N is not misinterpreted as a reset. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 11 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver If the link is in host mode, it can enable the external VBUS power source by setting the DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1505 will drive PSW_N to LOW to enable the external VBUS power source. If the link detects an overcurrent condition (the VBUS state in RXCMD is not 11b), it must disable the external VBUS supply by setting DRV_VBUS_EXT to logic 0. 7.10.10 DIR ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1505 holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1505 listens for data from the link. The ISP1505 pulls DIR to HIGH only when it has data to send to the link, which is for one of two reasons: * To send the USB receive data, RXCMD status updates and register read data to the link. * To block the link from driving the data bus during power-up, reset and low-power mode (suspend). For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. 7.10.11 STP ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet or a register write operation. When DIR is asserted, the link can optionally assert STP to abort the ISP1505, causing it to de-assert DIR in the next clock cycle. A weak pull-up resistor is incorporated into the STP pin as part of the interface protect feature. For details, see Section 9.3.1. For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. 7.10.12 NXT ULPI next data output pin. The ISP1505 holds NXT at LOW by default. When DIR is LOW and the link is sending data to the ISP1505, NXT will be asserted to notify the link to provide the next data byte. When DIR is at HIGH and the ISP1505 is sending data to the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not used for the register read data or the RXCMD status update. For details on NXT usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. 7.10.13 CLOCK A 60 MHz interface clock to synchronize the ULPI bus. CLOCK can be configured as input or output. The ISP1505 provides three clocking options: * A crystal attached between the XTAL1 and XTAL2 pins. * A clock driven into the XTAL1 pin, with the XTAL2 pin left floating. * A 60 MHz clock driven into the CLOCK pin, with XTAL1 tied to REG1V8 and XTAL2 left floating. For details on CLOCK usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 12 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 7.10.14 GND (die pad) Global ground signal. The die pad is exposed on the underside of the package as a ground plate. This acts as a ground to all circuits in the ISP1505. To ensure correct operation of the ISP1505, GND must be soldered to the cleanest ground available. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 13 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 8. Modes of operation 8.1 ULPI modes The ISP1505 ULPI bus can be programmed to operate in four modes. Each mode reconfigures the signals on the data bus as described in the following subsections. Setting more than one mode will lead to undefined behavior. 8.1.1 Synchronous mode This is default mode. At power-up, and when CLOCK is stable, the ISP1505 will enter synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the set-up and hold times as defined in Section 15. A description of the ULPI pin behavior in synchronous mode is given in Table 3. This mode is used by the link to perform the following tasks: * * * * High-speed detection handshake (chirp) Transmit and receive USB packets Read and write to registers Receive USB status updates (RXCMDs) For more information on various synchronous mode protocols, see Section 9. Table 3. ULPI signal description Signal name Direction on Signal description ISP1505 CLOCK I/O 60 MHz interface clock. If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1505 will drive a 60 MHz output clock; otherwise, the ISP1505 requires a 60 MHz input clock. DATA[7:0] I/O 8-bit data bus. In synchronous mode, the link drives DATA[7:0] to LOW by default. The link initiates transfers by sending a nonzero data pattern called TXCMD (transmit command). In synchronous mode, the direction of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines must be ignored for exactly one clock cycle whenever DIR changes value. This is called the turnaround cycle. Data lines have fixed direction and different meaning in low-power and serial modes. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 14 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 3. ULPI signal description ...continued Signal name Direction on Signal description ISP1505 DIR O Direction: Controls the direction of data bus DATA[7:0]. In synchronous mode, the ISP1505 drives DIR to LOW by default, making the data bus an input so that the ISP1505 can listen for TXCMDs from the link. The ISP1505 drives DIR to HIGH only when it has data for the link. When DIR and NXT are HIGH, the byte on the data bus contains decoded USB data. When DIR is HIGH and NXT is LOW, the byte contains status information called RXCMD (receive command). The only exception to this rule is when the PHY returns register read data, where NXT is also LOW, replacing the usual RXCMD byte. Every change in DIR causes a turnaround cycle on the data bus, during which DATA[7:0] is not valid and must be ignored by the link. DIR is always asserted during low-power and serial modes. STP I Stop: In synchronous mode, the link drives STP to HIGH for one cycle after the last byte of data is sent to the ISP1505. The link can optionally assert STP to force DIR to be de-asserted. In low-power and serial modes, the link holds STP at HIGH to wake up the ISP1505, causing the ULPI bus to return to synchronous mode. NXT O Next: In synchronous mode, the ISP1505 drives NXT to HIGH to throttle data. If DIR is LOW, the ISP1505 asserts NXT to notify the link to place the next data byte on DATA[7:0] in the following clock cycle. If DIR is HIGH, the ISP1505 asserts NXT to notify the link that a valid USB data byte is on DATA[7:0] in the current cycle. The ISP1505 always drives an RXCMD when DIR is HIGH and NXT is LOW, unless register read data is to be returned to the link in the current cycle. NXT is not used in low-power or serial mode. 8.1.2 Low-power mode When the USB is idle, the link can place the ISP1505 into low-power mode (also called suspend mode). In low-power mode, the data bus definition changes to that shown in Table 4. To enter low-power mode, the link sets the SUSPENDM bit in the Function Control register to logic 0. To exit low-power mode, the link asserts the STP signal. The ISP1505 will draw only suspend current from the VCC supply (see Table 41). During low-power mode, the clock on XTAL1 may be stopped. The clock must be started again before asserting STP to exit low-power mode. After exiting low-power mode, the ISP1505 will send an RXCMD to the link if a change was detected in any interrupt source, and the change still exists. An RXCMD may not be sent if the interrupt condition is removed before exiting. For more information on low-power mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. Table 4. Signal mapping during low-power mode Signal Maps to Direction Description LINESTATE0 DATA0 O combinatorial LINESTATE0 directly driven by analog receiver LINESTATE1 DATA1 O combinatorial LINESTATE1 directly driven by analog receiver ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 15 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 4. Signal mapping during low-power mode ...continued Signal Maps to Direction Description Reserved DATA2 O reserved; the ISP1505 will drive this pin to LOW INT DATA3 O active HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs Reserved DATA[7:4] O reserved; the ISP1505 will drive this pin to LOW 8.1.3 6-pin full-speed or low-speed serial mode If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1505 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0] bus definition changes to that shown in Table 5. To enter 6-pin serial mode, the link sets the 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial mode, the link asserts STP. This is provided primarily for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM register bit must be set to logic 1. For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. Table 5. Signal mapping for 6-pin serial mode Signal Maps to Direction Description TX_ENABLE DATA0 I active HIGH transmit enable TX_DAT DATA1 I transmit differential data on DP and DM TX_SE0 DATA2 I transmit single-ended zero on DP and DM INT DATA3 O active HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs RX_DP DATA4 O single-ended receive data from DP RX_DM DATA5 O single-ended receive data from DM RX_RCV DATA6 O differential receive data from DP and DM Reserved DATA7 O reserved; the ISP1505 will drive this pin to LOW 8.1.4 3-pin full-speed or low-speed serial mode If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed USB data, it can set the ISP1505 to 3-pin serial mode. In 3-pin serial mode, the data bus definition changes to that shown in Table 6. To enter 3-pin serial mode, the link sets the 3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial mode, the link asserts STP. This is primarily provided for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM register bit must be set to logic 1. For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 16 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 6. Signal mapping for 3-pin serial mode Signal Maps to Direction Description TX_ENABLE DATA0 I active HIGH transmit enable DAT DATA1 I/O transmit differential data on DP and DM when TX_ENABLE is HIGH receive differential data from DP and DM when TX_ENABLE is LOW SE0 DATA2 I/O transmit single-ended zero on DP and DM when TX_ENABLE is HIGH receive single-ended zero from DP and DM when TX_ENABLE is LOW INT DATA3 O active HIGH interrupt indication; will be asserted whenever any unmasked interrupt occurs Reserved DATA[7:4] O reserved; the ISP1505 will drive this pin to LOW 8.2 USB and OTG state transitions A Hi-Speed USB host or an OTG device handles more than one electrical state as defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2. The ISP1505 accommodates the various states through register bit settings of XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN. Table 7 summarizes operating states. The values of register settings in Table 7 will force resistor settings as also given in Table 7. Resistor setting signals are defined as follows: * * * * RPU_DP_EN enables the 1.5 k pull-up resistor on DP. RPD_DP_EN enables the 15 k pull-down resistor on DP. RPD_DM_EN enables the 15 k pull-down resistor on DM. HSTERM_EN enables the 45 termination resistors on DP and DM. It is up to the link to set the desired register settings. Table 7. Operating states and resistor settings Signaling mode Register settings Internal resistor settings XCVR SELECT [1:0] TERM SELECT OPMODE [1:0] DP_PULL DM_PULL RPU_ DOWN DOWN DP_EN RPD_ DP_EN RPD_ HSTERM DM_EN _EN 3-state drivers XXb Xb 01b Xb Xb 0b 0b 0b 0b Power-up or VBUS < VB_SESS_END 01b 0b 00b 1b 1b 0b 1b 1b 0b 00b 0b 10b 1b 1b 0b 1b 1b 1b General settings Host settings Host chirp Host high-speed 00b 0b 00b 1b 1b 0b 1b 1b 1b Host full-speed X1b 1b 00b 1b 1b 0b 1b 1b 0b Host high-speed or full-speed suspend 01b 1b 00b 1b 1b 0b 1b 1b 0b Host high-speed or full-speed resume 01b 1b 10b 1b 1b 0b 1b 1b 0b Host low-speed 10b 1b 00b 1b 1b 0b 1b 1b 0b ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 17 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 7. Operating states and resistor settings ...continued Signaling mode Register settings Internal resistor settings XCVR SELECT [1:0] TERM SELECT OPMODE [1:0] DP_PULL DM_PULL RPU_ DOWN DOWN DP_EN RPD_ DP_EN RPD_ HSTERM DM_EN _EN Host low-speed suspend 10b 1b 00b 1b 1b 0b 1b 1b 0b Host low-speed resume 10b 1b 10b 1b 1b 0b 1b 1b 0b Host Test J or Test K 00b 0b 10b 1b 1b 0b 1b 1b 1b Peripheral settings Peripheral chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b Peripheral high-speed 00b 0b 00b 0b 0b 0b 0b 0b 1b Peripheral full-speed 01b 1b 00b 0b 0b 1b 0b 0b 0b Peripheral high-speed or full-speed suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b Peripheral high-speed or full-speed resume 01b 1b 10b 0b 0b 1b 0b 0b 0b Peripheral Test J or Test K 00b 0b 10b 0b 0b 0b 0b 0b 1b OTG device peripheral chirp 00b 1b 10b 0b 1b 1b 0b 1b 0b OTG device peripheral high-speed 00b 0b 00b 0b 1b 0b 0b 1b 1b OTG device 01b peripheral full-speed 1b 00b 0b 1b 1b 0b 1b 0b OTG device peripheral high-speed and full-speed suspend 01b 1b 00b 0b 1b 1b 0b 1b 0b OTG device peripheral high-speed and full-speed resume 01b 1b 10b 0b 1b 1b 0b 1b 0b OTG device peripheral Test J or Test K 00b 0b 10b 0b 1b 0b 0b 1b 1b OTG settings ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 18 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 9. Protocol description The following subsections describe the protocol for using the ISP1505. 9.1 ULPI references The ISP1505 provides a 12-pin ULPI interface to communicate with the link. It is highly recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and UTMI+ Specification Rev. 1.0. 9.2 Power-On Reset (POR) An internal POR is generated when REG1V8 rises above VPOR(trip), for at least tw(REG1V8_H). The internal POR pulse will also be generated whenever REG1V8 drops below VPOR(trip) for more than tw(REG1V8_L), and then rises above VPOR(trip) again. The voltage on REG1V8 is generated from VCC. To give a better view of the functionality, Figure 3 shows a possible curve of REG1V8. The internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip level so that POR turns to logic 1 and a delay element will add another tPORP before it drops to logic 0. If REG1V8 dips from t2 to t3 for > tw(REG1V8_L), another POR pulse is generated. If the dip at t4 to t5 is too short, that is, < tw(REG1V8_L), the internal POR pulse will not react and will remain LOW. REG1V8 VPOR(trip) t0 t1 t2 tPORP t3 tPORP t4 t5 POR 004aaa751 Fig 3. Internal power-on reset timing 9.3 Power-up, reset and bus idle sequence Figure 4 shows a typical start-up sequence. On power-up, the ISP1505 performs an internal power-on reset and asserts DIR to indicate to the link that the ULPI bus cannot be used. On power-up, CLOCK is an input unless several edges are detected on XTAL1. When the internal PLL is stable, the ISP1505 de-asserts DIR. The power-up time depends on the VCC supply rise time, the crystal start-up time, and PLL start-up time tstartup(o)(CLOCK). Whenever DIR is asserted, the ISP1505 drives the NXT pin to LOW and drives DATA[7:0] with RXCMD values. When DIR is de-asserted, the link must drive the data bus to a valid level. By default, the link must drive data to LOW. When the ISP1505 initially de-asserts DIR on power-up, the link must ignore all RXCMDs until it resets the ISP1505. Before beginning USB packets, the link must set the RESET bit in the Function Control register to reset the ISP1505. After the RESET bit is set, the ISP1505 will assert DIR until the internal reset completes. The ISP1505 will automatically de-assert DIR and clear the RESET bit when reset has ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 19 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver completed. After every reset, an RXCMD is sent to the link to update USB status information. After this sequence, the ULPI bus is ready for use and the link can start USB operations. If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1505 will drive a 60 MHz clock out from the CLOCK pin when DIR de-asserts. This is shown as CLOCK (output) in Figure 4. If no crystal is attached and a 60 MHz clock is driven into the CLOCK pin, DIR will de-assert when internal clocks have synchronized. This is shown as CLOCK (input) in Figure 4. The recommended power-up sequence for the link is as follows: * The link waits for 1 ms, ignoring all the ULPI pin status. * The link may start to detect DIR status level. If DIR is detected as LOW for three clock cycles, the link may send a RESET command. * The ULPI interface is ready for use. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 20 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver VCC VCC(I/O) REG1V8 tPWRUP internal REG1V8 detector internal POR XTAL1 (input) CLOCK (input) XTAL1 (output) bus idle internal clocks stable tstartup(PLL) CLOCK (output) RESET command DATA[7:0] TXCMD D internal reset RXCMD update DIR STP NXT t1 t2 t3 t4 t5 t6 004aaa885 t1 = VCC and VCC(I/O) are applied to the ISP1505. The ISP1505 regulator starts to turn on. If the ISP1505 CLOCK pin is configured as an input, the VCC(I/O) power must be provided at the same time as the VCC power. If the VCC(I/O) power input is delayed with respect to VCC, input clock mode stability cannot be guaranteed. t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during tPWRUP. t3 = The POR threshold is reached and the POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined level. DIR is driven to HIGH and the other pins are driven to LOW. t4 = The 19.2 MHz or 26 MHz input clock starts. This clock may be started any time. t5 = The internal PLL is stabilized after tstartup(PLL). If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will be stabilized after tstartup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW. The DIR pin will remain LOW before the link issues a RESET command to the ISP1505. t6 = The power-up sequence is completed and the ULPI bus interface is ready for use. Fig 4. Power-up and reset sequence required before the ULPI bus is ready for use ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 21 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 9.3.1 Interface protection By default, the ISP1505 enables a weak pull-up resistor on STP. If the STP pin is unexpectedly HIGH at any time, the ISP1505 will protect the ULPI interface by enabling weak pull-down resistors on DATA[7:0]. The interface protect feature prevents unwanted activity of the ISP1505 whenever the ULPI interface is not correctly driven by the link. For example, when the link powers up more slowly than the ISP1505. The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1. 9.3.2 Interface behavior with respect to RESET_N The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the ISP1505 will assert DIR. All logic in the ISP1505 will be reset, including the analog circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW; otherwise undefined behavior may result. When RESET_N is de-asserted (HIGH), the DIR output will de-assert (LOW) four or five clock cycles later. Figure 5 shows the ULPI interface behavior when RESET_N is asserted (LOW), and when RESET_N is subsequently de-asserted (HIGH). If RESET_N is not used, it must be tied to VCC(I/O). CLOCK RESET_N DATA[7:0] Hi-Z (input) Hi-Z (link must drive) Hi-Z (input) Hi-Z (link must drive) Hi-Z (input) DIR STP Hi-Z (input) NXT 004aaa720 Fig 5. Interface behavior with respect to RESET_N 9.4 VBUS power and fault detection 9.4.1 Driving 5 V on VBUS The ISP1505 supports external 5 V supplies. The ISP1505 can control the external supply using the active-LOW PSW_N open-drain output pin. To enable the external supply by driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG Control register to logic 1. When the DRV_VBUS_EXT bit is set, the DRV_VBUS bit can be set to any value and will be ignored. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 22 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 9.4.2 Fault detection The ISP1505 supports external VBUS fault detector circuits. An overcurrent detection circuit is required for host applications that supply more than 100 mA on VBUS for voltages between 4.75 V to 5.25 V. For low-power applications supplying less than 100 mA, the VBUS power line can directly be connected to the VBUS pin on the ISP1505 and the link can utilize the internal A_VBUS_VLD comparator. The ISP1505 supports external VBUS fault detector circuits that output a digital fault indicator signal. The indicator signal must be connected to the VBUS/FAULT pin. To enable the ISP1505 to monitor the digital overcurrent input, the link must set the USE_EXT_VBUS_IND bit in the OTG Control register. By default, the digital indicator is interpreted by the ISP1505 as active LOW. That is, a LOW value on VBUS/FAULT indicates a fault condition has been detected. If the external fault detector provides an active HIGH digital indicator, the link must set the IND_COMPL bit in the Interface Control register to logic 1. The IND_PASSTHRU bit must be set to logic 1. By default, the ISP1505 will qualify the external FAULT input with the internal VBUS valid comparator. This can be disabled by setting the IND_PASSTHRU bit to logic 0. 9.5 TXCMD and RXCMD Commands between the ISP1505 and the link are described in the following subsections. 9.5.1 TXCMD By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1505 by sending a byte called TXCMD. Commands include USB packet transmissions, and register reads and writes. Once the TXCMD is interpreted and accepted by the ISP1505, the NXT signal is asserted and the link can follow up with the required number of data bytes. The TXCMD byte format is given in Table 8. Any values other than those in Table 8 are illegal and may result in undefined behavior. Various TXCMD packet and register sequences are shown in later sections. Table 8. TXCMD byte format Command Command code type name DATA[7:6] Command Command payload DATA[5:0] name Command description Idle 00b 00 0000b NOOP No operation. 00h is the idle value of the data bus. The link must drive NOOP by default. Packet transmit 01b 00 0000b NOPID Transmit USB data that does not have a PID, such as chirp and resume signaling. The ISP1505 starts transmitting only after accepting the next data byte. 00 XXXXb PID Transmit USB packet. DATA[3:0] indicates USB packet identifier PID[3:0]. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 23 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 8. TXCMD byte format ...continued Command Command code type name DATA[7:6] Command Command payload DATA[5:0] name Command description Register write 10 1111b EXTW Extended register write command (optional). The 8-bit address must be provided after the command is accepted. XX XXXXb REGW Register write command with 6-bit immediate address. 10 1111b EXTR Extended register read command (optional). The 8-bit address must be provided after the command is accepted. XX XXXXb REGR Register read command with 6-bit immediate address. Register read 10b 11b 9.5.2 RXCMD The ISP1505 communicates status information to the link by asserting DIR and sending an RXCMD byte on the DATA bus. The RXCMD data byte format is given in Table 9. The ISP1505 will automatically send an RXCMD whenever there is a change in any of the RXCMD data fields. The link must be able to accept an RXCMD at any time; including single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive packets when NXT is LOW. An example is shown in Figure 6. For details and diagrams, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt condition is removed before exiting. Table 9. RXCMD byte format DATA Name Description and value 1 to 0 LINESTATE LINESTATE signals: For a definition of LINESTATE, see Section 9.5.2.1. DATA0 -- LINESTATE[0] DATA1 -- LINESTATE[1] 3 to 2 5 to 4 VBUS state RxEvent Encoded VBUS voltage state: For an explanation of the VBUS state, see Section 9.5.2.2. Value VBUS voltage SESS_END SESS_VLD A_VBUS_VLD 00 VBUS < VB_SESS_END 1 0 0 01 VB_SESS_END VBUS < VB_SESS_VLD 0 0 0 10 VB_SESS_VLD VBUS < VA_VBUS_VLD X 1 0 11 VBUS VA_VBUS_VLD X X 1 Encoded USB event signals: For an explanation of RxEvent, see Section 9.5.2.3. Value RxActive RxError HostDisconnect 00 0 0 0 01 1 0 0 11 1 1 0 10 X X 1 6 reserved - 7 ALT_INT By default, this signal is not used and is not needed in typical designs. Optionally, the link can enable the BVALID_RISE and/or BVALID_FALL bits in the Power Control register. Corresponding changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit asserted. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 24 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver CLOCK Single RXCMD turnaround DATA[ 7:0] RXCMD Back-to-back RXCMDs turnaround turnaround RXCMD RXCMD turnaround DIR STP NXT 004aaa695 Fig 6. Single and back-to-back RXCMDs from the ISP1505 to the link 9.5.2.1 Linestate encoding LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1505 detects a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0] value. The value given on LINESTATE[1:0] depends on the setting of various registers. Table 10 shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to peripherals. Table 11 shows the LINESTATE[1:0] encoding for downstream facing ports, which applies to Host Controllers. Dual-role devices must choose the correct table, depending on whether it is in peripheral or host mode. Table 10. LINESTATE[1:0] encoding for upstream facing ports: peripherals DP_PULLDOWN = 0.[1] Mode Full-speed High-speed Chirp XCVRSELECT[1:0] 01, 11 00 00 TERMSELECT 1 0 1 LINESTATE[1:0] [1] 00 SE0 squelch squelch 01 FS-J !squelch !squelch and HS_Differential_Receiver_Output 10 FS-K invalid !squelch and !HS_Differential_Receiver_Output 11 SE1 invalid invalid !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 25 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 11. LINESTATE[1:0] encoding for downstream facing ports: host DP_PULLDOWN and DM_PULLDOWN = 1.[1] Mode Low-speed Full-speed High-speed Chirp XCVRSELECT[1:0] 10 01, 11 00 00 TERMSELECT 1 1 0 0 OPMODE[1:0] X X 00, 01, 11 10 00 SE0 SE0 squelch squelch 01 LS-K FS-J !squelch !squelch and HS_Differential_Receiver_Output 10 LS-J FS-K invalid !squelch and !HS_Differential_Receiver_Output 11 SE1 SE1 invalid invalid LINESTATE[1:0] [1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output. 9.5.2.2 VBUS state encoding USB devices must monitor the VBUS voltage for purposes such as overcurrent detection, starting a session and SRP. The VBUS state field in the RXCMD is an encoding of the voltage level on VBUS. The A_VBUS_VLD, SESS_VLD and SESS_END indicators in the VBUS state are directly taken from internal comparators built-in to the ISP1505, and encoded as shown in Table 9. An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt condition is removed before exiting. Note that VBUS and FAULT share the same pin and cannot be simultaneously used. A_VBUS_VLD and FAULT will be interpreted by the ISP1505 as shown in Figure 7. A description on how to use and select the VBUS state encoding is given in Section "Using and selecting the VBUS state encoding". A_VBUS_VLD comparator (VBUS < 4.4 V) internal A_VBUS_VLD VBUS/FAULT (0, X) RXCMD A_VBUS_VLD complement output (1, 1) IND_COMPL USE_EXT_VBUS_IND, IND_PASSTHRU 004aaa752 Fig 7. RXCMD A_VBUS_VLD indicator source ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 26 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Using and selecting the VBUS state encoding: The VBUS state encoding is shown in Table 9. The ISP1505 will send an RXCMD to the link whenever there is a change in the VBUS state. To receive the VBUS state updates, the link must first enable the corresponding interrupts in the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers. The link can use the VBUS state to monitor VBUS and take appropriate action. Table 12 shows the recommended usage for typical applications. Table 12. VBUS indicators in RXCMD for typical applications Application A_VBUS_VLD SESS_VLD SESS_END Standard host yes no no Standard peripheral no yes no OTG A-device yes yes no OTG B-device no yes yes Standard USB Host Controllers: For standard hosts, the system must be able to provide 500 mA on VBUS in the range of 4.75 V to 5.25 V. An external circuit must be used to detect overcurrent conditions. If the external overcurrent detector provides a digital fault signal, then the fault signal must be connected to the ISP1505 FAULT input pin, and the link must do the following: 1. If the external overcurrent circuit has an active LOW fault or overcurrent indicator, set the IND_COMPL bit in the Interface Control register to logic 1. 2. Set the IND_PASSTHRU bit in the Interface Control register to logic 1. 3. Set the USE_EXT_VBUS_IND bit in the OTG Control register to logic 1. Standard USB Peripheral Controllers: Standard peripherals must be able to detect when VBUS is at a sufficient level for operation. SESS_VLD must be enabled to detect the start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END thresholds is not needed for standard peripherals. OTG devices: The ISP1505 provides partial OTG support. A low-power OTG A-device that supplies less than 100 mA on VBUS can connect the VBUS power to the ISP1505 VBUS pin. The internal A_VBUS_VLD comparator can be used. If the OTG A-device provides more than 100 mA on VBUS, an overcurrent detector must be used and "Standard USB Host Controllers" applies. The OTG A-device also uses SESS_VLD to detect when an OTG A-device is initiating VBUS pulsing SRP. When an OTG device is configured as an OTG B-device, SESS_VLD must be used to detect when VBUS is at a sufficient level for operation. SESS_END must be used to detect when VBUS has dropped to a LOW level, allowing the B-device to safely initiate VBUS pulsing SRP. 9.5.2.3 RxEvent encoding The RxEvent field of the RXCMD informs the link of information related packets received on the USB bus. RxActive and RxError are defined in USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05. HostDisconnect is defined in UTMI+ Specification Rev. 1.0. A short definition is also given in the following subsections. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 27 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver RxActive: When the ISP1505 has detected a SYNC pattern on the USB bus, it signals an RxActive event to the link. An RxActive event can be communicated using two methods. The first method is for the ISP1505 to simultaneously assert DIR and NXT. The second method is for the ISP1505 to send an RXCMD to the link with the RxActive field in RxEvent bits set to logic 1. The link must be able to detect both methods. RxActive frames the receive packet from the first byte to the last byte. The link must assume that RxActive is set to logic 0 when indicated in an RXCMD or when DIR is de-asserted, whichever occurs first. The link uses RxActive to time high-speed packets and ensure that bus turnaround times are met. For more information on the USB packet timing, see Section 9.8.1. RxError: When the ISP1505 has detected an error while receiving a USB packet, it de-asserts NXT and sends an RXCMD with the RxError field set to logic 1. The received packet is no longer valid and must be dropped by the link. HostDisconnect: HostDisconnect is encoded into the RxEvent field of the RXCMD. HostDisconnect is valid only when the ISP1505 is configured as a host (both DP_PULLDOWN and DM_PULLDOWN are set to logic 1), and indicates to the Host Controller when a peripheral is connected or disconnected. The Host Controller must enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers, respectively. Changes in HostDisconnect will cause the PHY to send an RXCMD to the link with the updated value. 9.6 Register read and write operations Figure 8 shows register read and write sequences. The ISP1505 supports immediate addressing and extended addressing register operations. Extended register addressing is optional for links. Note that register operations will be aborted if the ISP1505 unexpectedly asserts DIR during the operation. When a register operation is aborted, the link must retry until successful. For more information on register operations, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 28 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver CLOCK TXCMD (REGW) D TXCMD (EXTW) AD D TXCMD (REGR) D TXCMD (EXTW) AD D DATA[7:0] immediate register write extended register write immediate register read extended register read DIR STP NXT 004aaa710 AD indicates the address byte, and D indicates the data byte. Fig 8. Example of register write, register read, extended register write and extended register read 9.7 USB reset and high-speed detection handshake (chirp) Figure 9 shows the sequence of events for USB reset and high-speed detection handshake (chirp). The sequence is shown for hosts and peripherals. Figure 9 does not show all RXCMD updates and timing is not to scale. The sequence is as follows: 1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow the remainder of this protocol. If a host detects a full-speed peripheral, it resets the peripheral by writing to the Function Control register and setting XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b, which drives SE0 on the bus (DP and DM connected to ground through 45 ). The host also sets OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled T0. Remark: To receive the chirp signaling, the host must also consider the high-speed differential receiver output. The Host Controller must interpret LINESTATE[1:0] as shown in Table 11. 2. High-speed detection handshake (chirp) a. Peripheral chirp: After detecting SE0 for no less than 2.5 s, if the peripheral is capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more than 7 ms after reset time T0. If the peripheral is in low-power mode, it must wake up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock). b. Host chirp: If the host does not detect the peripheral chirp, it must continue asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for no less than 2.5 s, then no more than 100 s after the bus leaves the Chirp K ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 29 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks and Js. Each Chirp K or Chirp J must last for no less than 40 s and no longer than 60 s. c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each Chirp K and Chirp J must be detected for at least 2.5 s. After seeing that minimum sequence, the peripheral sets TERMSELECT = 0b and OPMODE[1:0] = 00b. The peripheral is now in high-speed mode and sees !squelch (01b on LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it knows that the host has completed chirp and waits for the high-speed USB traffic to begin. After transmitting the chirp sequence, the host changes OPMODE[1:0] to 00b and begins sending USB packets. For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 30 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver USB reset high-speed detection handshake (chirp) T0 TXCMD (REGW) SE0 K HS idle host chirp peripheral chirp 00 TXCMD NOPID K ... J K J TXCMD (REGW) DATA [ 7:0] DIR ULPI host STP NXT 00 (HS) 01 (FS) XCVR SELECT TERM SELECT 00 (normal) 00 (normal) 01 (chirp) OP MODE J (01b) SE0 (00b) peripheral chirp K (10b) squelch (00b) host chirp K (10b) or chirp J (01b) squelch (00b) LINE STATE TXCMD SE0 (REGW) TXCMD NOPID K RXCMDs K ... K 00 K J K J K TXCMD J (REGW) 00 DATA [ 7:0] DIR ULPI peripheral STP NXT 00 (HS) 01 (FS) XCVR SELECT TERM SELECT 00 (normal) 10 (chirp) 00 (normal) OP MODE J (01b) SE0 (00b) peripheral chirp K (10b) squelch (00b) host chirp K or J (10b or 01b) !squelch (01b) squelch (00b) USB signals LINE STATE DP DM 004aaa711 Timing is not to scale. Fig 9. USB reset and high-speed detection handshake (chirp) sequence ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 31 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 9.8 USB packet transmit and receive An example of a packet transmit and receive is shown in Figure 10. For details on USB packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1. link sends TXCMD ISP1505 accepts TXCMD link sends the next data; ISP1505 link signals accepts end of data ISP1505 ISP1505 ISP1505 deasserts asserts DIR, ISP1505 sends sends DIR, causing causing RXCMD ULPI bus turnaround USB data turnaround (NXT LOW) (NXT HIGH) is idle cycle cycle CLOCK DATA[ 7:0] TXCMD turnaround DATA RXCMD DATA turnaround DIR STP NXT 004aaa705 Fig 10. Example of using the ISP1505 to transmit and receive USB data 9.8.1 USB packet timing 9.8.1.1 ISP1505 pipeline delays The ISP1505 delays are shown in Table 13. For a detailed description, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.2. Table 13. PHY pipeline delays Parameter name High-speed PHY delay Full-speed PHY delay Low-speed PHY delay RXCMD delay (J and K) 4 4 4 RXCMD delay (SE0) 4 4 to 6 16 to 18 TX start delay 1 to 2 6 to 10 74 to 75 TX end delay (packets) 3 to 4 not applicable not applicable TX end delay (SOF) 6 to 9 not applicable not applicable RX start delay 5 to 6 not applicable not applicable RX end delay 5 to 6 17 to 18 122 to 123 9.8.1.2 Allowed link decision time The amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back packets is given in Table 14. Link designs must follow values given in Table 14 for correct USB system operation. Examples of high-speed packet sequences and timing are shown in Figure 11 and Figure 12. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.3. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 32 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 14. Link decision times Packet sequence High-speed Full-speed link delay link delay Low-speed link delay Definition Transmit-Transmit (host only) 77 to 247 Number of clocks a host link must wait before driving the TXCMD for the second packet. 15 to 24 7 to 18 In high-speed, the link starts counting from the assertion of STP for the first packet. In full-speed, the link starts counting from the RXCMD, indicating LINESTATE has changed from SE0 to J for the first packet. The timing given ensures inter-packet delays of 2 bit times to 6.5 bit times. Receive-Transmit (host or peripheral) 1 to 14 7 to 18 77 to 247 Number of clocks the link must wait before driving the TXCMD for the transmit packet. In high-speed, the link starts counting from the end of the receive packet; de-assertion of DIR or an RXCMD, indicating RxActive is LOW. In full-speed or low-speed, the link starts counting from the RXCMD, indicating LINESTATE has changed from SE0 to J for the receive packet. The timing given ensures inter-packet delays of 2 bit times to 6.5 bit times. Receive-Receive (peripheral only) 1 1 1 Minimum number of clocks between consecutive receive packets. The link must be able to receive both packets. Transmit-Receive (host or peripheral) 92 80 718 Host or peripheral transmits a packet and will time-out after this amount of clock cycles if a response is not received. Any subsequent transmission can occur after this time. USB interpacket delay (88 to 192 high-speed bit times) DP or DM DATA IDLE EOP SYNC CLOCK DN-1 DN TXCMD D0 D1 DATA [7:0] DIR STP NXT link decision time (15 to 24 clocks) TX end delay (two to five clocks) TX start delay (one to two clocks) 004aaa712 Fig 11. High-speed transmit-to-transmit packet timing ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 33 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver USB interpacket delay (8 to 192 high-speed bit times) DP or DM IDLE EOP DATA SYNC CLOCK DN DN-2 DN-4 TXCMD D0 D1 DATA [7:0] DN-3 DN-1 turnaround DIR STP NXT RX end delay (three to eight clocks) link decision time (1 to 14 clocks) TX start delay (one to two clocks) 004aaa713 Fig 12. High-speed receive-to-transmit packet timing 9.9 Preamble Preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. To enter preamble mode, the link sets XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the ISP1505 operates just as in full-speed mode, and sends all data with the full-speed rise and fall times. Whenever the link transmits a USB packet in preamble mode, the ISP1505 will automatically send a preamble header at full-speed bit rate before sending the link packet at low-speed bit rate. The ISP1505 will ensure a minimum gap of four full-speed bit times between the last bit of the full-speed PRE PID and the first bit of the low-speed packet SYNC. The ISP1505 will drive a J for at least one full-speed bit time after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus. An example transmit packet is shown in Figure 13. In preamble mode, the ISP1505 can also receive low-speed packets from the full-speed bus. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 34 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver CLOCK TXCMD (low-speed packet ID) DATA[7:0] D0 D1 DIR STP NXT DP or DM FS SYNC FS PRE ID IDLE (min 4 FS bits) LS SYNC LS PID LS D0 LS D1 004aaa714 DP and DM timing is not to scale. Fig 13. Preamble sequence 9.10 USB suspend and resume 9.10.1 Full-speed and low-speed host-initiated suspend and resume Figure 14 illustrates how a host or a hub places a full-speed or low-speed peripheral into suspend and sometime later initiates resume signaling to wake up the downstream peripheral. Note that Figure 14 timing is not to scale, and does not show all RXCMD LINESTATE updates. The sequence of events for a host and a peripheral, both with ISP1505, is as follows: 1. Idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 k pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is set to 1b). 2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state. The peripheral link places the PHY into low-power mode by setting the SUSPENDM bit in the Function Control register, causing the PHY to draw only suspend current. The host may or may not be powered down. 3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to 10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on LINESTATE, and asserts STP to wake up the PHY. 4. EOP: When STP is asserted, the ISP1505 on the host side automatically appends an EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1505 on the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0] to 00b for normal operation. The peripheral link sees the EOP and also resumes normal operation. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 35 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver SUSPEND IDLE FS or LS host (XCVRSELECT = 01b (FS) or 10b (LS), DPPULLDOWN = 1b, DMPULLDOWN = 1b, TERMSELECT = 1b) TXCMD (REGW) EOP RESUME K TXCMD NOPID K K ... IDLE TXCMD K DATA [ 7:0] DIR STP NXT OPMODE 10b 00b LINE STATE K J 00b J SE0 FS or LS peripheral (XCVRSELECT = 01b (FS) or 10b (LS), DPPULLDOWN = 0b, TERMSELECT = 1b) CLK TXCMD (REGW) LINESTATE J LINE STATE K SE0 J DATA [ 7:0] DIR STP NXT OPMODE 00b 10b 00b SUSPEND M USB signals (only FS is shown) LINE STATE K J SE0 J DP DM 004aaa715 Timing is not to scale. Fig 14. Full-speed suspend and resume 9.10.2 High-speed suspend and resume Figure 15 illustrates how a host or a hub places a high-speed enabled peripheral into suspend and then initiates resume signaling. The high-speed peripheral will wake up and return to high-speed operations. Note that Figure 15 timing is not to scale, and does not show all RXCMD LINESTATE updates. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 36 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver The sequence of events related to a host and a peripheral, both with ISP1505, is as follows: 1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 terminations enabled (TERMSELECT is set to 0b). The peripheral has its 45 terminations enabled (TERMSELECT is set to 0b). 2. Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend state. The peripheral link places the ISP1505 into full-speed mode (XCVRSELECT is set to 01b), removes 45 terminations, and enables the 1.5 k pull-up resistor on DP (TERMSELECT is set to 1b). The peripheral link then places the ISP1505 into low-power mode by setting SUSPENDM, causing the ISP1505 to draw only suspend current. The host also changes the ISP1505 to full-speed (XCVRSELECT is set to 01b), removes 45 terminations (TERMSELECT is set to 1b), and then may or may not be powered down. 3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE to 10b and transmits a full-speed K for at least 20 ms. The peripheral link sees the resume K (10b) on LINESTATE, and asserts STP to wake up the ISP1505. 4. High-speed traffic: The host link sets high-speed (XCVRSELECT is set to 00b) and enables its 45 terminations (TERMSELECT is set to 0b). The peripheral link sees SE0 on LINESTATE and also sets high-speed (XCVRSELECT is set to 00b), and enables its 45 terminations (TERMSELECT is set to 0b). The host link sets OPMODE to 00b for normal high-speed operation. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 37 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver FS SUSPEND HS IDLE RESUME K TXCMD TXCMD (REGW) NOPID K K TXCMD (REGW) HS IDLE TXCMD ... K (REGW) ULPI HS host (DPPULLDOWN = 1b, DMPULLDOWN = 1b) DATA [ 7:0] DIR STP NXT XCVR SELECT 01b 00b 00b TERM SELECT OP MODE !SQUELCH SQUELCH (00b) (01b) LINE STATE 00b FS J (01b) 10b 00b FS K (10b) SQUELCH (00b) !SQUELCH (01b) CLK TXCMD (REGW) TXCMD SE0 (REGW) LINESTATE K LINESTATE J ULPI HS peripheral (DPPULLDOWN = 0b) DATA [ 7:0] DIR STP NXT XCVR SELECT 01b 00b 00b TERM SELECT OP MODE SUSPEND M USB signals LINE STATE 10b 00b !SQUELCH SQUELCH (01b) (00b) FS J (01b) FS K (10b) 00b SQUELCH (00b) !SQUELCH (01b) DP DM 004aaa717 Timing is not to scale. Fig 15. High-speed suspend and resume ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 38 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 9.10.3 Remote wake-up The ISP1505 supports peripherals that initiate remote wake-up resume. When placed into USB suspend, the peripheral link remembers at what speed it was originally operating. Depending on the original speed, the link follows one of the protocols detailed here. In Figure 16, timing is not to scale, and not all RXCMD LINESTATE updates are shown. The sequence of events related to a host and a peripheral, both with ISP1505, is as follows: 1. Both the host and the peripheral are assumed to be in low-power mode. 2. The peripheral begins remote wake-up by re-enabling its clock and setting its SUSPENDM bit to 1b. 3. The peripheral begins driving K on the bus to signal resume. Note that the peripheral link must assume that LINESTATE is K (01b) while transmitting because it will not receive any RXCMDs. 4. The host recognizes the resume, re-enables its clock and sets its SUSPENDM bit. 5. The host takes over resume driving within 1 ms of detecting the remote wake-up. 6. The peripheral stops driving resume. 7. The peripheral sees the host continuing to drive the resume. 8. The host stops driving resume and the ISP1505 automatically adds the EOP to the end of the resume. The peripheral recognizes the EOP as the end of resume. 9. Both the host and the peripheral revert to normal operation by writing 00b to OPMODE. If the host or the peripheral was previously in high-speed mode, it must revert to high-speed before the SE0 of the EOP is completed. This can be achieved by writing XCVRSELECT = 00b and TERMSELECT = 0b after LINESTATE indicates SE0. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 39 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver TXCMD REGW LINESTATE TXCMD NOPID TXCMD REGW 00h DATA [ 7:0] ULPI host DIR STP NXT XCVR SELECT 00b (HS only) 01b (FS), 10b (LS) TERM SELECT 0b (HS only) OP MODE 00b 10b LINESTATE TXCMD REGW TXCMD NOPID RXCMD 00h RXCMD TXCMD RXCMD REGW DATA [ 7:0] ULPI peripheral DIR STP NXT 00b (HS only) XCVR SELECT 00b (HS), 01b (FS), 10b (LS) TERM SELECT 0b (HS only) OP MODE 10b 00b 004aaa718 Timing is not to scale. Fig 16. Remote wake-up from low-power mode 9.11 No automatic SYNC and EOP generation (optional) This setting allows the link to turn off the automatic SYNC and EOP generation, and must be used for high-speed packets only. It is provided for backward compatibility with legacy controllers that include SYNC and EOP bytes in the data payload when transmitting packets. The ISP1505 will not automatically generate the SYNC and EOP patterns when OPMODE[1:0] is set to 11b. The ISP1505 will still NRZI encode data and perform bit stuffing. An example of a sequence is shown in Figure 17. The link must always send packets using the TXCMD (NOPID) type. The ISP1505 does not provide a mechanism to control bit stuffing in individual bytes, but will automatically turn off bit stuffing for EOP when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 40 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver PHY will not transmit any EOP. The ISP1505 will also detect if the PID byte is A5h, indicating an SOF packet, and automatically send a long EOP when STP is asserted. To transmit chirp and resume signaling, the link must set OPMODE[1:0] to 10b. CLOCK ULPI signals DN - 1 DATA [7:0] TXCMD 00h 00h 00h 80h PID D1 D2 D3 ... ... DN FEh DIR STP TX VALID TX READY TXBIT STUFF ENABLE USB bus UTMI+ equivalent signals NXT DP, DM IDLE SYNC PID DATA PAYLOAD EOP IDLE 004aaa719 Fig 17. Transmitting USB packets without the automatic SYNC and EOP generation 9.12 On-The-Go operations On-The-Go (OTG) is a supplement to Universal Serial Bus Specification Rev. 2.0 that allows a portable USB device to assume the role of a limited USB host by defining improvements, such as a small connector and low power. Non-portable devices, such as standard hosts and embedded hosts, can also benefit from OTG features. The ISP1505 OTG PHY is designed to support all the tasks specified in the OTG supplement. The ISP1505 provides the front-end analog support for Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The supporting components include: * Voltage comparators - A_VBUS_VLD - SESS_VLD (session valid, can be used for both A-session and B-session valid) - SESS_END (session end) * Pull-up and pull-down resistors on DP and DM * Charge and discharge resistors on VBUS For complete OTG support, the system designer must add a VBUS power supply and detect the value on the ID pin of the USB cable. This is not provided on the ISP1505. The following subsections describe how to use the ISP1505 OTG components. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 41 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 9.12.1 OTG comparators The ISP1505 provides comparators that conform to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2 requirements of VA_VBUS_VLD, VA_SESS_VLD, VB_SESS_VLD and VB_SESS_END. In this data sheet, VA_SESS_VLD and VB_SESS_VLD are combined into VB_SESS_VLD. Comparators are described in Section 7.6. Changes in comparator values are communicated to the link by RXCMDs as described in Section 9.5.2.2. Control over comparators is described in Section 10.1.5 to Section 10.1.8. 9.12.2 Pull-up and pull-down resistors The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link must set the required bus state using mode settings given in Table 7. 9.12.3 VBUS charge and discharge resistors A pull-up resistor, RUP(VBUS), is provided to perform VBUS pulsing SRP. A B-device is allowed to charge VBUS above the session valid threshold to request the host to turn on the VBUS power. A pull-down resistor, RDN(VBUS), is provided for a B-device to discharge VBUS. This is done whenever the A-device turns off the VBUS power; the B-device can use the pull-down resistor to ensure VBUS is below VB_SESS_END before starting a session. For details, refer to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2. 9.13 Serial modes The ISP1505 supports both 6-pin serial mode and 3-pin serial mode, controlled by bits 6PIN_FSLS_SERIAL and 3PIN_FSLS_SERIAL of the Interface Control register. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.10. Figure 18 and Figure 19 provide examples of 6-pin serial mode and 3-pin serial mode, respectively. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 42 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver TRANSMIT SYNC DATA RECEIVE EOP SYNC DATA EOP DATA0 (TX_ENABLE) DATA1 (TX_DAT) DATA2 (TX_SE0) DATA4 (RX_DP) DATA5 (RX_DM) DATA6 (RX_RCV) DP DM 004aaa692 Fig 18. Example of transmit followed by receive in 6-bit serial mode TRANSMIT SYNC DATA RECEIVE EOP SYNC DATA EOP DATA0 (TX_ENABLE) DATA1 (TX_DAT/ RX_RCV) DATA2 (TX_SE0/ RX_SE0) DP DM 004aaa693 Fig 19. Example of transmit followed by receive in 3-bit serial mode ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 43 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 9.14 Aborting transfers The ISP1505 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4. 9.15 Avoiding contention on the ULPI data bus Because the ULPI data bus is bidirectional, avoid situations in which both the link and the PHY simultaneously drive the data bus. The following points must be considered while implementing the data bus drive control on the link. After power-up and clock stabilization, default states are as follows: * The ISP1505 drives DIR to LOW. * The data bus is input to the ISP1505. * The ULPI link data bus is output, with all data bus lines driven to LOW. When the ISP1505 wants to take control of the data bus to initiate a data transfer, it changes the DIR value from LOW to HIGH. At this point, the link must disable its output buffers. This needs to be as fast as possible so the link must use a combinational path from DIR. The ISP1505 will not immediately enable its output buffers, but will delay the enabling of its buffers until the next clock edge, avoiding bus contention. When the data transfer is no longer required by the ISP1505, it changes DIR from HIGH to LOW and starts to immediately turn off its output drivers. The link senses the change of DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle, avoiding data bus contention. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 44 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 10. Register map Table 15. Register map overview Field name Size (bits Address (6 bits) R[1] W[2] S[3] C[4] References Vendor ID Low register 8 00h - - - Vendor ID High register 8 01h - - - Product ID Low register 8 02h - - - Product ID High register 8 03h - - - Function Control register 8 04h to 06h 04h 05h 06h Section 10.1.2 on page 46 Interface Control register 8 07h to 09h 07h 08h 09h Section 10.1.3 on page 47 OTG Control register 8 0Ah to 0Ch 0Ah 0Bh 0Ch Section 10.1.4 on page 48 USB Interrupt Enable Rising Edge register 8 0Dh to 0Fh 0Dh 0Eh 0Fh Section 10.1.5 on page 49 USB Interrupt Enable Falling Edge register 8 10h to 12h 10h 11h 12h Section 10.1.6 on page 50 USB Interrupt Status register 8 13h - - - Section 10.1.7 on page 50 Immediate register set Section 10.1.1 on page 45 USB Interrupt Latch register 8 14h - - - Section 10.1.8 on page 51 Debug register 8 15h - - - Section 10.1.9 on page 51 Scratch register 8 16h to 18h 16h 17h 18h Section 10.1.10 on page 52 Reserved (do not use) - Section 10.1.11 on page 52 19h to 2Eh - 2Fh 8 Vendor-specific registers 8 30h to 3Ch Section 10.1.13 on page 52 Power Control register 8 3Dh to 3Fh Section 10.1.14 on page 52 Extended register set - Address (8 bits) - Section 10.1.12 on page 52 Access extended register set Section 10.2 on page 53 Maps to immediate register set above 8 00h to 3Fh - Reserved (do not use) 40h to FFh - 8 [1] Read (R): A register can be read. Read-only if this is the only mode given. [2] Write (W): The pattern on the data bus will be written over all bits of a register. [3] Set (S): The pattern on the data bus is OR-ed with and written to a register. [4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero (cleared). 10.1 Immediate register set 10.1.1 Vendor ID and Product ID registers 10.1.1.1 Vendor ID Low register Table 16 shows the bit description of the register. Table 16. Vendor ID Low register (address R = 00h) bit description Bit Symbol Access Value Description 7 to 0 VENDOR_ID_ LOW[7:0] R Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF; has a fixed value of CCh CCh ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 45 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 10.1.1.2 Vendor ID High register The bit description of the register is given in Table 17. Table 17. Vendor ID High register (address R = 01h) bit description Bit Symbol Access Value Description 7 to 0 VENDOR_ID_ HIGH[7:0] R 04h Vendor ID High: Upper byte of the NXP vendor ID supplied by USB-IF; has a fixed value of 04h 10.1.1.3 Product ID Low register The bit description of the Product ID Low register is given in Table 18. Table 18. Product ID Low register (address R = 02h) bit description Bit Symbol Access 7 to 0 PRODUCT_ID_ R LOW[7:0] 10.1.1.4 Value Description 05h Product ID Low: Lower byte of the NXP product ID number; has a fixed value of 05h Product ID High register The bit description of the register is given in Table 19. Table 19. Product ID High register (address R = 03h) bit description Bit Symbol 7 to 0 PRODUCT_ID_ R HIGH[7:0] Access Value Description 15h Product ID High: Upper byte of the NXP product ID number; has a fixed value of 15h 10.1.2 Function Control register This register controls UTMI function settings of the PHY. The bit allocation of the register is given in Table 20. Table 20. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation Bit Symbol 7 6 5 reserved SUSPENDM RESET Reset Access 4 3 OPMODE[1:0] 2 TERM SELECT 1 0 XCVRSELECT[1:0] 0 1 0 0 0 0 0 1 R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 46 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 21. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description Bit Symbol Description 7 - reserved 6 SUSPENDM Suspend LOW: Active LOW PHY suspend. Places the PHY into low-power mode. The PHY will power down all blocks, except the full-speed receiver, OTG comparators and ULPI interface pins. To come out of low-power mode, the link must assert STP. The PHY will automatically clear this bit when it exits low-power mode. 0b -- Low-power mode 1b -- Powered (default) 5 RESET Reset: Active HIGH transceiver reset. After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not reset the ULPI interface or the ULPI register set. When reset is completed, the PHY will de-assert DIR and automatically clear this bit, followed by an RXCMD update to the link. 0b -- Do not reset (default) 1b -- Reset The link must wait for DIR to de-assert before using the ULPI bus. Does not reset the ULPI interface or the ULPI register set. 4 to 3 OPMODE[1:0] Operation Mode: Selects the required bit-encoding style during transmit. 00b -- Normal operation (default) 01b -- Non-driving 10b -- Disable bit-stuffing and NRZI encoding 11b -- Do not automatically add SYNC and EOP when transmitting; must be used only for high-speed packets 2 TERMSELECT Termination Select: Controls the internal 1.5 k full-speed pull-up resistor and 45 high-speed terminations. Control over bus resistors changes, depending on XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in Table 7. 1 to 0 XCVRSELECT[1:0] Transceiver Select: Selects the required transceiver speed. 00b -- Enable the high-speed transceiver 01b -- Enable the full-speed transceiver 10b -- Enable the low-speed transceiver 11b -- Enable the full-speed transceiver for low-speed packets (full-speed preamble is automatically prefixed) 10.1.3 Interface Control register The Interface Control register enables alternative interfaces. All of these modes are optional features provided for legacy link cores. Setting more than one of these fields results in undefined behavior. Table 22 provides the bit allocation of the register. Table 22. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation Bit Symbol 7 6 5 4 3 2 1 0 INTF_ PROT_DIS IND_PASS THRU IND_ COMPL reserved CLOCK_ SUSPENDM reserved 3PIN_ FSLS_ SERIAL 6PIN_ FSLS_ SERIAL 0 0 0 0 0 0 0 0 R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C Reset Access ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 47 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 23. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description Bit Symbol Description 7 INTF_PROT_DIS Interface Protect Disable: Controls circuitry built into the ISP1505 to protect the ULPI interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1505 will automatically detect when the link stops driving STP. 0b -- Enables the interface protect circuit (default). The ISP1505 attaches a weak pull-up resistor on STP. If STP is unexpectedly HIGH, the ISP1505 attaches weak pull-down resistors on DATA[7:0], protecting data inputs. 1b -- Disables the interface protect circuit, detaches weak pull-down resistors on DATA[7:0], and a weak pull-up resistor on STP. 6 IND_PASSTHRU Indicator Pass-through: The ISP1505 does not support the qualification of an external FAULT with the internal VA_VBUS_VLD comparator. Either a digital FAULT is input on the VBUS/FAULT pin or the VBUS power is connected to the VBUS/FAULT pin, not both. This bit must always be set to logic 1. 0b -- Not supported. 1b -- The complement output signal is not qualified with the internal A_VBUS_VLD comparator. The link must always set this bit to logic 1. 5 IND_COMPL Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the complement output. For details, see Section 9.5.2.2. 0b -- The ISP1505 will not invert the FAULT signal (default). 1b -- The ISP1505 will invert the FAULT signal. 4 - reserved 3 CLOCK_SUSPENDM Clock Suspend LOW: Active LOW clock suspend. Powers down the internal clock circuitry only. By default, the clock will not be powered in 6-pin serial mode or 3-pin serial mode. Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set to logic 1, otherwise this bit is ignored. 0b -- Clock will not be powered in 3-pin or 6-pin serial mode. 1b -- Clock will be powered in 3-pin and 6-pin serial modes. 2 - reserved 1 3PIN_FSLS_SERIAL 3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial interface. The PHY will automatically clear this bit when 3-pin serial mode is exited. 0b -- Full-speed or low-speed packets are sent using the parallel interface. 1b -- Full-speed or low-speed packets are sent using the 3-pin serial interface. 0 6PIN_FSLS_SERIAL 6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial interface. The PHY will automatically clear this bit when 6-pin serial mode is exited. 0b -- Full-speed or low-speed packets are sent using the parallel interface. 1b -- Full-speed or low-speed packets are sent using the 6-pin serial interface. 10.1.4 OTG Control register This register controls various OTG functions of the ISP1505. The bit allocation of the OTG Control register is given in Table 24. Table 24. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation Bit Symbol 7 USE_EXT_ DRV_ VBUS_IND VBUS_EXT Reset Access 6 5 4 3 2 1 0 DRV_ VBUS CHRG_ VBUS DISCHRG_ VBUS DM_PULL DOWN DP_PULL DOWN reserved 0 0 0 0 0 1 1 0 R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 48 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 25. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description Bit Symbol Description 7 USE_EXT_ VBUS_IND Use External VBUS Indicator: Informs the PHY to use an external VBUS overcurrent indicator. 0b -- Use the internal OTG comparator. 1b -- Use the external VBUS valid indicator signal input from the FAULT pin. 6 DRV_VBUS_EXT Drive VBUS External: Controls the external VBUS supply through the RESET_N/PSW_N pin. 0b -- Do not drive PSW_N to LOW, disabling VBUS. 1b -- Drive PSW_N to LOW, enabling VBUS. 5 DRV_VBUS Drive VBUS: Signals the ISP1505 to drive 5 V on VBUS. If DRV_VBUS_EXT is set to logic 1, then setting DRV_VBUS is optional. 4 CHRG_VBUS Charge VBUS: Charges VBUS through a resistor. Used for the VBUS pulsing SRP. The link must first check that VBUS is discharged (see the DISCHRG_VBUS bit), and that both the DP and DM data lines have been LOW (SE0) for 2 ms. 0b -- Do not charge VBUS 1b -- Charge VBUS 3 DISCHRG_VBUS Discharge VBUS: Discharges VBUS through a resistor. If the link sets this bit to logic 1, it waits for an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to 0 to stop the discharge. 0b -- Do not discharge VBUS 1b -- Discharge VBUS 2 DM_PULLDOWN DM Pull Down: Enables the 15 k pull-down resistor on DM. 0b -- Pull-down resistor is not connected to DM. 1b -- Pull-down resistor is connected to DM. 1 DP_PULLDOWN DP Pull Down: Enables the 15 k pull-down resistor on DP. 0b -- Pull-down resistor is not connected to DP. 1b -- Pull-down resistor is connected to DP. 0 - reserved; writing logic 1 will give undefined results 10.1.5 USB Interrupt Enable Rising Edge register The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB Interrupt Status register change from logic 0 to logic 1. By default, all transitions are enabled. Table 26 shows the bit allocation of the register. Table 26. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit allocation Bit 7 6 Symbol Reset Access 5 4 reserved 3 2 1 0 SESS_ END_R SESS_ VALID_R VBUS_ VALID_R HOST_ DISCON_R 0 0 0 1 1 1 1 1 R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 49 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 27. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit description Bit Symbol Description 7 to 4 - reserved 3 SESS_END_R Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on SESS_END. 2 SESS_VALID_R Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on SESS_VLD. 1 VBUS_VALID_R VBUS Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on A_VBUS_VLD. 0 HOST_DISCON_ Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on R HOST_DISCON. 10.1.6 USB Interrupt Enable Falling Edge register The bits in this register enable interrupts and RXCMDs to be sent when the corresponding bits in the USB Interrupt Status register change from logic 1 to logic 0. By default, all transitions are enabled. See Table 28. Table 28. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit allocation Bit 7 6 Symbol 4 reserved Reset Access Table 29. 5 3 2 1 0 SESS_ END_F SESS_ VALID_F VBUS_ VALID_F HOST_ DISCON_F 0 0 0 1 1 1 1 1 R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit description Bit Symbol Description 7 to 4 - reserved 3 SESS_END_F Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on SESS_END. 2 SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on SESS_VLD. 1 VBUS_VALID_F VBUS Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on A_VBUS_VLD. 0 HOST_DISCON_ Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on F HOST_DISCON. 10.1.7 USB Interrupt Status register This register (see Table 30) indicates the current value of the interrupt source signal. Table 30. USB Interrupt Status register (address R = 13h) bit allocation Bit 7 6 Symbol 5 4 reserved 3 2 1 0 SESS_ END SESS_ VALID VBUS_ VALID HOST_ DISCON Reset X X X 0 0 0 0 0 Access R R R R R R R R ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 50 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 31. USB Interrupt Status register (address R = 13h) bit description Bit Symbol Description 7 to 4 - reserved 3 SESS_END Session End: Reflects the current value of the session end voltage comparator. 2 SESS_VALID Session Valid: Reflects the current value of the session valid voltage comparator. 1 VBUS_VALID VBUS Valid: Reflects the current value of the VBUS valid voltage comparator. 0 HOST_DISCON Host Disconnect: Reflects the current value of the host disconnect detector. 10.1.8 USB Interrupt Latch register The bits of the USB Interrupt Latch register are automatically set by the ISP1505 when an unmasked change occurs on the corresponding interrupt source signal. The ISP1505 will automatically clear all bits when the link reads this register, or when the PHY enters low-power mode. Remark: It is optional for the link to read this register when the clock is running because all signal information will automatically be sent to the link through the RXCMD byte. The bit allocation of this register is given in Table 32. Table 32. USB Interrupt Latch register (address R = 14h) bit allocation Bit 7 6 Symbol 5 4 reserved 3 2 1 0 SESS_ END_L SESS_ VALID_L VBUS_ VALID_L HOST_ DISCON_L Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Table 33. USB Interrupt Latch register (address R = 14h) bit description Bit Symbol Description 7 to 4 - reserved 3 SESS_END_L Session End Latch: Automatically set when an unmasked event occurs on SESS_END. Cleared when this register is read. 2 SESS_VALID_L Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD. Cleared when this register is read. 1 VBUS_VALID_L VBUS Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD. Cleared when this register is read. 0 HOST_DISCON_L Host Disconnect Latch: Automatically set when an unmasked event occurs on HOST_DISCON. Cleared when this register is read. 10.1.9 Debug register The bit allocation of the Debug register is given in Table 34. This register indicates the current value of signals useful for debugging. Table 34. Debug register (address R = 15h) bit allocation Bit 7 6 5 Symbol 4 3 2 reserved 1 0 LINE STATE1 LINE STATE0 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 51 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 35. Debug register (address R = 15h) bit description Bit Symbol Description 7 to 2 - reserved 1 LINESTATE1 Line State 1: Contains the current value of LINESTATE 1 0 LINESTATE0 Line State 0: Contains the current value of LINESTATE 0 10.1.10 Scratch register Table 36 shows the bit description of the Scratch register. It is an empty register for testing purposes. Table 36. Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description Bit Symbol Access Value Description 7 to 0 SCRATCH [7:0] R/W/S/C 00h Scratch: This is an empty register byte for testing purposes. Software can read, write, set and clear this register; and the functionality of the PHY will not be affected. 10.1.11 Reserved Registers 19h to 2Eh are not implemented. Operating on these addresses will have no effect on the PHY. 10.1.12 Access extended register set Address 2Fh does not contain register data. Instead it links to the extended register set. The immediate register set maps to the lower end of the extended register set. 10.1.13 Vendor-specific registers Addresses 30h to 3Fh contains vendor-specific registers. 10.1.14 Power Control register Table 37 provides the bit allocation of the Power Control register. Table 37. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation Bit 7 6 Symbol 4 reserved Reset Access 5 3 2 1 0 BVALID_ FALL BVALID_ RISE reserved IGNORE_ RESET 0 0 0 0 0 0 0 0 R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C R/W/S/C ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 52 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 38. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description Bit Symbol Description 7 to 4 - reserved; the link must never write logic 1 to these bits. 3 BVALID_FALL BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID changes from HIGH to LOW, the ISP1505 will send an RXCMD to the link with the ALT_INT bit set to logic 1. This bit is optional and is not necessary for OTG devices. The session valid comparator must be used instead. 2 BVALID_RISE BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID changes from LOW to HIGH, the ISP1505 will send an RXCMD to the link with the ALT_INT bit set to logic 1. This bit is optional and is not necessary for OTG devices. The session valid comparator must be used instead. 1 - reserved 0 IGNORE_RESET Ignore Reset: Selects between the RESET_N and PSW_N functions of the RESET_N/PSW_N pin. The link must set this bit to logic 1, if PSW_N is used in a ganged mode configuration. 0b -- The RESET_N/PSW_N pin behaves as an active-LOW reset input (RESET_N). This is the default setting. 1b -- The RESET_N/PSW_N pin behaves as an active-LOW power switch output (PSW_N). 10.2 Extended register set Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This means a read, write, set or clear operation to these extended addresses will operate on the immediate register set. Addresses 40h to FFh are not implemented. Operating on these addresses will have no effect on the PHY. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 53 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 11. ElectroStatic Discharge (ESD) 11.1 ESD protection The pins that are connected to the USB connector (DP, DM, VBUS and GND) have a minimum of 4 kV ESD protection. Capacitors 0.1 F and 1 F must be connected in parallel from VBUS to GND to achieve this 4 kV ESD protection (see Figure 20). Remark: Capacitors 0.1 F and 1 F are also required by Universal Serial Bus Specification Rev. 2.0. For details on the requirements for CVBUS, see Section 16. RC 1 M RD 1500 charge current limit resistor discharge resistance DEVICE UNDER TEST VBUS A HIGH VOLTAGE DC SOURCE CS 100 pF storage capacitor B 0.1 F 1 F GND 004aaa881 Fig 20. Human body ESD test model 11.2 ESD test conditions A detailed report on test setup and results is available on request. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 54 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 12. Limiting values Table 39. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage VCC(I/O) input/output supply voltage VI input voltage Conditions electrostatic discharge voltage Max Unit -0.5 +4.6 V V -0.5 +4.6 on pins CLOCK, STP, DATA[7:0] and RESET_N/PSW_N -0.5 VCC(I/O) + 0.5 V V on pin VBUS/FAULT -0.5 +6.0 V -0.5 +2.5 V -4 +4 kV -2 +2 kV on pin XTAL1 VESD Min on pins DP, DM, VBUS and GND; ILI < 1 A [1] on all other pins; ILI < 1 A Ilu latch-up current -100 +100 mA Vlu latch-up voltage - 4.6 V Tstg storage temperature -40 +125 C Tj junction temperature -40 +125 C [1] Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor (Human Body Model JESD22-A114D). 13. Recommended operating conditions Table 40. Recommended operating conditions Symbol Parameter VCC supply voltage VCC(I/O) input/output supply voltage VI input voltage Tamb [1] Conditions [1] on pins CLOCK, STP, DATA[7:0] and RESET_N/PSW_N Min Typ Max Unit 3.0 3.3 3.6 V 1.65 - 3.6 V 0 - VCC(I/O) V on pin VBUS/FAULT 0 - 5.5 V on pins DP and DM 0 - 3.6 V on pin XTAL1 0 - 1.95 V -40 +25 +85 C ambient temperature VCC(I/O) should be less than or equal to VCC. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 55 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 14. Static characteristics Table 41. Static characteristics: supply pins VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Min Typ Max Unit V(REG3V3) voltage on pin REG3V3 3.0 3.3 3.6 V V(REG1V8) voltage on pin REG1V8 1.65 1.8 1.95 V 1.0 - 1.5 V low-power mode; VBUS valid detector disabled; 1.5 k pull-up resistor on pin DP disconnected - 30 85 A low-power mode; VBUS valid detector disabled; 1.5 k pull-up resistor on pin DP connected - 215 280 A full-speed idle; no USB activity - 10 - mA VPOR(trip) power-on reset trip voltage ICC supply current Conditions high-speed idle; no USB activity ICC(I/O) [1] supply current on pin VCC(I/O) - 19 - mA full-speed continuous data transmit; 50 pF load on pins DP and DM [1] - 15 - mA full-speed continuous data receive [1] - 11 - mA high-speed continuous data transmit; 45 load on pins DP and DM to ground [1] - 48 - mA high-speed continuous data receive [1] - 28 - mA - - 1 A static current; I/O pins are idle A continuous stream of 1 kB packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling. Table 42. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N) VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - - 0.3 x VCC(I/O) V Input levels VIL LOW-level input voltage VIH HIGH-level input voltage 0.7 x VCC(I/O) - - V IIL LOW-level input current VI = 0 V - - 1 A IIH HIGH-level input current VI = VCC(I/O) - - 1 A ILI input leakage current -1 +0.1 +1 A Output levels VOL LOW-level output voltage IOL = -2 mA - - 0.4 V VOH HIGH-level output voltage IOH = +2 mA VCC(I/O) - 0.4 V - - V IOH HIGH-level output current VO = VCC(I/O) - 0.4 V -4.8 - - mA IOL LOW-level output current VO = 0.4 V 4.2 - - mA IOZ off-state output current 0 V < VO < VCC(I/O) - - 1 A ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 56 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 42. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N) ...continued VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 45 - 65 Impedance load impedance ZL Pull-up and pull-down Ipd pull-down current interface protect enabled; DATA[7:0] pins only; VI = VCC(I/O) 25 50 90 A Ipu pull-up current interface protect enabled; STP pin only; VI = 0 V -30 -50 -80 A pins STP, RESET_N, CLOCK, DATA[7:0] - - 3.5 pF Capacitance input capacitance Cin Table 43. Static characteristics: pin VBUS/FAULT VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Applicable only when pin VBUS/FAULT is used as FAULT. Symbol Parameter Conditions Min Typ Max Unit Input levels VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V IIL LOW-level input current VI = 0 V - - 1 A IIH HIGH-level input current VI = VCC(I/O) - - 1 A Table 44. Static characteristics: analog I/O pins (DP, DM) VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Original USB transceiver (low-speed and full-speed) Input levels (differential receiver) VDI differential input sensitivity |VDP - VDM| 0.2 - - V VCM differential common mode voltage range includes VDI range 0.8 - 2.5 V Input levels (single-ended receivers) VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V Output levels VOL LOW-level output voltage pull-up on pin DP; RL = 1.5 k to 3.6 V 0.0 0.18 0.3 V VOH HIGH-level output voltage pull-down on pins DP and DM; RL = 15 k to GND 2.8 3.2 3.6 V ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 57 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 44. Static characteristics: analog I/O pins (DP, DM) ...continued VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit termination voltage for 1.5 k pull-up resistor 3.0 - 3.6 V 1425 1500 1575 Termination VTERM Resistance RUP(DP) pull-up resistance on pin DP High-speed USB transceiver Input levels (differential receiver) VHSSQ high-speed squelch detection threshold voltage (differential signal amplitude) 100 - 150 mV VHSDSC high-speed disconnect detection threshold voltage (differential signal amplitude) 525 - 625 mV VHSDI high-speed differential input sensitivity |VDP - VDM| 300 - - mV VHSCM high-speed data signaling common mode voltage range includes VDI range -50 - +500 mV VHSOI high-speed idle level -10 - +10 mV VHSOL high-speed data signaling LOW-level voltage -10 - +10 mV Output levels VHSOH high-speed data signaling HIGH-level voltage 360 - 440 mV VCHIRPJ Chirp J level (differential voltage) 700 - 1100 mV VCHIRPK Chirp K level (differential voltage) -900 - -500 mV -1 - +1 A - - 5 pF Leakage current off-state leakage current ILZ Capacitance input capacitance Cin pin to GND Resistance RDN(DP) pull-down resistance on pin DP 14.25 15 15.75 k RDN(DM) pull-down resistance on pin DM 14.25 15 15.75 k Termination driver output impedance on pin DP steady-state drive [1] 40.5 45 49.5 ZO(drv)(DM) driver output impedance on pin DM [1] 40.5 45 49.5 ZINP input impedance 10 - - M ZO(drv)(DP) [1] steady-state drive For high-speed USB and full-speed USB. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 58 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 45. Static characteristics: VBUS comparators VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter VA_VBUS_VLD A-device VBUS valid voltage Conditions Min Typ Max Unit 4.4 4.5 4.65 V VB_SESS_VLD B-device session valid voltage 0.8 1.6 2.0 V Vhys(B_SESS_VLD) B-device session valid hysteresis voltage 70 140 200 mV VB_SESS_END B-device session end voltage 0.2 0.5 0.8 V for A-device and B-device Table 46. Static characteristics: VBUS resistors VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit RUP(VBUS) pull-up resistance on pin VBUS connect to pin REG3V3 when CHRG_VBUS is logic 1 281 680 - RDN(VBUS) pull-down resistance on pin VBUS connect to GND when DISCHRG_VBUS is logic 1 656 850 - RI(idle)(VBUS) idle input resistance on pin VBUS 40 57 80 k Table 47. Static characteristics: resistor reference VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VO(RREF) output voltage on pin RREF SUSPENDM is logic 1 - 1.22 - V ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 59 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 15. Dynamic characteristics Table 48. Dynamic characteristics: reset and clock VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Reset tW(POR) internal power-on reset pulse width 0.2 - - s tw(REG1V8_H) REG1V8 HIGH pulse width 2 - - s tw(REG1V8_L) REG1V8 LOW pulse width 11 - - s tW(RESET_N) external RESET_N pulse width 200 - - ns tPWRUP regulator start-up time 4.7 F 20 % capacitor each on pins REG1V8 and REG3V3 - - 1 ms ISP1505ABS - 19.2 - MHz Crystal or clock applied to XTAL1 fi(XTAL1) input frequency on pin XTAL1 ISP1505CBS tjit(i)(XTAL1)RMS RMS input jitter on pin XTAL1 fi(XTAL1) input frequency tolerance on pin XTAL1 - 26 - MHz ISP1505ABS [1] - - 200 ps ISP1505CBS [1] - - 300 ps - 50 200 ppm tr(XTAL1) rise time on pin XTAL1 only for square wave input - - 5 ns tf(XTAL1) fall time on pin XTAL1 only for square wave input - - 5 ns V(XTAL1)(p-p) peak-to-peak voltage on pin XTAL1 only for square wave input 0.566 - 1.95 V - 60 - MHz - - 200 ps External clock input on CLOCK fi(CLOCK) input frequency on pin CLOCK [1] tjit(i)(CLOCK)RMS RMS input jitter on pin CLOCK fi(CLOCK) input frequency tolerance on pin CLOCK - 50 200 ppm i(CLOCK) input clock duty cycle on pin CLOCK 45 50 55 % - 60 - MHz - - 500 ps Output CLOCK characteristics fo(CLOCK) output frequency on pin CLOCK tjit(o)(CLOCK)RMS RMS output jitter on pin CLOCK o(CLOCK) output clock duty cycle on pin CLOCK 45 50 55 % tstartup(PLL) PLL startup time - 650 - s tstartup(o)(CLOCK) output CLOCK start-up time 450 650 900 s [1] active only when a crystal or clock is input on pin XTAL1 [1] measured from power good or assertion of pin STP RMS = Root Mean Square. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 60 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 49. Dynamic characteristics: digital I/O pins VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Output 60 MHz CLOCK, VCC(I/O) = 1.65 V to 1.95 V tsu(DATA) DATA set-up time with respect to 20 pF total external load the rising edge of pin CLOCK per pin 5.7 - - ns th(DATA) DATA hold time with respect to the rising edge of pin CLOCK 20 pF total external load per pin 0 - - ns td(DATA) DATA output delay with respect 20 pF total external load to the rising edge of pin CLOCK per pin - - 7.8 ns tsu(STP) STP set-up time with respect to the rising edge of pin CLOCK 20 pF total external load per pin 4.5 - - ns th(STP) STP hold time with respect to the rising edge of pin CLOCK 20 pF total external load per pin 0 - - ns td(DIR) DIR output delay with respect to 20 pF total external load the rising edge of pin CLOCK per pin - - 8.9 ns td(NXT) NXT output delay with respect to 20 pF total external load the rising edge of pin CLOCK per pin - - 8.9 ns Output 60 MHz CLOCK, VCC(I/O) = 3.0 V to 3.6 V tsu(DATA) DATA set-up time with respect to 30 pF total external load the rising edge of pin CLOCK per pin 3.3 - - ns th(DATA) DATA hold time with respect to the rising edge of pin CLOCK 0.8 - - ns td(DATA) DATA output delay with respect 30 pF total external load to the rising edge of pin CLOCK per pin - - 5.5 ns tsu(STP) STP set-up time with respect to the rising edge of pin CLOCK 30 pF total external load per pin 3.4 - - ns th(STP) STP hold time with respect to the rising edge of pin CLOCK 30 pF total external load per pin 0.8 - - ns td(DIR) DIR output delay with respect to 30 pF total external load the rising edge of pin CLOCK per pin - - 6.6 ns td(NXT) NXT output delay with respect to 30 pF total external load the rising edge of pin CLOCK per pin - - 6.6 ns 30 pF total external load per pin Input 60 MHz CLOCK, VCC(I/O) = 1.65 V to 1.95 V tsu(DATA) DATA set-up time with respect to 10 pF total external load the rising edge of pin CLOCK per pin 4.9 4.4 - ns th(DATA) DATA hold time with respect to the rising edge of pin CLOCK 0 - - ns td(DATA) DATA output delay with respect 10 pF total external load to the rising edge of pin CLOCK per pin 9.2 5.2 - ns tsu(STP) STP set-up time with respect to the rising edge of pin CLOCK 10 pF total external load per pin 3.5 3.4 - ns th(STP) STP hold time with respect to the rising edge of pin CLOCK 10 pF total external load per pin 0 - - ns td(DIR) DIR output delay with respect to 10 pF total external load the rising edge of pin CLOCK per pin - 4.9 9.3 ns td(NXT) NXT output delay with respect to 10 pF total external load the rising edge of pin CLOCK per pin - 4.9 9.3 ns 10 pF total external load per pin ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 61 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 49. Dynamic characteristics: digital I/O pins ...continued VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Input 60 MHz CLOCK, VCC(I/O) = 3.0 V to 3.6 V tsu(DATA) DATA set-up time with respect to 20 pF total external load the rising edge of pin CLOCK per pin 3.4 3.0 - ns th(DATA) DATA hold time with respect to the rising edge of pin CLOCK 0 - - ns td(DATA) DATA output delay with respect 20 pF total external load to the rising edge of pin CLOCK per pin 7.7 4.1 - ns tsu(STP) STP set-up time with respect to the rising edge of pin CLOCK 20 pF total external load per pin 3.1 2.7 - ns th(STP) STP hold time with respect to the rising edge of pin CLOCK 20 pF total external load per pin 0 - - ns td(DIR) DIR output delay with respect to 20 pF total external load the rising edge of pin CLOCK per pin 7.3 3.8 - ns td(NXT) NXT output delay with respect to 20 pF total external load the rising edge of pin CLOCK per pin 7.3 3.8 - ns 20 pF total external load per pin Table 50. Dynamic characteristics: analog I/O pins (DP, DM) VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit High-speed driver tHSR rise time (10 % to 90 %) 500 - - ps tHSF fall time (10 % to 90 %) 500 - - ps Full-speed driver tFR rise time CL = 50 pF; 10 % to 90 % of |VOH - VOL| 4 - 20 ns tFF fall time CL = 50 pF; 10 % to 90 % of |VOH - VOL| 4 - 20 ns tFRFM differential rise and fall time excluding the first transition matching from the idle state 90 - 111.1 % VCRS output signal crossover voltage excluding the first transition from the idle state 1.3 - 2.0 V Low-speed driver tLR transition time: rise time CL = 200 pF to 600 pF; 1.5 k pull-up on DM enabled; 10 % to 90 % of |VOH - VOL| 75 - 300 ns tLF transition time: fall time CL = 200 pF to 600 pF; 1.5 k pull-up on DM enabled; 10 % to 90 % of |VOH - VOL| 75 - 300 ns tLRFM rise and fall time matching tLR/tLF; excluding the first transition from the idle state 80 - 125 % ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 62 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 50. Dynamic characteristics: analog I/O pins (DP, DM) ...continued VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Driver timing tPLH(drv) driver propagation delay (LOW to HIGH) TX_DAT, TX_SE0 to DP, DM; see Figure 22 - - 11 ns tPHL(drv) driver propagation delay (HIGH to LOW) TX_DAT, TX_SE0 to DP, DM; see Figure 22 - - 11 ns tPHZ driver disable delay from HIGH level TX_ENABLE to DP, DM; see Figure 23 - - 12 ns tPLZ driver disable delay from LOW level TX_ENABLE to DP, DM; see Figure 23 - - 12 ns tPZH driver enable delay to HIGH TX_ENABLE to DP, DM; level see Figure 23 - - 20 ns tPZL driver enable delay to LOW TX_ENABLE to DP, DM; level see Figure 23 - - 20 ns Receiver timing Differential receiver tPLH(rcv) receiver propagation delay (LOW to HIGH) DP, DM to RX_RCV, RX_DP and RX_DM; see Figure 24 - - 17 ns tPHL(rcv) receiver propagation delay (HIGH to LOW) DP, DM to RX_RCV, RX_DP and RX_DM; see Figure 24 - - 17 ns Single-ended receiver tPLH(se) single-ended propagation delay (LOW to HIGH) DP, DM to RX_RCV, RX_DP and RX_DM; see Figure 24 - - 17 ns tPHL(se) single-ended propagation delay (HIGH to LOW) DP, DM to RX_RCV, RX_DP and RX_DM; see Figure 24 - - 17 ns ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 63 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 1.8 V 0.9 V logic input 0.9 V tHSF, tFF, tLF tHSR, tFR, tLR 0V VOH VOL 90 % tPLH(drv) 90 % tPHL(drv) VOH 10 % differential data lines 10 % VCRS VOL 004aaa861 Fig 21. Rise time and fall time VCRS 004aaa573 Fig 22. Timing of TX_DAT and TX_SE0 to DP and DM 2.0 V 1.8 V logic 0.9 V input differential data lines 0.9 V VCRS VCRS 0.8 V 0V VOH tPLH(rcv) tPLH(se) tPHZ tPLZ tPZH tPZL VOH VOH - 0.3 V differential data lines VOL + 0.3 V VOL 004aaa574 Fig 23. Timing of TX_ENABLE to DP and DM 0.9 V 0.9 V logic output VCRS VOL tPHL(rcv) tPHL(se) 004aaa575 Fig 24. Timing of DP and DM to RX_RCV, RX_DP and RX_DM 15.1 ULPI timing ULPI interface timing requirements are given in Figure 25. This timing applies to synchronous mode only. All timing is measured with respect to the ISP1505 CLOCK pin. All signals are clocked on the rising edge of CLOCK. CLOCK tsu(STP) th(STP) CONTROL IN (STP) tsu(DATA) th(DATA) DATA IN (8-BIT) td(DIR), td(NXT) CONTROL OUT (DIR, NXT) td(DATA) td(DIR), td(NXT) DATA OUT (8-BIT) 004aaa722 Fig 25. ULPI timing interface ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 64 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 16. Application information Table 51. Recommended bill of materials Designator[1] Application Value Comment Cbypass highly recommended for all applications 0.1 F - Cfilter highly recommended for all applications 4.7 F 20 %; use a LOW ESR capacitor (0.2 to 2 ) for best performance - CVBUS mandatory for peripherals 0.1 F and 1 F to 10 F in parallel mandatory for host 0.1 F and 120 F 20 % (min) in parallel - mandatory for OTG 0.1 F and 1 F to 6.5 F in parallel - DESD recommended for all ESD-sensitive applications IP4059CX5/LF Wafer-Level Chip-Scale Package (WLCSP); 1.34 mm x 0.96 mm x 0.41 mm; ESD IEC 61000-4-2 level 4; 8 kV contact; 15 kV air discharge Rpullup recommended; for applications 4.7 k to 100 k (10 k with an external VBUS supply recommended) controlled by PSW_N maximum value is determined by the voltage drop on PSW_N caused by leakage into PSW_N and the external supply control pin RRREF mandatory in all applications 12 k 1 % - RVBUS strongly recommended for peripheral or external 5 V applications only 1 k 5 % - RXTAL required only for applications driving a square wave into the XTAL1 pin 47 k 5 % used to avoid floating input on the XTAL1 pin XTAL crystal is used 19.2 MHz CL = 10 pF; RS < 220 ; CXTAL = 18 pF C(XTAL)SQ required only for applications 100 pF driving a square wave into the XTAL1 pin that has a DC offset 26 MHz [1] CL = 10 pF; RS < 130 ; CXTAL = 18 pF used to AC couple the input square wave to the XTAL1 pin For detailed information and alternative interface options, refer to the Interfacing to the ISP1504/5/6 (AN10048) application note. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 65 of 78 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors ISP1505A_ISP1505C_1 Product data sheet VCC VCC(I/O) +5 V Cbypass IN Rpullup ON FAULT VBUS SWITCH DATA1 Cbypass Cbypass DATA0 OUT VCC(I/O) 1 USB STANDARD OR MINI-A RECEPTACLE 3 4 5 6 7 8 VBUS RREF D- DM D+ DP GND VCC SHIELD RVBUS V BUS/FAULT SHIELD REG3V3 SHIELD SHIELD C1 A1 A3 C3 XTAL1 IP4059CX5/LF XTAL2 RESET_N/ PSW_N DESD 2 23 DATA2 VCC(I/O) DATA3 3 22 4 21 CLOCK 5 20 6 7 19 ISP1505 18 17 8 16 9 D0 D1 DATA4 DATA5 DATA6 DATA7 NXT D2 D3 D4 D5 HOST CONTROLLER D6 D7 NXT CLOCK 10 15 11 14 12 13 STP DIR STP DIR RESET_N (optional) REG1V8 004aaa589 GND (die pad) XTAL(1) CVBUS Cbypass Cfilter CXTAL CXTAL Cbypass 66 of 78 (c) NXP B.V. 2006. All rights reserved. (1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz. Fig 26. Using the ISP1505 with a USB Host Controller; external 5 V source with built-in FAULT and external crystal Cfilter ISP1505A; ISP1505C B2 24 ULPI HS USB host and peripheral transceiver Rev. 01 -- 19 October 2006 2 RRREF 1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors ISP1505A_ISP1505C_1 Product data sheet VCC(I/O) Cbypass VCC DATA1 Cbypass Cbypass DATA0 VCC(I/O) 2 3 USB MINI-B OR STANDARD-B 4 RECEPTACLE 5 6 7 D_ DM D+ DP GND SHIELD SHIELD SHIELD SHIELD C1 A1 A3 C3 IP4059CX5/LF 22 DATA3 CLOCK 21 3 4 20 DATA4 5 6 VCC 7 RVBUS V BUS/FAULT 8 DESD D2 D3 D5 18 DATA6 PERIPHERAL CONTROLLER D6 17 DATA7 D7 CLOCK 16 NXT REG3V3 9 B2 D1 D4 19 DATA5 ISP1505 D0 XTAL1 10 15 STP XTAL2 11 14 DIR RESET_N/PSW_N 12 13 NXT STP DIR REG1V8 RESET_N (optional) 004aaa590 GND (die pad) Cbypass Cfilter Cbypass 67 of 78 (c) NXP B.V. 2006. All rights reserved. Fig 27. Using the ISP1505 with a Peripheral Controller; external 60 MHz input on CLOCK Cfilter ISP1505A; ISP1505C 8 VBUS RREF 2 ULPI HS USB host and peripheral transceiver Rev. 01 -- 19 October 2006 1 RRREF 24 DATA2 VCC(I/O) 23 1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors ISP1505A_ISP1505C_1 Product data sheet VCC(I/O) Cbypass VCC DATA1 Cbypass Cbypass DATA0 VCC(I/O) 1 3 USB MINI-B OR STANDARD-B 4 RECEPTACLE 5 6 7 8 VBUS RREF D_ DM D+ DP GND SHIELD SHIELD SHIELD SHIELD C1 A1 A3 C3 2 3 4 20 DATA4 5 6 VCC 7 RVBUS V BUS/FAULT 8 IP4059CX5/LF 22 DATA3 CLOCK 21 19 DATA5 ISP1505 17 DATA7 DESD Cfilter D2 D3 D4 D5 PERIPHERAL CONTROLLER D6 D7 XTAL1 10 15 STP XTAL2 11 RESET_N/ PSW_N 12 14 DIR 13 NXT STP DIR RESET_N (optional) REG1V8 GND (die pad) Cbypass fi(XTAL1)(1) C(XTAL)SQ 68 of 78 (c) NXP B.V. 2006. All rights reserved. (1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz. Fig 28. Using the ISP1505 with a Peripheral Controller; external square wave input on pin XTAL1 RXTAL Cfilter 004aaa896 ISP1505A; ISP1505C Cbypass D1 CLOCK 16 NXT REG3V3 9 B2 18 DATA6 D0 ULPI HS USB host and peripheral transceiver Rev. 01 -- 19 October 2006 2 RRREF 24 DATA2 VCC(I/O) 23 1 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 17. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm A B D SOT616-1 terminal 1 index area A A1 E c detail X e1 C 1/2 e e 12 y y1 C v M C A B w M C b 7 L 13 6 e e2 Eh 1/2 e 1 18 terminal 1 index area 24 19 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 0.5 2.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT616-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 29. Package outline SOT616-1 (HVQFN24) ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 69 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 18. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 18.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 70 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 18.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a PbSn process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 52 and 53 Table 52. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 53. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 71 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 19. Abbreviations Table 54. Abbreviations Acronym Description ASIC Application-Specific Integrated Circuit ATX Analog USB Transceiver CD-RW Compact Disc-Rewritable EOP End-Of-Packet ESD ElectroStatic Discharge FS Full-Speed HBM Human Body Model HNP Host Negotiation Protocol HS High-Speed ID Identification LS Low-Speed MO Magneto-Optical NRZI Non-Return-to-Zero Inverted OTG On-The-Go PCB Printed-Circuit Board PDA Personal Digital Assistant PHY Physical Layer[1] PID Packet Identifier PLD Programmable Logic Device ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 72 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver Table 54. Abbreviations ...continued Acronym Description PLL Phase-Locked Loop POR Power-On Reset RMS Root Mean Square RoHS Restriction of Hazardous Substances RXCMD Receive Command SE0 Single-Ended Zero SOF Start-Of-Frame SRP Session Request Protocol STB Set-Top Box SYNC Synchronous TTL Transistor-Transistor Logic TXCMD Transmit Command USB Universal Serial Bus USB-IF USB Implementers Forum ULPI UTMI+ Low Pin Interface UTMI USB 2.0 Transceiver Macrocell Interface UTMI+ USB 2.0 Transceiver Macrocell Interface Plus [1] Physical layer containing the USB transceiver. The ISP1505 is a PHY. 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.2 [3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 [4] UTMI+ Specification Rev. 1.0 [5] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05 [6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) (JESD22-A114D) [7] Interfacing to the ISP1504/5/6 (AN10048) 21. Revision history Table 55. Revision history Document ID Release date Data sheet status Change notice Supersedes ISP1505A_ISP1505C_1 20061019 Product data sheet - - ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 73 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 22.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 22.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 22.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 23. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 74 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 24. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 ULPI signal description . . . . . . . . . . . . . . . . . .14 Signal mapping during low-power mode . . . . .15 Signal mapping for 6-pin serial mode . . . . . . .16 Signal mapping for 3-pin serial mode . . . . . . .17 Operating states and resistor settings . . . . . . .17 TXCMD byte format . . . . . . . . . . . . . . . . . . . . .23 RXCMD byte format . . . . . . . . . . . . . . . . . . . . .24 LINESTATE[1:0] encoding for upstream facing ports: peripherals . . . . . . . . . . . . . . . . .25 LINESTATE[1:0] encoding for downstream facing ports: host . . . . . . . . . . . . . . . . . . . . . . .26 VBUS indicators in RXCMD for typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . .27 PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .32 Link decision times . . . . . . . . . . . . . . . . . . . . .33 Register map overview . . . . . . . . . . . . . . . . . .45 Vendor ID Low register (address R = 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .45 Vendor ID High register (address R = 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .46 Product ID Low register (address R = 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .46 Product ID High register (address R = 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .46 Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation . . . . . . . . . . . . . . . . . . .46 Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description . . . . . . . . . . . . . . . . . .47 Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation . . . . . . . . . . . . . . . . . . .47 Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description . . . . . . . . . . . . . . . . . .48 OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation . . . . . . . . . . . . . . . . . . .48 OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description . . . . . . . . . . . . . . . . . .49 USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit allocation . . . . . . . . . . . . . . . . . . .49 USB Interrupt Enable Rising Edge register Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit description . . . . . . . . . . . . . . . . . . 50 USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit allocation . . . . . . . . . . . . . . . . . . . 50 USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit description . . . . . . . . . . . . . . . . . . 50 USB Interrupt Status register (address R = 13h) bit allocation . . . . . . . . . . . 50 USB Interrupt Status register (address R = 13h) bit description . . . . . . . . . . 51 USB Interrupt Latch register (address R = 14h) bit allocation . . . . . . . . . . . 51 USB Interrupt Latch register (address R = 14h) bit description . . . . . . . . . . 51 Debug register (address R = 15h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Debug register (address R = 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 52 Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description . . . 52 Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation . . . 52 Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description . . 53 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 55 Recommended operating conditions . . . . . . . . 55 Static characteristics: supply pins . . . . . . . . . . 56 Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N) . . . 56 Static characteristics: pin VBUS/FAULT . . . . . . 57 Static characteristics: analog I/O pins (DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Static characteristics: VBUS comparators . . . . 59 Static characteristics: VBUS resistors . . . . . . . . 59 Static characteristics: resistor reference . . . . . 59 Dynamic characteristics: reset and clock . . . . 60 Dynamic characteristics: digital I/O pins . . . . . 61 Dynamic characteristics: analog I/O pins (DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Recommended bill of materials . . . . . . . . . . . . 65 SnPb eutectic process (from J-STD-020C) . . . 71 Lead-free process (from J-STD-020C) . . . . . . 71 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 73 continued >> ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 75 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 25. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration HVQFN24; top view . . . . . . . . . .5 Internal power-on reset timing . . . . . . . . . . . . . . .19 Power-up and reset sequence required before the ULPI bus is ready for use. . . . . . . . . . . . . . . .21 Interface behavior with respect to RESET_N. . . .22 Single and back-to-back RXCMDs from the ISP1505 to the link. . . . . . . . . . . . . . . . . . . . . . . .25 RXCMD A_VBUS_VLD indicator source . . . . . . .26 Example of register write, register read, extended register write and extended register read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 USB reset and high-speed detection handshake (chirp) sequence . . . . . . . . . . . . . . . .31 Example of using the ISP1505 to transmit and receive USB data . . . . . . . . . . . . . . . . . . . . . . . . .32 High-speed transmit-to-transmit packet timing. . .33 High-speed receive-to-transmit packet timing . . .34 Preamble sequence . . . . . . . . . . . . . . . . . . . . . . .35 Full-speed suspend and resume . . . . . . . . . . . . .36 High-speed suspend and resume . . . . . . . . . . . .38 Remote wake-up from low-power mode . . . . . . .40 Transmitting USB packets without the automatic SYNC and EOP generation. . . . . .41 Example of transmit followed by receive in 6-bit serial mode . . . . . . . . . . . . . . . . . . . . . . .43 Example of transmit followed by receive in 3-bit serial mode . . . . . . . . . . . . . . . . . . . . . . .43 Human body ESD test model. . . . . . . . . . . . . . . .54 Rise time and fall time . . . . . . . . . . . . . . . . . . . . .64 Timing of TX_DAT and TX_SE0 to DP and DM . .64 Timing of TX_ENABLE to DP and DM. . . . . . . . .64 Timing of DP and DM to RX_RCV, RX_DP and RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .64 Using the ISP1505 with a USB Host Controller; external 5 V source with built-in FAULT and external crystal . . . . . . . . . . . . . . . . . . . . . . .66 Using the ISP1505 with a Peripheral Controller; external 60 MHz input on CLOCK . . . . . . . . . . . .67 Using the ISP1505 with a Peripheral Controller; external square wave input on pin XTAL1 . . . . . .68 Package outline SOT616-1 (HVQFN24) . . . . . . .69 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 continued >> ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 76 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 ULPI interface controller . . . . . . . . . . . . . . . . . . 7 7.2 USB serializer and deserializer. . . . . . . . . . . . . 7 7.3 Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7 7.4 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8 7.5 Crystal oscillator and PLL. . . . . . . . . . . . . . . . . 8 7.6 VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 8 7.6.1 VBUS valid comparator . . . . . . . . . . . . . . . . . . . 8 7.6.2 Session valid comparator . . . . . . . . . . . . . . . . . 9 7.6.3 Session end comparator. . . . . . . . . . . . . . . . . . 9 7.7 SRP charge and discharge resistors . . . . . . . . 9 7.8 Band gap reference voltage . . . . . . . . . . . . . . . 9 7.9 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.10 Detailed description of pins . . . . . . . . . . . . . . . 9 7.10.1 DATA[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.10.2 VCC(I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.10.3 RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.10.4 DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.10.5 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.10.6 VBUS/FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.10.6.1 VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.10.6.2 FAULT (external overcurrent or fault detector) 10 7.10.7 REG3V3 and REG1V8 . . . . . . . . . . . . . . . . . . 11 7.10.8 XTAL1 and XTAL2. . . . . . . . . . . . . . . . . . . . . . 11 7.10.9 RESET_N/PSW_N . . . . . . . . . . . . . . . . . . . . . 11 7.10.9.1 RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.10.9.2 PSW_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.10.10 DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.10.11 STP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.10.12 NXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.10.13 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.10.14 GND (die pad). . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Modes of operation . . . . . . . . . . . . . . . . . . . . . 14 8.1 ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 Synchronous mode. . . . . . . . . . . . . . . . . . . . . 14 8.1.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 15 8.1.3 6-pin full-speed or low-speed serial mode . . . 16 8.1.4 3-pin full-speed or low-speed serial mode . . . 16 8.2 USB and OTG state transitions . . . . . . . . . . . 9 Protocol description . . . . . . . . . . . . . . . . . . . . 9.1 ULPI references . . . . . . . . . . . . . . . . . . . . . . . 9.2 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 9.3 Power-up, reset and bus idle sequence . . . . . 9.3.1 Interface protection. . . . . . . . . . . . . . . . . . . . . 9.3.2 Interface behavior with respect to RESET_N. 9.4 VBUS power and fault detection . . . . . . . . . . . 9.4.1 Driving 5 V on VBUS . . . . . . . . . . . . . . . . . . . . 9.4.2 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 9.5 TXCMD and RXCMD . . . . . . . . . . . . . . . . . . . 9.5.1 TXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2.1 Linestate encoding . . . . . . . . . . . . . . . . . . . . . 9.5.2.2 VBUS state encoding . . . . . . . . . . . . . . . . . . . . 9.5.2.3 RxEvent encoding . . . . . . . . . . . . . . . . . . . . . 9.6 Register read and write operations . . . . . . . . 9.7 USB reset and high-speed detection handshake (chirp) . . . . . . . . . . . . . . . . . . . . . 9.8 USB packet transmit and receive . . . . . . . . . . 9.8.1 USB packet timing . . . . . . . . . . . . . . . . . . . . . 9.8.1.1 ISP1505 pipeline delays. . . . . . . . . . . . . . . . . 9.8.1.2 Allowed link decision time . . . . . . . . . . . . . . . 9.9 Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.10 USB suspend and resume . . . . . . . . . . . . . . . 9.10.1 Full-speed and low-speed host-initiated suspend and resume . . . . . . . . . . . . . . . . . . . 9.10.2 High-speed suspend and resume . . . . . . . . . 9.10.3 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 9.11 No automatic SYNC and EOP generation (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.12 On-The-Go operations . . . . . . . . . . . . . . . . . . 9.12.1 OTG comparators. . . . . . . . . . . . . . . . . . . . . . 9.12.2 Pull-up and pull-down resistors . . . . . . . . . . . 9.12.3 VBUS charge and discharge resistors . . . . . . . 9.13 Serial modes . . . . . . . . . . . . . . . . . . . . . . . . . 9.14 Aborting transfers. . . . . . . . . . . . . . . . . . . . . . 9.15 Avoiding contention on the ULPI data bus . . . 10 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Immediate register set . . . . . . . . . . . . . . . . . . 10.1.1 Vendor ID and Product ID registers . . . . . . . . 10.1.1.1 Vendor ID Low register. . . . . . . . . . . . . . . . . . 10.1.1.2 Vendor ID High register . . . . . . . . . . . . . . . . . 10.1.1.3 Product ID Low register . . . . . . . . . . . . . . . . . 10.1.1.4 Product ID High register. . . . . . . . . . . . . . . . . 10.1.2 Function Control register . . . . . . . . . . . . . . . . 10.1.3 Interface Control register . . . . . . . . . . . . . . . . 17 19 19 19 19 22 22 22 22 23 23 23 24 25 26 27 28 29 32 32 32 32 34 35 35 36 39 40 41 42 42 42 42 44 44 45 45 45 45 46 46 46 46 47 continued >> ISP1505A_ISP1505C_1 Product data sheet (c) NXP B.V. 2006. All rights reserved. Rev. 01 -- 19 October 2006 77 of 78 ISP1505A; ISP1505C NXP Semiconductors ULPI HS USB host and peripheral transceiver 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 10.1.9 10.1.10 10.1.11 10.1.12 10.1.13 10.1.14 10.2 11 11.1 11.2 12 13 14 15 15.1 16 17 18 18.1 18.2 18.3 18.4 19 20 21 22 22.1 22.2 22.3 22.4 23 24 25 26 OTG Control register . . . . . . . . . . . . . . . . . . . USB Interrupt Enable Rising Edge register . . USB Interrupt Enable Falling Edge register . . USB Interrupt Status register . . . . . . . . . . . . . USB Interrupt Latch register . . . . . . . . . . . . . . Debug register . . . . . . . . . . . . . . . . . . . . . . . . Scratch register. . . . . . . . . . . . . . . . . . . . . . . . Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . Access extended register set . . . . . . . . . . . . . Vendor-specific registers . . . . . . . . . . . . . . . . Power Control register . . . . . . . . . . . . . . . . . . Extended register set . . . . . . . . . . . . . . . . . . . ElectroStatic Discharge (ESD) . . . . . . . . . . . . ESD protection . . . . . . . . . . . . . . . . . . . . . . . . ESD test conditions . . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Application information. . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering . . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 49 50 50 51 51 52 52 52 52 52 53 54 54 54 55 55 56 60 64 65 69 70 70 70 70 71 72 73 73 74 74 74 74 74 74 75 76 77 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 October 2006 Document identifier: ISP1505A_ISP1505C_1