1
Standard Products
UT54ACS283/UT54ACTS283
4-Bit Binary Full Adders
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS283- SMD 5962-96584
UT54ACTS283 - SMD 5962-96585
DESCRIPTION
The UT54ACS283 and the UT54ACTS283 are 4-bit binary ad-
ders. The adders perform addition of two 4-bit binary word s.
The sum (∑) outputs are provided for each bit and the resultant
carry (C4) is obtained as the fifth bit. The adders feature full
internal look-ahead across all four bits for fast carry generation.
The devices are characterized over full military temperature
range of -55°C to +125°C.
LOGIC SYMB OL
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpa ck
Top View
0
(1)
Σ
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
(5)
A1 (3)
A2 (14)
A3 (12)
A4 3
(6)
B1 0
(2)
B2 (15)
B3 (11)
B4 3
(7)
C0 C1
(4)Σ1
P
Q
Σ2
(10)
(13)Σ3
Σ4
0
3
(9)C4
C0
1
2
3
4
5
7
6
16
15
14
13
12
10
11
B2
A2
Σ1
A1
B1
C0
VDD
B3
A3
Σ3
A4
B4
Σ4
8 9
VSS C4
Σ2
1
2
3
4
5
7
6
16
15
14
13
12
10
11
89
B2
A2
Σ1
A1
B1
C0
VSS
Σ2VDD
B3
A3
Σ3
A4
B4
Σ4
C4
2
FUNCTION TABLE
H = high level, L = low level
Note:
Input conditions at A1, A2, B1, B2, and C0 are used to determine outputs Σ1 and Σ2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4
are then used to determine outputs Σ3, Σ4, and C4.
INPUT OUTPUT
When C0 = L When C2 = L When C0 = H When C2 = H
A1 A3 B1 B3 A2 A4 B2 B4 Σ1Σ3Σ2Σ4C2 C4 Σ1Σ3Σ2Σ4C2 C4
LLLLLLLHLL
H L L L H L L L H L
L H L L H L L L H L
H H L L L H L H H L
L L H L L H L H H L
H L H L H H L L L H
L H H L H H L L L H
H H H L L L H H L H
L L L H L H L H H L
H L L H H H L L L H
L H L H H H L L L H
H H L H L L H H L H
L L H H L L H H L H
H L H H H L H L H H
L H H H H L H L H H
HHHHLHHHHH
3
LOGIC DIAGRAM
Σ1
Σ2
Σ3
Σ4
C4
(9)
(10)
(13)
(1)
(4)
(12)
(11)
(15)
(14)
(2)
(3)
(6)
(5)
(7)
B4
A4
B3
A3
B2
A2
B1
A1
C0
4
OPERATIONAL ENVIRONMENT1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD +.3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipatio n 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 °C
5
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -5 5 °C < TC < +125°C); Unless otherw ise noted, Tc is per the temperature range ordered.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIL Low-level input vo ltage 1
ACTS
ACS 0.8
.3VDD
V
VIH High-level input voltage 1
ACTS
ACS .5VDD
.7VDD
V
IIN Input leakage current
ACTS/ACS VIN = VDD or VSS -1 1μA
VOL Low-level output voltage 3
ACTS
ACS IOL = 8.0mA
IOL = 100μA0.40
0.25 V
VOH High-level output voltage 3
ACTS
ACS IOH = -8.0mA
IOH = -100μA.7VDD
VDD - 0.25 V
IOS Short-circuit output current 2 ,4
ACTS/ACS VO = VDD and VSS -200 200 mA
IOL Output current10
(Sink)
VIN = VDD or VSS
VOL = 0.4V
8mA
IOH Output current10
(Source)
VIN = VDD or VSS
VOH = VDD - 0.4V
-8 mA
Ptotal Power dissipatio n 2, 8, 9 CL = 50pF 1.9 mW/
MHz
IDDQ Quiescent Supply Cur rent VDD = 5.5V 10 μA
ΔIDDQ Quiescent Supply Current Delta
ACTS For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6 mA
CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz @ 0V 15 pF
6
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-3853 5, for current density ≤ 5.0E5 amps/cm 2, the maximum product of load capacitance (per output buf fer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
7
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPLH Propagation delay C0 to Σn 2 16 ns
tPHL Propagation delay C0 to Σn 2 19 ns
tPLH Propagation delay C0 to C4 2 16 ns
tPHL Propagation delay C0 to C4 2 17 ns
tPLH Propagation delay An, Bn to C4 2 16 ns
tPHL Propagation delay An, Bn to C4 2 15 ns
tPLH Propagation delay An, Bn to Σn 2 14 ns
tPHL Propagation delay An, Bn to Σn 2 16 ns
8
PACKAGING Side-Brazed Packages
9
FLATPACK PACKAGES
10
UT54ACS283/U T54ACTS283: SMD
5962 ***** ** * * **
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96584 = UT54ACS283
96585 = UT54AC TS283
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specif i ed.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when o rdering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offer ed with a TID toler ance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-8 83 Test Method 1019 Condition A.
11
COLORADO
Toll Free: 800-645-8862
Fax: 719-594-8468
SE AND MID-ATLANTIC
Tel: 321-951-4164
Fax: 321-951-4254
INTERNATIONAL
Tel: 805-778-9229
Fax: 805-778-1980
WEST COAST
Tel: 949-362-2260
Fax: 949-362-2266
NORTHEAST
Tel: 603-888-3975
Fax: 603-888-4585
CENTRAL
Tel: 719-594-8017
Fax: 719-594-8468
www.aeroflex.com info-ams@aeroflex.com
Our passion for perform a nce is defined by three
attributes represented by the s e three icons:
solution-minde d, perform an c e-d riven and custom e r-focu sed
Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex)
reserves the right to make changes to any products and
services herein at any time without notice. Consult Aeroflex
or an authorized sales representative to verify that the
information in this data sheet is current before using this
product. Aeroflex does not assume any responsibility or
liability arising out of the application or use of any product
or service described herein, except as expressly agreed to in
writing by Aeroflex; nor does the purchase, lease, or use of a
product or service from Aeroflex convey a license under any
patent rights, copyrights, trademark rights, or any other of the
intellectual rights of Aeroflex or of third parties.
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
