N-Channel Depletion-Mode 4-Channel DMOS FET Array CORPORATION SD5501 FEATURES DESCRIPTION * Normally ON Configuration * Low Interelectrode Capacitances Switching * High-Speed * Wide Dynamic Range APPLICATIONS * High-Speed Analog Switches * Wide-Band Dual Differential Amplifiers Cascode Amplifiers * Dual * High Intercept Point Double Balanced Mixers PIN CONFIGURATION The SD5501 is manufactured utilizing Calogic's proprietary high speed, low capacitance DMOS process featuring an N-Channel depletion-mode design. This "normally-ON" device is well suited for high speed instrumentation and communication systems where multiple channels are required for fast switching or dual amplification. Available in a 16-pin plastic dual in-line plastic package or chip form. ORDERING INFORMATION Part Package Temperature Range SD5501N XSD5501 Plastic Sorted Chips in Carriers SCHEMATIC DIAGRAM D1 1 16 D4 BODY 2 15 N/C G1 3 14 G4 S1 4 13 S4 S2 5 12 S3 11 G2 6 11 G3 9 N/C 7 10 N/C 14 D2 8 9 1 D3 4 16 1 5 8 9 16 S D 5 G S D 12 G 14 13 4 G 11 12 S D 6 6 8 G 3 3 CD2 -55oC to +125oC -55oC to +125oC D S 13 TOP VIEW 2 BODY SD5501 CORPORATION ABSOLUTE MAXIMUM RATINGS (TA = +25oC unless otherwise noted) VDS VSD VDB VSB VGS VGB VGD ID Drain-Source Voltage. . . . . . . . . . . . . . . . . . . . +30 Vdc Source-Drain Voltage. . . . . . . . . . . . . . . . . . . . +0.5 Vdc Drain-Body Voltage . . . . . . . . . . . . . . . . . . . . . . +30 Vdc Source-Body Voltage . . . . . . . . . . . . . . . . . . . . . +15 Vdc Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . +25 Vdc Gate-Body Voltage. . . . . . . . . . . . . . . . . . . . . . . +25 Vdc Gate-Body Voltage. . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc Gate-Drain Voltage . . . . . . . . . . . . . . . . . . . . . . +25 Vdc Continuous Drain Current . . . . . . . . . . . . . . . . . . 50 mA PD PD Tj TS Total Package Power Dissipation (at or below TA = +25oC) . . . . . . . . . . . . . . . . . 640 mW Linear Derating Factor . . . . . . . . . . . . . . . . 10.7 mW/oC Single Device Power Dissipation (at or below TA = +25oC) . . . . . . . . . . . . . . . . . 300 mW Linear Derating Factor . . . . . . . . . . . . . . . . . 5.0 mW/oC Operating Junction Temperature Range . . -55 to +85oC Storage Temperature Range . . . . . . . . . -55 to + 150oC ELECTRICAL CHARACTERISTCIS (TA = +25oC unless otherwise noted) SYMBOL CHARACTERISTIC MIN TYP MAX UNITS TEST CONDITIONS STATIC BVDS Drain-Source Breakdown Voltage BVSD Source-Drain Breakdown Voltage 10 BVDB Drain-Body Breakdown Voltage 25 15 BVSB Source-Body Breakdown Voltage IGSS(fwd) Forward Gate Leakage Current IG Gate Operating Current 20 ID = 10 nA, VGS = VBS = -5.6V V IS = 10A, VGB = 0, Drain Open 1.0 nA VGS = 25V, VDS = VBS = 0 -3.0 -100 pA -0.7 -10 nA VDG = 15V, ID = 5.0 mA, VBS = -5.6V VGS (off) Gate - Source Cutoff Voltage -1.0 -5.0 VGS (on) Gate-Source On Voltage -0.3 -3.0 IDSX Zero Gate Voltage Drain Current 7.0 40 V Drain-Source On Resistance TA = +125oC VDS = 10V, ID = 1.0A, VBS = 5.6V VDG = 10V, ID = 5mA, VSB = -5.6V mA 5.0 rDS (ON) IS = 10 nA, VGD = VBD = -5.6V ID = 10nA, VGB = 0, Source Open 100 150 ohms 7.5 12 mS 350 S VDS = 10V, VGS = 0, VBS = -5.6V TA = +125oC ID = 1.0mA, VGS = 0, VBS = -5.6V DYNAMIC (1) gfs Common-Source Forward Transconductance 6.0 gos Common-Source Output Conductance 200 Ciss Common-Source Input Capacitance 3.5 Coss Common-Source Output Capacitance 1.2 Crss Common-Source Reverse Transfer Capacitance 0.3 C(gs + sb) Source Node Capacitance 4.5 pF f = 1 KHz VDG = 10V ID = 5.0mA VBS = -5.6V f = 1 MHz MATCHING VGSM Gate Source Voltage Match rDS(on) Drain-Source On Resistance Match IDXSM gfsm 50 mV VDG = 10V, ID = 5.0mA, VBS = -5.6V 10% ID = 1.0 mA, VGS = 0, VBS = 5.6V Zero Gate Voltage Drain Current Match 10% Transconductance Match (1), (2) 10% VDG = 10V, ID = 5.0 mA, VBS = -5.6V Note 1: Pulse Test, 80 sec, 1% Duty Cycle Note 2: Match of 4 channels f = 1 KHz