N-Channel Depletion-Mode
4-Channel DMOS FET Array
SD5501
FEATURES
••Normally ON Configuration
••Low Intere lectrode Capacitances
••High-Speed Switching
••Wide Dynamic Range
APPLICATIONS
••High- S pe ed A n alog Switch e s
••Wi de- Ban d Dual Dif fere nt ia l Amp lifi ers
••Dual Cascode Amplifiers
••High I nt er cept Point Doubl e Bala nced M i xer s
DESCRIPTION
The SD5501 is manufactured utilizing Calogic’s proprietary
high speed, low capacitance DMOS process featuring an
N-Channel depletion-mode design. This "normally-ON"
device is well suited for high speed instrumentation and
communication systems where multiple channels ar e re q uired
for fast switching or dual amplification. Avai lable in a 16-pin
plastic dua l in-l ine plastic pack age or chip for m.
ORDERING INFORMATION
Part Package Temperature Range
SD5501N Plastic -55oC to +125oC
XSD5501 Sort ed Chips in Car rier s -55oC to +125oC
CORPORATION
TOP VIEW
D4
N/C
G4
S4
S3
G3
N/C
D3
1
2
3
4
5
6
7
8
S1
S2
G2
D2
N/C
D1
G1
BODY
16
15
14
13
12
11
10
9
PIN CONFIGUR ATI O N
CD2
SCHEMAT IC DI AGRAM
G
DS4
5
12
13
2
G
DS
G
DS
G
DS
3
1
6
8
11
9
16
14
3
1
6
8
11
9
16
14
4
5
12
13
BODY
SD5501
CORPORATION
ABSOLUTE M AXIM UM R A T INGS (TA = +25oC un less other wise note d)
VDS Dra in-So ur ce Volt age. . . . . . . . . . . . . . . . . . . . +30 Vdc
VSD Sour ce- Dr ain Voltage. . . . . . . . . . . . . . . . . . . . +0.5 Vdc
VDB Drain -Bo dy Volt age . . . . . . . . . . . . . . . . . . . . . . +30 Vdc
VSB Sour ce- Bod y Voltag e. . . . . . . . . . . . . . . . . . . . . +15 Vdc
VGS Gat e-Sour ce Volt age . . . . . . . . . . . . . . . . . . . . . +25 Vdc
VGB Gat e-Body Volt age. . . . . . . . . . . . . . . . . . . . . . . +25 Vdc
Gate- Body Volt age. . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc
VGD Gat e- Dra in V o ltag e . . . . . . . . . . . . . . . . . . . . . . +25 Vdc
IDCont inuou s Drain Curren t . . . . . . . . . . . . . . . . . . 5 0 mA
PDTotal Packa ge Power Dissipation
(at or below TA = + 25oC) . . . . . . . . . . . . . . . . . 6 4 0 m W
Linear Der ating Fac to r. . . . . . . . . . . . . . . . 10.7 m W/ oC
PDSingle Device Powe r Dissipation
(at or below TA = + 25oC) . . . . . . . . . . . . . . . . . 3 0 0 m W
Linear Der ating Fac to r. . . . . . . . . . . . . . . . . 5.0 mW /oC
TjOperat ing Jun ction Temper ature Rang e . . -55 to +85oC
TSStorage Temperature Range . . . . . . . . . -55 to + 150 oC
ELECTRICA L CHARACTERI STCI S (TA = +25oC unless otherwise noted)
SYMBOL CHARACTERISTIC MIN TYP MAX UNITS TEST CONDITIONS
STATIC
BVDS Drain-Source Breakdown Voltage 20
V
ID = 10 nA, VGS = VBS = -5.6V
BVSD Source-Drain Breakdown Voltage 10 IS = 10 nA, VGD = VBD = -5.6V
BVDB Drain-Body Breakdown Voltage 25 ID = 10nA, VGB = 0, Source Open
BVSB Sour ce-Body Brea kd own Vo lta ge 15 IS = 10µA, VGB = 0, Drain Open
IGSS(fwd) Forward Gate Leakage Current 1.0 nA VGS = 25V, VDS = VBS = 0
IGGate Operating Current -3.0 -100 pA VDG = 15V, ID = 5.0 mA ,
VBS = -5.6V
-0.7 -10 nA TA = +125 oC
VGS (off) Gate - Source Cutoff Voltage -1.0 -5.0 VVDS = 10V, ID = 1.0µA, VBS = 5.6V
VGS (on) Gate-Source On Voltage -0.3 -3.0 VDG = 10V, ID = 5mA, VSB = -5.6V
IDSX Zero Gate Vol tage Drain Curren t 7.0 40 mA VDS = 10V, VGS = 0,
VBS = -5.6V
5.0 TA = +125oC
rDS (ON) Drain-Source On Resistance 100 150 ohms ID = 1.0mA, VGS = 0, VBS = -5.6V
DYNAMIC
gfs Common-Source Forward Tr ansconductance (1) 6.0 7.5 12 mS
VDG = 10V
ID = 5.0mA
VBS = -5.6V
f = 1 KHz
gos Common-Source Output Conductance 200 350 µS
Ciss Common-Sourc e Inp ut Capacitance 3.5
pF f = 1 MHz
Coss Common-Source Output Cap acitance 1.2
Crss Common-Source Reverse Transfer Capacitance 0.3
C(gs + sb) Source Node Capacitance 4.5
MATCHING
VGSM Gate Source Vol tage Match 50 mV VDG = 10V, ID = 5.0mA, VBS = -5.6V
rDS(on) Drain-Source On Resistanc e Match 10% ID = 1.0 mA, VGS = 0, VBS = 5.6V
IDXSM Zero Gate Vol tage Drain Current M at ch 10% VDG = 10V, ID = 5.0 mA,
VBS = -5.6V
gfsm T ransc onductance Match (1), (2) 10% f = 1 KHz
No te 1: Pulse Test, 80 sec, 1% Duty Cycle
No te 2: M atch of 4 cha nn els
