VDD
V4
V3
V2
OUT
CD
VSS
V1
RIN
CIN
C
CD
Cell 2
Cell 1
RVD
CVD
CIN
RIN
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
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bq7716xy Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries
with External Delay Capacitor
1 Features 3 Description
The bq7716xy device family provides an overvoltage
1• 2-, 3-, and 4-Series Cell Overvoltage Protection monitor and protector for Li-Ion battery pack systems.
• External Capacitor-Programmed Delay Timer Each cell is monitored independently for an
• Fixed OVP Threshold overvoltage condition. For quicker production-line
testing, the bq7716xy device provides a Customer
• High-Accuracy Overvoltage Protection: Test Mode with greatly reduced delay time.
±10 mV
• Low Power Consumption ICC ≈1 µA In the bq7716xy device, an external delay timer is
initiated upon detection of an overvoltage condition
(VCELL(ALL) < VPROTECT)on any cell. Upon expiration of the delay timer, the
• Low Leakage Current Per Cell Input < 100 nA output is triggered into its active state (either high or
• Small Package Footprint low, depending on the configuration). The external
– 8-pin WSON (3.00 mm × 4.00 mm) delay timer feature also includes the ability to detect
an open or shorted delay capacitor on the CD pin,
which will similarly trigger the output driver in an
2 Applications overvoltage condition.
• Power Tools
• UPS Battery Backup Table 1. Device Information Table(1)
• Light Electric Vehicles PART NUMBER PACKAGE BODY SIZE (NOM)
– eBike bq771600 WSON (8) 3.00 mm × 4.00 mm
– eScooter (1) For all available packages, see the orderable addendum at
the end of the data sheet and the Device Comparison Table.
– Pedal Assist Bicycles
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
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Table of Contents
8.4 Device Functional Modes........................................ 10
1 Features.................................................................. 19 Application and Implementation ........................ 12
2 Applications ........................................................... 19.1 Application Information............................................ 12
3 Description............................................................. 19.2 Typical Application.................................................. 13
4 Simplified Schematic............................................. 110 Power Supply Recommendations ..................... 14
5 Revision History..................................................... 211 Layout................................................................... 14
6 Pin Configuration and Functions......................... 311.1 Layout Guidelines ................................................. 14
7 Specifications......................................................... 411.2 Layout Example .................................................... 14
7.1 Absolute Maximum Ratings ...................................... 412 Device and Documentation Support................. 15
7.2 ESD Ratings ............................................................ 412.1 Related Links ........................................................ 15
7.3 Recommended Operating Conditions....................... 412.2 Community Resources.......................................... 15
7.4 Thermal Information.................................................. 412.3 Trademarks........................................................... 15
7.5 Electrical Characteristics........................................... 512.4 Electrostatic Discharge Caution............................ 15
7.6 Typical Characteristics.............................................. 712.5 Export Control Notice............................................ 15
8 Detailed Description.............................................. 812.6 Glossary................................................................ 15
8.1 Overview................................................................... 813 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram......................................... 8Information ........................................................... 16
8.3 Feature Description................................................... 8
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2014) to Revision D Page
• Changed QFN to WSON ....................................................................................................................................................... 1
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Changed the bq771605 to Production Data........................................................................................................................... 3
• Added table note 2, which was hidden inadvertently............................................................................................................. 4
• Moved Pin Details to Feature Description section ................................................................................................................. 8
• Moved from Application Information section to Design Requirements section ................................................................... 13
Changes from Revision B (June 2014) to Revision C Page
• Added the bq771612 device to Production Data.................................................................................................................... 3
Changes from Revision A (September 2013) to Revision B Page
• Changed the data sheet format.............................................................................................................................................. 1
• Added the bq771611 device to Production Data.................................................................................................................... 3
Changes from Original (December 2012) to Revision A Page
• Added the bq771604 device to Production Data.................................................................................................................... 3
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1
2
3
4
8
7
6
5
VDD
V4
V3
V2
OUT
CD
VSS
V1
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Table 2. Device Comparison Table
TAPE AND REEL
PART NUMBER OVP (V) OV HYSTERESIS (V) OUTPUT DRIVE TAPE AND REEL (SMALL)
(LARGE)
bq771600 4.3 0.3 CMOS Active High bq771600DPJR bq771600DPJT
bq771601 4.225 0.05 CMOS Active High bq771601DPJR bq771601DPJT
bq771602 4.225 0.05 NCH Active Low, Open Drain bq771602DPJR bq771602DPJT
bq771603(1) 4.325 0.05 NCH Active Low, Open Drain bq771603DPJR bq771603DPJT
bq771604 4.2 0.05 CMOS Active High bq771604DPJR bq771604DPJT
bq771605 3.85 0.25 NCH Active Low bq771605DPJR bq771605DPJT
bq771607(1) 4.2 0.25 CMOS Active High bq771607DPJR bq771607DPJT
bq771608(1) 4.225 0.25 CMOS Active High bq771608DPJR bq771608DPJT
bq771609(1) 4.25 0.05 CMOS Active High bq771609DPJR bq771609DPJT
bq771610(1) 4.250 0.25 CMOS Active High bq771610DPJR bq771610DPJT
bq771611 4.35 0.3 CMOS Active High bq771611DPJR bq771611DPJT
bq771612 3.9 0.3 CMOS Active High bq771612DPJR bq771612DPJT
bq771613(1) 4.2 0.05 NCH Active Low bq771613DPJR bq771613DPJT
bq771614(1) 4.225 0.25 NCH Active Low bq771614DPJR bq771614DPJT
bq771615(1) 4.25 0.05 NCH Active Low bq771615DPJR bq771615DPJT
CMOS Active High or NCH
bq7716xy future options(2) 3.85–4.65 0–0.3 bq7716xyTBD bq7716xyTBD
Active Low, Open Drain
(1) Product Preview only.
(2) Contact TI.
6 Pin Configuration and Functions
DPJ Package
8-Pin WSON
Top View
Pin Functions
PIN TYPE DESCRIPTION
NAME NO. I/O(1)
CD 7 I/O External capacitor connection for delay timer
OUT 8 OA Output drive for overvoltage fault signal
VDD 1 P Power supply
VSS 6 P Electrically connected to IC ground and negative terminal of the lowest cell in the stack
V1 5 I Sense input for positive voltage of the lowest cell in the stack
V2 4 I Sense input for positive voltage of the second cell from the bottom of the stack
V3 3 I Sense input for positive voltage of the third cell from the bottom of the stack
V4 2 I Sense input for positive voltage of the fourth cell from the bottom of the stack
(1) IA = Input Analog, OA = Output Analog, P = Power Connection
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range(2) VDD–VSS –0.3 30 V
Input voltage range(2) V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS –0.3 30 V
Output voltage range(2) OUT–VSS –0.3 30 V
See package
Continuous total power dissipation, PTOT dissipation rating.
Functional temperature –40 110 °C
Lead temperature (soldering, 10 s), TSOLDER 300 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Absolute maximum ratings for input voltage range, output voltage range, and supply voltage are assured by design and not tested in
production.
7.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
VESD Rating V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VDD(1) Supply voltage 3 20 V
V4–V3, V3–V2,
V2–V1, V1–VSS, or Input voltage range 0 5 V
CD–VSS
TAOperating ambient temperature range –40 110 °C
(1) See Typical Application.
7.4 Thermal Information bq7716xy
THERMAL METRIC(1) DPJ (WSON) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 56.6 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 56.4 °C/W
RθJB Junction-to-board thermal resistance 30.6 °C/W
ψJT Junction-to-top characterization parameter 1.0 °C/W
ψJB Junction-to-board characterization parameter 37.8 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 11.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
Typical values stated where TA= 25°C and VDD = 14.4 V, MIN/MAX values stated where TA= –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE PROTECTION THRESHOLD VCx
bq771600 4.300 V
bq771601 4.225 V
bq771602 4.225 V
bq771603(1) 4.325 V
bq771604 4.200 V
bq771605 3.850 V
bq771607(1) 4.200 V
V(PROTECT)
VOV Overvoltage bq771608(1) 4.225 V
Detection bq771609(1) 4.250 V
bq771610(1) 4.250 V
bq771611 4.350 V
bq771612 3.900 V
bq771613(1) 4.200 V
bq771614(1) 4.225 V
bq771615(1) 4.250 V
bq771600 250 300 400 mV
bq771601 25 50 75 mV
bq771602 25 50 75 mV
bq771603(1) 25 50 75 mV
bq771604 25 50 75 mV
bq771605 200 250 300 mV
bq771607(1) 200 250 300 mV
OV Detection
VHYS bq771608(1) 200 250 300 mV
Hysteresis bq771609(1) 25 50 75 mV
bq771610(1) 200 250 300 mV
bq771611 250 300 400 mV
bq771612 250 300 400 mV
bq771613(1) 25 50 75 mV
bq771614(1) 200 250 300 mV
bq771615(1) 25 50 75 mV
OV Detection
VOA TA= 25°C –10 10 mV
Accuracy TA= –40°C –40 44 mV
OV Detection TA= 0°C –20 20 mV
VOADRIFT Accuracy Across TA= 60°C –24 24 mV
Temperature TA= 110°C –54 54 mV
SUPPLY AND LEAKAGE CURRENT
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
ICC Supply Current 1 2 µA
(See Figure 10.)
Input Current at Vx (V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
IIN –0.1 0.1 µA
Pins (See Figure 10.)
(1) Future option. Contact TI.
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Electrical Characteristics (continued)
Typical values stated where TA= 25°C and VDD = 14.4 V, MIN/MAX values stated where TA= –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT DRIVE OUT, CMOS ACTIVE HIGH VERSIONS ONLY
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD 6 V
= 14.4 V, IOH = 100 µA
If three of four cells are short circuited, only one cell
Output Drive
VOUT1 remains powered and > VOV, VDD = Vx (cell voltage), VDD – 0.3 V
Voltage, Active High IOH = 100 µA
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,250 400 mV
VDD = 14.4 V, IOL = 100 µA measured into OUT pin
OUT Source Current (V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
IOUTH1 4.5 mA
(During OV) = 14.4 V, OUT = 0 V. Measured out of OUT pin
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
OUT Sink Current
IOUTL1 VDD = 14.4 V, OUT = VDD. 0.5 14 mA
(No OV) Measured into OUT pin
OUTPUT DRIVE OUT, NCH OPEN DRAIN ACTIVE LOW VERSIONS ONLY
Output Drive (V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
VOUT2 250 400 mV
Voltage, Active Low = 14.4 V, IOL = 100 µA measured into OUT pin
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV, VDD
OUT Sink Current
IOUTH2 = 14.4 V. OUT = VDD. 0.5 14 mA
(During OV) Measured into OUT pin
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV,
IOUTLK OUT Pin Leakage 100 nA
VDD = 14.4 V, OUT = VDD. Measured out of OUT pin
DELAY TIMER
CCD = 0.1 µF
tCD OV Delay Time 1 1.5 2 s
(For capacitor sizing, see .)
CD Fault Detection
External Comparator The CD pin will first be quickly charged to this value
VCD 1.5 V
Threshold, Initial before being discharged back to VSS.
Charge Value
tCHGDELAY CD Charging Delay OVP to OUT delay with CD shorted to ground 20 170 ms
OV Detection CD pin fast charging current from VSS to VCD to begin
ICHG 300 µA
Charging Current delay countdown
OV Detection
IDSG CD pin discharging current from VDELAY to VSS 100 nA
Discharging Current
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−3.88
−3.86
−3.84
−3.82
−3.80
−3.78
−3.76
−3.74
−3.72
−3.70
−3.68
−50 −25 0 25 50 75 100 125
Temperature (°C)
IOUT (mA)
G005
0
1
2
3
4
5
6
7
8
0 5 10 15 20 25 30
VDD (V)
VOUT (V)
G006
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
−50 −25 0 25 50 75 100 125
Temperature (°C)
IDD (µA)
G003
0.6
0.8
1.0
1.2
1.4
1.6
1.8
−50 −25 0 25 50 75 100 125
Temperature (°C)
ICELL (µA)
G004
4.30
4.31
4.32
4.33
4.34
4.35
4.36
4.37
4.38
4.39
4.40
−50 −25 0 25 50 75 100 125
Temperature (°C)
VOUT (V)
Mean
Min
Max
G001
0.312
0.313
0.314
0.315
0.316
−50 −25 0 25 50 75 100 125
Temperature (°C)
VHYS (V)
G002
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7.6 Typical Characteristics
Figure 2. Overvoltage Threshold (OVT) vs. Temperature Figure 3. Hysteresis VHYS vs. Temperature
Figure 4. IDD Current Consumption vs. Figure 5. ICELL vs. Temperature
Temperature at VDD = 16 V at VCELL= 9.2 V
Figure 6. Output Current IOUT vs. Temperature Figure 7. VOUT vs. VDD
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OUT
VC4
VC3
VC1
VC2
VSS
VDD
CD
Delay
Charging/
Discharging
Circuit
PACK+
PACK–
RIN
CIN
CCD
CVD
RVD
V
OV
Sensing Circuit
Enable
Active
CIN
CIN
CIN
RIN
RIN
RIN
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8 Detailed Description
8.1 Overview
In the bq7716xy family of devices for overvoltage protection, each cell is monitored independently and an
external delay timer is initiated if an overvoltage condition is detected when any cell voltage is higher than the
protection voltage threshold, VOV. After the delay time expires, the OUT pin is inserted.
For quicker production-line testing, the device provides a Customer Test Mode with greatly reduced delay time.
8.2 Functional Block Diagram
8.3 Feature Description
In the bq7716xy device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, a timer
circuit is activated. This timer circuit charges the CD pin to a nominal value, then slowly discharges it with a fixed
current back down to VSS. When the CD pin falls below a nominal threshold near VSS, the OUT terminal goes
from inactive to active state. Additionally, a timeout detection circuit checks to ensure that the CD pin
successfully begins charging to above VSS and subsequently drops back down to VSS, and if a timeout error is
detected in either direction, it will similarly trigger the OUT pin to become active. See Figure 8 for reference.
For an NCH Open Drain Active Low configuration, the OUT pin pulls down to VSS when active (OV present), and
is high impedance when inactive (no OV).
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V
CD
Fault condition
present
tCHGDELAY
tCD
V(CD)
I(CD)
ICHG
IDSG
Fault response
becomes active
V
OUT1
V(OUT)
Note: Active High OUT version shown
V
OV
VOV –VHYS
Cell Voltage (V)
OUT (V) tDELAY
(V4–V3, V3–V2, V2–V1, V1–VSS)
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Feature Description (continued)
Figure 8. Timing for Overvoltage Sensing
Figure 9 shows an overview of the behavior of the CD pin during an OV sequence.
Figure 9. CD Pin Mechanism
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Feature Description (continued)
8.3.1 Sense Positive Input for Vx
This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for
each input is required for noise filtering and stable voltage monitoring.
8.3.2 Output Drive, OUT
This terminal serves as the fault signal output, and may be ordered in either active HIGH or LOW options.
8.3.3 Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
8.3.4 External Delay Capacitor, CD
This terminal is connected to an external capacitor that is used for setting the delay timer during an overvoltage
fault event.
The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or
open capacitor during an overvoltage event.
The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the OV
threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor
discharges below a set voltage, the OUT transitions from an inactive to active state.
To calculate the delay, use the following equation:
tCD (s) = K × CCD (µF), where K = 10 to 20 range. (1)
Example: If CCD= 0.1 µF (typical), then the delay timer range is
tCD (s) = 10 × 0.1 = 1 s (Minimum)
tCD (s) = 20 × 0.1 = 2 s (Maximum)
NOTE
The tolerance on the capacitor used for CCD increases the range of the tCD timer.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode.
The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–V2), and (V4–V3).
The OUT pin is inactive and if configured:
• Active high is low
• Active low is being externally pulled up and is an open drain
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltages exceeds the overvoltage threshold, VOV for
configured OV delay time. The OUT pin is activated after a delay time set by the capacitance in the CD pin. The
OUT pin will either pull high internally, if configured as active high, or will be pulled low internally, if configured as
active low. When all of the cell voltages fall below the (VOV–VHYS), the device returns to NORMAL mode
8.4.3 Customer Test Mode
It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD
capacitor to VSS. In this case, the OV delay would be reduced to the t(CHGDELAY) value, which has a maximum of
170 ms.
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VDD
V4
V3
V2
OUT
CD
VSS
V1
Cell 4
Cell 3
Cell 2
Cell 1
ICC
IIN
IIN
IIN
IIN
V(OUT)
V(VCELL)
OV Condition
≤170 ms
V(CD) CD pin held low
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Device Functional Modes (continued)
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part
into Customer Test Mode. Also avoid exceeding Absolute Maximum Voltages for the
individual cell voltages (V4–V3), (V3–V2), (V2–V1), and (V1–VSS). Stressing the pins
beyond the rated limits may cause permanent damage to the device.
Figure 10 shows the timing for the Customer Test Mode.
Figure 10. Timing for Customer Test Mode
Figure 11 shows the measurement for current consumption for the product for both VDD and Vx.
Figure 11. Configuration for IC Current Consumption Test
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VDD
V4
V3
V2
OUT
CD
VSS
V1
CIN
CCD
Cell 4
Cell 3
Cell 2
Cell1
RVD
CVD
RIN
RIN
RIN
RIN
CIN
CIN
CIN
bq771600
,
bq771601
,
bq771602
bq771604
,
bq771605
,
bq771611
,
bq771612
SLUSAX0D –DECEMBER 2012–REVISED JULY 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 12 shows each external component.
Figure 12. Application Configuration
NOTE
In the case of an Open Drain Active Low configuration, an external pull-up resistor is
required on the OUT terminal.
Changes to the ranges stated in Table 3 will impact the accuracy of the cell
measurements.
NOTE
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this
recommended value changes the accuracy of the cell voltage measurements and VOV
trigger level.
12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: bq771600 bq771601 bq771602 bq771604 bq771605 bq771611 bq771612
VDD
V4
V3
V2
OUT
CD
VSS
V1
CIN
RIN
CCD
Cell 3
Cell 2
Cell 1
RVD
CVD
CIN
CIN
RIN
RIN
VDD
V4
V3
V2
OUT
CD
VSS
V1
RIN
CIN
C
CD
Cell 2
Cell 1
RVD
CVD
CIN
RIN
bq771600
,
bq771601
,
bq771602
bq771604
,
bq771605
,
bq771611
,
bq771612
www.ti.com
SLUSAX0D –DECEMBER 2012–REVISED JULY 2015
9.2 Typical Application
Figure 13. 2-Series Cell Configuration with Capacitor- Figure 14. 3-Series Cell Configuration with Capacitor-
Programmed Delay Programmed Delay
NOTE
In these application examples of 2 s and 3 s, an external pull-up resistor is required on the
OUT terminal to configure for an Open Drain Active Low operation.
9.2.1 Design Requirements
Changes to the ranges stated in Table 3 will impact the accuracy of the cell measurements.
Table 3. Design Parameters
PARAMETER EXTERNAL COMPONENT MIN NOM MAX UNIT
Voltage monitor filter resistance RIN 900 1000 1100 Ω
Voltage monitor filter capacitance CIN 0.01 0.1 µF
Supply voltage filter resistance RVD 100 1K Ω
Supply voltage filter capacitance CVD 0.1 µF
CD external delay capacitance CCD 0.1 1 µF
OUT Open drain version pull-up ROUT 100k Ω
resistance to PACK+
9.2.2 Detailed Design Procedure
1. Determine the number of cells in series. The device supports a 2-S to 4-S cell configuration. For 2S and 3S,
the top unused pin(s) should be shorted as shown in Figure 13 and Figure 14.
2. Determine the overvoltage protection delay. Follow the calculation example described in External Delay
Capacitor, CD . Select the correct capacitor to connect to the CD pin.
3. Follow the application schematic to connect the device. If the OUT pin is configured to open drain, an
external pull-up resistor should be used. Refer to the Out Sink Current specification, IOUTH2 to ensure a
proper pull-up resistor value is used, so that the OUT pin sink current is able to pull down the pin during OV
condition.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: bq771600 bq771601 bq771602 bq771604 bq771605 bq771611 bq771612
VCELL1
VCELL3
VCELL2
OUT
VDD
Pack +
Pack -
V3
V2 V1
V4 CD
VSS
PWPD
Power Trace Line
Place the RC filters close to the
device terminals
OUT
Place close to the CD pin
0.312
0.313
0.314
0.315
0.316
−50 −25 0 25 50 75 100 125
Temperature (°C)
VHYS (V)
G002
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
−50 −25 0 25 50 75 100 125
Temperature (°C)
IDD (µA)
G003
bq771600
,
bq771601
,
bq771602
bq771604
,
bq771605
,
bq771611
,
bq771612
SLUSAX0D –DECEMBER 2012–REVISED JULY 2015
www.ti.com
9.2.3 Application Curves
Figure 15. Hysteresis VHYS vs. Temperature Figure 16. IDD Current Consumption vs.
Temperature at VDD = 16 V
10 Power Supply Recommendations
The maximum power of this device is 20 V on VDD.
11 Layout
11.1 Layout Guidelines
1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal,
reducing the tracing loop area.
2. The capacitor for CD pin should be placed close to the IC terminals.
11.2 Layout Example
Figure 17. Layout
14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: bq771600 bq771601 bq771602 bq771604 bq771605 bq771611 bq771612
bq771600
,
bq771601
,
bq771602
bq771604
,
bq771605
,
bq771611
,
bq771612
www.ti.com
SLUSAX0D –DECEMBER 2012–REVISED JULY 2015
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
bq771600 Click here Click here Click here Click here Click here
bq771601 Click here Click here Click here Click here Click here
bq771602 Click here Click here Click here Click here Click here
bq771604 Click here Click here Click here Click here Click here
bq771605 Click here Click here Click here Click here Click here
bq771611 Click here Click here Click here Click here Click here
bq771612 Click here Click here Click here Click here Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: bq771600 bq771601 bq771602 bq771604 bq771605 bq771611 bq771612
bq771600
,
bq771601
,
bq771602
bq771604
,
bq771605
,
bq771611
,
bq771612
SLUSAX0D –DECEMBER 2012–REVISED JULY 2015
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: bq771600 bq771601 bq771602 bq771604 bq771605 bq771611 bq771612
PACKAGE OPTION ADDENDUM
www.ti.com 22-Jul-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
BQ771600DPJR ACTIVE WSON DPJ 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 771600
BQ771600DPJT ACTIVE WSON DPJ 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 771600
BQ771601DPJR ACTIVE WSON DPJ 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 771601
BQ771601DPJT ACTIVE WSON DPJ 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 771601
BQ771602DPJR ACTIVE WSON DPJ 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 771602
BQ771602DPJT ACTIVE WSON DPJ 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 771602
BQ771604DPJR ACTIVE WSON DPJ 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 771604
BQ771604DPJT ACTIVE WSON DPJ 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 771604
BQ771605DPJR PREVIEW WSON DPJ 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 771605
BQ771605DPJT PREVIEW WSON DPJ 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 771605
BQ771611DPJR ACTIVE WSON DPJ 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 771611
BQ771611DPJT ACTIVE WSON DPJ 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 771611
BQ771612DPJR ACTIVE WSON DPJ 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 771612
BQ771612DPJT ACTIVE WSON DPJ 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 771612
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Jul-2015
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ771600DPJR WSON DPJ 8 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771600DPJT WSON DPJ 8 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771601DPJR WSON DPJ 8 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771601DPJT WSON DPJ 8 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771602DPJR WSON DPJ 8 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771602DPJT WSON DPJ 8 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771604DPJR WSON DPJ 8 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771604DPJT WSON DPJ 8 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771611DPJR WSON DPJ 8 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771611DPJT WSON DPJ 8 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771612DPJR WSON DPJ 8 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
BQ771612DPJT WSON DPJ 8 250 180.0 12.4 3.3 4.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Jul-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ771600DPJR WSON DPJ 8 3000 367.0 367.0 35.0
BQ771600DPJT WSON DPJ 8 250 210.0 185.0 35.0
BQ771601DPJR WSON DPJ 8 3000 367.0 367.0 35.0
BQ771601DPJT WSON DPJ 8 250 210.0 185.0 35.0
BQ771602DPJR WSON DPJ 8 3000 367.0 367.0 35.0
BQ771602DPJT WSON DPJ 8 250 210.0 185.0 35.0
BQ771604DPJR WSON DPJ 8 3000 367.0 367.0 35.0
BQ771604DPJT WSON DPJ 8 250 210.0 185.0 35.0
BQ771611DPJR WSON DPJ 8 3000 367.0 367.0 35.0
BQ771611DPJT WSON DPJ 8 250 210.0 185.0 35.0
BQ771612DPJR WSON DPJ 8 3000 367.0 367.0 35.0
BQ771612DPJT WSON DPJ 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Jul-2015
Pack Materials-Page 2
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