S i 5 3 4 1/40 L O W - J I T T E R, 1 0 - O U T P U T , A NY -F R E Q U E N C Y, A NY -O U T P U T CLOCK GENERATOR Features Generates up to 10 independent output clocks Ultra-low jitter: <100 fs RMS typical MultiSynthTM technology enables anyfrequency synthesis on any-output Highly configurable outputs compatible with LVDS, LVPECL, CML, LVCMOS, HCSL, or programmable voltage Input frequency range: External crystal: 25, 48-54 MHz Differential clock: 10 to 750 MHz LVCMOS clock: 10 to 250 MHz Output frequency range: Differential: 100 Hz to 712.5 MHz LVCMOS: 100 Hz to 250 MHz Output-output skew: 20 ps typ Adjustable output-output delay Optional zero delay mode Independent glitchless on-the-fly output frequency changes DCO mode with frequency steps as low as 0.001 ppb Independent output clock supply pins: 3.3 V, 2.5 V, or 1.8 V Built-in power supply filtering and regulation Status monitoring: LOS, LOL Serial Interface: I2C or SPI (3-wire or 4-wire) User programmable (2x) non-volatile OTP memory ClockBuilderTM Pro software utility simplifies device configuration and assigns customer part numbers Si5341: 4 input, 10 output, compact 9x9 mm, 64 QFN Si5340: 4 input, 4 output, compact 7x7 mm, 44 QFN Temperature range: -40 to +85 C Pb-free, RoHS-6 compliant Ordering Information See Section 8. Functional Block Diagram Si5341/40 Max Output Frequency 712.5 MHz 350 MHz 712.5 MHz 350 MHz IN0 /INT Frequency Synthesis Mode IN1 /INT Integer + Fractional IN2 /INT Integer Only Clock tree generation replacing XOs, buffers, signal format translators Any-frequency clock translation Clocking for FPGAs, processors, memory OSC XB /INT Ethernet switches/routers OTN framers/mappers/processors Test equipment & instrumentation Broadcast video OUT0 Multi Synth /INT OUT1 Multi Synth /INT OUT2 Multi Synth /INT OUT3 Multi Synth /INT OUT4 /INT OUT5 NVM /INT OUT6 I2C/SPI /INT OUT7 The Si5341/40 can be quickly and easily configured using ClockBuilder Pro software. Custom part numbers are automatically assigned using a ClockBuilder Pro for fast, free, and easy factory pre-programming, or the Si5341/40 can be programmed incircuit via I2C and SPI serial interfaces. Control/ Status /INT OUT8 /INT OUT9 Rev. 1.0 7/15 Copyright (c) 2015 by Silicon Laboratories Si5341 /INT Si5340 Multi Synth Description The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL with proprietary MultiSynth fractional synthesizer technology to offer a versatile and high performance clock generator platform. This highly flexible architecture is capable of synthesizing a wide range of integer and non-integer related frequencies up to 712.5 MHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter performance with 0 ppm error. Each of the clock outputs can be assigned its own format and output voltage enabling the Si5341/40 to replace multiple clock ICs and oscillators with a single device making it a true "clock tree on a chip". PLL XA FB_IN Applications 7x7 mm IN_SEL[1:0] Device Selector Guide Grade Si534xA Si534xB Si534xC Si534xD 9x9 mm XTAL Si5341/40 Si5341/40 2 Rev. 1.0 Si5341/40 TABLE O F C ON TENTS 1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1. Power-up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3. Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.5. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.6. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.8. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.9. Custom Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.10. Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 9.1. Si5341 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 9.2. Si5340 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Rev. 1.0 3 Si5341/40 1. Typical Application Schematic 161.1328125 MHz Buffer Buffer 2x 161.1328125 MHz LVDS 133.33 MHz 2x 133.33 MHz 1.8V LVCMOS Buffer 125 MHz Level Translator Delay Line 3x 125 MHz LVPECL Buffer Clock Generator Level Translator XA 4x 125 MHz 3.3V LVCMOS 200 MHz 2.5V LVCMOS 25 MHz XB "Traditional Discrete" Clock Tree One Si5341 replaces: 3x crystal oscillators (XO) 2x buffers 1x Clock Generator 2x level translators 1x delay line 1x 161.1328125 MHz LVDS 1x 161.1328125 MHz LVDS XA 2x 133.33 MHz 1.8V LVCMOS 25 MHz XB Si5341 1x 125 MHz LVPECL 1x 125 MHz LVPECL 1x 125 MHz LVPECL 2x 125 MHz 3.3V LVCMOS 2x 125 MHz 3.3V LVCMOS 2x 200 MHz 2.5V LVCMOS "Clock Tree On-a-Chip" 2x 200 MHz 2.5V LVCMOS Figure 1. Using The Si5341 to Replace a Traditional Clock Tree 4 Rev. 1.0 Si5341/40 2. Electrical Specifications Table 1. Recommended Operating Conditions (VDD = 1.8 V 5%, VDDA = 3.3 V 5%,TA = -40 to 85 C) Parameter Ambient Temperature Symbol TA Min -40 Typ 25 Max 85 Units C Junction Temperature TJMAX -- -- 125 C Core Supply Voltage VDD 1.71 1.80 1.89 V VDDA 3.14 3.30 3.47 V VDDO 3.14 3.30 3.47 V 2.38 2.50 2.62 V 1.71 1.80 1.89 V Output Driver Supply Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise noted. Rev. 1.0 5 Si5341/40 Table 2. DC Characteristics (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 5%, TA = -40 to 85 C) Parameter Core Supply Current Symbol IDD Test Condition Si5341 Note 1 IDDA Output Buffer Supply Current IDDOx Total Power Dissipation Pd Si5340 Note 2 Min -- -- Si5341 Note 1 -- 115 125 mA Si5340 Note 2 -- 115 125 mA LVPECL Output3 @ 156.25 MHz -- 21 25 mA LVDS Output3 @ 156.25 MHz -- 15 18 mA 3.3 V LVCMOS4 output @ 156.25 MHz -- 21 25 mA 2.5 V LVCMOS4 output @ 156.25 MHz -- 16 18 mA 1.8 V LVCMOS4 output @ 156.25 MHz -- 12 13 mA Si5341 Notes 1,5 -- 830 980 mW Si5340 2,5 -- 685 815 mW Notes Typ 100 85 Max 150 130 Units mA mA Notes: 1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors. 2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors. 3. Differential outputs terminated into an ac-coupled 100 load. 4. LVCMOS outputs measured into a 6-inch 50 PCB trace with 5 pF load. The LVCMOS outputs were set to OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5341/40 Family Reference Manual for more details on register settings. Differential Output Test Configuration IDDO OUT 50 LVCMOS Output Test Configuration IDDO 0.1 uF 100 OUT 50 6 inch OUTa OUTb 50 5 pF 0.1 uF 5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not available. All EVBs support detailed current measurements for any configuration. 6 Rev. 1.0 Si5341/40 Table 3. Input Specifications (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Units Differential or Single-Ended/LVCMOS -- AC-Coupled (IN0/IN0, IN1/IN1, IN2/IN2, FB_IN/FB_IN) Input Frequency Range Input Voltage Swing5 fIN VIN Differential 10 -- 750 MHz Single-ended/LVCMOS 10 -- 250 Differential AC Coupled fin < 250 MHz 100 -- 1800 mVpp_se Differential AC Coupled 250 MHz < fin < 750 MHz 225 -- 1800 mVpp_se Single-ended AC Coupled fin < 250 MHz 100 -- 3600 mVpp_se Slew Rate1, 2 SR 400 -- -- V/s Duty Cycle DC 40 -- 60 % Capacitance CIN -- 2 -- pF DC-Coupled CMOS Input Buffer (IN0, IN1, IN2)4 Input Frequency fIN 10 -- 250 MHz Input Voltage VIL -0.2 -- 0.33 V VIH 0.49 -- -- V SR 400 -- -- V/s Slew Rate 1, 2 Duty Cycle DC Clock Input 40 -- 60 % Minimum Pulse Width PW Pulse Input 1.6 -- -- ns Input Resistance RIN -- 8 -- k 48 -- 200 MHz 10 -- 200 MHz 365 -- 2000 mVpp_se Differential or Single-Ended/LVCMOS Clock at XA/XB Input Frequency Range Input Single-ended Voltage Swing fIN Frequency range for best output jitter performance VIN_SE Notes: 1. Imposed for jitter performance. 2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) * VIN_Vpp_se) / SR. 3. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. 4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended LVCMOS inputs to IN0,1,2 it is required to ac-couple into the differential input buffer. 5. Voltage swing is specified as single-ended mVpp. 6. Contact Silicon Labs Technical Support for more details. Rev. 1.0 7 Si5341/40 Table 3. Input Specifications (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, TA = -40 to 85 C) Parameter Input Differential Voltage Swing Symbol Test Condition VIN_DIFF Slew rate1, 2 SR Input Duty Cycle DC Imposed for best jitter performance Min Typ Max Units 365 -- 2500 mVpp_diff 400 -- -- V/s 40 -- 60 % Notes: 1. Imposed for jitter performance. 2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) * VIN_Vpp_se) / SR. 3. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. 4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended LVCMOS inputs to IN0,1,2 it is required to ac-couple into the differential input buffer. 5. Voltage swing is specified as single-ended mVpp. 6. Contact Silicon Labs Technical Support for more details. Table 4. Control Input Pin Specifications (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, VDDS = 3.3 V 5%, 1.8 V 5%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Units Si5341 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, SYNC, A1, SCLK, A0/CS, FINC, FDEC, SDA/SDIO) Input Voltage VIL -- -- 0.3xVDDIO* V VIH 0.7xVDDIO* -- -- V Input Capacitance CIN -- 2 -- pF Input Resistance RIN -- 20 -- k Minimum Pulse Width TPW RST, SYNC, FINC, and FDEC 100 -- -- ns Frequency Update Rate FUR FINC and FDEC -- -- 1 MHz Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, A1, SDA, SDI, SCLK, A0/CS, SDA/SDIO) Input Voltage VIL -- -- 0.3xVDDIO* V VIH 0.7xVDDIO* -- -- V Input Capacitance CIN -- 2 -- pF Input Resistance RIN -- 20 -- k Minimum Pulse Width TPW 100 -- -- ns RST only *Note: VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Reference Manual for more details on register settings. 8 Rev. 1.0 Si5341/40 Table 5. Differential Clock Output Specifications (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 5%, TA = -40 to 85 C) Parameter Symbol Output Frequency fOUT Duty Cycle DC Output-Output Skew TSK OUT-OUT Skew TSK_OUT Test Condition Min Typ Max Units 0.0001 -- 712.5 MHz fOUT < 400 MHz 48 -- 52 % 400 MHz < fOUT < 712.5 MHz 45 -- 55 % Outputs on same Multisynth, Normal Mode -- 20 50 ps Outputs on same Multisynth, Pow Power Mode -- 20 100 ps Measured from the positive to negative output pins -- 0 100 ps mVpp_se Output Amplitude1, 5 Normal Mode VOUT VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS 350 470 550 VDDO = 3.3 V or 2.5 V LVPECL 660 810 1000 Low Power Mode VOUT VDDO = 3.3 V, 2.5 V, or 1.8 V LVDS 300 420 530 VDDO = 3.3 V or 2.5 V LVPECL 620 820 1060 mVpp_se Notes: 1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference Manual. 2. Driver output impedance depends on selected output mode (Normal, Low Power). 3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/ 3.3 V = 100 mVpp) and noise spur amplitude measured. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to application note, "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems", guidance on crosstalk minimization. 5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual. 6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them. 7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs. Rev. 1.0 9 Si5341/40 Table 5. Differential Clock Output Specifications (Continued) (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 5%, TA = -40 to 85 C) Parameter Common Mode Voltage Symbol Test Condition 1 Min Typ Max Units V Normal Mode or Low Power Modes VCM VDDO = 3.3 V LVDS 1.10 1.25 1.35 LVPECL 1.90 2.05 2.15 VDDO = 2.5 V LVPECL LVDS 1.15 1.25 1.35 VDDO = 1.8 V Sub-LVDS 0.87 0.93 1.0 Normal Mode -- 170 240 Low Power Mode -- 300 430 Normal Mode -- 100 -- Low Power Mode -- 650 -- dBc tR/tF Rise and Fall Times (20% to 80%) Differential Output Impedance2 Power Supply Noise Rejection 3 ZO ps Normal Mode PSRR 10 kHz sinusoidal noise -- -93 -- 100 kHz sinusoidal noise -- -93 -- 500 kHz sinusoidal noise -- -84 -- 1 MHz sinusoidal noise -- -79 -- Low Power Mode 10 kHz sinusoidal noise -- -98 -- 100 kHz sinusoidal noise -- -95 -- 500 kHz sinusoidal noise -- -84 -- 1 MHz sinusoidal noise -- -76 -- dBc Notes: 1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference Manual. 2. Driver output impedance depends on selected output mode (Normal, Low Power). 3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/ 3.3 V = 100 mVpp) and noise spur amplitude measured. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to application note, "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems", guidance on crosstalk minimization. 5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual. 6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them. 7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs. 10 Rev. 1.0 Si5341/40 Table 5. Differential Clock Output Specifications (Continued) (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 5%, TA = -40 to 85 C) Parameter Symbol Output-Output Crosstalk Test Condition XTALK Min Typ Max Units Note 4 -- -75 -- dBc Si5341 Note 6 -- -85 -- dBc Si5340 Note 7 -- -85 -- dBc Si5341 Notes: 1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference Manual. 2. Driver output impedance depends on selected output mode (Normal, Low Power). 3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/ 3.3 V = 100 mVpp) and noise spur amplitude measured. OUTx Vcm Vpp_se Vcm Vpp_se Vpp_diff = 2*Vpp_se OUTx 4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to application note, "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems", guidance on crosstalk minimization. 5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual. 6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them. 7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs. Table 6. Output Status Pin Specifications (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, VDDS = 3.3 V 5%, 1.8 V 5%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Units Si5341 Status Output Pins (LOL, INTR), SDA/SDIO2, SDO Output Voltage VOH IOH = -2 mA VDDIO1 x 0.75 -- -- V VOL IOL = 2 mA -- -- VDDIO1 x 0.15 V -- -- V -- 1 V Si5340 Status Output Pins (INTR), LOL, LOS_XAXB, SDA/SDIO2, SDO Output Voltage VOH VOL IOH = -2 mA IOL = 2 mA VDDIO1 x 0.75 -- VDDIO x 0.15 Notes: 1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Reference Manual for more details on register settings. 2. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused with I2C_SEL pulled high. VOL remains valid in all cases. Rev. 1.0 11 Si5341/40 Table 7. LVCMOS Clock Output Specifications (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 5%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Units 0.0001 -- 250 MHz fOUT < 100 MHz 47 -- 53 % 100 MHz < fOUT < 250 MHz 44 -- 55 -- -- 100 ps VDDO x 0.75 -- -- V -- -- -- -- -- -- -- -- -- -- -- -- -- -- Output Frequency Duty Cycle DC Output-to-Output Skew TSK Output Voltage High1, 2, 3 VOH VDDO = 3.3 V OUTx_CMOS_DRV=1 IOH = -10 mA OUTx_CMOS_DRV=2 IOH = -12 mA OUTx_CMOS_DRV=3 IOH = -17 mA VDDO = 2.5 V OUTx_CMOS_DRV=1 IOH = -6 mA OUTx_CMOS_DRV=2 IOH = -8 mA OUTx_CMOS_DRV=3 IOH = -11 mA VDDO x 0.75 V VDDO = 1.8 V OUTx_CMOS_DRV=2 IOH = -4 mA OUTx_CMOS_DRV=3 IOH = -5 mA VDDO x 0.75 V Notes: 1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the Reference Manual for more details on register settings. 2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration. 3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 PCB trace. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3. DC Test Configuration AC Test Configuration Trace length 5 inches IOL/IOH 499 IDDO 4.7 pF OUT Zs 0.1 uF 50 OUT VOL/VOH 499 0.1 uF 50 4.7 pF 12 Rev. 1.0 50 probe, scope 56 56 50 probe, scope Si5341/40 Table 7. LVCMOS Clock Output Specifications (Continued) (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 5%, TA = -40 to 85 C) Parameter Symbol Output Voltage Low1, 2, 3 VOL Test Condition Min Typ Max Units VDDO x 0.15 V VDDO x 0.15 V VDDO x 0.15 V VDDO = 3.3 V OUTx_CMOS_DRV=1 IOL = 10 mA -- -- OUTx_CMOS_DRV=2 IOL = 12 mA -- -- OUTx_CMOS_DRV=3 IOL = 17 mA -- -- VDDO = 2.5 V OUTx_CMOS_DRV=1 IOL = 6 mA -- -- OUTx_CMOS_DRV=2 IOL = 8 mA -- -- OUTx_CMOS_DRV=3 IOL = 11 mA -- -- VDDO = 1.8 V LVCMOS Rise and Fall Times3 (20% to 80%) OUTx_CMOS_DRV=2 IOL = 4 mA -- -- OUTx_CMOS_DRV=3 IOL = 5 mA -- -- VDDO = 3.3V -- 420 550 ps VDDO = 2.5 V -- 475 625 ps VDDO = 1.8 V -- 525 705 ps tr/tf Notes: 1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the Reference Manual for more details on register settings. 2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration. 3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 PCB trace. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3. DC Test Configuration AC Test Configuration Trace length 5 inches IOL/IOH 499 IDDO 4.7 pF OUT Zs 0.1 uF 50 OUT VOL/VOH 499 56 0.1 uF 50 4.7 pF Rev. 1.0 50 probe, scope 50 probe, scope 56 13 Si5341/40 Table 8. Performance Characteristics (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, TA = -40 to 85 C) Parameter Min Typ Max Units FVCO 13.5 -- 14.256 GHz PLL Loop Bandwidth fBW -- 1.0 -- MHz Initial Start-Up Time tSTART -- 30 45 ms -- -- 15 ms VCO Frequency Range Symbol Test Condition Time from power-up to when the device generates clocks (Input Frequency > 48 MHz) POR1 to Serial Interface Ready tRDY PLL Lock Time6 tACQ fIN = 19.44 MHz 22 -- 180 ms tDELAY_- fVCO = 14 GHz Delay is controlled by the MultiSynth -- 0.28 -- ps -- 71.4 -- ps -- 9.14 -- ns Integer Mode3 12 kHz to 20 MHz -- 0.135 0.175 ps RMS Fractional/DCO Mode4 12 kHz to 20 MHz -- 0.160 0.205 ps RMS Derived from integrated phase noise -- 0.140 -- ps pk-pk -- 0.250 -- ps pk N = 10,000 cycles Integer or Fractional Mode3,4. Measured in the time domain. Performance is limited by the noise floor of the equipment. -- 7.3 -- ps pk-pk -- 8.1 -- ps pk Output Delay Adjustment frac tDELAY_int tRANGE Jitter Generation Locked to External Clock2 JGEN JPER JCC JPER JCC Notes: 1. Measured as time from valid VDD and VDD33 rails (90% of their value) to when the serial interface is ready to respond to commands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz. 2. Jitter generation test conditions fIN = 100 MHz, fOUT = 156.25 MHz LVPECL. 3. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value. 4. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the feedback divider is integer. 5. Initiate a soft reset command to align the outputs to within +/- 100 ps. 6. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input clock. The time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time. 14 Rev. 1.0 Si5341/40 Table 8. Performance Characteristics (Continued) (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, TA = -40 to 85 C) Parameter Jitter Generation Locked to External XTAL Symbol Test Condition Min Typ Max Units XTAL Frequency = 48 MHz JGEN JPER JCC JPER JCC Integer Mode3 12 kHz to 20 MHz -- 0.090 0.150 ps RMS Fractional/DCO Mode4 12 kHz to 20 MHz -- 0.120 0.165 ps RMS Derived from integrated phase noise -- 0.150 -- ps pk-pk -- 0.270 -- ps pk N = 10, 000 cycles Integer or Fractional Mode3,4 . Measured in the time domain. Performance is limited by the noise floor of the equipment. -- 7.3 -- ps pk-pk -- 7.8 -- ps pk Integer Mode 12 kHz to 20 MHz 0.125 0.330 ps RMS Fractional 12 kHz to 20 MHz 0.170 0.360 ps RMS XTAL Frequency = 25 MHz JGEN Notes: 1. Measured as time from valid VDD and VDD33 rails (90% of their value) to when the serial interface is ready to respond to commands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz. 2. Jitter generation test conditions fIN = 100 MHz, fOUT = 156.25 MHz LVPECL. 3. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value. 4. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the feedback divider is integer. 5. Initiate a soft reset command to align the outputs to within +/- 100 ps. 6. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input clock. The time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time. Rev. 1.0 15 Si5341/40 Table 9. I2C Timing Specifications (SCL,SDA) Parameter Symbol Test Condition Min Max Min Standard Mode 100 kbps SCL Clock Frequency Max Units Fast Mode 400 kbps fSCL -- 100 -- 400 kHz Hold Time (Repeated) START Condition tHD:STA 4.0 -- 0.6 -- s Low Period of the SCL Clock tLOW 4.7 -- 1.3 -- s HIGH Period of the SCL Clock tHIGH 4.0 -- 0.6 -- s Set-up Time for a Repeated START Condition tSU:STA 4.7 -- 0.6 -- s Data Hold Time tHD:DAT 100 -- 100 -- ns Data Set-up Time tSU:DAT 250 -- 100 -- ns Rise Time of Both SDA and SCL Signals tr -- 1000 20 300 ns Fall Time of Both SDA and SCL Signals tf -- 300 -- 300 ns Set-up Time for STOP Condition tSU:STO 4.0 -- 0.6 -- s Bus Free Time between a STOP and START Condition tBUF 4.7 -- 1.3 -- s Data Valid Time tVD:DAT -- 3.45 -- 0.9 s Data Valid Acknowledge Time tVD:ACK -- 3.45 -- 0.9 s 16 Rev. 1.0 Si5341/40 Figure 2. I2C Serial Port Timing Standard and Fast Modes Rev. 1.0 17 Si5341/40 Table 10. SPI Timing Specifications (4-Wire) (VDD = 1.8 V 5%, VDDA = 3.3V 5%, TA = -40 to 85 C) Parameter Symbol Min Typ Max Units SCLK Frequency fSPI -- -- 20 MHz SCLK Duty Cycle TDC 40 -- 60 % SCLK Period TC 50 -- -- ns Delay Time, SCLK Fall to SDO Active TD1 -- 12.5 18 ns Delay Time, SCLK Fall to SDO TD2 -- 10 15 ns Delay Time, CS Rise to SDO Tri-State TD3 -- 10 15 ns Setup Time, CS to SCLK TSU1 5 -- -- ns Hold Time, CS to SCLK Rise TH1 5 -- -- ns Setup Time, SDI to SCLK Rise TSU2 5 -- -- ns Hold Time, SDI to SCLK Rise TH2 5 -- -- ns Delay Time Between Chip Selects (CS) TCS 2 -- -- TC TSU1 TD1 TC SCLK TH1 CS TSU2 TH2 TCS SDI TD2 TD3 SDO Figure 3. 4-Wire SPI Serial Interface Timing 18 Rev. 1.0 Si5341/40 Table 11. SPI Timing Specifications (3-Wire) (VDD = 1.8 V 5%, VDDA = 3.3 V 5%, TA = -40 to 85 C) Parameter Symbol Min Typ Max Units SCLK Frequency fSPI -- -- 20 MHz SCLK Duty Cycle TDC 40 -- 60 % SCLK Period TC 50 -- -- ns Delay Time, SCLK Fall to SDIO Turn-on TD1 -- 12.5 20 ns Delay Time, SCLK Fall to SDIO Next-bit TD2 -- 10 15 ns Delay Time, CS Rise to SDIO Tri-State TD3 -- 10 15 ns Setup Time, CS to SCLK TSU1 5 -- -- ns Hold Time, CS to SCLK Rise TH1 5 -- -- ns Setup Time, SDI to SCLK Rise TSU2 5 -- -- ns Hold Time, SDI to SCLK Rise TH2 5 -- -- ns Delay Time Between Chip Selects (CS) TCS 2 -- -- TC TSU1 TC SCLK TD1 CS TSU2 TH1 TD2 TH2 TCS SDIO TD3 Figure 4. 3-Wire SPI Serial Interface Timing Rev. 1.0 19 Si5341/40 Table 12. Crystal Specifications Parameter Crystal Frequency Range Symbol Test Condition Min Typ Max Units fXTAL_48-54 Frequency range for best jitter performance 48 -- 54 MHz Load Capacitance CL_48-54 -- 8 -- pF Shunt Capacitance CO_48-54 -- -- 2 pF Crystal Drive Level dL_48-54 -- -- 200 W Equivalent Series Resistance rESR_48-54 Refer to the Si5341/40 Family Reference Manual to determine ESR. fXTAL_25 -- 25 -- MHz Load Capacitance CL_25 -- 8 -- pF Shunt Capacitance CO_25 -- -- 3 pF Crystal Drive Level dL_25 -- -- 200 W Crystal Frequency Range Equivalent Series Resistance rESR_25 Refer to the Si5341/40 Family Reference Manual to determine ESR Notes: 1. The Si5341/40 is designed to work with crystals that meet the specifications in Table 12. 2. Refer to the Si5341/40 Family Reference Manual for recommended 48 to 54 MHz crystals. 20 Rev. 1.0 Si5341/40 Table 13. Thermal Characteristics Parameter Symbol Test Condition* Value Units JA Still Air 22 C/W Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.3 Si5341 -- 64QFN Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case JC 9.5 Thermal Resistance Junction to Board JB 9.4 JB 9.3 JT 0.2 Thermal Resistance Junction to Top Center Si5340-44QFN Thermal Resistance Junction to Ambient JA Still Air 22.3 Air Flow 1 m/s 19.4 Air Flow 2 m/s 18.4 Thermal Resistance Junction to Case JC 10.9 Thermal Resistance Junction to Board JB 9.3 JB 9.2 JT 0.23 Thermal Resistance Junction to Top Center C/W *Note: Based on PCB Dimension: 3" x 4.5", PCB Thickness: 1.6 mm, PCB Land/Via under GND pad: 36, Number of Cu Layers: 4 Rev. 1.0 21 Si5341/40 Table 14. Absolute Maximum Ratings1,2,3,4 Parameter Symbol Test Condition Value Units Storage Temperature Range TSTG -55 to +150 C DC Supply Voltage VDD -0.5 to 3.8 V VDDA -0.5 to 3.8 V VDDO -0.5 to 3.8 V Input Voltage Range Latch-up Tolerance VI1 IN0-IN2, FB_IN -0.85 to 3.8 V VI2 IN_SEL[1:0], RST, OE, SYNC, I2C_SEL, SDI, SCLK, A0/CS A1, SDA/SDIO FINC/FDEC -0.5 to 3.8 V VI3 XA/XB -0.5 to 2.7 V LU ESD Tolerance HBM Junction Temperature Soldering Temperature (Pb-free profile)4 Soldering Temperature Time at TPEAK (Pb-free profile)4 JESD78 Compliant 100 pF, 1.5 k 2.0 kV TJCT -55 to 150 C TPEAK 260 C TP 20-40 sec Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. 64-QFN and 44-QFN packages are RoHS-6 compliant. 3. For MSL and more packaging information, go to www.silabs.com/support/quality/pages/rohsinformation.aspx. 4. The device is compliant with JEDEC J-STD-020. 22 Rev. 1.0 Si5341/40 3. Typical Operating Characteristics D D Figure 5. Integer Mode--48 MHz Crystal, 625 MHz Output (2.5 V LVDS) Rev. 1.0 23 Si5341/40 D D Figure 6. Integer Mode--48 MHz Crystal, 156.25 MHz Output (2.5 V LVDS) 24 Rev. 1.0 Si5341/40 D D Figure 7. Fractional Mode--48 MHz Crystal, 155.52 MHz Output (2.5 V LVDS) Rev. 1.0 25 Si5341/40 VDDA VDD 4. Detailed Block Diagrams 3 Si5341 IN_SEL[1:0] Clock Generator /P0 IN2 PD /P2 IN2 LPF / MultiSynth OSC N / 0n N0d t0 N1n N1d t1 N2n N2d t2 N / 3n N3d t3 N4n N4d t4 XA / Zero Delay Mode FB_IN / /Pfb FB_IN I2C_SEL RST A0/CS NVM Status Monitors Figure 8. Si5341 Block Diagram 26 /R2 VDDO2 OUT2 OUT2 /R3 VDDO3 OUT3 OUT3 /R4 VDDO4 OUT4 OUT4 /R5 VDDO5 OUT5 OUT5 /R6 VDDO6 OUT6 OUT6 /R7 VDDO7 OUT7 OUT7 /R8 VDDO8 OUT8 OUT8 /R9 VDDO9 OUT9 OUT9 Frequency Control FINC SCLK SPI/ I2C INTR A1/SDO / LOL SDA/SDIO Mn Md / PXAXB XB 25MHz, 48-54MHz XTAL /R1 VDDO1 OUT1 OUT1 PLL /P1 IN1 VDDO0 OUT0 OUT0 Rev. 1.0 OE IN1 FDEC IN0 /R0 SYNC IN0 Dividers/ Drivers 4 VDDA VDD Si5341/40 2 Si5340 Clock Generator /PXAXB XB 25MHz, 48-54MHz XTAL OSC PLL IN0 IN0 IN1 IN1 IN2 IN2 Dividers/ Drivers MultiSynth XA /P0 LPF /P1 PD Md / Mn /P2 / Nn0 Nd0 t0 /R0 VDDO0 OUT0 OUT0 / Nn1 Nd1 t1 /R1 VDDO1 OUT1 OUT1 / N2n N2d t2 /R2 VDDO2 OUT2 OUT2 / N3n N3d t3 /R3 VDDO3 OUT3 OUT3 IN_SEL[1:0] Zero Delay Mode OE SCLK NVM A0/CS A1/SDO I2C_SEL LOSXAB SDA/SDIO SPI/ I2C Status Monitors LOL /Pfb INTR FB_IN RST FB_IN Figure 9. Si5340 Detailed Block Diagram Rev. 1.0 27 Si5341/40 5. Functional Description The Si5341/40 combines a wide band PLL with next generation MultiSynth technology to offer the industry's most versatile and high performance clock generator. The PLL locks to either an external crystal between XA/XB or to an external clock connected to XA/XB or IN0,1,2. A fractional or integer multiplier takes the selected input clock or crystal frequency up to a very high frequency that is then divided by the MultiSynth output stage to any frequency in the range of 100 Hz to 712.5 MHz on each output. The MultiSynth stage can divide by both integer and fractional values.The high-resolution fractional MultiSynth dividers enables true any-frequency input to any-frequency on any of the outputs. The output drivers offer flexible output formats which are independently configurable on each of the outputs. This clock generator is fully configurable via its serial interface (I2C/SPI) and includes in-circuit programmable non-volatile memory. 5.1. Power-up and Initialization Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A hard reset is functionally similar to a device powerup. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. Power-Up Hard Reset bit asserted RST pin asserted NVM download Soft Reset bit asserted Initialization Serial interface ready Figure 10. Si5341 Power-up and Initialization 28 Rev. 1.0 Si5341/40 5.2. Frequency Configuration The phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is to phase lock to the selected input and provide a common reference to the MultiSynth high-performance fractional dividers. A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional output integer dividers provide further frequency division by an even integer from 2 to (2^25)-2. The frequency configuration of the device is programmed by setting the input dividers (P), the PLL feedback fractional divider (Mn/ Md), the MultiSynth fractional dividers (Nn/Nd), and the output integer dividers (R). Silicon Labs' Clockbuilder Pro configuration utility determines the optimum divider values for any desired input and output frequency plan. 5.3. Inputs The Si5341/40 requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0,1,2. 5.3.1. XA/XB Clock and Crystal Input An internal crystal oscillator exists between pin XA and XB. When this oscillator is enabled, an external crystal connected across these pins will oscillate and provide a clock input to the PLL. A crystal frequency of 25 MHz can be used although crystals in the frequency range of 48 MHz to 54 MHz are recommended for best jitter performance. Frequency offsets due to CL mismatch can be adjusted using the frequency adjustment feature which allows frequency adjustments of 1000 ppm. The Si5341/40 Family Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Refer to Table 12 for crystal specifications. The Si5341/40 can also accommodate an external input clock instead of a crystal. This allows the use of crystal oscillator (XO) instead of a XTAL. Selection between the external XTAL or input clock is controlled by register configuration. The internal crystal load capacitors (CL) are disabled in the input clock mode. Refer to Table 3 for the input clock requirements at XAXB. Both a single-ended or a differential input clock can be connected to the XA/XB pins as shown in Figure 11. A PXAXB divider is available to accommodate external clock frequencies higher than 54 MHz. Rev. 1.0 29 Si5341/40 DifferentialConnection Singleended XO Connection nc X1 nc X2 nc X1 nc X2 Note: 2.0 Vpp_se max 0.1 uf 100 2xCL 0.1 uf XA 2xCL XA 100 OSC OSC XB XO with Clipped Sine Wave Output 2xCL 0.1 uf XB 2xCL Si5341/40 0.1 uf Si5341/40 Note: 2.5 Vpp diff max Crystal Connection Singleended Connection nc X1 nc X2 Note: 2.0 Vpp_se max X1 2xC L CMOS Output 0.1 uf R1 XA OSC XO VDD 3.3 V 2.5 V 1.8 V R1 523 475 158 R2 442 649 866 2xCL XA R2 0.1 uf 0.1 uf XTAL OSC XB XB 2xCL Si5341/40 X2 2xC L Si5341/40 Figure 11. XAXB External Crystal and Clock Connections 5.3.2. Input Clocks (IN0, IN1, IN2) A differential or single-ended clock can be applied at IN2, IN1, or IN0. The recommended input termination schemes are shown in Figure 12. AC Coupled Differential 0.1 uf 50 Si5341/40 50 0.1 uf Differential Driver LVDS, LVPECL, CML INx 50 50 INx 0.1 uf AC Coupled LVCMOS or Single Ended 50 3.3V, 2.5V, 1.8V LVCMOS or Single Ended Signal Si5341/40 0.1 uf INx 0.1 uf INx Figure 12. Termination of Differential and LVCMOS Input Signals 30 Rev. 1.0 Si5341/40 5.3.3. Input Selection (IN0, IN1, IN2, XA/XB) The active clock input is selected using the IN_SEL[1:0] pins or by register control. A register bit determines input selection as pin or register selectable. There are internal pull ups on the IN_SEL pins. Table 15. Manual Input Selection Using IN_SEL[1:0] Pins IN_SEL[1:0] Selected Input 0 0 IN0 0 1 IN1 1 0 IN2 1 1 XA/XB 5.4. Fault Monitoring The Si5341/40 provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of lock (LOL) for the PLL. This is shown in Figure 13. IN0 IN0 IN1 IN1 IN2 /P0 LOS0 /P1 LOS1 /P2 IN2 Si5341/40 LOL PLL PD LOS2 LPF / Mn Md LOSXAB /Pfb INTR LOL LOSFB LOS0 FB_IN LOSXAB FB_IN OSC LOS2 XB LOS1 XA Figure 13. LOS and LOL Fault Monitors 5.4.1. Status Indicators The state of the status monitors are accessible by reading registers through the serial interface or with dedicated pin (LOL). Each of the status indicator register bits has a corresponding sticky bit in a separate register location. Once a status bit is asserted its corresponding sticky bit (_FLG) will remain asserted until cleared. Writing a logic zero to a sticky register bit clears its state. 5.4.2. Interrupt Pin (INTR) An interrupt pin (INTR) indicates a change in state with any of the status registers. All status registers are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the status registers. Rev. 1.0 31 Si5341/40 5.5. Outputs The Si5341 supports 10 differential output drivers which can be independently configured as differential or LVCMOS. The Si5340 supports 4 output drivers independently configurable as differential or LVCMOS. 5.5.1. Output Signal Format The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal formats including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. 5.5.2. Differential Output Terminations The differential output drivers support both ac-coupled and dc-coupled terminations as shown in Figure 14. AC Coupled LVDS/LVPECL DC Coupled LVDS VDDO = 3.3V, 2.5V, 1.8V VDDO = 3.3V, 2.5V, 1.8V 50 OUTx 50 OUTx 100 OUTx 100 OUTx 50 50 Internally self-biased Si5341/40 Si5341/40 AC Coupled LVPECL/CML DC Coupled LVCMOS 3.3V, 2.5V, 1.8V LVCMOS VDDO = 3.3V, 2.5V, 1.8V VDD - 1.3V VDDO = 3.3V, 2.5V 50 50 OUTx Rs OUTx OUTx 50 50 Si5341/40 Si5341/40 Rs AC Coupled HCSL VDDRX VDDO = 3.3V, 2.5V, 1.8V R1 OUTx R1 50 Standard HCSL Receiver OUTx 50 Si5341/40 R2 R2 1 V For VOption CM = 0.37 VDDRX 3.3 V 2.5 V 1.8 V R1 R2 442 Ohms 56.2 Ohms 332 Ohms 59 Ohms 243 Ohms 63.4 Ohms Figure 14. Supported Differential Output Terminations 32 50 OUTx Rev. 1.0 50 Si5341/40 5.5.3. Differential Output Modes There are two selectable* differential output modes: Normal and Low Power. Each output can support a unique mode. In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards. Differential Normal Mode: When an output driver is configured in normal mode, its output amplitude is selectable as one of 7 settings ranging from ~130 mVpp_se to ~920 mVpp_se in increments of ~100 mV. See Appendix A for additional information. The output impedance in the normal mode is 100 differentialAny of the terminations shown in Figure 14 are supported in this mode. Differential Low Power Mode: When an output driver is configured in low power mode, its output amplitude is configurable as one of 7 settings ranging from ~200 mVpp_se to ~1600 mVpp_se in increments of ~200 mV. When in Differential Low Power Mode, the output impedance of the driver is much greater than 100 however the signal integrity will still be optimum as long as the differential clock traces are properly terminated in their characteristic impedance. Any of the terminations shown in Figure 14 are supported in this mode. *Note: Not all amplitude levels are available for selection in the CBPro device configuration Wizard. Refer to Sections 5.9 and 5.10 for more information. See also Appendix A of the Si5341/40 Reference Manual. 5.5.4. Programmable Common Mode Voltage For Differential Outputs The common mode voltage (VCM) for the differential Normal and Low Power modes are programmable so that LVDS specifications can be met and for the best signal integrity with different supply voltages. When dc coupling the output driver it is essential that the receiver should have a relatively high common mode impedance so that the common mode current from the output driver is very small. 5.5.5. LVCMOS Output Terminations LVCMOS outputs are typically dc-coupled as shown in Figure 15. DC Coupled LVCMOS 3.3V, 2.5V, 1.8V LVCMOS VDDO = 3.3V, 2.5V, 1.8V 50 OUTx Rs OUTx 50 Rs Figure 15. LVCMOS Output Terminations Rev. 1.0 33 Si5341/40 5.5.6. LVCMOS Output Impedance And Drive Strength Selection Each LVCMOS driver has a configurable output impedance. It is highly recommended that the minimum output impedance (strongest drive setting) is selected and a suitable series resistor (Rs) is chosen to match the trace impedance. Table 16. Nominal Output Impedance vs OUTx_CMOS_DRV (register) CMOS_DRIVE_Selection VDDO OUTx_CMOS_DRV=1 OUTx_CMOS_DRV=2 OUTx_CMOS_DRV=3 3.3 V 38 30 22 2.5 V 43 35 24 1.8 V -- 46 31 *Note: Refer to the Si5341/40 Family Reference Manual for more information on register settings. 5.5.7. LVCMOS Output Signal Swing The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. 5.5.8. LVCMOS Output Polarity When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By default the clock on the OUTx pin is generated with complementary polarity with the clock on the OUTx pin. The LVCMOS OUTx and OUTx outputs can also be generated in phase. 5.5.9. Output Enable/Disable The OE pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high all outputs will be disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be individually disabled through register control. 5.5.10. Output Driver State When Disabled The disabled state of an output driver is configurable as: disable low or disable high. 5.5.11. Synchronous/Asynchronous Output Disable Feature Outputs can be configured to disable synchronously or asynchronously. The default state is synchronous output disable. In synchronous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately without waiting for the period to complete. 34 Rev. 1.0 Si5341/40 5.5.12. Output Delay Control (t0 - t4) The Si5341/40 uses independent MultiSynth dividers (N0 - N4) to generate up to 5 unique frequencies to its 10 outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (t0 - t4) associated with each of these dividers is available for applications that need a specific output skew configuration. Each delay path is controlled by a register parameter call Nx_DELAY with a resolution of ~0.28 ps over a range of ~9.14 ns. This is useful for PCB trace length mismatch compensation. After the delay controls are configured, the soft reset bit SOFT_RST must be set high so that the output delay takes effect and the outputs are re-aligned. /N0 t0 /R0 VDDO0 OUT0 OUT0 VDDO1 OUT1 OUT1 /N1 t1 /R1 /N2 t2 /R2 VDDO2 OUT2 OUT2 /N3 t3 /R3 VDDO3 OUT3 OUT3 /N4 t4 /R4 VDDO4 OUT4 OUT4 /R5 VDDO5 OUT5 OUT5 /R6 VDDO6 OUT6 OUT6 /R7 VDDO7 OUT7 OUT7 /R8 VDDO8 OUT8 OUT8 /R9 VDDO9 OUT9 OUT9 Figure 16. Example of Independently Configurable Path Delays All delay values are restored to their NVM programmed values after power-up or after a hard reset. Delay default values can be written to the NVM allowing a custom delay offset configuration at power-up or after a hardware reset. Rev. 1.0 35 Si5341/40 5.5.13. Zero Delay Mode A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in Figure 17. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. It is recommended to connect OUT9 (Si5341) or OUT3 (Si5340) to FB_IN for external feedback. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance. Si5341 IN0 IN0 fIN IN1 IN1 IN2 IN2 VDDO0 OUT0 OUT0 VDDO1 OUT1 OUT1 / P0 VDDO2 OUT2 OUT2 / P1 / P2 VDDO3 OUT3 OUT3 IN_SEL[1:0] FB_IN Zero Delay Mode 100 /Pfb fFB = fIN PD VDDO7 OUT7 OUT7 LPF / FB_IN MultiSynth & Dividers PLL Mn Md VDDO8 OUT8 OUT8 / N9n N9d /R9 VDDO9 OUT9 OUT9 External Feedback Path Figure 17. Si5341 Zero Delay Mode Setup 5.5.14. Sync Pin (Synchronizing R Dividers) All the output R dividers are reset to the default NVM register state after a power-up or a hard reset. This ensures consistent and repeatable phase alignment across all output drivers to within 100 ps of the expected value from the NVM download. Resetting the device using the RST pin or asserting the hard reset bit will have the same result. The SYNC pin provides another method of re-aligning the R dividers without resetting the device, however, the outputs will only align to within 50 ns when using the SYNC pin. This pin is positive edge triggered. Asserting the sync register bit provides the same function as the SYNC pin. A soft reset will align the outputs to within 100 ps of the expected value based upon the Nx_DELAY parameter. 5.5.15. Output Crosspoint The output crosspoint allows any of the N dividers to connect to any of the clock outputs. 36 Rev. 1.0 Si5341/40 5.5.16. Digitally Controlled Oscillator (DCO) Modes Each MultiSynth can be digitally controlled to so that all outputs connected to the MultiSynth change frequency in real time without any transition glitches. There are two ways to control the MultiSynth to accomplish this task: Use the Frequency Increment/Decrement Pins or register bits Write directly to the numerator of the MultiSynth divider. An output that is controlled as a DCO is useful for simple tasks such as frequency margining or CPU speed control. The output can also be used for more sophisticated tasks such as FIFO management by adjusting the frequency of the read or write clock to the FIFO or using the output as a variable Local Oscillator in a radio application. 5.5.16.1. DCO with Frequency Increment/Decrement Pins/Bits Each of the MultiSynth fractional dividers can be independently stepped up or down in predefined steps with a resolution as low as 0.001 ppb. Setting of the step size and control of the frequency increment or decrement is accomplished by setting the step size with the 44 bit Frequency Step Word (FSTEPW). When the FINC or FDEC pin or register bit is asserted the output frequency will increment or decrement respectivley by the amount specified in the FSTEPW. 5.5.16.2. DCO with Direct Register Writes When a MultiSynth numerator and its corresponding update bit is written, the new numerator value will take effect and the output frequency will change without any glitches. The MultiSynth numerator and denominator terms can be left and right shifted so that the least significant bit of the numerator word represents the exact step resolution that is needed for your application. 5.6. Power Management Several unused functions can be powered down to minimize power consumption. Consult the Si5341/40 Family Reference Manual and ClockBuilder Pro configuration utility for details. 5.7. In-Circuit Programming The Si5341/40 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer accessible. Refer to the Si5341/40 Family Reference Manual for a detailed procedure for writing registers to NVM. 5.8. Serial Interface Configuration and operation of the Si5341/40 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin selects I2C or SPI operation. Communication with both 3.3V and 1.8V host is supported. The SPI mode operates in either 4-wire or 3-wire. See the Si5341/40 Family Reference Manual for details. 5.9. Custom Factory Preprogrammed Devices For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly and easily request and generate a custom part number for your configuration. In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your design's configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local Silicon Labs sales representative. Samples of your preprogrammed device will ship to you typically within two weeks. Rev. 1.0 37 Si5341/40 5.10. Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.silabs.com and opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes are. This update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data sheet and the Si5341/40 Family Reference Manual. However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register setting, but the feature or register setting is NOT yet available in CBPro, you must contact a Silicon Labs applications engineer for assistance. An example of this type of feature or custom setting is the customizable amplitudes for the clock outputs. After careful review of your project file and custom requirements, a Silicon Labs applications engineer will email back your CBPro project file with your specific features and register settings enabled, using what is referred to as the manual "settings override" feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro design report are shown below: Setting Overrides Location Customer Name Engineering Name Type Target Dec Value Hex Value 0x0435[0] FORCE_HOLD_PLLA OLA_HO_FORCE No NVM N/A 1 0x1 0x0B48[0:4] OOF_DIV_CLK_DIS OOF_DIV_CLK_DIS User OPN & EVB 0 0x00 Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after startup with the values in the NVM file, including the Silicon Labs-supplied override settings. Place sample order Start Do I need a preprogrammed device with a feature or setting which is unavailable in ClockBuilder Pro? No Configure device using CBPro Generate Custom OPN in CBPro Yes Contact Silicon Labs Technical Support to submit & review your nonstandard configuration request & CBPro project file Receive updated CBPro project file from Silicon Labs with "Settings Override" Yes Load project file into CBPro and test Does the updated CBPro Project file match your requirements? Figure 18. Flowchart to Order Custom Parts with Features not Available in CBPro 38 Rev. 1.0 Si5341/40 6. Register Map The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible registers such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as frequency configuration, and general device settings. A high level map of the registers is shown in section "6.2. High-Level Register Map" . Refer to the Si5341/40 Family Reference Manual for a complete list of registers descriptions and settings. 6.1. Addressing Scheme The device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register address. By default the page address is set to 0x00. Changing to another page is accomplished by writing to the `Set Page Address' byte located at address 0x01 of each page. 6.2. High-Level Register Map Table 17. High-Level Register Map 16-Bit Address Content 8-bit Page Address 8-bit Register Address Range 00 00 Revision IDs 01 Set Page Address 02-0A Device IDs 0B-15 Alarm Status 17-1B INTR Masks 1C Reset controls 2C-E1 Alarm Configuration E2-E4 NVM Controls FE Device Ready Status 01 Set Page Address 08-3A Output Driver Controls 41-42 Output Driver Disable Masks FE Device Ready Status 01 Rev. 1.0 39 Si5341/40 Table 17. High-Level Register Map (Continued) 16-Bit Address 8-bit Page Address 8-bit Register Address Range 02 01 Set Page Address 02-05 XTAL Frequency Adjust 08-2F Input Divider (P) Settings 30 Input Divider (P) Update Bits 35-3D PLL Feedback Divider (M) Settings 3E PLL Feedback Divider (M) Update Bit 47-6A Output Divider (R) Settings 6B-72 User Scratch Pad Memory FE Device Ready Status 01 Set Page Address 02-37 MultiSynth Divider (N0-N4) Settings 0C MultiSynth Divider (N0) Update Bit 17 MultiSynth Divider (N1) Update Bit 22 MultiSynth Divider (N2) Update Bit 2D MultiSynth Divider (N3) Update Bit 38 MultiSynth Divider (N4) Update Bit 39-58 FINC/FDEC Settings N0-N4 59-62 Output Delay (t) Settings 63-94 Frequency Readback N0-N4 FE Device Ready Status 04-08 00-FF Reserved 09 01 Set Page Address 49 Input Settings 1C Zero Delay Mode Settings 00-FF Reserved 03 A0-FF 40 Content Rev. 1.0 Si5341/40 7. Pin Descriptions XA 8 XB 9 X2 10 GND Pad 41 VDDO3 42 OUT3 7 34 X1 OUT3 OUT6 43 35 44 6 36 5 RST 37 SYNC VDD OUT6 I2C_SEL IN_SEL1 45 38 4 FB_IN VDD IN_SEL1 40 VDD FB_IN VDDO7 46 41 OUT7 49 3 IN0 OUT7 50 LOL IN_SEL0 42 VDDO8 51 FINC 47 IN0 OUT8 52 48 2 43 OUT8 53 1 IN1 44 RSVD OUT9 58 54 OUT9 59 55 VDD 60 VDDO9 FB_IN 61 RSVD FB_IN 62 56 IN0 63 57 IN0 64 IN1 39 Si5340 44QFN Top View Si5341 64QFN Top View IN1 1 33 INTR IN1 2 32 IN_SEL0 3 31 VDD OUT2 VDDO6 X1 4 30 OUT2 OUT5 XA 5 29 VDDO2 OUT5 XB 6 28 LOS_XAXB 7 27 LOL 8 26 VDDS 25 OUT1 40 VDDO5 39 I2C_SEL X2 VDDA GND Pad Rev. 1.0 17 18 19 20 21 22 RST OUT0 OUT0 VDD NC 16 A0/CS VDDO0 15 12 A1/SDO 32 VDD 14 31 OUT2 SCLK 30 OUT2 13 29 OE SDA/SDIO 28 VDDO3 OUT1 VDDO2 OUT3 33 27 34 16 26 15 OUT1 IN2 SCLK VDDO1 OUT3 25 35 FDEC 14 24 VDDO1 IN2 OUT0 23 23 11 OUT0 IN2 22 VDDO4 VDDO0 36 21 13 RSVD OUT1 VDDA 20 24 RSVD 10 19 IN2 A0/CS VDDA OUT4 18 OUT4 37 17 38 12 A1/SDO 11 INTR SDA/SDIO OE 9 41 Si5341/40 Table 18. Pin Descriptions Pin Number Pin Type1 Function 5 I 9 6 I Crystal and External Clock Input These pins are used to connect an external crystal or an external clock. See section "5.3.1. XA/XB Clock and Crystal Input" and "Figure 11. XAXB External Crystal and Clock Connections" for connection information. If IN_SEL[1:0] = 11b, then the XAXB input is selected. If the XAXB input is not used and powered down, then both inputs can be left unconnected. ClockBuilder Pro will power down an input that is set as "Unused". X1 7 4 I X2 10 7 I IN0 63 43 I IN0 64 44 I IN1 1 1 I IN1 2 2 I IN2 14 10 I IN2 15 11 I FB_IN 61 41 I FB_IN 62 42 I Pin Name Si5341 Si5340 XA 8 XB Inputs XTAL Shield Connect these pins directly to the XTAL ground pins. X1, X2, and the XTAL ground pins must not be connected to the PCB ground plane. DO NOT GROUND THE CRYSTAL GROUND PINS. Refer to the Si5341/40 Family Reference Manual for layout guidelines. These pins should be left disconnected when connecting XA/XB pins to an external reference clock. Clock Inputs These pins accept both differential and single-ended clock signals. Refer to "5.3.2. Input Clocks (IN0, IN1, IN2)" on page 30 for input termination options. These pins are high-impedance and must be terminated externally. If both the INx and INx (with overstrike) inputs are un-used and powered down, then both inputs can be left floating. ClockBuilder Pro will power down an input that is set as "Unused". External Feedback Input These pins are used as the external feedback input (FB_IN/ FB_IN) for the optional zero delay mode. See "5.5.13. Zero Delay Mode" on page 36 for details on the optional zero delay mode. If FB_IN and FB_IN (with overstrike) are un-used and powered down, then both inputs can be left floating. ClockBuilder Pro will power down an input that is set as "Unused". Notes: 1. I = Input, O = Output, P = Power. 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings. 3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK low. 42 Rev. 1.0 Si5341/40 Table 18. Pin Descriptions (Continued) Pin Number Pin Type1 Function 20 O 23 19 O OUT1 28 25 O OUT1 27 24 O OUT2 31 31 O Output Clocks These output clocks support a programmable signal amplitude when configured as a differential output. Desired output signal format is configurable using register control. Termination recommendations are provided in "5.5.2. Differential Output Terminations" on page 32 and "5.5.5. LVCMOS Output Terminations" on page 33. Unused outputs should be left unconnected. OUT2 30 30 O OUT3 35 36 O OUT3 34 35 O OUT4 38 -- O OUT4 37 -- O OUT5 42 -- O OUT5 41 -- O OUT6 45 -- O OUT6 44 -- O OUT7 51 -- O OUT7 50 -- O OUT8 54 -- O OUT8 53 -- O OUT9 59 -- O OUT9 58 -- O Pin Name Si5341 Si5340 OUT0 24 OUT0 Outputs Notes: 1. I = Input, O = Output, P = Power. 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings. 3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK low. Rev. 1.0 43 Si5341/40 Table 18. Pin Descriptions (Continued) Pin Name Pin Number Si5341 Si5340 Pin Type1 Function Serial Interface I2C_SEL 39 38 I I2C Select2 This pin selects the serial interface mode as I2C (I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled up by a ~ 20 k resistor to the voltage selected by the IO_VDD_SEL register bit. SDA/SDIO 18 13 I/O Serial Data Interface2 This is the bidirectional data pin (SDA) for the I2C mode, or the bidirectional data pin (SDIO) in the 3-wire SPI mode, or the input data pin (SDI) in 4-wire SPI mode. When in I2C mode, this pin must be pulled-up using an external resistor of at least 1 k. No pull-up resistor is needed when in SPI mode. A1/SDO 17 15 I/O Address Select 1/Serial Data Output2 In I2C mode, this pin functions as the A1 address input pin and does not have an internal pull up or pull down resistor. In 4-wire SPI mode this is the serial data output (SDO) pin (SDO) pin and drives high to the voltage selected by the IO_VDD_SEL pin. SCLK 16 14 I Serial Clock Input2 This pin functions as the serial clock input for both I2C and SPI modes.This pin is internally pulled up by a ~20 k resistor to the voltage selected by the IO_VDD_SEL register bit. In I2C mode this pin should have an external pull up of at least 1 k. No pull-up resistor is needed when in SPI mode. A0/CS 19 16 I Address Select 0/Chip Select2 This pin functions as the hardware controlled address A0 in I2C mode. In SPI mode, this pin functions as the chip select input (active low). This pin is internally pulled up by a ~20 k resistor to the voltage selected by the IO_VDD_SEL register bit. Notes: 1. I = Input, O = Output, P = Power. 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings. 3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK low. 44 Rev. 1.0 Si5341/40 Table 18. Pin Descriptions (Continued) Pin Number Pin Type1 Function 33 O Interrupt2 This pin is asserted low when a change in device status has occurred. This interrupt has a push pull output and should be left unconnected when not in use. 6 17 I Device Reset2 Active low input that performs power-on reset (POR) of the device. Resets all internal logic to a known state and forces the device registers to their default values. Clock outputs are disabled during reset. This pin is internally pulled up with a ~20 k resistor to the voltage selected by the IO_VDD_SEL bit. OE 11 12 I Output Enable2 This pin disables all outputs when held high. This pin is internally pulled low and can be left unconnected when not in use. LOL 47 -- O Loss Of Lock2 This output pin indicates when the DSPLL is locked (high) or outof-lock (low). An external pull up or pull down is not needed. -- 27 O Loss Of Lock This output pin indicates when the DSPLL is locked (high) or outof-lock (low). An external pull up or pull down is not needed. The voltage on the VDDS pin sets the VOH/VOL for this pin. See Table 6. LOS_XAXB -- 28 O Loss Of Signal This output pin indicates a loss of signal at the XA/XB pins. SYNC 5 -- I Output Clock Synchronization2 An active low signal on this pin resets the output dividers for the purpose of re-aligning the output clocks. For a tighter alignment of the clocks, a soft reset should be applied. This pin is internally pulled up with a ~20 k resistor to the voltage selected by the IO_VDD_SEL bitand can be left unconnected when not in use. FDEC 25 -- I Frequency Decrement Pin2 This pin is used to step-down the output frequency of a selected output. The affected output driver and its frequency change step size is register configurable. This pin is internally pulled low with a ~20 k resistor and can be left unconnected when not in use. Pin Name Si5341 Si5340 INTR 12 RST Control/Status Notes: 1. I = Input, O = Output, P = Power. 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings. 3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK low. Rev. 1.0 45 Si5341/40 Table 18. Pin Descriptions (Continued) Pin Number Pin Type1 Function -- I Frequency Increment Pin2 This pin is used to step-up the output frequency of a selected output. The affected output and its frequency change step size is register configurable. This pin is internally pulled low with a ~20 k resistor and can be left unconnected when not in use. 3 3 I IN_SEL1 4 37 I Input Reference Select2 The IN_SEL[1:0] pins are used in the manual pin controlled mode to select the active clock input as shown in Table 15. These pins are internally pulled up with a ~20 k resistor to the voltage selected by the IO_VDD_SEL bit and can be left unconnected when not in use. RSVD 20 -- -- 21 -- -- 55 -- -- 56 -- -- -- 22 -- No Connect These pins are not connected to the die. Leave disconnected. 32 21 P 46 32 Core Supply Voltage The device core operates from a 1.8 V supply. A 1.0 f bypass capacitor is recommended 60 39 -- 40 13 8 P -- 9 P Core Supply Voltage 3.3 V This core supply pin requires a 3.3 V power source. A 1.0 f bypass capacitor is recommended. -- 26 P Pin Name Si5341 Si5340 FINC 48 IN_SEL0 NC Reserved These pins are connected to the die. Leave disconnected. Power VDD VDDA VDDS Status Output Voltage The voltage on this pin determines the VOL/VOH on LOL and LOS_XAXB status output pins. A 0.1 f to 1.0 f bypass capacitor is recommended. Notes: 1. I = Input, O = Output, P = Power. 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings. 3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK low. 46 Rev. 1.0 Si5341/40 Table 18. Pin Descriptions (Continued) Pin Number Pin Type1 Function 18 P 26 23 P VDDO2 29 29 P VDDO3 33 34 P VDDO4 36 -- P Output Clock Supply Voltage 0-9 Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTx, OUTx outputs. See the Si5341/40 Family Reference Manual for power supply filtering recommendations. Leave VDDO pins of unused output drivers unconnected. An alternate option is to connect the VDDO pin to a power supply and disable the output driver to minimize current consumption. VDDO5 40 -- P VDDO6 43 -- P VDDO7 49 -- P VDDO8 52 -- P VDDO9 57 -- P Pin Name Si5341 Si5340 VDDO0 22 VDDO1 GND PAD P Ground Pad This pad provides electrical and thermal connection to ground and must be connected for proper operation. Use as many vias as practical and keep the via length to an internal ground plan as short as possible. Notes: 1. I = Input, O = Output, P = Power. 2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings. 3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK low. Rev. 1.0 47 Si5341/40 8. Ordering Guide Si534fg-Rxxxxx-GM Timing product family f = Clock generator family member (1, 0) g = Device grade (A, B) Product Revision* Custom ordering part number (OPN) sequence ID** Package, ambient temperature range (QFN, -40C to +85C) *See Ordering Guide table for current product revision ** 5 digits; assigned by ClockBuilder Pro Ordering Part Number (OPN) Number of Input/Output Clocks Output Clock Frequency Range (MHz) Frequency Synthesis Mode Package Temperature Range 64-Lead 9x9 QFN -40 to 85 C 44-Lead 7x7 QFN -40 to 85 C Evaluation Board -- Si5341 Si5341A-B-GM1,2 Si5341B-B-GM 0.0001 to 712.5 MHz 1,2 Si5341C-B-GM 1,2 4/10 Si5341D-B-GM1,2 0.0001 to 350 MHz 0.0001 to 712.5 MHz 0.0001 to 350 MHz Integer and fractional mode Integer mode only Si5340 Si5340A-B-GM1,2 Si5340B-B-GM1,2 Si5340C-B-GM1,2 0.0001 to 712.5 MHz 4/4 Si5340D-B-GM1,2 0.0001 to 350 MHz 0.0001 to 712.5 MHz 0.0001 to 350 MHz Integer and fractional mode Integer Only Si5341/40-EVB Si5341-EVB Si5340-EVB -- -- -- Notes: 1. Add an R at the end of the OPN to denote tape and reel ordering options. 2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuilder Pro software utility. 3. Custom part number format is: e.g., Si5341A-Bxxxxx-GM, where "xxxxx" is a unique numerical sequence representing the preprogrammed configuration. 4. See Sections 5.9 and 5.10 for important notes about specifying a preprogrammed device to use features or device register settings not yet available in CBPro. 48 Rev. 1.0 Si5341/40 9. Package Outlines 9.1. Si5341 9x9 mm 64-QFN Package Diagram Figure 19 illustrates the package details for the Si5341. Table 19 lists the values for the dimensions shown in the illustration. Figure 19. 64-Pin Quad Flat No-Lead (QFN) Table 19. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 9.00 BSC 5.10 5.20 e 0.50 BSC E 9.00 BSC 5.30 E2 5.10 5.20 5.30 L 0.30 0.40 0.50 aaa -- -- 0.15 bbb -- -- 0.10 ccc -- -- 0.08 ddd -- -- 0.10 eee -- -- 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 49 Si5341/40 9.2. Si5340 7x7 mm 44-QFN Package Diagram Figure 20 illustrates the package details for the Si5340. Table 20 lists the values for the dimensions shown in the illustration. Figure 20. 44-Pin Quad Flat No-Lead (QFN) Table 20. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 7.00 BSC 5.10 5.20 e 0.50 BSC E 7.00 BSC 5.30 E2 5.10 5.20 5.30 L 0.30 0.40 0.50 aaa -- -- 0.15 bbb -- -- 0.10 ccc -- -- 0.08 ddd -- -- 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 50 Rev. 1.0 Si5341/40 10. PCB Land Pattern Figure 21 illustrates the PCB land pattern details for the devices. Table 21 lists the values for the dimensions shown in the illustration. Si5341 Si5340 Figure 21. PCB Land Pattern Rev. 1.0 51 Si5341/40 Table 21. PCB Land Pattern Dimensions Dimension Si5341 (Max) Si5340 (Max) C1 8.90 6.90 C2 8.90 6.90 E 0.50 0.50 X1 0.30 0.30 Y1 0.85 0.85 X2 5.30 5.30 Y2 5.30 5.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 8. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 52 Rev. 1.0 Si5341/40 11. Top Marking Si5341gRxxxxx-GM YYWWTTTTTT e4 TW Si5340gRxxxxx-GM YYWWTTTTTT TW e4 64-QFN 44-QFN Figure 22. Si5341-40 Top Markings Table 22. Si5341-40 Top Marking Explanation Line Characters Description 1 Si5341gSi5340g- Base part number and Device Grade for Low Jitter, Any-Frequency, 10output Clock Generator. Si5341: 10-output, 64-QFN Si5340: 4-output, 44-QFN g = Device Grade (A, B, C, D). See "8. Ordering Guide" on page 48 for more information. - = Dash character. 2 Rxxxxx-GM R = Product revision. (See ordering guide for current revision). xxxxx = Customer specific NVM sequence number. Optional NVM code assigned for custom, factory pre-programmed devices. Characters are not included for standard, factory default configured devices. See Ordering Guide for more information. -GM = Package (QFN) and temperature range (-40 to +85 C) 3 YYWWTTTTTT YYWW = Characters correspond to the year (YY) and work week (WW) of package assembly. TTTTTT = Manufacturing trace code. 4 Circle w/ 1.6 mm (64-QFN) Pin 1 indicator; left-justified or 1.4 mm (44-QFN) diameter e4 TW Pb-free symbol; Center-Justified TW = Taiwan; Country of Origin (ISO Abbreviation) Rev. 1.0 53 Si5341/40 12. Device Errata Please log in or register at www.silabs.com to access the device errata document. 54 Rev. 1.0 Si5341/40 DOCUMENT CHANGE LIST Revision 0.9 to Revision 0.95 Removed advanced product information revision history. Updated Ordering Guide and changed references to revision B Updated parametric Tables 2,3,5,6,7,8 to reflect production characterization Updated terminology to align with ClockBuilder Pro software 9: I2C data hold time specification corrected to 100 ns from 5 s Table Revision 0.95 to Revision 1.0 General updates to typos in Tables 2,3,4,5,8,11, and 12. Changed Vin_diff minimum value in Table 3 to be the same as Vin_se. Added crosstalk spec for Si5340 to Table 5. Changed the schematic for AC Test Configuration in Table 7. Changed the PLL lock time in Table 8. Added a spec to Table 8 for the VCO frequency range. Changed the "Delay Time Between Chip Selects" to be 2.0 clock periods. Changed Note 2 in Table 12 as only 25 and 48- 54 Mhz crystals are supported. the timing specs for I2C and SPI. Added a 1.0 f bypass capacitor recommendation to be consistent with the reference manual. Updated output-to-output skew spec. Changed Rev. 1.0 55 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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