Rev. 1.0 6/14 Copyright © 2014 by Silicon Labo ratories Si501/2/3
Si501/2/3
32 KHZ–100 MHZ CMEMS OSCILLATOR
Features
Applications
Description
The Si501/2/3 CMEMS oscillator family provides monolithic, MEMS-based IC
replacements for traditional crystal oscillators. Silicon Laboratories’ CMEMS
technology combines standard CMOS + MEMS in a single, monolithic IC to provide
integrated, high-quality and high-reliability oscillators. Each device is factory tested
and configured for guaranteed performance to data sheet specifications across
voltage, process, temperature, shock, vibration, and aging.
Additional information on the Si50x CMEMS oscillator architecture and CMEMS
technology is available in white papers on the Silicon Labs website at
www.siliconlabs.com/cmems.
Functional Block Diagram
Wide frequency range: 32 kHz to
100 MHz
Contact Silicon Labs for
frequencies above 100 MHz
Si501 single frequency w/ OE
Si502 dual frequency w/ OE/FS
Si503 quad frequency w/ FS
±20/30/50 ppm frequency stability
including 10-year aging
LVCMOS output
Low period jitter
Low power
Continuous supply voltage range:
+1.71 V to +3.63 V
User selectable tRise/tFall options
Glitchless start and stop
Excellent short-term stability, long-
term aging
Industry standard footprints:
2x2.5, 2.5x3.2, 3.2x5 mm
RoHS compliant, Pb-free
Short lead times: <2 weeks
–20 to +70 °C: Extnd commercial
–40 to +85 °C: Industrial
The Si50x family also includes the
Si504 for in-circuit programmability
(See the Si504 Data Sheet)
Storage (SATA/SAS/PCIe)
General purpose processors
Industrial controllers
Embedded controllers
Motor control
Flow control
Office/Home automation
IP cameras/surveillance
Display and control panels
Outdoor electronics
Multi-function printers
Office equipment
Temp Comp /
Digital
Control
NVM
M
RAM
M
ROM
Temperature
Sensor ÷
VCO
CLK
GND
Digital
Frequency-Locked
Loop (FLL)
Resonator
& Oscillator
LDO
VDD
FS/OE
Patents pending
Ordering Information:
See Section 5.
Pin Assignments
VDD
FS/OE
GND CLK
1
23
4
Si501/2/3
2 Rev. 1.0
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Si501/2/3 Typical Applications Circuits, AC Waveforms, and Functional
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si501/2 Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Si501/2 AC Waveforms and Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3. Si503 Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.4. Si503 AC Waveform and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1. OE Enable and Disable States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2. Output Rise and Fall settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1. Si501 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.2. Si502 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.3. Si503 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6. Package Dimensions and Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.1. Package Outline: 3.2 x 5 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.2. Package Outline: 2.5 x 3.2 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.3. Package Outline: 2 x 2.5 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.1. 3.2 x 5 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.2. 3.2 x 5 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.3. 2.5 x 3.2 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.4. 2.5 x 3.2 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.5. 2 x 2.5 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7.6. 2 x 2.5 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Si501/2/3
Rev. 1.0 3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
VDD=1.71 to 3.63 V, TA= –40 to 85 C, unless otherwise specified
Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage1VDD 1.71 — 3.63 V
Supply Current IDD1 CL=4 pF, 3.3 VDD, FCLK=1.0 MHz, low
power option
—1.72.5mA
CL=4 pF, 3.3 VDD, FCLK=100 MHz, low
power option
—5.36.5mA
CL=4 pF, 3.3 VDD, FCLK=1.0 MHz, low
jitter option
—3.94.9mA
CL=4 pF, 3.3 VDD, FCLK=100 MHz, low
jitter option
—7.68.9mA
Static Supply
Current
IDD2 Mode=Stop2, low power option
FCLK=1 MHz
—1.72.5mA
Mode=Stop2, low jitter option
FCLK=1 MHz
—3.94.9mA
Mode=Doze2—670890µA
Mode=Sleep2—0.31µA
Input High Voltage VIH FS/OE pin 0.70 x
VDD
——V
Input Low Voltage VIL FS/OE pin — — 0.30 x
VDD
V
OE Internal Pull
Resistor
RIOrdering option 40 50 60 k
Operating
Temperature
TAExtended commercial grade –20 — 70 C
Industrial grade –40 — 85 C
Notes:
1. The supply voltage range is continuous from 1.71 to 3.63 V.
2. Si501 and Si502 only. Si503 has FS only and does not support Stop, Doze, or Sleep. See Section 3. Functional
Description for more information on operational modes.
Si501/2/3
4 Rev. 1.0
Table 2. Output Clock Characteristics
VDD=1.71 to 3.63 V, TA= –40 to 85 C, unless otherwise specified.
Parameter Symbol Test Condition Min Typ Max Unit
Frequency
Range
FCLK 0.032 — 100 MHz
Clock Period TCLK 1/FCLK 31,250 — 10 ns
Total Stability1FSTAB –20 — +20 ppm
–30 — +30 ppm
–50 — +50 ppm
Initial
Accuracy
FIMeasured at 25 C at the time of
shipping
— ±2 — ppm
Startup Time2TSU From VDD crossing 1.71 V to first
clock output
—2.5 4 ms
Resume
Time3,4
TRUN From Sleep mode — 2.5 5 ms
From Doze mode — 1.7 2.55 ms
From Stop mode5— — 1.5 x TCLK +
35
ns
Output Disable
Time3,4
TDTo Sleep/Doze mode, from output
running
—— 225 µs
To Stop, from output running — — 1.5 x TCLK +
35
ns
Frequency
Update
Time4,6
TNEW_FREQ —— 5 ms
Notes:
1. Orderable option. Stability budget consists of initial tolerance, operating temperature range, rated power supply voltage
change, load change, 10-year aging, shock, and vibration.
2. Hold FS/OE high (strong or weak) during powerup for fastest time to clock.
3. Si501 and Si502 only. Si503 has FS only and does not support Stop, Doze, or Sleep.
4. Asserted FS/OE actions must be held stable for the maximum duration of the invoked FS/OE event (e.g., TRUN,
TNEW_FREQ, TD, etc).
5. If the Si502 frequency is switched while the device is in Stop mode, the frequency prior to Stop will be output briefly until
the glitchless switch to the other frequency. Doze mode and Sleep mode do not have this behavior.
6. Si502 and Si503 only. Si501 is a single frequency device with OE only.
Si501/2/3
Rev. 1.0 5
Table 3. Output Clock Levels and Symmetry
VDD = 1.71 to 3.63 V, TA= –40 to 85 C unless otherwise indicated.
Parameter Symbol Test Co ndition Min Typ Max Unit
Output High Voltage VOH 1st ordering option code: A and H
IOH=–4 mA
0.90 x
VDD
—— V
Output Low Voltage VOL 1st ordering option code: A and H
IOH=+4 mA
— — 0.10 x
VDD
V
Rise/Fall
Time1
tRise
/tFall
1st ordering option code2: A and H
Z0=25 @ 3.3 V
0.4 0.721.2 ns
1st ordering option code: B and J
Z0= 50 @ 3.3 V
11.31.6ns
1st ordering option code: C and K
Z0= 50 @ 2.5 V
11.31.6ns
1st ordering option code: D and L
Z0 = 50 @ 1.8 V
11.31.6ns
1st ordering option code: E and M
Z0= 110 @ 3.3 V
234ns
1st ordering option code: F and N
Z0=220 @ 3.3 V3
457ns
1st ordering option code: G and P
Z0=440 @ 3.3 V3
7811ns
Duty Cycle DC Drive strength selected such that
tRise/tFall (20% to 80%)<10% of
period
45 50 55 %
Notes:
1. CL=15 pF, tRise/tFall (20% to 80%), 3.3 V, unless otherwise stated.
2. Recommended series termination resistor (RS) = 24.9 for Z0=50 
3. Ordering options F, N, G, and P are not recommended for FCLK > 5 MH2.
Si501/2/3
6 Rev. 1.0
Table 4. Output Clock Jitter and Phase Noise
VDD = 1.71 to 3.63 V, TA= –40 to 85 C unless otherwise indicated.
Parameter Symbol Test Condition Min Typ Max Unit
Cycle-to-Cycle Jitter JCCPP 100 MHz, Low Jitter Option
1st ordering option code: H
— 14 25 ps pk-pk
100 MHz, Low Power Option
1st ordering option code: A
— 16 26 ps pk-pk
Period Jitter JPRMS 100 MHz, Low Jitter Option
1st ordering option code: H
— 1 1.6 ps rms
100 MHz, Low Power Option
1st ordering option code: A
— 1.3 1.9 ps rms
Period Jitter Pk-Pk JPPKPK Low Jitter Option
10k samples
1st ordering option code: H
—9 13ps pk-pk
Low Power Option
10k samples
1st ordering option code: A
— 10 16 ps pk-pk
Phase Jitter175 MHz
FOFFSET=900 kHz to 7.5 MHz
Low Jitter Option
1st ordering option code: H
— 1 1.3 ps rms
75 MHz
FOFFSET=900 kHz to 7.5 MHz
Low Power Option
1st ordering option code: A
— 2.5 3.2 ps rms
Notes:
1. Integrated phase jitter exceeds the requirements of some high-performance data communications systems. See
AN783 for additional information.
Si501/2/3
Rev. 1.0 7
Table 5. Environmental Compliance and Package Information
Parameter Test Condition
Mechanical Shock MIL-STD-883, Method 2002, Cond B. (1,500 g)
Mechanical Shock High g MIL-STD-883, Method 2002, Cond E. (10,000 g)
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 2003
Temperature Cycle JESD22, Method A104
Resistance to Solder Heat MIL-STD-883, Method 2036
Contact Pads Gold over Nickel/Palladium
Table 6. Thermal Conditions
Parameter Symbol Test Condition Value Unit
Thermal Impedance JA 3.2x5 mm, still air 187
°C/W
2.5x3.2 mm, still air 239
2x2.5 mm, still air 241
Table 7. Absolute Maximum Limits1
Parameter Symbol Rating Unit
Maximum Operating Temperature TMAX 85 °C
Storage Temperature TS–55 to +125 °C
Supply Voltage VDD –0.5 to +3.8 V
Input Voltage VIN –0.5 to VDD
+0.3V
V
ESD Sensitivity (JESD22-A114) HBM 2000 V
ESD Sensitivity (CDM) CDM 500 V
Soldering Temperature (Pb-free profile)2TPEAK 260 °C
Soldering Time at TPEAK
(PB-free profile)2
TP20–40 s
Junction Temperature TJ125 °C
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
Si501/2/3
8 Rev. 1.0
2. Si501/2/3 Typical Applications Circuits, AC Waveforms, and Functional
Descriptions
The Si501/2/3 family has various applications circuits and ac waveforms depending on the selected device and
ordering configuration options. Pay careful attention when reading the following section to be sure you refer to the
correct diagrams.
2.1. Si501/2 Applications Circuits
Figure 1. Si501/2 Applications Circuit with Optional Output Series Resistor
Note: The dotted line box in Figure 1 is an optional component depending on tRise/tFall configuration option. This diagram
applies to all Si50x product drive strength configuration options. See Table 3 for RS recommendations. See Section 5.
"Ordering Guide” for configuration options.
Note: The dotted line boxes in Figure 2 show resistor options depending on MCU pull-up resistors configuration and the
Si501/2 internal resistor configuration options. See Section 5. "Ordering Guide” for configuration options. Users should
design only one of the pin 1 dotted-line options. The series resistor (RS) on pin 3 is also optional. See Table 3 for RS
recommendations.
Figure 2. Si501/2 Applications Circuit with MCU Configuration Options
GND CLK
1
2 3
4
Z0= 50
CLK
VDD
Si501/2
0.1 F
RS
VDD
RUP
FS/OE VDD
FS/OE
VDD
1
RUP
MCU
OUTPUT
DRIVER
VDD
~50K
RUP
Si501/2
4
VDD
0.1F
GND 2CLK
3
Z0=50
CLK
VDD
RS
VDD
Si501/2/3
Rev. 1.0 9
2.2. Si501/2 AC Waveforms and Functional Descriptions
Figure 3. Si501/2 Power On Time (refer to Table 2)
Figure 4. Si501/2 AC Waveform (refer to Table 2)
Table 8. Si502 FS/OE States and Resistor Values
FS/OE Pin State RUP Clock Output
Strong High 0 RUP 1kFrequency 1
Weak High 20 kRUP 200 kFrequency 2
Low — Hi-Z
Notes:
1. If the Si502 internal pull-up resistor configuration option is not selected, an
MCU internal pull-up resistor or an external pull-up resistor should be used.
2. The parallel combination of all pull-up resistors on the FS/OE pin, including
the optional internal device pull-up resistor must be > 20 kto select the
Weak High state.
3. If the Si502 internal pull-up resistor is enabled with no other external FS/OE
connections, the FS/OE state will be detected as `Weak High' which selects
the Frequency 2 output by default.
Supply Voltage (VDD)
CLK
TSU
VDD=1.71V
FS/OE
T
D
T
RUN
CLK
Hi-Z Hi-Z
T
NEW_ FREQ
R
UP
<1k:R
UP
<1k:R
UP
>20k:
Si501/2/3
10 Rev. 1.0
2.3. Si503 Applications Circuits
Note: The dotted line boxes show optional components depending on tRise/tFall and internal pull up resistor configuration
options. See Section 5. "Ordering Guide” for configuration options. See Table 3 for RS recommendations.
Figure 5. Si503 Applications Circuit with Configuration Options
Table 9. Si503 Frequency Select with External Resistor Options
FS/OE Pin State RUP RDOWN Clock Output
Strong High 0 RUP 1kDo not populate Frequency 1
Weak High 20 kRUP 200 kDo not populate Frequency 2
Weak Low Do not populate 20 kRDOWN 200 kFrequency 3
Strong Low Do not populate 0 RDOWN 1kFrequency 4
Note: If the Si503 internal pull-up resistor is enabled with no other external FS/OE connections, the FS/OE state will
be detected as `Weak High' which selects the Frequency 2 output by default.
Si501/2/3
Rev. 1.0 11
Note: The dotted line boxes in Figure 6 show resistor options depending on MCU pull-up resistors configuration and the Si503
internal resistor configuration options. See Section 5. "Ordering Guide” for configuration options. Users should design
only one of the pin 1 dotted-line options. The series resistor (RS) on pin 3 is also optional. See Table 3 for RS recommen-
dations.
Figure 6. Si503 Applications Circuit with MCU and Configuration Options
2.4. Si503 AC Waveform and Functional Description
Figure 7. Si503 Power On Time (refer to Table 2)
Table 10. Si503 Frequency Select
FS/OE Pin State MCU Output 1 MCU Output 2 Clock Output
Strong High High Hi-Z Frequency 1
Weak High Hi-Z Hi-Z Frequency 2
Weak Low Hi-Z Low Frequency 3
Strong Low Low Hi-Z Frequency 4
Note: If the Si50x internal pull-up resistor is enabled with no other external OE connections, the OE state will be
detected as `Weak High' which selects the Frequency 2 output by default.
FS/OE
VDD
1
MCU
~50K
Si503
4
VDD
0.1 F
GND 2
OUTPUT
DRIVER
6K
OUTPUT
DRIVER
RUP
VDD
RUP
VDD
CLK
3
Z0=50
CLK
VDD
RS
VDD
1.71V
VDD
TSU
Si501/2/3
12 Rev. 1.0
Figure 8. Si503 AC Waveform (refer to Table 2)
3. Functional Description
The Si50x series oscillator family includes four base devices. All devices are configurable according to the Section
5. "Ordering Guide”. The four devices each support a single clock output frequency at any one time and are
segmented according to the number of clock frequencies they store in on-chip memory.
The Si501 supports a single stored frequency, enabled with the OE functionality. The Si502 stores two frequencies
that can be selected with FS and enabled/disabled with OE functionality. The Si503 stores four frequencies,
selected with FS functionality. The Si503 does not support OE functionality. The Si501/2/3 are covered in this data
sheet.
The Si504 is a programmable oscillator, controlled through a single pin interface (C1D). It is covered in its own
Si504 data sheet available at www.siliconlabs.com/cmems.
All devices in the Si50x CMEMS series employ a cost-optimized, power-efficient, digital FLL architecture to
produce a highly accurate and stable output clock from a passively compensated MEMS resonator reference
frequency.
The architecture uses the MEMS resonator as its reference frequency along with a divided signal from an on-chip,
digitally-controlled VCO to drive a frequency comparator for the FLL’s digital loop filter. The digital loop filter
accumulates and further processes the frequency error values to produce the target output frequency.
The architecture also uses a high-resolution, low-noise temperature sensor and temperature compensation
algorithm to offset any temperature drift of the passively compensated MEMS resonator. Each device is calibrated
for temperature and MEMS-resonator frequency pairs and derives a device-specific compensation polynomial. As
the temperature changes, this compensation circuitry offsets any frequency drift.
This tightly coupled system is extremely accurate and fast because the MEMS resonator and CMOS compensation
circuitry are in a single, monolithic chip, and, therefore, separated by a few microns.
The complete system process occurs many thousands of times per second, providing excellent frequency
accuracy and stability across temperature changes, including any fast temperature transients. The oscillator also
supports a low-power version that reduces the sampling cycle to a longer period, reducing power consumption for
applications that can tolerate relaxed jitter specifications of approximately 1 ps RMS to reduce power by
approximately 2-3 mA. See Table 1 for exact specifications.
3.1. OE Enable and Disable States
The Si50x CMEMS series supports four operational output states via the FS/OE configuration pin. If enabled, the
Si50x is in Run mode, the clock is output and power is as specified in Table 1. The disable modes are Stop, Sleep,
and Doze. Each of these states has a different power consumption profile as specified in Table 1.
3.1.1. Stop Mode
The Si50x output in Stop mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Stop mode disables
the output driver, but the digital core and MEMS resonator remain enabled for fast transition to Run mode. The
output is stopped and held at High-Z after completing the last cycle glitch-free. No other power saving measure is
taken in Stop mode.
FS
CLK Hi-Z Hi-Z
TNEW_ FREQ
TNEW_ FREQ
RUP >20k:RUP <1k:
RDOWN >20k:
Si501/2/3
Rev. 1.0 13
3.1.2. Doze Mode
The Si50x output in Doze mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Doze mode disables
the output driver, the VCO, and the MEMS resonator, but the digital core remains enabled. The output is stopped
and is held at High-Z after completing the last cycle glitch-free.
3.1.3. Sleep Mode
The Si50x output in Sleep mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Sleep mode disables
power to all circuitry except for low-leakage circuitry that retains the last device configuration. The output is stopped
and is held at High-Z after completing the last cycle glitch-free.
3.2. Output Rise and Fall Settings
The Si50x clock output is programmable. This enables reduction of electromagnetic interference (EMI) radiation
from the clock output. The amount of EMI reduction is dependent on the output frequency, the harmonic of interest,
and the board layout. Lab results using a 50 MHz FOUT and changing the clock tRise/tFall time from 0.7 ns to 8 ns
show up to 14 dB of EMI reduction.
The tRise/tFall feature also allows the Si50x to match competing devices’ rise and fall times. Crystal oscillator
tRise/tFall behavior is largely dependent on the supply voltage. In crystal-based oscillators, a higher supply voltage
will generally drive a more rapid tRise/tFall time. The Si50x configuration options allow the user to match the
tRise/tFall to the supply voltage. The Si50x also provides a specified tRise/tFall with a given supply voltage and a
50 trace impedance. See Table 3 for Si50x tRise/tFall specifications.
4. Pin Descriptions
Figure 9. Si501/2/3
Table 11. Pin Description
Pin Name Function
1 FS/OE FS=Frequency Select. Si502 and Si503 only.
OE=Output Enable. Si501 and Si502 only.
2 GND Ground.
3 CLK Output clock.
4V
DD Power supply.
Bypass with a 0.1F capacitor placed as close to the VDD pin as possible.
VDD
FS/OE
GND CLK
1
23
4
Si501/2/3
14 Rev. 1.0
5. Ordering Guide
The Si50x family of CMEMS oscillators are highly configurable. Each orderable part number must be specified
according to the guidelines below. Each customized part’s performance is guaranteed to operate within the data
sheet specifications. An on-line configuration and ordering tool is available at www.siliconlabs.com/cmems.
5.1. Si501 Ordering Guide and Part Number Synt ax
Figure 10. Si501 Part Number Syntax
501 J C A ͲͲͲͲͲͲͲD A G
Ppm
A±50
B±30
C±20
Package
Dimension
B3.2x5mm4
C2.5x3.2mm
D2x2.5mm
R
Temp
Range
FͲ20to70°C
GͲ40to85°C
Reel
RReel
CutTape
Frequency
Code Description
Mxxxxxx fOUT <1MHz
xMxxxxx1MHzчfOUT <10MHz
xxMxxxx10MHzчfOUT <100MHz
100M000fOUT =100MHz
xxxxxx 6Ͳdigitcodefor>6decimalresolution
Revision
OE
High
OE
Low
Internal
PullResistor
AEnable Stop PullͲUp
BEnable Doze PullͲUp
CEnable Sleep PullͲUp
DStop Enable PullͲDown
EDoze Enable PullͲDown
FSleep Enable PullͲDown
GEnable Stop None
HEnable Doze None
JEnable Sleep None
KStop Enable None
LDoze Enable None
MSleep Enable None
VDD Jittervs
Power
TYP
TR/TF
A1.7Ͳ3.6
Low
Power
0.7ns1
B3.3V 1.3ns2
C2.5V 1.3ns2
D1.8V 1.3ns2
E1.7Ͳ3.6 3ns3
F1.7Ͳ3.6 5ns3
G1.7Ͳ3.6 8ns3
H1.7Ͳ3.6
Low
Jitter
0.7ns1
J3.3V 1.3ns2
K2.5V 1.3ns2
L1.8V 1.3ns2
M1.7Ͳ3.6 3ns3
N1.7Ͳ3.6 5ns3
P1.7Ͳ3.6 8ns3
OPN
Prefix Description
501 Singlefrequency
502 Dual frequency
503 Quad frequency
504 Anyfrequency
Note:
1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2.
2. Series termination resistor is not needed for this configuration. Output impedance is 50 for the indicated supply
condition.
3. Series termination resistor is not needed for this configuration. Reduced EMI setting.
4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm
footprint.
Si501/2/3
Rev. 1.0 15
5.2. Si502 Ordering Guide and Part Number Synt ax
Figure 11. Si502 Part Number Syntax
502 J C A Ͳ Ͳ Ͳ Ͳ Ͳ Ͳ Ͳ D A G
Ppm
A±50
B±30
C±20
Package
Dimension
B3.2x5mm4
C2.5x3.2mm
D2x2.5mm
R
Temp
Range
FͲ20to70°C
GͲ40to85°C
Reel
RReel
CutTape
Frequency
Code Description
xxxxxx 6ͲdigitcodefromSilicon Labs
Revision
OE
Low5
Internal
PullResistor
AStop PullͲUp
BDoze PullͲUp
CSleep PullͲUp
DStop None
EDoze None
FSleep None
VDD Jittervs
Power
TYP
TR/TF
A1.7Ͳ3.6
Low
Power
0.7ns1
B3.3V 1.3ns2
C2.5V 1.3ns2
D1.8V 1.3ns2
E1.7Ͳ3.6 3ns3
F1.7Ͳ3.6 5ns3
G1.7Ͳ3.6 8ns3
H1.7Ͳ3.6
Low
Jitter
0.7ns1
J3.3V 1.3ns2
K2.5V 1.3ns2
L1.8V 1.3ns2
M1.7Ͳ3.6 3ns3
N1.7Ͳ3.6 5ns3
P1.7Ͳ3.6 8ns3
OPN
Prefix Description
501 Singlefrequency
502 Dual frequency
503 Quad frequency
504 Anyfrequency
Note:
1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2.
2. Series termination resistor is not needed for this configuration. Output impedance is 50 for the indicated supply
condition.
3. Series termination resistor is not needed for this configuration. Reduced EMI setting.
4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm
footprint.
5. The Si502 OE pin has three (3) states: OE High = Freq 1; OE Weak High = Freq 2; OE Low is configurable.
Si501/2/3
16 Rev. 1.0
5.3. Si503 Ordering Guide and Part Number Synt ax
Figure 12. Si503 Part Number Syntax
503 J C A ͲͲͲͲͲͲͲD A G
Ppm
A±50
B±30
C±20
Package
Dimension
B3.2x5mm4
C2.5x3.2mm
D2x2.5mm
R
Temp
Range
FͲ20to70°C
GͲ40to85°C
Reel
RReel
CutTape
Frequency
Code Description
xxxxxx 6ͲdigitcodefromSiliconLabs
Revision
Internal
PullResistor
APullͲUp
BNone
VDD Jittervs
Power
TYP
TR/TF
A1.7Ͳ3.6
Low
Power
0.7ns1
B3.3V 1.3ns2
C2.5V 1.3ns2
D1.8V 1.3ns2
E1.7Ͳ3.6 3ns3
F1.7Ͳ3.6 5ns3
G1.7Ͳ3.6 8ns3
H1.7Ͳ3.6
Low
Jitter
0.7ns1
J3.3V 1.3ns2
K2.5V 1.3ns2
L1.8V 1.3ns2
M1.7Ͳ3.6 3ns3
N1.7Ͳ3.6 5ns3
P1.7Ͳ3.6 8ns3
OPN
Prefix Description
501 Singlefrequency
502 Dual frequency
503 Quad frequency
504 Anyfrequency
Note:
1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2.
2. Series termination resistor is not needed for this configuration. Output impedance is 50 for the indicated supply
condition.
3. Series termination resistor is not needed for this configuration. Reduced EMI setting.
4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm
footprint.
Si501/2/3
Rev. 1.0 17
6. Package Dimensions and Land Pat terns
6.1. Package Outline: 3.2 x 5 mm 4-pin DFN
Figure 13. 3.2 x 5 mm 4-pin DFN
6.2. Package Outline: 2.5 x 3.2 mm 4-pin DFN
Figure 14. 2.5 x 3.2 mm 4-pin DFN
6.3. Package Outline: 2 x 2.5 mm 4-pin DFN
Figure 15. 2 x 2.5 mm 4-pin DFN
4.00±0.15
3.20±0.15 1.20
0.90 Max
1.20
0.94
1.34
#1 #2
#4 #3
2.54
2.20
1.50
1.60
Note: Layout and pin-compatible with indu stry-s tand ard 3.2 x 5 mm footprint.
Top View
VDD CLK
GND
FS/OE
0.90 Max
0.90
0.70
0.90
1.20
2.50±0.15
3.20±0.15 2.20
1.90
1.20
1.40
#1 #2
#4 #3
Top View
1.90
1.50
1.10
1.00
0.65
1.00
0.55
0.70
2.50±0.15
2.00±0.15
0.90 Max
#1 #2
#4 #3
Top View
Si501/2/3
18 Rev. 1.0
7. Top Markings
7.1. 3.2 x 5 mm Top Marking
7.2. 3.2 x 5 mm Top Marking Explanation
Mark Method: Laser
Font Size: 0.60 mm
Right-Justified
Line 1 Marking: TTTTTT=Trace Code Manufacturing Code from the
Assembly Purchase Order form.
Line 2 Marking Circle=0.5 mm
Diameter
Left-Justified
Pin 1 Indicator
YY=Year
WW=Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the build date.
Si501/2/3
Rev. 1.0 19
7.3. 2.5 x 3.2 mm Top Marking
7.4. 2.5 x 3.2 mm Top Markin g E xpl a na t ion
Mark Method: Laser
Font Size: 0.50 mm
Right-Justified
Line 1 Marking: TTTTT=Trace Code Manufacturing Code from the
Assembly Purchase Order form.
Line 2 Marking: Circle=0.3 mm Diameter
Left-Justified
Pin 1 Indicator
Y=Year
WW=Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the build date.
Si501/2/3
20 Rev. 1.0
7.5. 2 x 2.5 mm Top Marking
7.6. 2 x 2.5 mm Top Marking Explanation
Mark Method: Laser
Font Size: 0.50 mm
Right-Justified
Line 1 Marking: TTTT=Trace Code Manufacturing Code from the
Assembly Purchase Order form.
Line 2 Marking: Circle=0.3 mm Diameter
Left-Justified
Pin 1 Indicator
Y=Year
WW=Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the build date.
Si501/2/3
Rev. 1.0 21
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Combined Si501/2/3 data sheets.
Modified title page.
Modified Table 2.
Modified Table 4.
Modified Section 2.
Modified Section 3.
Modified Section 4.
Modified Section 5.
Revision 0.3 to Revision 0.4
Modified title page.
Modified Table 1.
Modified Table 2.
Modified Table 3.
Modified Table 4.
Modified Table 5.
Modified Table 6.
Modified Table 7.
Modified Section 2.
Modified Section 4.
Modified Section 5.
Modified Section 6.
Revision 0.4 to Revision 0.41
Modified Table 4.
Revision 0.41 to Revision 0.7
Revised supported frequency range.
Added MIN/MAX figures to all relevant tables.
Revision 0.7 to Revision 0.71
Revised Table 3.
Revised Section 5.
Revision 0.71 to Revision 0.72
Revised Table 1.
Revised Table 2.
Revised Table 3.
Revised Table 5.
Modified Section 2.
Added Section 3.
Modified Section 4.
Revision 0.72 to Revision 1.0
Updated Table 3.
Updated Section 6.
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
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