February 2009 Rev 5 1/136
1
ST7LITEUS2
ST7LITEUS5
8-bit MCU with single voltage Flash memory, ADC, timers
Features
■Memories
– 1 Kbytes single-voltage Flash Program
memory with readout protection, ICP and
IAP)
10 K write/erase cycles guaranteed
data retention: 20 years at 55 °C
– 128 bytes RAM
■Clock, Reset and Supply management
– 3-level low-voltage supervisor (LVD) and
auxiliary voltage detector (AVD) for safe
power-on/off
– Clock sources: internal trimmable 8 MHz
RC oscillator, internal low power, low
frequency RC oscillator or external clock
– Five power saving modes: Halt, Auto-
wakeup from Halt, Active-halt, Wait, Slow
■Interrupt management
– 11 interrupt vectors plus TRAP and RESET
– 5 external interrupt lines (on 5 vectors)
■I/O ports
– 5 multifunctional bidirectional I/O lines
– 1 additional Output line
– 6 alternate function lines
– 5 high sink outputs
■2 Timers
– One 8-bit Lite timer (LT) with prescaler
including: watchdog, one realtime base and
one 8-bit input capture.
– One 12-bit auto-reload timer (AT) with
output compare function and PWM
■A/D Converter
– 10-bit resolution for 0 to VDD
– 5 input channels
■Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8x8 unsigned multiply instruction
■Development Tools
– Full hardware/software development
package
– Debug module
Plastic DIP8 SO8
150” DFN8 Plastic DIP16
Table 1. Device summary
Features ST7LITEUS2 ST7LITEUS5
Program memory 1 Kbytes
RAM (stack) 128 (64) bytes
Peripherals LT Timer w/ Wdg, AT Timer w/ 1 PWM
ADC - 10-bit
Operating Supply 2.4 to 3.3 V @fCPU=4 MHz, 3.3 to 5.5 V @fCPU=8 MHz
CPU Frequency up to 8 MHz RC
Operating Temperature -40 to +85 °C / -40 to 125 °C
Packages SO8 150”, Pastic DIP8, DFN8, Pastic DIP16(1)
1. For development or tool prototyping purposes only. Not orderable in production quantities.
www.st.com
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.2 In application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.2 Flash Write/Erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7.1 Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.4 Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.5 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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6.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.1 Main Clock Control/Status register (MCCSR) . . . . . . . . . . . . . . . . . . . . 30
6.3.2 RC Control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.3 System Integrity (SI) Control/status register (SICSR) . . . . . . . . . . . . . . 31
6.3.4 AVD Threshold Selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . 32
6.3.5 Clock Controller Control/Status register (CKCNTCSR) . . . . . . . . . . . . . 32
6.4 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.3 External Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5.1 Multiplexed I/O Reset Control register 1 (MUXCR1) . . . . . . . . . . . . . . . 37
6.5.2 Multiplexed I/O Reset Control register 0 (MUXCR0) . . . . . . . . . . . . . . . 37
7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3 Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3.1 External Interrupt Control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 41
7.3.2 External Interrupt Control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 42
7.4 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4.4 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.4 Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.4.1 Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.5 Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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8.5.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.3 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.6 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1 Lite timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.1.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.1.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.2 12-bit auto-reload timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.2.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.3 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.3.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.3.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1.1 Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.4 Indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.5 Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1.6 Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1.7 Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.1 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . 95
12.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . 96
12.3.4 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.4.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.4.2 Internal RC oscillator supply current characteristics . . . . . . . . . . . . . . 100
12.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
12.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.7 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
12.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 105
12.7.2 Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
12.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 106
12.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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12.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
12.8.2 Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 109
12.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14 Device configuration and ordering information . . . . . . . . . . . . . . . . . 123
14.1 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.1.1 OPTION BYTE 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
14.1.2 OPTION BYTE 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14.2 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
14.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.1 Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.2 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.4 Order codes for development and programming tools . . . . . . . . . . . . . 128
14.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
15 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Device pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. FLASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Clock register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. Multiplexed IO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 10. Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 11. Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 12. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 13. System integrity register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 14. Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 16. AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 17. DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 18. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 19. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 21. Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 22. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 23. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24. Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 25. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 26. Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 27. Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 28. Interrupt events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 29. Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 30. Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 31. Effect of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 32. Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 33. Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 34. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 35. Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 36. ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 37. Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 38. Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 86
Table 39. Instructions supporting direct, indexed, indirect and indirect indexed addressing modes . 87
Table 40. Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 41. ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 42. Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 43. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 44. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 45. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 46. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 47. Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 48. Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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Table 49. Voltage drop between AVD flag set and LVD reset generation . . . . . . . . . . . . . . . . . . . . . 96
Table 50. Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 51. Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 52. Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 53. Internal RC oscillator supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 54. On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 55. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 56. Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 57. RAM and Hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 58. Flash Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 59. EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 60. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 61. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 62. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 63. General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 64. Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 65. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 66. 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 67. ADC accuracy with VDD = 3.3 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 68. ADC accuracy with VDD = 2.7 to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 69. ADC accuracy with VDD = 2.4V to 2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 70. 8-lead very thin fine pitch dual flat no-lead package mechanical data . . . . . . . . . . . . . . . 118
Table 71. 8-pin plastic small outline package, 150-mil width, package mechanical
data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 72. 8-pin plastic dual in-line package, 300-mil width package mechanical data. . . . . . . . . . . 120
Table 73. 16-pin plastic dual in-line package, 300-mil width, package mechanical
data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 74. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 75. Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 76. LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 77. Definition of sector 0 size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 79. Supported order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 80. Development tool order codes for the ST7LITEUSx family . . . . . . . . . . . . . . . . . . . . . . . 129
Table 81. ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 82. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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List of figures
Figure 1. General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. 8-pin SO and Plastic DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. 8-pin DFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. 16-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Typical I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 14. Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 15. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 18. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 19. Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 20. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 21. Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 22. Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 23. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 24. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 25. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 26. AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 27. AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 28. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 29. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30. Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 31. Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 32. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 33. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 34. PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 35. PWM signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 36. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 37. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 38. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 39. fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . . . 95
Figure 40. Typical accuracy with RCCR=RCCR0 vs VDD= 2.4-6.0 V and temperature . . . . . . . . . . . 98
Figure 41. Typical accuracy with RCCR=RCCR1 vs VDD= 2.4-6.0V and temperature. . . . . . . . . . . . 98
Figure 42. Typical IDD in run mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 101
Figure 43. Typical IDD in WFI mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 101
Figure 44. Typical IDD in Slow, Slow-wait and Active-halt mode vs VDD & int
RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 45. IDD vs temp @VDD 5 V & int RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 46. IDD vs temp @VDD 5 V & int RC = 4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 47. IDD vs temp @VDD 5 V & int RC = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Figure 48. Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 49. Typical IPU vs. VDD with VIN=VSSl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 50. Typical VOL at VDD = 2.4 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 51. Typical VOL at VDD = 3 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 52. Typical VOL at VDD = 5 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 53. Typical VOL at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 54. Typical VOL at VDD = 3 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 55. Typical VOL at VDD = 5 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 56. Typical VDD-VOH at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 57. Typical VDD-VOH at VDD = 3 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 58. Typical VDD-VOH at VDD = 5 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 59. Typical VOL vs. VDD (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 60. Typical VDD-VOH vs. VDD (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 61. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 62. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 63. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 64. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 65. 8-lead very thin fine pitch dual flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 66. 8-pin plastic small outline package, 150-mil width package outline . . . . . . . . . . . . . . . . . 119
Figure 67. 8-pin plastic dual in-line package, 300-mil width package outline . . . . . . . . . . . . . . . . . . 120
Figure 68. 16-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 121
Figure 69. Option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ST7LITEUS2, ST7LITEUS5 Introduction
11/136
1 Introduction
The ST7LITEUS2 and ST7LITEUS5 are members of the ST7 microcontroller family. All ST7
devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set.
The ST7LITEUS2 and ST7LITEUS5 feature FLASH memory with byte-by-byte In-Circuit
Programming (ICP) and In-Application Programming (IAP) capability.
Under software control, the ST7LITEUS2 and ST7LITEUS5 can be placed in Wait, Slow, or
Halt mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
For easy reference, all parametric data are located in Section 12 on page 92.
The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD).
For a description of the DM registers, refer to the ST7 I2C protocol reference manual.
Figure 1. General block diagram
8-BIT CORE
ALU
ADDRESS AND DATA BUS
PA3 / RESET
PORT A
10-BIT ADC
with WATCHDOG
Internal
Clock
CONTROL
RAM
(128 Bytes)
PA5:0
(6 bits)
VSS
VDD POWER
SUPPLY
8-MHz RC OSC
LITE TIMER
MEMORY
12-BIT AUTO-
RELOAD TIMER
FLASH
1 KByte
LVD
AWU RC OSC
External
Clock
Pin description ST7LITEUS2, ST7LITEUS5
12/136
2 Pin description
Figure 2. 8-pin SO and Plastic DIP package pinout
1. HS: High sink capability.
2. eix : associated external interrupt vector
Figure 3. 8-pin DFN package pinout
1. HS: High sink capability.
2. eix : associated external interrupt vector
VDD
PA5 (HS) / AIN4 / CLKIN
PA3 / RESET
VSS
PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA2 (HS) / LTIC / AIN2
PA1 (HS) / AIN1 / ICCCLK
PA4 (HS) / AIN3/MCO
1
2
3
4
8
7
6
5
ei4
ei3
ei2
ei1
ei0
VDD
PA5 (HS) / AIN4 / CLKIN
PA3 / RESET
VSS
PA0 (HS) / AIN0 / ATPWM / ICCDATA
PA2 (HS) / LTIC / AIN2
PA1 (HS) / AIN1 / ICCCLK
PA4 (HS) / AIN3/MCO
1
2
3
4
8
7
6
5
ei4
ei3
ei2
ei1
ei0
ST7LITEUS2, ST7LITEUS5 Pin description
13/136
Figure 4. 16-pin package pinout
1. Reserved pins must be tied to ground.
2. The differences versus the 8-pin packages are listed below:
The I2C signals (ICCCLK and ICCDATA) are mapped on dedicated pins.
The RESET signal is mapped on a dedicated pin. It is not multiplexed with PA3.
PA3 pin is always configured as output. Any change on multiplexed IO reset control registers (MUXCR1
and MUXCR2) will have no effect on PA3 functionality. Refer to Section 6.5: Register description on
page 37.
Reserved 1)
VDD
ICCCLK
NC
VSS
PA1 (HS) / AIN1
PA0 (HS) / AIN0 / ATPWM
RESET
1
2
3
4
1
1
1
1
ei4
ei3
ei1
ei0
PA5 (HS) / AIN4 / CLKIN
PA4 (HS) / AIN3/MCO
NC
NC
ICCDATA
NC
PA2 (HS) / LTIC / AIN2
PA3
5
7
6
8
12
11
10
9
ei2
Pin description ST7LITEUS2, ST7LITEUS5
14/136
Legend/abbreviations for Tab le 2
Type: I = input, O = output, S = supply
In/Output level: CT= CMOS 0.3 VDD /0.7 VDD with input trigger
Output level: HS = High sink (on N-buffer only)
Port and control configuration
●Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
●Output: OD = open drain, PP = push-pull
The RESET configuration of each pin is shown in bold which is valid as long as the device is
in reset state.
Table 2. Device pin description
Pin
no. Pin name
Type
Level Port/control Main
function
(after
reset)
Alternate function
Input
Output
Input Output
float
wpu
int
ana
OD
PP
1V
DD S Main power supply
2 PA5/AIN4/CLKIN I/
O CTHS X ei4 X X X Port A5 Analog input 4 or External Clock
Input
3PA4/AIN3/MCO
I/
O CTHS X ei3 X X X Port A4 Analog input 3 or main clock output
4 PA3/RESET (1) O X X X Port A3 RESET(1)
5 PA2/AIN2/LTIC I/
O CTHS X ei2 X X X Port A2 Analog input 2 or Lite Timer Input
Capture
6PA1 /AI N1/
ICCCLK
I/
O CTHS X ei1 X X X Port A1
Analog input 1 or In Circuit
Communication Clock
Caution: During normal operation
this pin must be pulled-up, internally
or externally (external pull-up of 10k
mandatory in noisy environment).
This is to avoid entering I2C mode
unexpectedly during a reset. In the
application, even if the pin is
configured as output, any reset will
put it back in pull-up
7PA0 /AI N0/ ATPW
M/ICCDATA
I/
O CTHS X ei0 X X X Port A0
Analog input 0 or Auto-Reload
Timer PWM or In Circuit
Communication Data
8V
SS S Ground
1. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to
MUXCR0 and AAh to MUXCR1. For further details, please refer to Section 6.5 on page 37.
ST7LITEUS2, ST7LITEUS5 Register and memory map
15/136
3 Register and memory map
As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM
and 1 Kbyte of user program memory. The RAM space includes up to 64 bytes for the stack
from 00C0h to 00FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (FE00h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by option byte.
Warning: Memory locations marked as “Reserved” must never be
accessed. Accessing a reserved area can have unpredictable
effects on the device.
Figure 5. Memory map
1. See Table 3.
2. See Section 6.2 on page 28 for the description of RCCRHx registers.
3. See Ta ble 9.
0000h
RAM
Flash Memory
(1 Kbytes)
Interrupt & Reset vectors
(3)
HW registers(1)
0080h
007Fh
FFE0h
FFFFh
0100h
00FFh
Short addressing
RAM (zero page)
64-byte stack
00FFh
0080h
00C0h
(128 Bytes)
b
FC00h
FBFFh
Reserved
FFDFh
0.5 Kbytes
0.5 Kbytes
SECTOR 1
SECTOR 0
1Kbytes FLASH
FFFFh
FE00h
FDFFh
FC00h
PROGRAM MEMORY
DEE0h RCCRH0
RCCRL0
DEE1h
RCCRH1
RCCRL1
DEE2h
DEE3h
Register and memory map ST7LITEUS2, ST7LITEUS5
16/136
Table 3. Hardware register map (1)
Address Block Register
label Register name Reset status Remarks
0000h
0001h
0002h
Port A
PAD R
PADDR
PAO R
Port A Data register
Port A Data Direction register
Port A Option register
00h(2)
08h
02h(3)
R/W
R/W
R/W
0003h-
000Ah Reserved area (8 bytes)
000Bh
000Ch
LITE
TIMER
LTCSR
LTICR
Lite Timer Control/Status register
Lite Timer Input Capture register
0xh
00h
R/W
Read only
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
AUTO-
RELOAD
TIMER
ATC SR
CNTRH
CNTRL
ATR H
ATR L
PWMCR
PWM0CSR
Timer Control/Status register
Counter register High
Counter register Low
Auto-Reload register High
Auto-Reload register Low
PWM Output Control register
PWM 0 Control/Status register
00h
00h
00h
00h
00h
00h
00h
R/W
Read only
Read only
R/W
R/W
R/W
R/W
0014h to
0016h Reserved area (3 bytes)
0017h
0018h
AUTO-
RELOAD
TIMER
DCR0H
DCR0L
PWM 0 Duty Cycle register High
PWM 0 Duty Cycle register Low
00h
00h
R/W
R/W
0019h to
002Eh Reserved area (22 bytes)
0002Fh FLASH FCSR Flash Control/Status register 00h R/W
0030h to
0033h Reserved area (4 bytes)
0034h
0035h
0036h
ADC
ADCCSR
ADCDRH
ADCDRL
A/D Control Status register
A/D Data register High
A/D Data register Low
00h
xxh
00h
R/W
Read only
R/W
0037h ITC EICR1 External Interrupt Control register 1 00h R/W
0038h MCC MCCSR Main Clock Control/Status register 00h R/W
0039h
003Ah
Clock and
Reset
RCCR
SICSR
RC oscillator Control register
System Integrity Control/Status register
FFh
0000 0x00b
R/W
R/W
003Bh to
003Ch Reserved area (2 bytes)
003Dh ITC EICR2 External Interrupt Control register 2 00h R/W
003Eh AVD AVDTHCR AVD Threshold Selection register 03h R/W
003Fh Clock
controller CKCNTCSR Clock Controller Control/Status register 09h R/W
0040h to
0046h Reserved area (7 bytes)
0047h
0048h
MuxIO-
reset
MUXCR0
MUXCR1
Mux IO-Reset Control register 0
Mux IO-Reset Control register 1
00h
00h
R/W
R/W
ST7LITEUS2, ST7LITEUS5 Register and memory map
17/136
0049h
004Ah AWU AWUPR
AWUCSR
AWU Prescaler register
AWU Control/Status register
FFh
00h
R/W
R/W
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
DM(4)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM Control register
DM Status register
DM Breakpoint register 1 High
DM Breakpoint register 1 Low
DM Breakpoint register 2 High
DM Breakpoint register 2 Low
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
0051h to
007Fh Reserved area (47 bytes)
1. Legend: x=undefined, R/W=read/write
2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
3. The bits associated with unavailable pins must always keep their reset value.
4. For a description of the DM registers, see the ST7 I2C Protocol Reference Manual.
Table 3. Hardware register map (continued)(1)
Address Block Register
label Register name Reset status Remarks
Flash program memory ST7LITEUS2, ST7LITEUS5
18/136
4 Flash program memory
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or on-
board using in-circuit programming or in-application programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2 Main features
●ICP (in-circuit programming)
●IAP (in-application programming)
●ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●Sector 0 size configurable by option byte
●Readout and write protection
4.3 Programming modes
The ST7 can be programmed in three different ways:
●Insertion in a programming tool
In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or
erased.
●In-circuit programming
In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or
erased without removing the device from the application board.
●In-application programming
In this mode, sector 1 can be programmed or erased without removing the device from
the application board and while the application is running.
4.3.1 In-circuit programming (ICP)
ICP uses a protocol called I2C (in-circuit communication) which allows an ST7 plugged on a
printed circuit board (PCB) to communicate with an external programming device connected
via cable. ICP is performed in three steps:
●Switch the ST7 to I2C mode. This is done by driving a specific signal sequence on the
ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters I2C mode,
it fetches a specific RESET vector which points to the ST7 system memory containing
ST7LITEUS2, ST7LITEUS5 Flash program memory
19/136
the I2C protocol routine. This routine enables the ST7 to receive bytes from the I2C
interface.
●Download ICP driver code in RAM from the ICCDATA pin
●Execute ICP driver code in RAM to program the FLASH memory
Depending on the ICP driver code downloaded in RAM, FLASH memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
4.3.2 In application programming (IAP)
This mode uses an IAP driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc).
IAP mode can be used to program any memory areas except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.4 I2C interface
ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These
pins are:
●RESET: device reset
●VSS: device power supply ground
●ICCCLK: I2C output serial clock pin
●ICCDATA: I2C input serial data pin
●CLKIN: main clock input for external source
●VDD: application board power supply
Refer to Figure 6 for a description of the I2C interface.
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the programming tool is plugged to the board, even if an
I2C session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the programming
tool documentation for recommended resistor values.
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5 mA at high level (push pull output or pull-up resistor<1 kΩ). A schottky diode can be used
to isolate the application RESET circuit in this case. When using a classical RC network with
R>1 kΩ or a reset management IC with open drain output and pull-up resistor>1 kΩ, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the I2C session.
The use of Pin 7 of the I2C connector depends on the programming tool architecture. This
pin must be connected when using most ST programming tools (it is used to monitor the
application power supply). Please refer to the programming tool manual.
Flash program memory ST7LITEUS2, ST7LITEUS5
20/136
Pin 9 has to be connected to the CLKIN pin of the ST7 when I2C mode is selected with
option bytes disabled (35-pulse I2C entry mode). When option bytes are enabled (38-pulse
I2C entry mode), the internal RC clock (internal RC or AWU RC) is forced. If internal RC is
selected in the option byte, the internal RC is provided. If AWU RC or external clock is
selected, the AWU RC oscillator is provided.
A serial resistor must be connected to I2C connector pin 6 in order to prevent contention on
PA3/RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin
forces the opposite state in output mode. The resistor value is defined to limit the current
below 2 mA at 5 V. If PA3 is used as output push-pull, then the application must be switched
off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to
drive the RESET pin below VIL, special care must also be taken when a pull-up is placed on
PA3 for application reasons.
Caution: During normal operation, ICCCLK pin must be pulled- up, internally or externally (external
pull-up of 10 kΩ mandatory in noisy environment). This is to avoid entering I2C mode
unexpectedly during a reset. In the application, even if the pin is configured as output, any
reset will put it back in input pull-up.
Figure 6. Typical I2C interface
4.5 Memory protection
There are two different types of memory protection: readout protection and Write/Erase
Protection which can be applied individually.
4.5.1 Readout protection
Readout protection, when selected provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller. Program memory is protected.
I2C CONNECTOR
ICCDATA
ICCCLK
RESET
VDD
HE10 CONNECTOR TYPE
APPLICATION
POWER SUPPLY
1
246810
975 3
PROGRAMMING TOOL
I2C CONNECTOR
APPLICATION BOARD
I2C Cable
(See Note 3)
ST7
CLKIN
OPTIONAL
See Note 1
See Note 1 and Caution
See Note 2
APPLICATION
RESET SOURCE
APPLICATION
I/O
(See Note 4)
3.3kΩ
(See Note 5)
ST7LITEUS2, ST7LITEUS5 Flash program memory
21/136
In flash devices, this protection is removed by reprogramming the option. In this case,
program memory is automatically erased, and the device can be reprogrammed.
Readout protection selection depends on the device type:
●In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
●In ROM devices it is enabled by mask option specified in the option list.
4.5.2 Flash Write/Erase protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program
memory. Its purpose is to provide advanced security to applications and prevent any change
being made to the memory content.
Warning: Once set, Write/erase protection can never be removed. A
write-protected flash device is no longer reprogrammable.
Write/erase protection is enabled through the FMP_W bit in the option byte.
4.6 Related documentation
For details on Flash programming and I2C protocol, refer to the ST7 Flash programming
reference manual and to the ST7 I2C protocol reference manual.
Flash program memory ST7LITEUS2, ST7LITEUS5
22/136
4.7 Register description
4.7.1 Flash Control/Status register (FCSR)
This register controls the XFlash erasing and programming using ICP, IAP or other
programming methods.
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
Reset value: 000 0000 (00h)
7 0
00000OPTLATPGM
Read/write
Table 4. FLASH register map and reset values
Address
(Hex.)
Register
Label 76543210
002Fh
FCSR
Reset
value 00000
OPT
0
LAT
0
PGM
0
ST7LITEUS2, ST7LITEUS5 Central processing unit
23/136
5 Central processing unit
5.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.
5.2 Main features
●63 basic instructions
●Fast 8-bit by 8-bit multiply
●17 main addressing modes
●Two 8-bit index registers
●16-bit stack pointer
●Low power modes
●Maskable hardware interrupts
●Non-maskable software interrupt
5.3 CPU registers
The six CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
5.3.1 Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
5.3.2 Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. (The cross-assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
5.3.3 Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is
the LSB) and PCH (program counter high which is the MSB).
Central processing unit ST7LITEUS2, ST7LITEUS5
24/136
Figure 7. CPU registers
1. X = Undefined value
5.3.4 Condition Code register (CC)
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Reset value: 111x1xxx
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
STACK POINTER
CONDITION CODE REGISTER
PROGRAM COUNTER
70
1C1 1 HI NZ
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
70
70
70
0
7
15 8
PCH PCL
15 870
RESET VALUE = STACK HIGHER ADDRESS
RESET VALUE = 1X11X1XX
RESET VALUE = XXh
RESET VALUE = XXh
RESET VALUE = XXh
7 0
111HINZC
Read/Write
ST7LITEUS2, ST7LITEUS5 Central processing unit
25/136
Bit 7:5 Set to ‘1’
Bit 4 H Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instruction. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Bit 3 I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the
JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I
is cleared. By default an interrupt routine is not interruptible because the I bit
is set by hardware at the start of the routine and reset by the IRET
instruction at the end of the routine. If the I bit is cleared by software in the
interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
Bit 2 N Negative
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 Z Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and
JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.
Central processing unit ST7LITEUS2, ST7LITEUS5
26/136
5.3.5 Stack Pointer (SP)
Reset value: 00 FFh
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 8.
●When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call is located at two locations and an interrupt five locations in the stack area.
15 8
00000000
Read/write
7 0
1 1 SP5 SP4 SP3 SP2 SP1 SP0
Read/write
ST7LITEUS2, ST7LITEUS5 Central processing unit
27/136
Figure 8. Stack manipulation example
1. Stack higher address = 00FFh.
2. Stack lower address = 00C0h.
PCH
PCL
SP
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
SP
Y
CALL
subroutine Interrupt
event
PUSH Y POP Y IRET RET
or RSP
@ 00FFh
@ 00C0h
Supply, reset and clock management ST7LITEUS2, ST7LITEUS5
28/136
6 Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components.
6.1 Main features
●Clock management
– 8 MHz internal RC oscillator (enabled by option byte)
– External clock Input (enabled by option byte)
●Reset sequence manager (RSM)
●System integrity management (SI)
– Main supply low voltage detection (LVD) with reset generation (enabled by option
byte)
– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply
6.2 Internal RC oscillator adjustment
The ST7 contains an internal RC oscillator with a specific accuracy for a given device,
temperature and voltage. It can be selected as the start up clock through the CKSEL[1:0]
option bits (see Section 14.1 on page 123). It must be calibrated to obtain the frequency
required in the application. This is done by software writing a 10-bit calibration value in the
RCCR (RC Control register) and in the bits [6:5] in the SICSR (SI Control Status register).
Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each
time the device is reset, the calibration value must be loaded in the RCCR. Predefined
calibration values are stored in Flash memory for 3.3 and 5 V VDD supply voltages at 25°C,
as shown in the following table.
Table 5. Predefined RC oscillator calibration values
RCCR Conditions ST7LITEUS2/ST7LITEUS5 address
RCCRH0 VDD=5 V
TA=25 °C
fRC=8 MHz
DEE0h(1) (CR[9:2] bits)
1. DEE0h, DEE1h, DEE2h and DEE3h are located in a reserved area butare special bytes containing also
the RC calibration values which are read-accessible only in user mode. If all the Flash space (including the
RC calibration value locations) has been erased (after the readout protection removal), then the RC
calibration values can still be obtained through these two addresses.
RCCRL0 DEE1h 1) (CR[1:0] bits)
RCCRH1 VDD=3.3 V
TA=25 °C
fRC=8 MHz
DEE2h 1) (CR[9:2] bits)
RCCRL1 DEE3h 1) (CR[1:0] bits)
ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management
29/136
Note: 1 In I2C mode, the internal RC oscillator is forced as a clock source, regardless of the
selection in the option byte. Refer to note 5 in Section 4.4 on page 19 for further details.
2See Section 12: Electrical characteristics for more information on the frequency and
accuracy of the RC oscillator.
3 To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7
device.
Caution: If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Refer to application note AN2326 for information on how to calibrate the RC frequency using
an external reference signal.
The ST7LITEUS2 and ST7LITEUS5 also contain an Auto-wakeup RC oscillator. This RC
oscillator should be enabled to enter Auto-wakeup from Halt mode.
The Auto-wakeup RC oscillator can also be configured as the startup clock through the
CKSEL[1:0] option bits (see Section 14.1 on page 123).
This is recommended for applications where very low power consumption is required.
Switching from one startup clock to another can be done in run mode as follows (see
Figure 9):
Case 1
Switching from internal RC to AWU:
1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator
2. The RC_FLAG is cleared and the clock output is at 1.
3. Wait 3 AWU RC cycles till the AWU_FLAG is set
4. The switch to the AWU clock is made at the positive edge of the AWU clock signal
5. Once the switch is made, the internal RC is stopped
Case 2
Switching from AWU RC to internal RC:
1. Reset the RC/AWU bit to enable the internal RC oscillator
2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is
running on internal RC clock.
3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC
cycles)
4. The switch to the internal RC clock is made at the positive edge of the internal RC clock
signal
5. Once the switch is made, the AWU RC is stopped
Note: 1 When the internal RC is not selected, it is stopped so as to save power consumption.
2 When the internal RC is selected, the AWU RC is turned on by hardware when entering
Auto-wakeup from Halt mode.
3 When the external clock is selected, the AWU RC oscillator is always on.
Supply, reset and clock management ST7LITEUS2, ST7LITEUS5
30/136
Figure 9. Clock switching
6.3 Register description
6.3.1 Main Clock Control/Status register (MCCSR)
Reset value: 0000 0000 (00h)
Internal RC AWU RC
Set RC/AWU
Poll AWU_FLAG until set
Internal RC
Reset RC/AWU
Poll RC_FLAG until set
AWU RC
7 0
000000MCOSMS
Read / Write
Bits 7:2 Reserved, must be kept cleared.
Bit 1 MCO Main Clock Out enable bit
This bit is read/write by software and cleared by hardware after a reset. This bit
allows to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 SMS Slow Mode select
This bit is read/write by software and cleared by hardware after a reset. This bit
selects the input clock fOSC or fOSC/32.
0: Normal mode (fCPU = fOSC )
1: Slow mode (fCPU = fOSC/32)
ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management
31/136
6.3.2 RC Control register (RCCR)
Reset value: 1111 1111 (FFh)
6.3.3 System Integrity (SI) Control/status register (SICSR)
Reset value: 0000 0x00 (0xh)
7 0
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2
Read / Write
Bits 7:0 CR[9:2] RC Oscillator Frequency Adjustment Bits
These bits, as well as CR[1:0] bits in the SICSR register must be written
immediately after reset to adjust the RC oscillator frequency and to obtain the
required accuracy. The application can store the correct value for each voltage
range in Flash memory and write it to this register at startup.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of different values in the register until the
correct frequency is reached. The fastest method is to use a dichotomy
starting with 80h.
7 0
0 CR1 CR0 0 0 LVDRF AVDF AVDIE
Read / Write
Bit 7 Reserved, must be kept cleared.
Bits 6:5 CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCR register must be written
immediately after reset to adjust the RC oscillator frequency and to obtain the
required accuracy. Refer to Section 6.2 on page 28.
Bits 4:3 Reserved, must be kept cleared.
Bits 2:0 System Integrity bits. Refer to Section 7.4 on page 43.
Supply, reset and clock management ST7LITEUS2, ST7LITEUS5
32/136
6.3.4 AVD Threshold Selection register (AVDTHCR)
Reset value: 0000 0011 (03h)
6.3.5 Clock Controller Control/Status register (CKCNTCSR)
Read/Write
Reset value: 0000 1001 (09h)
7 0
CK2 CK1 CK0 0 0 0 AVD1 AVD0
Read / Write
Bits 7:5 CK[2:0] Internal RC Prescaler Selection
These bits are set by software and cleared by hardware after a reset. These bits
select the prescaler of the internal RC oscillator. See Figure 10 on page 34 and
Ta b l e 6 .
Bits 4:2 Reserved, must be kept cleared.
Bits 1:0 AVD Threshold Selection bits. Refer to Section 7.4: System integrity management
(SI).
Table 6. Internal RC prescaler selection bits(1)
1. If the internal RC is used with a supply operating range below 3.3 V, a division ratio of at least 2 must be
enabled in the RC prescaler.
CK2 CK1 CK0 fOSC
000 f
RC
001 f
RC/2
010 f
RC/4
011 f
RC/8
100 f
RC/16
7 0
0000AWU_FLAG
RC_
FLAG 0RC/AWU
Read / Write
Bits 7:4 Reserved, must be kept cleared.
Bit 3 AWU_FLAG AWU Selection
This bit is set and cleared by hardware
0: No switch from AWU to RC requested
1: AWU clock activated and temporization completed
ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management
33/136
Bit 2 RC_FLAG RC Selection
This bit is set and cleared by hardware
0: No switch from RC to AWU requested
1: RC clock activated and temporization completed
Bit 1 = Reserved, must be kept cleared.
Bit 0 = RC/AWU RC/AWU Selection
0: RC enabled
1: AWU enabled (default value)
Table 7. Clock register map and reset values
Address
(Hex.)
Register
label 7654 3 2 1 0
0038h MCCSR
Reset value 0000 0 0
MCO
0
SMS
0
0039h RCCR
reset value
CR9
1
CR8
1
CR7
1
CR6
1
CR5
1
CR4
1
CR3
1
CR2
1
003Ah SICSR
reset value 0 CR1 CR0 0 0 LVDRF
x
AVDF
0
AVDIE
0
003Eh AVDTHCR
reset value
CK2
0
CK1
0
CK0
000 0
AVD1
1
AVD2
1
003Fh CKCNTCSR
reset value 0000
AWU_FLAG
1
RC_FLAG
00RC/AWU
1
Supply, reset and clock management ST7LITEUS2, ST7LITEUS5
34/136
Figure 10. Clock management block diagram
MCCSR
SMS
PERIPHERALS
(1ms timebase @ 8 MHz fOSC)
fOSC/32
fOSC
fOSC
fLTIMER
LITE TIMER COUNTER
13-BIT
fCPU
TO CPU AND
0
1
CR6CR9 CR2CR3CR4CR5CR8 CR7 RCCR
fOSC
CLKIN
Tunable
Oscillatorinternal RC
Option bits
CKSEL[1:0]
/2
DIVIDER
AWU
8MHz
2MHz
1MHz
4MHz
Prescaler
RC
8MHz(fRC)
33kHz
Clock
Controller
Ext Clock
AWU CKRC OSC
CR1 CR0 SICSR
/32 DIVIDER
fCLKIN
CKCNTCSR
RC/AWU
MCO
MCO
500 kHz
ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management
35/136
6.4 Reset sequence manager (RSM)
6.4.1 Introduction
The reset sequence manager includes three reset sources as shown in Figure 12:
●External RESET source pulse
●Internal LVD reset (low voltage detection)
●Internal WATCHDOG reset
Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Figure 12.
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in Figure 11:
●Active phase depending on the reset source
●64 CPU clock cycle delay
●RESET vector fetch
Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 64 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery
has taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock cycles.
Figure 11. Reset sequence phases
RESET
Active phase INTERNAL RESET
64 CLOCK CYCLES
FETCH
VECTOR
Supply, reset and clock management ST7LITEUS2, ST7LITEUS5
36/136
Figure 12. Reset block diagram
1. Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset conditions
6.4.2 Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A RESET signal originating from an external source must have a duration of at least
th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and
therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
6.4.3 External Power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until VDD is over
the minimum level specified for the selected fCLKIN frequency.
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
6.4.4 Internal low voltage detector (LVD) reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●Power-on reset
●Voltage Drop reset
The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or
VDD<VIT- (falling edge) as shown in Figure 13.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
RESET
RON
VDD
INTERNAL
RESET
PULSE
GENERATOR
FILTER
LVD RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET 1)
ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management
37/136
6.4.5 Internal watchdog reset
The reset sequence generated by a internal watchdog counter overflow is shown in
Figure 13.
Starting from the watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
Figure 13. Reset sequences
6.5 Register description
6.5.1 Multiplexed I/O Reset Control register 1 (MUXCR1)
Reset value: 0000 0000 (00h)
6.5.2 Multiplexed I/O Reset Control register 0 (MUXCR0)
Reset value: 0000 0000 (00h)
VDD
Run
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
VIT+(LVD)
VIT-(LVD)
th(RSTL)in
Run
WATCHDOG UNDERFLOW
tw(RSTL)out
Run Run
RESET
RESET
SOURCE
EXTERNAL
RESET
LVD
RESET
WATCHDOG
RESET
INTERNAL RESET (64 TCPU)
VECTOR FETCH
ACTIVE
PHASE
ACTIVE
PHASE
7 0
MIR15 MIR14 MIR13 MIR12 MIR11 MIR10 MIR9 MIR8
Read / Write once
7 0
MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1 MIR0
Read / Write once
Bits 15:0 MIR[15:0]
Supply, reset and clock management ST7LITEUS2, ST7LITEUS5
38/136
This 16-bit register is read/write by software but can be written only once between two reset
events. It is cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers
are at 00h, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as
output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.
These registers are one-time writable only.
●To configure PA3 as general purpose output:
After power-on / reset, the application program has to configure the I/O port by writing
to these registers as described above. Once the pin is configured as an I/O output, it
cannot be changed back to a reset pin by the application code.
●To configure PA3 as RESET:
An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear the
two registers and the pin will act again as a reset function. Otherwise, a power-down is
required to put the pin back in reset configuration.
Table 8. Multiplexed IO register map and reset values
Address
(Hex.)
Register
label 76543210
0047h
MUXCR0
reset
value
MIR7
0
MIR6
0
MIR5
0
MIR4
0
MIR3
0
MIR2
0
MIR1
0
MIR0
0
0048h
MUXCR1
reset
value
MIR15
0
MIR14
0
MIR13
0
MIR12
0
MIR11
0
MIR10
0
MIR9
0
MIR8
0
ST7LITEUS2, ST7LITEUS5 Interrupts
39/136
7 Interrupts
The ST7 core may be interrupted by one of two different methods: Maskable hardware
interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt
(TRAP). The Interrupt processing flowchart is shown in Figure 14.
The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
However, disabled interrupts may be latched and processed when they are enabled (see
external interrupts subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
●Normal processing is suspended at the end of the current instruction execution.
●The PC, X, A and CC registers are saved onto the stack.
●The I bit of the CC register is set to prevent additional interrupts.
●The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table
for vector addresses).
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction, the I bit is cleared and the main program
resumes.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority
defines which one will be serviced first (see Table 9: Interrupt mapping).
Interrupts and low power mode
All interrupts allow the processor to leave the Wait low power mode. Only external and
specifically mentioned interrupts allow the processor to leave the Halt low power mode (refer
to the “Exit from Halt” column in Table 9: Interrupt mapping).
7.1 Non maskable software interrupt
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It is serviced according to the flowchart in Figure 14.
Interrupts ST7LITEUS2, ST7LITEUS5
40/136
7.2 External interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
Halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies
to the ei source. In case of a NANDed source (as described in the I/O ports section), a low
level on an I/O pin, configured as input with interrupt, masks the interrupt request even in
case of rising-edge sensitivity.
7.3 Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●The I bit of the CC register is cleared.
●The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
●Writing “0” to the corresponding bit in the status register or
●Access to the status register while the flag is set followed by a read or write of an
associated register.
Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
Figure 14. Interrupt processing flowchart
I BIT SET?
Y
N
IRET?
Y
N
FROM RESET
LOAD PC FROM INTERRUPT VECTOR
STACK PC, X, A, CC
SET I BIT
FETCH NEXT INSTRUCTION
EXECUTE INSTRUCTION
THIS CLEARS I BIT BY DEFAULT
RESTORE PC, X, A, CC FROM STACK
INTERRUPT
Y
N
PENDING?
ST7LITEUS2, ST7LITEUS5 Interrupts
41/136
7.3.1 External Interrupt Control register 1 (EICR1)
Reset value: 0000 0000 (00h)
Table 9. Interrupt mapping
N° Source block Description Register
label
Priority
order
Exit
from
Halt
Address
vector
RESET Reset N/A
Highest
priority
Lowest
priority
yes FFFEh-FFFFh
TRAP Software interrupt no FFFCh-FFFDh
0 AWU Auto-wakeup interrupt AWUCSR yes(1) FFFAh-FFFBh
1 ei0 External interrupt 0
N/A
yes
FFF8h-FFF9h
2 ei1 External interrupt 1 FFF6h-FFF7h
3 ei2 External interrupt 2 FFF4h-FFF5h
4 Not used no FFF2h-FFF3h
5 ei3 External interrupt 3 yes FFF0h-FFF1h
6 2) ei4 2) External interrupt 4 2) no(2) FFEEh-FFEFh
7 SI AVD interrupt SICSR no FFECh-FFEDh
8AT T I ME R AT TIMER Output Compare Interrupt
PWMxCS
R or
ATC SR
no FFEAh-FFEBh
9 AT TIMER Overflow Interrupt ATCSR yes(3) FFE8h-FFE9h
10 LITE TIMER LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h
11 LITE TIMER RTC1 Interrupt LTCSR yes(3) FFE4h-FFE5h
12 Not used no FFE2h-FFE3h
13 Not used no FFE0h-FFE1h
1. This interrupt exits the MCU from Auto-wakeup from Halt mode only.
2. This interrupt exits the MCU from Wait and Active-halt modes only. Moreover, IS4[1:0] = 01 is the only safe configuration to
avoid spurious interrupt in Halt and AWUFH mode
3. These interrupts exit the MCU from Active-halt mode only.
7 0
0 0 IS21 IS20 IS11 IS10 IS01 IS00
Read/Write
Bits 7:6 Reserved
Bits 5:4 IS2[1:0] ei2 sensitivity
These bits define the interrupt sensitivity for ei2 according to Ta b l e 1 0 .
Bits 3:2 IS1[1:0] ei1 sensitivity
These bits define the interrupt sensitivity for ei1 according to Ta b l e 1 0 .
Bits 1:0 IS0[1:0] ei0 sensitivity
These bits define the interrupt sensitivity for ei0 according to Ta b l e 1 0 .
Interrupts ST7LITEUS2, ST7LITEUS5
42/136
Note: 1 These 8 bits can be written only when the I bit in the CC register is set.
2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
can be used to clear unwanted pending interrupts. Refer to Section : External interrupt
function.
7.3.2 External Interrupt Control register 2 (EICR2)
Reset value: 0000 0000 (00h)
Note: 1 These 8 bits can be written only when the I bit in the CC register is set.
2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This
can be used to clear unwanted pending interrupts. Refer to Section : External interrupt
function.
3 IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH
modes.
7 0
0 0 0 0 IS41 IS40 IS31 IS30
Read/Write
Bits 7:4 Reserved
Bits 3:2 IS4[1:0] ei4 sensitivity
These bits define the interrupt sensitivity for ei1 according to Ta b l e 1 0 .
Bits 1:0 IS3[1:0] ei3 sensitivity
These bits define the interrupt sensitivity for ei0 according to Ta b l e 1 0 .
Table 10. Interrupt sensitivity bits
ISx1 ISx0 External interrupt sensitivity
0 0 Falling edge & low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge
ST7LITEUS2, ST7LITEUS5 Interrupts
43/136
7.4 System integrity management (SI)
The System Integrity Management block contains the low voltage detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 11.2.1: Illegal opcode reset for further details.
7.4.1 Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when VDD is below:
●VIT+(LVD) when VDD is rising
●VIT-(LVD) when VDD is falling
The LVD function is illustrated in Figure 15.
The voltage threshold can be configured by option byte to be low, medium or high. See
Section 14.1: Option bytes.
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),
the MCU can only be in two modes:
●Under full software control
●In static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
Note: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull VDD down to 0V to ensure optimum restart
conditions. Refer to circuit example in Figure 62 and note 4.
The LVD is an optional function which can be selected by option byte. See Section 14.1 on
page 123. It allows the device to be used without any external RESET circuitry. If the LVD is
disabled, an external circuitry must be used to ensure a proper Power-on reset.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.
Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels
are not correlated. Refer to Table 47 on page 95 and Table 48 on page 96 for more details.
Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will
clear the watchdog flag.
Interrupts ST7LITEUS2, ST7LITEUS5
44/136
Figure 15. Low voltage detector vs reset
Figure 16. Reset and supply management block diagram
VDD
VIT+(LVD)
RESET
VIT-(LVD)
Vhys
LOW VOLTAGE
DETECTOR
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
RESET
VSS
VDD
RESET SEQUENCE
MANAGER
(RSM)
AVD Interrupt Request
SYSTEM INTEGRITY MANAGEMENT
WATCHDOG
SICSR
TIMER (WDG)
AVDAVDLVD
RF IE
0F
0
STATUS FLAG
11
70
0
ST7LITEUS2, ST7LITEUS5 Interrupts
45/136
7.4.2 Auxiliary voltage detector (AVD)
The voltage detector function (AVD) is based on an analog comparison between a VIT-(AVD)
and VIT+(AVD) reference value and the VDD main supply voltage (VAVD). The VIT-(AVD)
reference value for falling voltage is lower than the VIT+(AVD) reference value for rising
voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator is directly readable by the application software through a
real time status bit (AVDF) in the SICSR register. This bit is read only.
Monitoring the VDD main supply
The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register.
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
VIT+(AVD) or VIT-(AVD) threshold (AVDF bit is set).
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 17.
The interrupt on the rising edge is used to inform the application that the VDD warning state
is over
Note: Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels
are not correlated. Refer to Table 47 on page 95 and Table 48 on page 96 for more details.
Figure 17. Using the AVD to monitor VDD
VDD
VIT+(AVD)
VIT-(AVD)
AVDF bit 01
RESET
IF AVDIE bit = 1
Vhyst
AVD INTERRUPT
REQUEST
INTERRUPT Cleared by
VIT+(LVD)
VIT-(LVD)
LVD RESET
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
01
hardware
INTERRUPT Cleared by
reset
Interrupts ST7LITEUS2, ST7LITEUS5
46/136
7.4.3 Low power modes
Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
7.4.4 Register description
System Integrity (SI) Control/Status register (SICSR)
Reset value: 0000 0x00 (0xh)
Table 11. Description of low power modes
Mode Description
Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode.
Halt
The SICSR register is frozen.
The AVD remains active but the AVD interrupt cannot be used to exit from Halt
mode.
Table 12. Description of interrupt events
Interrupt Event Event flag Enable
control bit
Exit from
Wait
Exit from
Halt
AVD event AVDF AVDIE Yes No
7 0
0 CR1 CR0 0 0 LVDRF AVDF AVDIE
Read/write
Bit 7 Reserved, must be kept cleared.
Bits 6:5 CR[1:0] RC Oscillator Frequency Adjustment bits
These bits, as well as CR[9:2] bits in the RCCR register must be written
immediately after reset to adjust the RC oscillator frequency and to obtain the
required accuracy. Refer to Section 6.2: Internal RC oscillator adjustment on
page 28.
Bits 4:3 Reserved, must be kept cleared.
ST7LITEUS2, ST7LITEUS5 Interrupts
47/136
AVD Threshold Selection register (AVDTHCR)
Refer to Section 6.3.4: AVD Threshold Selection register (AVDTHCR) for a full description of
this register.
Application notes
The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
Bit 2 LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared when read. See WDGRF flag description in
Section 10.1.6 on page 69 for more details. When the LVD is disabled by OPTION
BYTE, the LVDRF bit value is undefined.
Note: If the selected clock source is one of the two internal ones, and if VDD
remains below the selected LVD threshold during less than TAWU (33us
typ.), the LVDRF flag cannot be set even if the device is reset by the LVD.
If the selected clock source is the external clock (CLKIN), the flag is never
set if the reset occurs during Halt mode. In run mode the flag is set only if
fCLKIN is greater than 10 MHz.
Bit 1 AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit is set. Refer to Figure 17 for
additional details
0: VDD over AVD threshold
1: VDD under AVD threshold
Bit 0 AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated when
the AVDF flag is set. The pending interrupt information is automatically cleared
when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
Table 13. System integrity register map and reset values
Address
(Hex.)
Register
label 76543210
003Ah
SICSR
reset
value
01100
LVDR F
x
AVDF
0
AVDIE
0
003Eh
AVDTHCR
reset
value
CK2
0
CK1
0
CK0
0000
AVD1
1
AVD2
1
Power saving modes ST7LITEUS2, ST7LITEUS5
48/136
8 Power saving modes
8.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 18):
●Slow
●Wait (and Slow-wait)
●Active-halt
●Auto-wakeup from Halt (AWUFH)
●Halt
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency (fOSC).
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 18. Power saving mode transitions
POWER CONSUMPTION
Wait
Slow
Run
Active halt
High
Low
Slow wait
Halt
ST7LITEUS2, ST7LITEUS5 Power saving modes
49/136
8.2 Slow mode
This mode has two targets:
●To reduce power consumption by decreasing the internal clock in the device,
●To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
Slow mode.
In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked
at this lower frequency.
Note: Slow-wait mode is activated when entering Wait mode while the device is already in Slow
mode.
Figure 19. Slow mode clock transition
8.3 Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to
enable all interrupts. All other registers and memory remain unchanged. The MCU remains
in Wait mode until an interrupt or reset occurs, whereupon the Program Counter branches to
the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wakeup.
Refer to Figure 20 for a description of the Wait mode flowchart.
SMS
fCPU
NORMAL RUN MODE
REQUEST
fOSC
fOSC/32 fOSC
Power saving modes ST7LITEUS2, ST7LITEUS5
50/136
Figure 20. Wait mode flowchart
1. 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
8.4 Active-halt and Halt modes
Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active-
halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
ON
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
0
ON
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
ON
X1)
ON
64 CPU CLOCK CYCLE
DELAY
Table 14. Enabling/disabling Active-halt and Halt modes
LTCSR TBIE
bit
ATCSR OVFIE
bit ATCSRCK1 bit ATCSRCK0 bit Meaning
0xx0
Active-halt mode disabled00xx
0111
1xxx
Active-halt mode enabled
x101
ST7LITEUS2, ST7LITEUS5 Power saving modes
51/136
8.4.1 Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled.
The MCU can exit Active-halt mode on reception of a Lite Timer / AT Timer interrupt or a
reset.
●When exiting Active-halt mode by means of a reset, a 64 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation by fetching the reset vector which woke
it up (see Figure 22).
●When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes
operation by servicing the interrupt vector which woke it up (see Figure 22).
When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
Caution: As soon as Active-halt is enabled, executing a HALT instruction while the watchdog is active
does not generate a reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 21. Active-halt timing overview
haltRun Run
64 CPU
CYCLE DELAY 1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION FETCH
VECTOR
Active
[Active-halt Enabled]
Power saving modes ST7LITEUS2, ST7LITEUS5
52/136
Figure 22. Active-halt mode flowchart
1. This delay occurs only if the MCU exits Active-halt mode by means of a reset.
2. Peripherals clocked with an external clock source can still be active.
3. Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from Active-halt mode.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
8.4.2 Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when Active-halt mode is disabled.
The MCU can exit Halt mode on reception of either a specific interrupt (see Tab le 9:
Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt,
the main oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize
it. After the start up delay, the CPU resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Figure 24).
When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the watchdog
system is enabled, can generate a watchdog reset (see Section 14.1: Option bytes for more
details).
HALT INSTRUCTION
RESET
INTERRUPT 3)
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
IBIT
ON
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS 2)
IBIT
ON
OFF
X4)
ON
CPU
OSCILLATOR
PERIPHERALS
IBITS
ON
ON
X4)
ON
64 CPU CLOCK CYCLE
DELAY
(Active-halt enabled)
ST7LITEUS2, ST7LITEUS5 Power saving modes
53/136
Figure 23. Halt timing overview
1. A reset pulse of at least 42µs must be applied when exiting from Halt mode.
Figure 24. Halt mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 9: Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
HaltRun Run
64 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION FETCH
VECTOR
[Active-halt disabled]
HALT INSTRUCTION
RESET
INTERRUPT 3)
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS 2)
IBIT
OFF
OFF
0
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
IBIT
ON
OFF
X4)
ON
CPU
OSCILLATOR
PERIPHERALS
IBITS
ON
ON
X4)
ON
64 CPU CLOCK CYCLE
DELAY 5)
WATCHDOG
ENABLE
DISABLE
WDGHALT 1) 0
WATCHDOG
RESET
1
(Active-halt disabled)
Power saving modes ST7LITEUS2, ST7LITEUS5
54/136
Halt mode recommendations
●Make sure that an external event is available to wakeup the microcontroller from Halt
mode.
●When using an external interrupt to wakeup the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
●The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
interrupt routine corresponding to the wakeup event (reset or external interrupt).
8.5 Auto-wakeup from Halt mode
Auto-wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of a specific
internal RC oscillator for wakeup (Auto-wakeup from Halt oscillator) which replaces the main
clock which was active before entering Halt mode. Compared to Active-halt mode, AWUFH
has lower power consumption (the main clock is not kept running), but there is no accurate
realtime clock available.
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
register has been set.
Figure 25. AWUFH mode block diagram
As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (fAWU_RC). Its frequency is divided by
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed, the following actions
are performed:
●The AWUF flag is set by hardware,
●An interrupt wakes-up the MCU from Halt mode,
●The main oscillator is immediately turned on and the 64 CPU cycle delay is used to
stabilize it.
AWU RC
AWUFH
fAWU_RC
AWUFH
(ei0 source)
oscillator
prescaler/1 .. 255
interrupt
/64
divider
to 8-bit Timer input capture
ST7LITEUS2, ST7LITEUS5 Power saving modes
55/136
After this startup delay, the CPU resumes operation by servicing the AWUFH interrupt. The
AWU flag and its associated interrupt are cleared by software reading the AWUCSR
register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency fAWU_RC and then calculating the right prescaler value.
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects fAWU_RC to the input capture of the 8-bit lite timer, allowing the
fAWU_RC to be measured using the main oscillator clock as a reference timebase.
Similarities with Halt mode
The following AWUFH mode behavior is the same as normal Halt mode:
●The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see Section 8.4: Active-halt and Halt modes).
●When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
●In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
●The compatibility of watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
when executed while the watchdog system is enabled, can generate a watchdog reset.
Figure 26. AWUF Halt timing diagram
AWUFH interrupt
fCPU
RUN MODE HALT MODE 64 tCPU RUN MODE
fAWU_RC
Clear
by software
tAWU
Power saving modes ST7LITEUS2, ST7LITEUS5
56/136
Figure 27. AWUFH mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external
interrupt). Refer to Table 9: Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
RESET
INTERRUPT 3)
Y
N
N
Y
CPU
MAIN OSC
PERIPHERALS 2)
I[1:0] BITS
OFF
OFF
10
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
MAIN OSC
PERIPHERALS
I[1:0] BITS
ON
OFF
XX 4)
ON
CPU
MAIN OSC
PERIPHERALS
I[1:0] BITS
ON
ON
XX 4)
ON
64 CPU CLOCK
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT 1) 0
WATCHDOG
RESET
1
CYCLE
AWU RC OSC ON
AWU RC OSC OFF
AWU RC OSC OFF
HALT INSTRUCTION
(Active-Halt disabled)
(AWUCSR.AWUEN=1)
ST7LITEUS2, ST7LITEUS5 Power saving modes
57/136
8.5.1 Register description
AWUFH Control/ Status register (AWUCSR)
Reset value: 0000 0000 (00h)
AWUFH Prescaler register (AWUPR)
Reset value: 1111 1111 (FFh)
7 0
00000
AWU
FAWUM AWUEN
Read/Write
Bits 7:3 Reserved
Bit 2 AWUF Auto-wakeup Flag
This bit is set by hardware when the AWU module generates an interrupt and
cleared by software on reading AWUCSR. Writing to this bit does not change its
value.
0: No AWU interrupt occurred
1: AWU interrupt occurred
Bit 1 AWUM Auto-wakeup Measurement
This bit enables the AWU RC oscillator and connects its output to the input capture
of the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC
oscillator dispersion and then compensate this dispersion by providing the right
value in the AWUPRE register.
0: Measurement disabled
1: Measurement enabled
Bit 0 AWUEN Auto-wakeup From Halt Enabled
This bit enables the Auto-wakeup From Halt feature: once Halt mode is entered, the
AWUFH wakes up the microcontroller after a time delay dependent on the AWU
prescaler value. It is set and cleared by software.
0: AWUFH (Auto-wakeup From Halt) mode disabled
1: AWUFH (Auto-wakeup From Halt) mode enabled
Note: Whatever the clock source, this bit should be set to enable the AWUFH
mode once the HALT instruction has been executed.
7 0
AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0
Read/Write
Bits 7:0 AWUPR[7:0] Auto-wakeup Prescaler
These 8 bits define the AWUPR Dividing factor (see Table 15: Configuring the
dividing factor)
Power saving modes ST7LITEUS2, ST7LITEUS5
58/136
In AWU mode, the period that the MCU stays in Halt Mode (tAWU in Figure 26) is defined by
This prescaler register can be programmed to modify the time that the MCU stays in Halt
mode before waking up automatically.
Note: If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately
after a HALT instruction, or the AWUPR remains unchanged.
Table 15. Configuring the dividing factor
AWUPR[7:0] Dividing factor
00h Forbidden
01h 1
... ...
FEh 254
FFh 255
tAWU 64 AWUPR×1
fAWURC
--------------------------t
RCSTRT
+×=
Table 16. AWU register map and reset values
Address
(Hex.)
Register
label 76543210
0049h
AWUPR
Reset
value
AWUP
R7
1
AWUP
R6
1
AWUP
R5
1
AWUP
R4
1
AWUP
R3
1
AWUP
R2
1
AWUP
R1
1
AWUP
R0
1
004Ah
AWUCSR
Reset
value
00000AWUFAWUM
AWUE
N
ST7LITEUS2, ST7LITEUS5 I/O ports
59/136
9 I/O ports
9.1 Introduction
The I/O port offers different functional modes:
●Transfer of data through digital inputs and outputs
and for specific pins:
●External interrupt generation
●Alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 6 pins. Each pin (except PA3/RESET) can be programmed
independently as digital input (with or without interrupt generation) or digital output.
9.2 Functional description
Each port has 2 main registers:
●Data register (DR)
●Data Direction register (DDR)
and one optional register:
●Option register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
The following description takes into account the OR register, (for specific ports which do not
provide this register refer to the I/O Port Implementation section). The generic I/O block
diagram is shown in Figure 28.
9.2.1 Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.
2 PA3 cannot be configured as input.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be used to clear unwanted pending
interrupts.
I/O ports ST7LITEUS2, ST7LITEUS5
60/136
Spurious interrupts
When enabling/disabling an external interrupt by setting/resetting the related OR register bit,
a spurious interrupt is generated if the pin level is low and its edge sensitivity includes
falling/rising edge. This is due to the edge detector input which is switched to '1' when the
external interrupt is disabled by the OR register.
To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and
falling edge for disabling) has to be selected before changing the OR register bit and
configuring the appropriate sensitivity again.
Caution: In case a pin level change occurs during these operations (asynchronous signal input), as
interrupts are generated according to the current sensitivity, it is advised to disable all
interrupts before and to reenable them after the complete previous sequence in order to
avoid an external interrupt occurring on the unwanted edge.
This corresponds to the following steps:
1. To enable an external interrupt:
a) Set the interrupt mask with the SIM instruction (in cases where a pin level change
could occur)
b) Select rising edge
c) Enable the external interrupt through the OR register
d) Select the desired sensitivity if different from rising edge
e) Reset the interrupt mask with the RIM instruction (in cases where a pin level
change could occur)
2. To disable an external interrupt:
a) Set the interrupt mask with the SIM instruction SIM (in cases where a pin level
change could occur)
b) Select falling edge
c) Disable the external interrupt through the OR register
d) Select rising edge
9.2.2 Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain.
Table 17. DR register value and output pin status(1)
1. When switching from input to output mode, the DR register has to be written first to drive the correct level
on the pin as soon as the port is configured as an output.
DR Push-pull Open-drain
0V
SS VSS
1V
DD Floating
ST7LITEUS2, ST7LITEUS5 I/O ports
61/136
9.2.3 Alternate functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming under the
following conditions:
●When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open drain according to the peripheral).
●When the signal is going to an on-chip peripheral, the I/O pin must be configured in
floating input mode. In this case, the pin state is also digitally readable by addressing
the DR register.
Note: 1 Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input.
2 When an on-chip peripheral use a pin as input and output, this pin has to be configured in
input floating mode.
Figure 28. I/O port general block diagram
DR
DDR
OR
DATA BUS
PAD
VDD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT 1
0
OR SEL
DDR SEL
DR SEL
PULL-UP
CONDITION
P-BUFFER
(see table below)
N-BUFFER
PULL-UP
(see table below)
1
0
ANALOG
INPUT
If implemented
ALTERNATE
INPUT
VDD
DIODES
(see table below)
FROM
OTHER
BITS
EXTERNAL
SOURCE (eix)
INTERRUPT
POLARITY
SELECTION
CMOS
SCHMITT
TRIGGER
REGISTER
ACCESS
I/O ports ST7LITEUS2, ST7LITEUS5
62/136
Table 18. I/O port mode options(1)
1. NI stands for not implemented; Off for implemented not activated; On for implemented and activated.
Configuration mode Pull-up P-buffer
Diodes
to VDD to VSS
Input Floating with/without Interrupt Off Off
On On
Pull-up with/without Interrupt On
Output Push-pull Off On
Open Drain (logic level) Off
Table 19. I/O port configurations
Hardware configuration
INPUT (1)
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
reading the DR register will read the alternate function output status.
OPEN-DRAIN OUTPUT (2)
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
the alternate function reads the pin status given by the DR register content.
PUSH-PULL OUTPUT (2)
CONDITION
PAD
VDD
RPU
EXTERNAL INTERRUPT
POLARITY
DATA BUS
PULL-UP
INTERRUPT
DR REGISTER ACCESS
W
R
FROM
OTHER
PINS
SOURCE (eix)
SELECTION
DR
REGISTER
CONDITION
ALTERNATE INPUT
ANALOG INPUT
PAD
RPU
DATA BUS
DR
DR REGISTER ACCESS
R/W
VDD
ALTERNATEALTERNATE
ENABLE OUTPUT
REGISTER
PAD
RPU
DATA BUS
DR
DR REGISTER ACCESS
R/W
VDD
ALTERNATEALTERNATE
ENABLE OUTPUT
REGISTER
ST7LITEUS2, ST7LITEUS5 I/O ports
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Caution: The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
Warning: The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
9.3 Unused I/O pins
Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.8.
9.4 Low power modes
9.5 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Table 20. Effect of low power modes on I/O ports
Mode Description
Wait No effect on I/O ports. External interrupts cause the device to exit from Wait
mode.
Halt No effect on I/O ports. External interrupts cause the device to exit from Halt
mode.
Table 21. Description of interrupt events
Interrupt event Event flag Enable
control bit
Exit from
Wait
Exit from
Halt
External interrupt on selected
external event -DDRx
ORx Ye s Ye s
I/O ports ST7LITEUS2, ST7LITEUS5
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9.6 I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 29.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 29. Interrupt I/O port state transitions
The I/O port register configurations are summarized in Ta bl e 2 2 .
After reset, to configure PA3 as a general purpose output, the application has to program
the MUXCR0 and MUXCR1 registers. See Section 6.5: Register description on page 37
Table 22. Port configuration
Port Pin name
Input (DDR=0) Output (DDR=1)
OR = 0 OR = 1 OR = 0 OR = 1
Port A
PA0:2,
PA4 :5 floating pull-up interrupt open drain push-pull
PA3 - - open drain push-pull
Table 23. I/O port register map and reset values
Address
(Hex.)
Register
label 76543210
0000h
PAD R
Reset
value
MSB
0000000
LSB
0
0001h
PADDR
Reset
value
MSB
0000100
LSB
0
0002h
PAO R
Reset
value
MSB
0000001
LSB
0
01
floating/pull-up
interrupt
INPUT
00
floating
(reset state)
INPUT
10
open-drain
OUTPUT
11
push-pull
OUTPUT
XX = DDR, OR
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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10 On-chip peripherals
10.1 Lite timer (LT)
10.1.1 Introduction
The Lite Timer can be used for general-purpose timing functions. It is based on a free-
running 13-bit upcounter with two software-selectable timebase periods, an 8-bit input
capture register and watchdog function.
10.1.2 Main features
●Real-time clock
– 13-bit upcounter
– 1 ms or 2 ms timebase period (@ 8 MHz fOSC)
– Maskable timebase interrupt
●Input capture
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt mode capability
●Watchdog
– Enabled by hardware or software (configurable by option byte)
– Optional reset on HALT instruction (configurable by option byte)
– Automatically resets the device unless disable bit is refreshed
– Software reset (forced watchdog reset)
– Watchdog reset status flag
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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Figure 30. Lite timer block diagram
10.1.3 Functional description
The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the
counter rolls over from 1F39h to 00h. If fOSC = 8 MHz, then the time period between two
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR register.
When the timer overflows, the TBF bit is set by hardware and an interrupt request is
generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.
Watchdog
The watchdog is enabled using the WDGE bit. The normal watchdog timeout is 2 ms (@
fosc = 8 MHz), after which it then generates a reset.
To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is
cleared by hardware after tWDG. This means that software must write to the WDGD bit at
regular intervals to prevent a watchdog reset occurring. Refer to Figure 31.
If the watchdog is not enabled immediately after reset, the first watchdog timeout will be
shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms
period has already elapsed after the last MCU reset, the watchdog reset will take place as
soon as the WDGE bit is set. For these reasons, it is recommended to enable the watchdog
immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog
reset will not occur for at least 2 ms.
Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
LTCSR
WATCHDOG
13-bit UPCOUNTER
/2
8-bit
fLTIMER
fWDG
8 MSB
LTIC
fOSC
WDGDWDGE
WDG
TBF TBIETBICFICIE
WATCHDOG RESET
LTTB INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
LTICR
INPUT CAPTURE
REGISTER
1
01 or 2 ms
Timebase
(@ 8MHz
fOSC)
To 12-bit AT TImer
fLTIMER
RF
07
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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A watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the
WDGRF bit has to be set.
The WDGRF bit also acts as a flag, indicating that the watchdog was the source of the reset.
It is automatically cleared after it has been read.
Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is
enabled (by hardware or software), the microcontroller will be immediately reset.
Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR is not used.
Refer to the option byte description in the "device configuration and ordering information"
section.
Using Halt mode with the watchdog (option)
If the watchdog reset on Halt option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite
Timer stops counting and is no longer able to generate a watchdog reset until the
microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks.
If a reset is generated, the watchdog is disabled (reset state).
If Halt mode with watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Figure 31. Watchdog timing diagram
Input capture
The 8-bit input capture register is used to latch the free-running upcounter after a rising or
falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and
the LTICR register contains the MSB of the free-running upcounter. An interrupt is
generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
The LTICR is a read only register and always contains the data from the last input capture.
Input capture is inhibited if the ICF bit is set.
tWDG
fWDG
INTERNAL
WATCHDOG
RESET
WDGD BIT
SOFTWARE SETS
WDGD BIT
HARDWARE CLEARS
WDGD BIT
WATCHDOG RESET
(2ms @ 8 MHz fOSC)
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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10.1.4 Low power modes
10.1.5 Interrupts
They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt
mask in the CC register is reset (RIM instruction).
Figure 32. Input capture timing diagram
Table 24. Description of low power modes
Mode Description
Wait No effect on Lite timer
Active-Halt No effect on Lite timer
Halt Lite timer stops counting
Table 25. Interrupt events(1)
1. The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
Interrupt event Event
flag
Enable
control
bit
Exit
from
Wait
Exit
from
Halt
Exit
from
Active-halt
Timebase Event TBF TBIE Yes No Yes
IC Event ICF ICIE Yes No No
0004h
13-bit COUNTER
t
0001h
fOSC
xxh
0002h 0003h 0005h 0006h 0007h
04h
LTIC PIN
ICF FLAG
LTICR REGISTER
CLEARED
125 ns
(@ 8 MHz fOSC)
fCPU
BY S/W
07h
READING
LTIC REGISTER
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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10.1.6 Register description
Lite timer control/status register (LTCSR)
Reset value: 0000 0x00 (0xh)
7 0
ICIE ICF TB TBIE TBF WDGR WDGE WDGD
Read / Write
Bit 7 ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 ICF Input Capture Flag.
This bit is set by hardware and cleared by software by reading the LTICR register.
Writing to this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR
register
Bit 5 TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1 ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz)
Bit 4 TBIE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB) interrupt disabled
1: Timebase (TB) interrupt enabled
Bit 3 TBF Timebase Interrupt Flag.
This bit is set by hardware and cleared by software reading the LTCSR register.
Writing to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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Lite Timer Input Capture register (LTICR)
Reset value: 0000 0000 (00h)
Bit 2 WDGRF Force Reset/ Reset Status Flag
This bit is used in two ways: it is set by software to force a watchdog reset. It is set
by hardware when a watchdog reset occurs and cleared by hardware or by
software. It is cleared by hardware only when an LVD reset occurs. It can be cleared
by software after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
Bit 1 WDGE Watchdog Enable
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
Bit 0 WDGD Watchdog Reset Delay
This bit is set by software. It is cleared by hardware at the end of each tWDG period.
0: Watchdog reset not delayed
1: Watchdog reset delayed
7 0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Read only
Bit 7:0 ICR[7:0] Input capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit
in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a
rising or falling edge occurs on the LTIC pin.
Table 26. Lite timer register map and reset values
Address
(Hex.) Register label76543210
0B LTCSR
Reset value
ICIE
0
ICF
0
TB
0
TBIE
0
TBF
0
WDGRF
x
WDGE
0
WDGD
0
0C LTICR
Reset value
ICR7
0
ICR6
0
ICR5
0
ICR4
0
ICR3
0
ICR2
0
ICR1
0
ICR0
0
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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10.2 12-bit auto-reload timer (AT)
10.2.1 Introduction
The 12-bit auto-reload timer can be used for general-purpose timing functions. It is based on
a free-running 12-bit upcounter with a PWM output channel.
10.2.2 Main features
●12-bit upcounter with 12-bit auto-reload register (ATR)
●Maskable overflow interrupt
●PWM signal generator
●Frequency range 2 kHz - 4 MHz (@ 8 MHz fCPU)
– Programmable duty-cycle
– Polarity control
– Maskable compare interrupt
●Output compare function
Figure 33. Block diagram
10.2.3 Functional description
PWM mode
This mode allows a pulse width modulated signals to be generated on the PWM0 output pin
with minimum core processing overhead. The PWM0 output signal can be enabled or
disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is
configured as output push-pull alternate function.
Note: CMPF0 is available in PWM mode (see Section : PWM0 control/status register
(PWM0CSR)).
ATCSR
CMPIEOVFIEOVFCK0CK1000
12-BIT AUTO-RELOAD VALUE
12-BIT UPCOUNTER
CMPF0 bit
CMPF0
CMP INTERRUPT
REQUEST
OVF INTERRUPT
REQUEST
fCPU
ATR
PWM GENERATION
POL-
ARITY
OP0 bit
PWM0
COMP-
PARE
fCOUNTER
fPWM
OUTPUT CONTROL
OE0 bit
CNTR
(1 ms timebase
fLTIMER
DCR0H DCR0L
Update on OVF Event
Preload Preload
@ 8 MHz)
70
on OVF Event
0
1
12-BIT DUTY CYCLE VALUE (shadow)
OE0 bit
IF OE0=1
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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PWM frequency and duty cycle
The PWM signal frequency (fPWM) is controlled by the counter period and the ATR register
value.
fPWM = fCOUNTER / (4096 - ATR)
Following the above formula, if fCPU is 8 MHz, the maximum value of fPWM is 4 MHz (ATR
register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).
Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution below.
When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter,
the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0
signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals
is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register
must be greater than the contents of the ATR register.
The polarity bit can be used to invert the output signal.
The maximum available resolution for the PWM0 duty cycle is:
Resolution = 1 / (4096 - ATR)
Note: To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum
resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by
changing the polarity.
Caution: As soon as the DCR0H is written, the compare function is disabled and will start only when
the DCR0L value is written. If the DCR0H write occurs just before the compare event, the
signal on the PWM output may not be set to a low level. In this case, the DCRx register
should be updated just after an OVF event. If the DCR and ATR values are close, then the
DCRx register should be updated just before an OVF event, in order not to miss a compare
event and to have the right signal applied on the PWM output.
Figure 34. PWM function
DUTY CYCLE
REGISTER
AUTO-RELOAD
REGISTER
PWM0 OUTPUT
t
4095
000
WITH OE0=1
AND OP0=0
(ATR)
(DCR0)
WITH OE0=1
AND OP0=1
COUNTER
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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Figure 35. PWM signal example
Output compare mode
To use this function, the OE bit must be 0, otherwise the compare is done with the shadow
register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H
and DCR0L registers. This value will be loaded immediately (without waiting for an OVF
event).
The DCR0H must be written first, the output compare function starts only when the DCR0L
value is written.
When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L
registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is
generated if the CMPIE bit is set.
Note: The output compare function is only available for DCRx values other than 0 (reset value).
Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value
has not yet been written (in this case, the shadow register will contain the new DCR0H value
and the old DCR0L value), then:
– If OE=1 (PWM mode): the compare is done between the timer counter and the
shadow register (and not DCRx)
– If OE=0 (OCMP mode): the compare is done between the timer counter and
DCRx. There is no PWM signal.
The compare between DCRx or the shadow register and the timer counter is
locked until DCR0L is written.
10.2.4 Low power modes
COUNTER
PWM0 OUTPUT
t
WITH OE0=1
AND OP0=0
FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh
DCR0=FFEh
ATR= FFDh
fCOUNTER
Table 27. Description of low power modes
Mode Description
Slow The input frequency is divided by 32
Wait No effect on AT timer
Active-halt AT timer halted except if CK0=1, CK1=0 and OVFIE=1
Halt AT timer halted
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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10.2.5 Interrupts
10.2.6 Register description
Timer control status register (ATCSR)
Reset value: 0000 0000 (00h)
Table 28. Interrupt events
Interrupt event (1)
1. The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC
register is reset (RIM instruction).
Event
flag
Enable
control
bit
Exit
from
Wait
Exit
from
Halt
Exit
from
Active-halt
Overflow event OVF OVFIE Yes No Yes(2)
2. Only if CK0=1 and CK1=0
CMP event CMPFx CMPIE Yes No No
7 0
0 0 0 CK1 CK0 OVF OVFIE CMPIE
Read/write
Bits 7:5 Reserved, must be kept cleared.
Bits 4:3 CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and cleared by hardware after a reset.
They select the clock frequency of the counter (see Table 29: Counter clock
selection).
Bit 2 OVF Overflow flag.
This bit is set by hardware and cleared by software by reading the ATCSR register.
It indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
When set, the OVF bit stays high for 1 fCOUNTER cycle (up to 1ms depending on the
clock selection) after it has been cleared by software.
Bit 1 OVFIE Overflow interrupt enable.
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
Bit 0 CMPIE Compare interrupt enable.
This bit is read/write by software and clear by hardware after a reset. It allows to
mask the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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Counter register high (CNTRH)
Reset value: 0000 0000 (00h)
Counter register low (CNTRL)
This 12-bit register is read by software and cleared by hardware after a reset. The counter is
incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software
should read the counter value in two consecutive read operations. As there is no latch, it is
recommended to read LSB first. In this case, CNTRH can be incremented between the two read
operations and to have an accurate result when ftimer = fCPU, special care must be taken when
CNTRL values close to FFh are read.
When a counter overflow occurs, the counter restarts from the value specified in the ATR register.
Reset value: 0000 0000 (00h)
Auto reload register (ATRH)
Reset value: 0000 0000 (00h)
Table 29. Counter clock selection
Counter clock selection CK1 CK0
OFF 0 0
fLTIM ER (1 ms timebase @ 8 MHz) 0 1
fCPU 10
Reserved 1 1
15 8
0 0 0 0 CN11 CN10 CN9 CN8
Read only
7 0
CN7 CN6 CN5 CN4 CN3 CN2 CN1 CN0
Read only
Bits 15:12 Reserved, must be kept cleared.
Bits 11:0 CNTR[11:0] Counter value.
15 8
0 0 0 0 AT R 1 1 AT R 1 0 AT R 9 AT R 8
Read/Write
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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Auto reload register (ATRL)
This is a 12-bit register which is written by software. The ATR register value is automatically
loaded into the upcounter when an overflow occurs. The register value is used to set the
PWM frequency.
Reset value: 0000 0000 (00h)
PWM0 duty cycle register high (DCR0H)
Reset value: 0000 0000 (00h)
PWM0 duty cycle register low (DCR0L)
This 12-bit value is written by software. The high register must be written first.
In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of
the PWM0 output signal (see Figure 34). In Output Compare mode, (OE0=0 in the PWMCR
register) they define the value to be compared with the 12-bit upcounter value.
Reset value: 0000 0000 (00h)
7 0
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
Read/Write
Bits 15:12 Reserved, must be kept cleared.
Bits 11:0 ATR[11:0] Auto-reload Register.
15 8
0 0 0 0 DCR11 DCR10 DCR9 DCR8
Read/Write
7 0
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
Read/Write
Bits 15:12 Reserved, must be kept cleared.
Bits 11:0 DCR[11:0] PWMx duty cycle value
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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PWM0 control/status register (PWM0CSR)
Reset value: 0000 0000 (00h)
PWM output control register (PWMCR)
Reset value: 0000 0000 (00h)
7 0
000000OP0CMPF0
Read/Write
Bit 7:2 Reserved, must be kept cleared.
Bit 1 OP0 PWM0 output polarity.
This bit is read/write by software and cleared by hardware after a reset. This bit
selects the polarity of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
Bit 0 CMPF0 PWM0 Compare Flag.
This bit is set by hardware and cleared by software by reading the PWM0CSR
register. It indicates that the upcounter value matches the DCR0 register value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
7 0
0000000OE0
Read/Write
Bits 7:1 Reserved, must be kept cleared.
Bit 0 OE0 PWM0 Output enable.
This bit is set and cleared by software.
0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O)
1: PWM0 output enabled
Table 30. Register map and reset values
Address
(Hex.)
Register
label 76543210
0D ATCSR
Reset value 000
CK1
0
CK0
0
OVF
0
OVFIE
0
CMPIE
0
0E CNTRH
Reset value 0000
CN11
0
CN10
0
CN9
0
CN8
0
0F CNTRL
Reset value
CN7
0
CN6
0
CN5
0
CN4
0
CN3
0
CN2
0
CN1
0
CN0
0
10 ATRH
Reset value 0000
AT R 1 1
0
ATR 10
0
ATR 9
0
AT R 8
0
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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11 ATRL
Reset value
AT R 7
0
ATR 6
0
ATR 5
0
ATR 4
0
ATR 3
0
ATR 2
0
ATR 1
0
AT R 0
0
12 PWMCR
Reset value 0000000
OE0
0
13 PWM0CSR
Reset value 000000
OP
0
CMPF0
0
17 DCR0H
Reset value 0000
DCR11
0
DCR10
0
DCR9
0
DCR8
0
18 DCR0L
Reset value
DCR7
0
DCR6
0
DCR5
0
DCR4
0
DCR3
0
DCR2
0
DCR1
0
DCR0
0
Table 30. Register map and reset values (continued)
Address
(Hex.)
Register
label 76543210
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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10.3 10-bit A/D converter (ADC)
10.3.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 5
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 5 different sources.
The result of the conversion is stored in a 10-bit Data register. The A/D converter is
controlled through a Control/Status register.
10.3.2 Main features
●10-bit conversion
●Up to 5 channels with multiplexed input
●Linear successive approximation
●Data register (DR) which contains the results
●Conversion complete status flag
●On/off bit (to reduce consumption)
The block diagram is shown in Figure 36.
10.3.3 Functional description
Analog power supply
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to
device pin out description) they are internally connected to the VDD and VSS pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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Figure 36. ADC block diagram
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Electrical
Characteristics Section.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the alloted time.
A/D conversion phases
The A/D conversion is based on two conversion phases:
●Sample capacitor loading [duration: tSAMPLE]
During this phase, the VAIN input voltage to be measured is loaded into the CADC
sample capacitor.
●A/D conversion [duration: tHOLD]
During this phase, the A/D conversion is computed (8 successive approximations
CH2 CH1EOC SPEED ADON 0 CH0 ADCCSR
AIN0
AIN1 ANALOG TO DIGITAL
CONVERTER
AINx
ANALOG
MUX
D4 D3D5D9 D8 D7 D6 D2
ADCDRH
3
D1 D0
ADCDRL 00 00SLOW 0
0
RADC
CADC
HOLD CONTROL
fADC
fCPU
0
1
1
0
DIV 2
DIV 4
SLOW
bit
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
81/136
cycles) and the CADC sample capacitor is disconnected from the analog input pin to get
the optimum analog to digital conversion accuracy.
●The total conversion time:
tCONV = tSAMPLE + tHOLD
While the ADC is on, these two phases are continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous
measurement load. The advantage of this behavior is that it minimizes the current
consumption on the analog pin in case of single input channel measurement.
A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the “I/O
ports” chapter. Using these pins as analog inputs does not affect the ability of the port to be
read as a logic input.
In the ADCCSR register, select the CS[2:0] bits to assign the analog channel to convert.
ADC conversion mode
In the ADCCSR register, set the ADON bit to enable the A/D converter and to start the
conversion. From this time on, the ADC performs a continuous conversion of the selected
channel. When a conversion is complete:
●The EOC bit is set by hardware.
●The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read ADCDRL
3. Read ADCDRH. This clears EOC automatically.
To read only 8 bits, perform the following steps:
1. Poll EOC bit
1. Read ADCDRH. This clears EOC automatically.
10.3.4 Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 31. Effect of low power modes
Mode Description
Wait No effect on A/D converter
Halt
A/D converter disabled.
After wakeup from Halt mode, the A/D converter requires a stabilization time
tSTAB (see Section 12: Electrical characteristics) before accurate conversions
can be performed.
On-chip peripherals ST7LITEUS2, ST7LITEUS5
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10.3.5 Interrupts
None.
10.3.6 Register description
Control/Status register (ADCCSR)
Reset value: 0000 0000 (00h)
Note: A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the
EOC bit and starts a new conversion.
7 0
EOC SPEED ADON 0 0 CH2 CH1 CH0
Read/Write (Except bit 7 read only)
Bit 7 EOC End of Conversion
This bit is set by hardware. It is cleared by software reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete
Bit 6 SPEED ADC clock selection
This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description.
Bit 5 ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bits 4:3 Reserved. Must be kept cleared.
Bits 2:0 CH[2:0] Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
Table 32. Channel selection
Channel pin CH2 CH1 CH0
AIN0 0 0 0
AIN1 0 0 1
AIN2 0 1 0
AIN3 0 1 1
AIN4 1 0 0
ST7LITEUS2, ST7LITEUS5 On-chip peripherals
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ADC data register high (ADCDRH)
Reset value: 0000 0000 (00h)
ADC control/data register Low (ADCDRL)
Reset value: 0000 0000 (00h)
7 0
D9 D8 D7 D6 D5 D4 D3 D2
Read only
Bits 7:0 D[9:2] MSB of Analog Converted value
7 0
0000SLOW0D1D0
Read/write
Bits 7:4 Reserved. Forced by hardware to 0.
Bit 3 SLOW Slow mode
This bit is set and cleared by software. It is used together with the SPEED bit to
configure the ADC clock speed as shown on the table below (see Tabl e 3 3 :
Configuring the ADC clock speed).
Bit 2 Reserved. Forced by hardware to 0.
Bits 1:0 D[1:0] LSB of Analog Converted value
Table 33. Configuring the ADC clock speed
fADC SLOW SPEED
fCPU/2 0 0
fCPU 01
fCPU/4 1 x
Table 34. ADC register map and reset values
Address
(Hex.)
Register
label 76543210
0034h ADCCSR
Reset value
EOC
0
SPEED
0
ADON
0
0
0
0
0
CH2
0
CH1
0
CH0
0
0035h ADCDRH
Reset value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
0036h ADCDRL
Reset value
0
0
0
0
0
0
0
0
SLOW
0
0
0
D1
0
D0
0
Instruction set ST7LITEUS2, ST7LITEUS5
84/136
11 Instruction set
11.1 ST7 addressing modes
The ST7 Core features 17 different addressing modes which can be classified in seven main
groups:
The ST7 instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two submodes
called long and short:
●Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 35. Description of addressing modes
Addressing mode Example
Inherent nop
Immediate ld A,#$55
Direct ld A,$55
Indexed ld A,($55,X)
Indirect ld A,([$55],X)
Relative jrne loop
Bit operation bset byte,#5
Table 36. ST7 addressing mode overview (1)
Mode Syntax Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
Inherent nop + 0
Immediate ld A,#$55 + 1
Short Direct ld A,$10 00..FF + 1
Long Direct ld A,$1000 0000..FFFF + 2
No Offset Direct Indexed ld A,(X) 00..FF + 0 (with X register)
+ 1 (with Y register)
Short Direct Indexed ld A,($10,X) 00..1FE + 1
Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2
Short Indirect ld A,[$10] 00..FF 00..FF byte + 2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2
ST7LITEUS2, ST7LITEUS5 Instruction set
85/136
11.1.1 Inherent mode
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2
Relative Direct jrne loop PC-128/PC+1271) + 1
Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF byte + 2
Bit Direct bset $10,#7 00..FF + 1
Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2
Bit Direct Relative btjt $10,#7,skip 00..FF + 2
Bit Indirect Relative btjt
[$10],#7,skip 00..FF 00..FF byte + 3
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
Table 36. ST7 addressing mode overview (continued)(1)
Mode Syntax Destination/
source
Pointer
address
Pointer
size
Length
(bytes)
Table 37. Instructions supporting inherent addressing mode
Inherent instruction Function
NOP No operation
TRAP S/W Interrupt
WFI Wait For Interrupt (low power mode)
HALT Halt Oscillator (lowest power mode)
RET Subroutine return
IRET Interrupt subroutine return
SIM Set interrupt mask
RIM Reset interrupt mask
SCF Set carry flag
RCF Reset carry flag
RSP Reset stack pointer
LD Load
CLR Clear
PUSH/POP Push/Pop to/from the stack
INC/DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 complement
MUL Byte multiplication
SLL, SRL, SRA, RLC, RRC Shift and rotate operations
SWAP Swap nibbles
Instruction set ST7LITEUS2, ST7LITEUS5
86/136
11.1.2 Immediate
Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte
contains the operand value.
11.1.3 Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (short) addressing mode
the address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
addressing space.
Direct (long) addressing mode
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
11.1.4 Indexed mode (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
Indexed mode (no offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed mode (short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
addressing space.
Indexed mode (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
Table 38. Instructions supporting inherent immediate addressing mode
Immediate instruction Function
LD Load
CP Compare
BCP Bit compare
AND, OR, XOR Logical operations
ADC, ADD, SUB, SBC Arithmetic operations
ST7LITEUS2, ST7LITEUS5 Instruction set
87/136
11.1.5 Indirect modes (short, long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect mode (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect mode (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
11.1.6 Indirect indexed modes (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect indexed mode (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect indexed mode (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
Table 39. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Instructions Function
Long and short instructions
LD Load
CP Compare
AND, OR, XOR Logical operations
ADC, ADD, SUB, SBC Arithmetic addition/subtraction operations
BCP Bit compare
Short instructions only
CLR Clear
INC, DEC Increment/decrement
TNZ Test negative or zero
Instruction set ST7LITEUS2, ST7LITEUS5
88/136
11.1.7 Relative modes (direct, indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed
offset to it.
The relative addressing mode consists of two submodes:
Relative mode (Direct)
The offset follows the opcode.
Relative mode (Indirect)
The offset is defined in memory, of which the address follows the opcode.
11.2 Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
CPL, NEG 1 or 2 complement
BSET, BRES Bit operations
BTJT, BTJF Bit test and jump operations
SLL, SRL, SRA, RLC, RRC Shift and rotate operations
SWAP Swap nibbles
CALL, JP Call or jump subroutine
Table 39. Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes (continued)
Instructions Function
Table 40. Instructions supporting relative modes
Available relative direct/indirect instructions Function
JRxx Conditional jump
CALLR Call relative
Table 41. ST7 instruction set
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit operation BSET BRES
Conditional bit test and branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
ST7LITEUS2, ST7LITEUS5 Instruction set
89/136
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the number of bytes required to compute
the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using
indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
11.2.1 Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented. If a code to be executed does not
correspond to any opcode or prebyte value, a reset is generated. This, combined with the
watchdog, allows the detection and recovery from an unexpected fault or interference.
Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
Shift and rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional jump or call JRA JRT JRF JP CALL CALLR NOP RET
Conditional branch JRxx
Interruption management TRAP WFI HALT IRET
Condition code flag modification SIM RIM SCF RCF
Table 41. ST7 instruction set (continued)
Table 42. Illegal opcode detection
Mnemo Description Function/example Dst Src H I N Z C
ADC Add with carry A = A + M + C A M H - N Z C
ADD Addition A = A + M A M H - N Z C
AND Logical and A = A . M A M - - N Z -
BCP Bit compare A, Memory tst (A . M) A M - - N Z -
Instruction set ST7LITEUS2, ST7LITEUS5
90/136
BRES Bit Reset bres Byte, #3 M - - - - - -
BSET Bit Set bset Byte, #3 M - - - - - -
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M - - - - - C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M - - - - - C
CALL Call subroutine - - - - - - -
CALLR Call subroutine relative - - - - - - -
CLR Clear reg, M - - - 0 1 -
CP Arithmetic compare tst(Reg - M) reg M - - N Z C
CPL One Complement A = FFH-A reg, M - - - N Z 1
DEC Decrement dec Y reg, M - - - N Z -
HALT Halt - - - 0 - - -
IRET Interrupt routine return Pop CC, A, X, PC - - H I N Z C
INC Increment inc X reg, M - - - N Z -
JP Absolute jump jp [TBL.w] - - - - - - -
JRA Jump relative always - - - - - - -
JRT Jump relative - - - - - - -
JRF Never jump jrf * - - - - - - -
JRIH Jump if ext. interrupt = 1 - - - - - - -
JRIL Jump if ext. interrupt = 0 - - - - - - -
JRH Jump if H = 1 H = 1 ? - - - - - - -
JRNH Jump if H = 0 H = 0 ? - - - - - - -
JRM Jump if I = 1 I = 1 ? - - - - - - -
JRNM Jump if I = 0 I = 0 ? - - - - - - -
JRMI Jump if N = 1 (minus) N = 1 ? - - - - - - -
JRPL Jump if N = 0 (plus) N = 0 ? - - - - - - -
JREQ Jump if Z = 1 (equal) Z = 1 ? - - - - - - -
JRNE Jump if Z = 0 (not equal) Z = 0 ? - - - - - - -
JRC Jump if C = 1 C = 1 ? - - - - - - -
JRNC Jump if C = 0 C = 0 ? - - - - - - -
JRULT Jump if C = 1 Unsigned < - - - - - - -
JRUGE Jump if C = 0 Jmp if unsigned ≥- - -----
JRUGT Jump if (C + Z = 0) Unsigned > - - - - - - -
JRULE Jump if (C + Z = 1) Unsigned ≤- - -----
LD Load dst ≤ src reg, M M, reg - - N Z -
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 - - - 0
Table 42. Illegal opcode detection (continued)
Mnemo Description Function/example Dst Src H I N Z C
ST7LITEUS2, ST7LITEUS5 Instruction set
91/136
NEG Negate (2's compl) neg $10 reg, M - - - N Z C
NOP No operation - - - - - - -
OR OR operation A = A + M A M - - N Z -
POP Pop from the stack pop reg reg M - - - - -
pop CC CC M H I N Z C
PUSH Push onto the stack push Y M reg, CC - - - - -
RCF Reset carry flag C = 0 - - - - - - 0
RET Subroutine return - - - - - - -
RIM Enable Interrupts I = 0 - - - 0 - - -
RLC Rotate left true C C ≤ Dst ≤ C reg, M - - - N Z C
RRC Rotate right true C C ≥ Dst ≥ C reg, M - - - N Z C
RSP Reset Stack Pointer S = Max allowed - - - - - - -
SBC Subtract with carry A = A - M - C A M - - N Z C
SCF Set carry flag C = 1 - - - - - - 1
SIM Disable interrupts I = 1 - - - 1 - - -
SLA Shift left arithmetic C ≤ Dst ≤ 0reg, M---NZC
SLL Shift left logic C ≤ Dst ≤ 0reg, M---NZC
SRL Shift right logic 0 ≥ Dst ≥ Creg, M---0ZC
SRA Shift right arithmetic Dst7 ≥ Dst ≥ C reg, M - - - N Z C
SUB Subtraction A = A - M A M - - N Z C
SWAP SWAP nibbles Dst[7..4] ≤ ≥Dst[3..0] reg, M - - - N Z -
TNZ Test for Neg & Zero tnz lbl1 - - - - N Z -
TRAP S/W trap S/W interrupt - - - 1 - -
WFI Wait for interrupt - - - 0 - - -
XOR Exclusive OR A = A XOR M A M - - N Z -
Table 42. Illegal opcode detection (continued)
Mnemo Description Function/example Dst Src H I N Z C
Electrical characteristics ST7LITEUS2, ST7LITEUS5
92/136
12 Electrical characteristics
12.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
12.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA=25 °C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
12.1.2 Typical values
Unless otherwise specified, typical data are based on TA=25 °C, VDD=5 V (for the
4.5 V≤VDD≤5.5 V voltage range), VDD=3.75 V (for the 3 V≤VDD≤4.5 V voltage range) and
VDD=2.7 V (for the 2.4 V≤VDD≤3 V voltage range). They are given only as design guidelines
and are not tested.
12.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
12.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 37.
Figure 37. Pin loading conditions
CL
ST7 PIN
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
93/136
12.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 38.
Figure 38. Pin input voltage
12.2 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected
change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down
resistor (typical: 10 kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or
VSS according to their reset configuration.
VIN
ST7 PIN
Table 43. Voltage characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 7.0 V
VIN Input voltage on any pin(1)
1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
VSS-0.3 to VDD+0.3
VESD(HBM)
Electrostatic discharge voltage (Human Body
Model) see Section 12.7.2
VESD(MM)
Electrostatic discharge voltage (Machine
Model) see Section 12.7.2
Electrical characteristics ST7LITEUS2, ST7LITEUS5
94/136
12.3 Operating conditions
12.3.1 General operating conditions
TA = -40 to +125 °C unless otherwise specified.
Table 44. Current characteristics
Symbol Ratings Maximum value Unit
IVDD Total current into VDD power lines (source)(1)
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
75
mA
IVSS Total current out of VSS ground lines (sink)(1) 150
IIO
Output current sunk by any standard I/O and
control pin 20
Output current sunk by any high sink I/O pin 40
Output current source by any I/Os and control
pin -25
IINJ(PIN) (2)(3)
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents
throughout the device including the analog inputs. To avoid undesirable effects on the analog functions,
care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the
analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject
the current as far as possible from the analog input pins.
Injected current on RESET pin ± 5
Injected current on any other pin(4)
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
± 5
ΣIINJ(PIN)(2) Total injected current (sum of all I/O and control
pins)(4) ± 20
Table 45. Thermal characteristics
Symbol Ratings value Unit
TSTG Storage temperature range -65 to +150 °C
TJMaximum junction temperature (see Section 13: Package characteristics)
Table 46. General operating conditions
Symbol Parameter Conditions Min Max Unit
VDD Supply voltage fCPU = 4 MHz max. 2.4 5.5 V
fCPU = 8 MHz max. 3.3 5.5
fCPU CPU clock frequency 3.3 V≤ VDD≤5.5 V up to 8 MHz
2.4 V≤VDD<3.3 V up to 4
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
95/136
Figure 39. fCPU maximum operating frequency versus VDD supply voltage
12.3.2 Operating conditions with low voltage detector (LVD)
TA = -40 to 125 °C, unless otherwise specified
fCPU [MHz]
SUPPLY VOLTAGE [V]
8
4
2
0
2.0 2.4
3.3 3.5 4.0 4.5 5.0
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
5.5
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
2.7
Table 47. Operating characteristics with LVD
Symbol Parameter Conditions Min Typ Max Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
High threshold
Med. threshold
Low threshold
3.9
3.2
2.5
4.2
3.5
2.7
4.5
3.8
3.0 V
VIT-(LVD)
Reset generation threshold
(VDD fall)
High threshold
Med. threshold
Low threshold
3.7
3.0
2.4
4.0
3.3
2.6
4.3
3.6
2.9
Vhys
LVD voltage threshold
hysteresis VIT+(LVD)-VIT-(LVD) 150 mV
VtPOR VDD rise time rate (1)(2)
1. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset
release. When the VDD slope is outside these values, the LVD may not release properly the reset of the MCU
2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is
recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 61 on
page 114.
20 μs/V
IDD(LVD)
(3)
3. Not tested in production.
LVD/AVD current consumption VDD = 5 V 220 μA
Electrical characteristics ST7LITEUS2, ST7LITEUS5
96/136
12.3.3 Auxiliary voltage detector (AVD) thresholds
TA = −40 to 125°C, unless otherwise specified.
12.3.4 Internal RC oscillator
To improve clock stability and frequency accuracy, it is recommended to place a decoupling
capacitor, typically 100 nF, between the VDD and VSS pins as close as possible to the ST7
device.
Internal RC oscillator calibrated at 5.0 V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option
byte).
Table 48. Operating characteristics with AVD(1)
1. Refer to Section : Monitoring the VDD main supply.
Symbol Parameter Conditions Min
(2)
2. Not tested in production, guaranteed by characterization.
Typ
(2) Max
(2) Unit
VIT+(AVD)
1 => 0 AVDF flag toggle threshold
(VDD rise)
High threshold
Med. threshold
Low threshold
4.0
3.4
2.6
4.4
3.7
2.9
4.8
4.1
3.2 V
VIT-(AVD)
0 => 1 AVDF flag toggle threshold
(VDD fall)
High threshold
Med. threshold
Low threshold
3.9
3.3
2.5
4.3
3.6
2.8
4.7
4.0
3.1
Vhys AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 150 mV
Table 49. Voltage drop between AVD flag set and LVD reset generation
Parameter Min (1)
1. Not tested in production, guaranteed by characterization.
Typ (1) Max (1) Unit
AVD med. threshold - AVD low. threshold 800 850 950
mV
AVD high. threshold - AVD low threshold 1400 1450 1550
AVD high. threshold - AVD med. threshold 600 650 750
AVD low threshold - LVD low threshold 100 200 250
AVD med. threshold - LVD low threshold 950 1050 1150
AVD med. threshold - LVD med. threshold 250 300 400
AVD high. threshold - LVD low threshold 1600 1700 1800
AVD high. threshold - LVD med. threshold 900 1000 1050
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
97/136
Internal RC oscillator calibrated at 3.3 V
The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option
byte).
Table 50. Internal RC oscillator characteristics (5.0 V calibration)
Symbol Parameter Conditions Min Typ Max Unit
fRC
Internal RC oscillator
frequency
RCCR = FF (reset value),
TA= 25 °C, VDD= 5 V 4.4
MHz
RCCR = RCCR0(1), TA= 25 °C, VDD
= 5 V 8
ACCRC
Accuracy of internal RC
oscillator with
RCCR=RCCR0(1)
TA= 25 °C, VDD = 4.5 to 5.5 V (2) -2.0 +2.0 %
TA= 0 to +85 °C,
VDD = 4.5 to 5.5 V (2) -2.5 +4.0 %
TA= 0 to +125 °C,
VDD= 4.5 to 5.5 V (2) -3.0 +5.0 %
TA= -40 °C to 0 °C,
VDD= 4.5 to 5.5 V (2) -4.0 +2.5 %
tsu(RC) RC oscillator setup time TA= 25°C, VDD= 5 V 4 (2) μs
1. See Section 6.2: Internal RC oscillator adjustment
2. Tested in production at 5.0 V only
Table 51. Internal RC oscillator characteristics (3.3 V calibration)
Symbol Parameter Conditions Min Typ Max Unit
fRC
Internal RC oscillator
frequency
RCCR = FF (reset value),
TA=25 °C,VDD= 3.3 V 4.3
MHz
RCCR = RCCR1(1) ,
TA=25 °C,VDD= 3.3 V 8
ACCRC
Accuracy of internal RC
oscillator with
RCCR=RCCR1(1)
TA=25°C, VDD = 3.0 to 3.6 V(2) -1.0 +1.0 %
TA=0 to +85 °C, VDD = 3.0 to 3.6 V (2) -2.5 +4.0 %
TA=0 to +125 °C, VDD = 3.0 to 3.6 V (2) -3.0 +5.0 %
TA = -40 °C to 0 °C,
VDD = 3.0 to 3.6 V (2) -4.0 +2.5 %
tsu(RC) RC oscillator setup time TA= 25 °C, VDD = 3.3 V 4 (2) μs
1. See Section 6.2: Internal RC oscillator adjustment
2. Tested in production at 3.3 V only
Electrical characteristics ST7LITEUS2, ST7LITEUS5
98/136
Figure 40. Typical accuracy with RCCR=RCCR0 vs VDD= 2.4-6.0 V and temperature
Figure 41. Typical accuracy with RCCR=RCCR1 vs VDD= 2.4-6.0V and temperature
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.8
3.2
3.6
4.0
4.4
4.8
5.2
5.6
6.0
Accuracy (%)
RC5V@-45C
RC5V@25C
RC5V@90C
RC5V@130C
RC5V@0C
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
5.2
5.6
6.0
Accuracy (%)
RC3.3V@-45C
RC3.3V@25C
RC3.3V@90C
RC3.3V@130C
RC3.3V@0C
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
99/136
12.4 Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped). Refer to Section 12.4.2: Internal RC oscillator supply current
characteristics.
TA = -40 to +125 °C unless otherwise specified.
12.4.1 Supply current
Table 52. Supply current characteristics
Symbol Parameter Conditions Typ Max Unit
IDD
Supply current in Run mode (1)
VDD=5 V
fCPU = 4 MHz 2.5 4.5(2)
mA
fCPU = 8 MHz 5.0 7.5
Supply current in Wait mode(3) fCPU = 4 MHz 0.85 2.0(2)
fCPU = 8 MHz 1.2 3.5
Supply current in Wait mode(4) fCPU/32 = 250 kHz 600 950
μA
Supply current in Slow-Wait mode(5) fCPU/32 = 250 kHz 450 750
Supply current in AWUFH mode (6)(7) 45 100(2)
Supply current in Active-halt mode 100 250
Supply current in Halt mode (8) TA = 85 °C 0.5 3.0
TA = 125 °C 0.5 5.0
Supply current in Run mode(1)
VDD=3 V
fCPU = 4 MHz 1.30 2.0 (2)
mA
Supply current in Wait mode(3) fCPU = 4 MHz 0.36 0.5 (2)
Supply current in Slow mode(4) fCPU/32 = 250 kHz 300 400(2)
μA
Supply current in Slow-wait mode (5) fCPU/32 = 250 kHz 250 350(2)
Supply current in AWUFH mode(6)(7) 20 50 (2)
Supply current in Active-halt mode 90 150(2)
Supply current in Halt mode(8) TA = 85 °C 0.25 2.5 (2)
TA = 125 °C 0.25 4.5 (2)
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in
reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. Data based on characterization, not tested in production.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
4. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
5. Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
8. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
Electrical characteristics ST7LITEUS2, ST7LITEUS5
100/136
12.4.2 Internal RC oscillator supply current characteristics
Table 53. Internal RC oscillator supply current
Symbol Parameter Conditions Min Typ Max (1) Unit
IDD
Supply current in Run mode (2)
RC oscillator calibrated at 5.0V
TA=25 °C, int RC = 4 MHz 3.2 5.5
mA
TA=25 °C, int RC = 8 MHz 5.7 8.5
TA=25 °C, AWU RC 0.13 0.2
Supply current in Wait mode (3) TA=25 °C, int RC = 4 MHz 1.5 3.0
TA=25 °C, int RC = 8 MHz 1.9 4.5
Supply current in Slow mode (4) TA=25 °C, int RC/32 = 250 kHz 1.3 2.0
Supply current in Slow-Wait
mode (5) TA=25 °C, int RC/32 = 250 kHz 1.1 1.8
Supply current in Active-halt
mode 0.8 1.25
IDD
Supply current in Run mode (2)
RC oscillator calibrated at 3.3 V
TA=25 °C, int RC = 4 MHz 2.0 3.0
mA
TA=25 °C, int RC = 2 MHz 1.3 2.0
TA=25 °C, AWU RC 0.1 0.18
Supply current in Wait mode (3) TA=25 °C, int RC = 4 MHz 1.0 1.6
TA=25 °C, int RC = 2 MHz 0.9 1.5
Supply current in Slow mode (4) TA=25 °C, int RC/32 = 250 kHz 0.95 1.5
Supply current in Slow-Wait
mode (5) TA=25 °C, int RC/32 = 250 kHz 0.85 1.4
Supply current in Active-halt
mode 0.8 1.3
1. Data based on characterization results, not tested in production.
2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in
reset state; CPU clock provided by the internal RC, LVD disabled.
3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; CPU clock provided by
the internal RC, LVD disabled.
4. Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no
load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.
5. Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS
(no load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
101/136
Figure 42. Typical IDD in run mode vs. internal clock frequency and VDD
Figure 43. Typical IDD in WFI mode vs. internal clock frequency and VDD
Figure 44. Typical IDD in Slow, Slow-wait and Active-halt mode vs VDD & int
RC = 8 MHz
Idd RUN mode @amb vs int clock freq
0.00
1.00
2.00
3.00
4.00
5.00
6.00
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
VDD [V]
Idd RUN [mA]
RC 8 MHz
RC 4 MHz
RC 2 MHz
AWU
Idd WFI mode @amb vs int RC freq
0.700
1.200
1.700
2.200
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
5.6
VDD [V]
Idd RUN [mA]
8 MHz
4 MHz
2 MHz
Idd slow, slowwait & acthalt mode,
int Rc 8Mhz@amb
0.700
0.900
1.100
1.300
1.500
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
5.6
VDD [V]
Idd RUN [mA]
Slo w
slowwait
act hlt
Electrical characteristics ST7LITEUS2, ST7LITEUS5
102/136
Figure 45. IDD vs temp @VDD 5 V & int RC = 8 MHz
Figure 46. IDD vs temp @VDD 5 V & int RC = 4 MHz
Figure 47. IDD vs temp @VDD 5 V & int RC = 2 MHz
0.0
1.0
2.0
3.0
4.0
5.0
6.0
-45
25
90
130
Temp [°C]
Idd [mA]
run
wfi
slow
slowwait
acthlt
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
45
25
90
30
Idd [mA]
run
wfi
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-45
25
90
130
Temp [°C]
Idd [mA]
run
wfi
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
103/136
12.4.3 On-chip peripherals
12.5 Clock and timing characteristics
Subject to general operating conditions for VDD, fOSC, and TA.
Table 54. On-chip peripheral characteristics
Symbol Parameter Conditions Typ (1) Unit
IDD(AT) 12-bit auto-reload timer supply current (2) fCPU = 4 MHz VDD= 3.0 V 15
μA
fCPU = 8 MHz VDD= 5.0 V 30
IDD(ADC) ADC supply current when converting (3) fADC = 2 MHz VDD= 3.0 V 450
fADC = 4 MHz VDD= 5.0 V 750
1. Not tested in production, guaranteed by characterization.
2. Data based on a differential IDD measurement between reset configuration (timer stopped) and the timer running in PWM
mode at fcpu = 8 MHz.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with amplifier
off.
Table 55. General timings
Symbol Parameter(1)
1. Data based on characterization. Not tested in production.
Conditions Min Typ(2)
2. Data based on typical application software.
Max Unit
tc(INST) Instruction cycle time fCPU=8 MHz 2312t
CPU
250 375 1500 ns
tv(IT)
Interrupt reaction time(3)
tv(IT) = Δtc(INST) + 10
3. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
fCPU=8 MHz 10 22 tCPU
1.25 2.75 μs
Table 56. Auto-wakeup RC oscillator
Parameter Conditions Min Typ Max Unit
Supply Voltage Range 2.4 5.0 5.5 V
Operating Temperature Range -40 25 125 °C
Current Consumption(1)
1. Data guaranteed by design.
Without prescaler 2.0 8.0 14.0 µA
Consumption(1) AWU RC switched off 0 µA
Output Frequency(1) 20 33 60 kHz
Electrical characteristics ST7LITEUS2, ST7LITEUS5
104/136
12.6 Memory characteristics
TA = -40 to 125 °C, unless otherwise specified;
Table 57. RAM and Hardware registers
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode 1) Halt mode (or Reset) 1.6 V
Table 58. Flash Program memory
Symbol Parameter Conditions Min Typ Max Unit
VDD
Operating voltage for Flash
write/erase 2.4(1)
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under reset) or in
hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.
5.5 V
tprog
Programming time for 1~32
bytes(2)
2. Up to 32 bytes can be programmed at a time.
TA=−40 to +125°C 5 10 ms
Programming time for 1 kByte TA=+25°C 0.16 0.32 s
tRET Data retention(3)
3. Data based on reliability test results and monitored in production.
TA=+55°C(4)
4. The data retention time increases when the TA decreases.
20 years
NRW Write erase cycles TA=+25°C 10k(5)
5. Design target value pending full product characterization.
cycles
IDD Supply current(6)
6. Guaranteed by Design. Not tested in production.
Read / Write / Erase
modes, fCPU = 8 MHz,
VDD = 5.5 V
2.6 mA
No Read/No Write
Mode 100 μA
Power down mode /
Halt 00.1μA
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
105/136
12.7 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
12.7.1 Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●Corrupted program counter
●Unexpected reset
●Critical Data corruption (control registers...)
Pre-qualification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 59. EMC characteristics
Symbol Parameter Conditions Level/
class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD=5V, T
A=+25 °C, fOSC=8MHz,
SO8 package,
conforms to IEC 1000-4-2
3B
VFFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VDD
pins to induce a functional disturbance
VDD=5V, T
A=+25 °C, fOSC=8MHz,
SO8 package,
conforms to IEC 1000-4-4
4B
Electrical characteristics ST7LITEUS2, ST7LITEUS5
106/136
12.7.2 Electromagnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
12.7.3 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model
can be simulated: Human Body Model. This test conforms to the JESD22-A114A/A115A
standard.
Static and dynamic latchup
●LU: 3 complementary static tests are required on 10 parts to assess the latchup
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latchup standard. For more details,
refer to the application note AN1181.
●DLU: Electrostatic discharges (one positive then one negative test) are applied to each
pin of 3 samples when the micro is running to assess the latchup performance in
Table 60. EMI characteristics(1)
1. Data based on characterization results, not tested in production.
Symbol Parameter Conditions Monitored
frequency band
Max vs.
[fOSC/fCPU]Unit
-/8 MHz
SEMI Peak level
VDD=5V, T
A=+25 °C,
SO8 package,
conforming to SAE J
1752/3
0.1 MHz to
30 MHz 21
dBμV
30 MHz to
130 MHz 23
130 MHz to
1GHz 10
SAE EMI Level 3 -
Table 61. Absolute maximum ratings
Symbol Ratings Conditions Maximum
value(1)
1. Data based on characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge voltage
(human body model) TA=+25°C > 4000 V
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
107/136
dynamic mode. Power supplies are set to the typical values, the oscillator is connected
as near as possible to the pins of the micro and the component is put in reset mode.
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,
refer to the application note AN1181.
Table 62. Electrical sensitivities
Symbol Parameter Conditions Class(1)
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
LU Static latchup class TA=+125 °C A
DLU Dynamic latchup class VDD=5.5 V, fOSC=4MHz,
TA=+25 °C A
Electrical characteristics ST7LITEUS2, ST7LITEUS5
108/136
12.8 I/O port pin characteristics
12.8.1 General characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Figure 48. Two typical applications with unused I/O pin
1. Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally (external pull-
up of 10k mandatory in noisy environment). This is to avoid entering I2C mode unexpectedly during a reset.
2. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of
greater EMC robustness and lower cost.
Table 63. General characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage -40°C to 125°C 0.3VDD V
VIH Input high level voltage 0.7VDD
Vhys
Schmitt trigger voltage
hysteresis(1)
1. Data based on characterization results, not tested in production.
400 mV
ILInput leakage current VSS≤VIN≤VDD ±1
μA
IS
Static current
consumption induced by
each floating input pin(2)
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of
the I/O for example or an external pull-up or pull-down resistor (see Figure 48). Static peak current value
taken at a fixed VIN value, based on design simulation and technology characteristics, not tested in
production. This value depends on VDD and temperature values.
Floating input mode 400
RPU
Weak pull-up equivalent
resistor(3)
(4)
3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current
characteristics described in Figure 49).
4. RPU not applicable on PA3 because it is multiplexed on RESET pin
VIN=VS
S
VDD=5 V 80 120 170
kΩ
VDD=3 V 200(1)
CIO I/O pin capacitance 5 pF
tf(IO)out
Output high to low level
fall time 1) CL=50 pF
Between 10% and 90%
25
ns
tr(IO)out
Output low to high level
rise time 1) 25
tw(IT)in
External interrupt pulse
time(5)
5. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured
as an external interrupt source.
1t
CPU
10kΩUNUSED I/O PORT
ST7XXX
10kΩUNUSED I/O PORT
ST7XXX
VDD
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
109/136
Figure 49. Typical IPU vs. VDD with VIN=VSSl
12.8.2 Output driving current characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
0
10
20
30
40
50
60
70
80
90
VDD [V]
IPU [uA]
-45°C
25°C
90°C
Table 64. Output driving current characteristics
Symbol Parameter Conditions Min Max Unit
VOL (1)
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 52)
VDD=5 V
IIO= +5 mA,TA≤ 125 °C 1200
mV
IIO = +2 mA,TA≤ 125 °C 400
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time (see Figure 55)
IIO=+20 mA,TA≤ 125 °C 1300
IIO = +8 mA,TA≤ 125 °C 750
VOH (2) Output high level voltage for an I/O pin when 4 pins
are sourced at same time (see Figure 58)
IIO= -5 mA,TA≤ 125 °C VDD-1500
IIO = -2 mA,TA≤ 125 °C VDD-800
VOL (1)(3)
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 51)
VDD=3 V
IIO = +2 mA,TA≤ 125 °C 500
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time (see Figure 54)
IIO = +2 mA,TA≤ 125 °C 180
IIO = +8 mA,TA≤ 125 °C 600
VOH
(2)(3) Output high level voltage for an I/O pin when 4 pins
are sourced at same time (see Figure 57)IIO = -2 mA,TA≤ 125 °C VDD-800
VOL (1)(3)
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 53)
VDD=2.4 V
IIO = +2 mA,TA≤ 125 °C 700
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time (see Figure 53)
IIO = +2 mA,TA≤ 125 °C 200
IIO=+8 mA,TA≤ 125 °C 800
VOH
(2)(3) Output high level voltage for an I/O pin when 4 pins
are sourced at same time (see Figure 56)IIO=-2 mA,TA≤ 125 °C VDD-900
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 52 and the sum of IIO (I/O ports and control pins)
must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 52 and the sum of IIO (I/O ports and control pins)
must not exceed IVDD. True open drain I/O pins do not have VOH.
3. Not tested in production, based on characterization results.
Electrical characteristics ST7LITEUS2, ST7LITEUS5
110/136
Figure 50. Typical VOL at VDD = 2.4 V (standard pins)
Figure 51. Typical VOL at VDD = 3 V (standard pins)
Figure 52. Typical VOL at VDD = 5 V (standard pins)
0
200
400
600
800
1000
1200
1400
024
Iol [mA]
VOL [mV]
-45°C
25°C
90°C
130°C
0
200
400
600
800
1000
1200
1400
02468
Iol [mA]
VOL
[
mV
]
-45°C
25°C
90°C
130°C
0
200
400
600
800
1000
1200
02468
Iol [mA]
VOL [mV]
-45°C
25°C
90°C
13 0 °C
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
111/136
Figure 53. Typical VOL at VDD = 2.4 V (HS pins)
Figure 54. Typical VOL at VDD = 3 V (HS pins)
Figure 55. Typical VOL at VDD = 5 V (HS pins)
0
200
400
600
800
1000
1200
0246810121416
Iol [mA]
VOL [mV]
-45°C
25°C
90°C
130°C
0
200
400
600
800
1000
1200
1400
0 2 4 6 8 101214161820
Iol [mA]
VOL [mV]
-45°C
25°C
90°C
130°C
0
100
200
300
400
500
600
700
800
02468101214161820
Iol [mA]
VOL [mV]
-45°C
25°C
90°C
130°C
Electrical characteristics ST7LITEUS2, ST7LITEUS5
112/136
Figure 56. Typical VDD-VOH at VDD = 2.4 V (HS pins)
Figure 57. Typical VDD-VOH at VDD = 3 V (HS pins)
Figure 58. Typical VDD-VOH at VDD = 5 V (HS pins)
0
200
400
600
800
1000
1200
1400
1600
1800
024681012
Iol [mA]
VDD-VOH [mV]
-45°C
25°C
90°C
130°C
0
200
400
600
800
1000
1200
1400
1600
1800
0 2 4 6 8 10 12 14 16 18
Iol [mA]
VDD-VOH [mV]
-45°C
25°C
90°C
130°C
0
100
200
300
400
500
600
700
800
900
1000
0 2 4 6 8 101214161820
Iol [mA]
VDD-VOH [mV]
-45°C
25°C
90°C
130°C
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
113/136
Figure 59. Typical VOL vs. VDD (HS pins)
Figure 60. Typical VDD-VOH vs. VDD (HS pins)
12.9 Control pin characteristics
The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the
RESET pin can go below the VIL max. level specified in Ta bl e 6 5 . Otherwise the reset will
not be taken into account internally.
Because the reset circuit is designed to allow the internal reset to be output in the RESET
pin, the user must ensure that the current sunk on the RESET pin is less than the absolute
maximum value specified for IINJ(RESET) in Ta b l e 4 4 .
Refer to Figure 61 and Figure 62 for a description of the RESET pin protection circuit with
LVD enabled and disabled.
40
50
60
70
80
90
100
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6
Vdd [V]
VOL [mV] vs VDD at ILOAD=2mA
-45°C
25°C
90°C
130°C
100
150
200
250
300
350
400
450
500
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6
Vdd [V]
VOL [mV] vs VDD at ILOAD=8mA
-45°C
25°C
90°C
130°C
200
300
400
500
600
700
800
900
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6
Vdd [V]
VOL [mV] vs VDD at ILOAD=12mA
-45°C
25°C
90°C
130°C
40
60
80
100
120
140
160
180
200
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6
Vdd [V]
VDD-VOH [mV] vs VDD @ ILOAD=2 mA
-45°C
25°C
90°C
130°C
100
200
300
400
500
600
700
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6
Vdd [V]
VDD-VOH [mV] vs VDD @ ILOAD=6 mA
-45°C
25°C
90°C
130°C
Electrical characteristics ST7LITEUS2, ST7LITEUS5
114/136
Refer also to Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset
conditions.
Figure 61. RESET pin protection when LVD is enabled
1. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-
down capacitor is required to filter noise on the reset line.
2. When using the LVD:
- Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in
Table 2 and text above)
- Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709
and AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET
pin.
- The capacitors connected on the RESET pin and also the power supply are key to avoid any startup
marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace
10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.”
3. In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will
add 5µA to the power consumption of the MCU).
Table 65. Asynchronous RESET pin characteristics (1)
1. TA = -40°C to 125°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage VSS -
0.3 0.3VDD
V
VIH Input high level voltage 0.7VDD
VDD +
0.3
Vhys
Schmitt trigger voltage
hysteresis(2)
2. Data based on characterization results, not tested in production.
2V
VOL Output low level voltage(3)
3. The IIO current sunk must always respect the absolute maximum rating specified in Table 44 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
VDD=5 V IIO=+2 mA 400 mV
RON Pull-up equivalent resistor(4)
4. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin
between VILmax and VDD.
VIN=VSS
VDD=5 V 30 50 70 kΩ
VDD=3 V 90(2)
tw(RSTL)out Generated reset pulse duration Internal reset sources 90(2) μs
th(RSTL)in External reset pulse hold time(5)
5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses
applied on RESET pin with a duration below th(RSTL)in can be ignored.
20 μs
tg(RSTL)in Filtered glitch duration 200 ns
0.01μF
ST7XXX
PULSE
GENERATOR
Filter
RON
VDD
INTERNAL
RESET
RESET
EXTERNAL
Required
1MΩ
Optional
(note 3)
WATCHDOG
LVD RESET
ILLEGAL
OPCODE 5)
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
115/136
Figure 62. RESET pin protection when LVD is disabled
12.10 ADC characteristics
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
0.01μF
EXTERNAL
RESET
CIRCUIT
USER
Required
ST7XXX
PULSE
GENERATOR
Filter
RON
VDD
INTERNAL
RESET
WATCHDOG
ILLEGAL OPCODE 5)
Table 66. 10-bit ADC characteristics
Symbol Parameter Conditions Min Typ(1)
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5 V. They are given only as
design guidelines and are not tested.
Max Unit
fADC ADC clock frequency(2)
2. The maximum ADC clock frequency allowed within VDD = 2.4 to 2.7 V operating range is 1 MHz.
4MHz
VAIN Conversion voltage range(3)
3. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
VSSA VDDA V
RAIN External input resistor
VDD = 5 V, fADC=4 MHz 8(4)
4. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than
10k
Ω
). Data based on characterization results, not tested in production.
kΩ
VDD = 3.3 V,
fADC=4 MHz 7(4)
2.7 V ≤ VDD ≤5.5 V,
fADC=2 MHz 10(4)
2.4 V ≤ VDD ≤2.7 V,
fADC=1 MHz TBD(4)
CADC
Internal sample and hold
capacitor 3pF
tSTAB
Stabilization time after ADC
enable
fCPU=8 MHz,
fADC=4 MHz
0(5)
5. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the
enable is then always valid.
μs
tADC
Conversion time
(Sample+Hold) 3.5
- Sample capacitor loading
time
- Hold conversion time
4
10 1/fADC
Electrical characteristics ST7LITEUS2, ST7LITEUS5
116/136
Figure 63. Typical application with ADC
Table 67. ADC accuracy with VDD = 3.3 to 5.5 V
Symbol
(1)
1. Data based on characterization results over the whole temperature range.
Parameter Conditions Typ Max Unit
|ET| Total unadjusted error
fCPU=8 MHz,
fADC=4 MHz(1)
2.1 5.0
LSB
|EO| Offset error 0.2 2.5
|EG| Gain Error 0.3 1.5
|ED| Differential linearity error 1.9 3.5
|EL| Integral linearity error 1.9 4.5
Table 68. ADC accuracy with VDD = 2.7 to 3.3 V
Symbol
(1)
1. Data based on characterization results over the whole temperature range.
Parameter Conditions Typ Max Unit
|ET| Total unadjusted error
fCPU=4 MHz,
fADC=2 MHz(1)
2.0 3.0
LSB
|EO| Offset error 0.1 1.5
|EG| Gain Error 0.4 1.4
|ED| Differential linearity error 1.8 2.5
|EL| Integral linearity error 1.7 2.5
Table 69. ADC accuracy with VDD = 2.4V to 2.7V
Symbol
(1)
1. Data based on characterization results at a temperature ≥ 25°C.
Parameter Conditions Typ Max Unit
|ET| Total unadjusted error
fCPU=2 MHz,
fADC=1 MHz(1)
2.2 3.5
LSB
|EO| Offset error 0.5 1.5
|EG| Gain Error 0.5 1.5
|ED| Differential linearity error 1.8 2.5
|EL| Integral linearity error 1.8 2.5
AINx
ST7LITEUSx
VDD
IL
±1μA
VT
0.6V
VT
0.6V CADC
VAIN
RAIN 10-Bit A/D
Conversion
ST7LITEUS2, ST7LITEUS5 Electrical characteristics
117/136
Figure 64. ADC accuracy characteristics
1. Example of an actual transfer curve
2. The ideal transfer curve
3. End point correlation line
4. ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
5. EO=Offset Error: deviation between the first actual transition and the first ideal one.
6. EG=Gain Error: deviation between the last ideal transition and the last actual one.
7. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
8. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation
line.
EO
EG
1LSB
IDEAL
1LSBIDEAL
VDD VSS
–
1024
--------------------------------=
Vin (LSBIDEAL)
Digital Result ADCDR
1023
1022
1021
5
4
3
2
1
0
7
6
1234567 1021 1022 1023 1024
(1)
(2)
ET
ED
EL
(3)
VDD
VSS
Package characteristics ST7LITEUS2, ST7LITEUS5
118/136
13 Package characteristics
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
13.1 Package mechanical data
Figure 65. 8-lead very thin fine pitch dual flat no-lead package outline
Table 70. 8-lead very thin fine pitch dual flat no-lead package mechanical data
Dim.
mm inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 0.80 0.90 1.00 0.0310 0.0350 0.0390
A1 0.00 0.02 0.05 0.0000 0.0010 0.0020
A3 0.20 0.0080
b 0.25 0.30 0.35 0.0100 0.0120 0.0140
D4.50 0.1770
D2 3.50 3.65 3.75 0.1380 0.1440 0.1480
E3.50 0.1380
E2 1.96 2.11 2.21 0.0770 0.0830 0.0870
e0.80 0.0310
L 0.30 0.40 0.50 0.0120 0.0160 0.0200
Number of pins
N8
A1
A3
(D/2 x E/2)
D
E
A
b
e
(D/2 x E/2) L
E2
TOP VIEW
SIDE VIEW BOTTOM VIEW
D2
INDEX AREA
INDEX AREA
ST7LITEUS2, ST7LITEUS5 Package characteristics
119/136
Figure 66. 8-pin plastic small outline package, 150-mil width package outline
Table 71. 8-pin plastic small outline package, 150-mil width, package mechanical
data
Dim.
mm inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.35 1.75 0.0530 0.0690
A1 0.10 0.25 0.0040 0.0100
A2 1.10 1.65 0.0430 0.0650
B 0.33 0.51 0.0130 0.0200
C 0.19 0.25 0.0070 0.0100
D 4.80 5.00 0.1890 0.1970
E 3.80 4.00 0.1500 0.1580
e 1.27 0.0500
H 5.80 6.20 0.2280 0.2440
h 0.25 0.50 0.0100 0.0200
α0d 8d
L 0.40 1.27 0.0160 0.0500
Number of pins
N8
D
B
A1
A
h x 45°
A2
HE
e
L
C
α
Package characteristics ST7LITEUS2, ST7LITEUS5
120/136
Figure 67. 8-pin plastic dual in-line package, 300-mil width package outline
Table 72. 8-pin plastic dual in-line package, 300-mil width package mechanical data
Dim.
mm inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 5.33 0.2100
A1 0.38 0.0150
A2 2.92 3.30 4.95 0.1150 0.1300 0.1950
b 0.36 0.46 0.56 0.0140 0.0180 0.0220
b2 1.14 1.52 1.78 0.0450 0.0600 0.0700
b3 0.76 0.99 1.14 0.0300 0.0390 0.0450
c 0.20 0.25 0.36 0.0080 0.0100 0.0140
D 9.02 9.27 10.16 0.3550 0.3650 0.4000
D1 0.13 0.0050
e 2.54 0.1000
eB 10.92 0.4300
E 7.62 7.87 8.26 0.3000 0.3100 0.3250
E1 6.10 6.35 7.11 0.2400 0.2500 0.2800
L 2.92 3.30 3.81 0.1150 0.1300 0.1500
Number of pins
N8
8
1 4
A
L
b2
e
D
b
D1
E1
b3 eB
5
A2
E
c
A1
D
ST7LITEUS2, ST7LITEUS5 Package characteristics
121/136
Figure 68. 16-pin plastic dual in-line package, 300-mil width, package outline
Table 73. 16-pin plastic dual in-line package, 300-mil width, package mechanical
data
Dim.
mm inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 5.33 0.2100
A1 0.38 0.0150
A2 2.92 3.30 4.95 0.1150 0.1300 0.1950
b 0.36 0.46 0.56 0.0140 0.0180 0.0220
b2 1.14 1.52 1.78 0.0450 0.0600 0.0700
c 0.20 0.25 0.36 0.0080 0.0100 0.0140
D 18.67 19.18 19.69 0.7350 0.7550 0.7750
E 7.62 7.87 8.26 0.3000 0.3100 0.3250
E1 6.10 6.35 7.11 0.2400 0.2500 0.2800
e 2.54 0.1000
e1 17.78 0.7
eA 7.62 0.3000
eB 10.92 0.4300
L 2.92 3.30 3.81 0.1150 0.1300 0.1500
NNumber of pins
16
17_ME
A2
A1
A
L
b
e
D
E1
8
1
c
eA
b2
eB
E
e1
Package characteristics ST7LITEUS2, ST7LITEUS5
122/136
13.2 Thermal characteristics
Table 74. Thermal characteristics
Symbol Ratings Value Unit
RthJA
Package thermal resistance
(junction to ambient)
Plastic DIP8 82
°C/W
SO8 130
DFN8 (on 4-layer
PCB)
DFN8 (on 2-layer
PCB)
50
106
TJmax
Maximum junction
temperature(1)
1. The maximum chip-junction temperature is based on technology characteristics.
150 °C
PDmax Power dissipation(2)
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
The power dissipation of an application can be defined by the user with the formula: PD=PINT+PPORT
where PINT is the chip internal power (IDD x VDD) and PPORT is the port power dissipation depending on the
ports used in the application.
Plastic DIP8 300
mW
SO8 180
DFN8 (on 4-layer
PCB) 500
DFN8 (on 2-layer
PCB) 250
ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information
123/136
14 Device configuration and ordering information
Each device is available for production in user programmable versions (FLASH) as well as in
factory coded versions (FASTROM). Refer to Ta bl e 7 9 for the full list of supported part
numbers:
●ST7FLITEUSA2xx and ST7FLITEUSA5xx XFlash devices are shipped to customers
with a default program memory content (FFh).
●Factory Advanced Service Technique ROM (FASTROM) versions are also available:
they are factory-programmed XFlash devices.
The FASTROM factory coded parts contain the code supplied by the customer. This implies
that FLASH devices have to be configured by the customer using the Option Bytes while the
FASTROM devices are factory-configured.
14.1 Option bytes
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
14.1.1 OPTION BYTE 1
Bit 7:6 CKSEL[1:0] Startup clock selection.
This bit is used to select the startup frequency. By default, the internal RC is
selected (see Table 75: Startup clock selection).
Bit 5 Reserved, must always be 1.
Bit 4 Reserved, must always be 0.
Bits 3:2 LV D[1:0 ] Low Voltage Detection selection
These option bits enable the LVD block with a selected threshold as shown in
Table 76: LVD threshold configuration.
Bit 1 WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Bit 0 WDG HALT Watchdog Reset on Halt
This option bit determines if a reset is generated when entering Halt mode while the
watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Device configuration and ordering information ST7LITEUS2, ST7LITEUS5
124/136
14.1.2 OPTION BYTE 0
Table 75. Startup clock selection
Configuration CKSEL1 CKSEL0
Internal RC as Startup Clock 0 0
Reserved 0 0
AWU RC as a Startup Clock 0 1
Reserved 1 0
External Clock on pin PA5 1 1
Table 76. LVD threshold configuration
Configuration LVD1 LVD0
LVD Of f 11
Highest voltage threshold 1 0
Medium voltage threshold 0 1
Lowest voltage threshold 0 0
Bits 7:4 Reserved, must always be 1.
Bit 3 Reserved, must always be 0.
Bit 2 SEC0 Sector 0 size definition
This option bit indicates the size of sector 0 according to the following table (see
Table 77: Definition of sector 0 size).
Bit 1 FMP_R Readout protection
Readout protection, when selected provides a protection against program memory
content extraction and against write access to Flash memory. Erasing the option
bytes when the FMP_R option is selected will cause the whole memory to be
erased first, and the device can be reprogrammed. Refer to Section 4.5 and the
ST7 Flash Programming Reference Manual for more details.
0: Readout protection off
1: Readout protection on
Bit 0 FMP_W FLASH write protection
This option indicates if the FLASH program memory is write protected.
Warning: When this option is selected, the program memory (and the option bit
itself) can never be erased or programmed again.
0: Write protection off
1: Write protection on
Table 77. Definition of sector 0 size
Sector 0 Size SEC0
0.5k 0
1k 1
ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information
125/136
14.2 Ordering information
Customer code is made up of the FASTROM contents and the list of the selected options (if
any). The FASTROM contents are to be sent on diskette, or by electronic means, with the
S19 hexadecimal file generated by the development tool. All unused bytes must be set to
FFh. The selected options are communicated to STMicroelectronics using the correctly
completed option list appended.
Refer to application note AN1635 for information on the counter listing returned by ST after
code has been transferred.
The STMicroelectronics Sales Organization will be pleased to provide detailed information
on contractual points.
Table 78:
OPTION BYTE 0
7 0
OPTION BYTE 1
7 0
Reserved SEC0 FMPR FMPW CKSEL
1
CKSEL
0Res Res LVD1 LVD0 WDG
SW
WDG
HALT
Default
value 111100 0 0 0 0 10111 1
Table 79. Supported order codes (1)
Order code
Program
memory
(bytes)
RAM
(bytes) ADC Temperature
range Package Conditioning
ST7FLITEUSA2B6
1Kbyte
FLASH 128
-
-40°C +85°C
DIP8 Tube
ST7FLITEUSA2M6 - SO8 Tube
ST7FLITEUSA2M6TR - SO8 Tape & Reel
ST7FLITEUSA2U6TR - DFN8 Tape & Reel
ST7FLITEUSA5B6
1Kbyte
FLASH 128
10-bit
-40°C +85°C
DIP8 Tube
ST7FLITEUSA5M6 10-bit SO8 Tube
ST7FLITEUSA5M6TR 10-bit SO8 Tape & Reel
ST7FLITEUSA5U6 10-bit DFN8 Tray
ST7FLITEUSA5U6TR 10-bit DFN8 Tape & Reel
ST7FLITEUSICD 1Kbyte
FLASH 128 - -40°C +125°C DIP16(2) Tube
ST7PLUSA2B6
1Kbyte
FASTROM 128
-
-40°C +85°C
DIP8 Tube
ST7PLUSA2M6 - SO8 Tube
ST7PLUSA2M6TR - SO8 Tape & Reel
ST7PLUSA2U6TR - DFN8 Tape & Reel
Device configuration and ordering information ST7LITEUS2, ST7LITEUS5
126/136
ST7PLUSA5B6
1Kbyte
FASTROM 128
10-bit
-40°C +85°C
DIP8 Tube
ST7PLUSA5M6 10-bit SO8 Tube
ST7PLUSA5M6TR 10-bit SO8 Tape & Reel
ST7PLUSA5U6 10-bit DFN8 Tray
ST7PLUSA5U6TR 10-bit DFN8 Tape & Reel
ST7PLUSA2B3
1Kbyte
FLASH 128
-
-40°C +125°C
DIP8 Tube
ST7PLUSA2M3 - SO8 Tube
ST7PLUSA2M3TR - SO8 Tape & Reel
ST7PLUSA2U3TR - DFN8 Tape & Reel
ST7PLUSA5B3
1Kbyte
FLASH 128
10-bit
-40°C +125°C
DIP8 Tube
ST7PLUSA5M3 10-bit SO8 Tube
ST7PLUSA5M3TR 10-bit SO8 Tape & Reel
ST7PLUSA5U3 10-bit DFN8 Tray
ST7PLUSA5U3TR 10-bit DFN8 Tape & Reel
ST7PLUSA2B3
1Kbyte
FASTROM 128
-
-40°C +125°C
DIP8 Tube
ST7PLUSA2M3 - SO8 Tube
ST7PLUSA2M3TR - SO8 Tape & Reel
ST7PLUSA2U3TR - DFN8 Tape & Reel
ST7PLUSA5B3
1Kbyte
FASTROM 128
10-bit
-40°C +125°C
DIP8 Tube
ST7PLUSA5M3 10-bit SO8 Tube
ST7PLUSA5M3TR 10-bit SO8 Tape & Reel
ST7PLUSA5U3 10-bit DFN8 Tray
ST7PLUSA5U3TR 10-bit DFN8 Tape & Reel
1. Contact ST sales office for product availability.
2. For development or tool prototyping purposes only, not orderable in production quantities.
Table 79. Supported order codes (1) (continued)
Order code
Program
memory
(bytes)
RAM
(bytes) ADC Temperature
range Package Conditioning
ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information
127/136
Figure 69. Option list
ST7LITEUS FASTROM MICROCONTROLLER OPTION LIST
(Last update: February 2009)
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/FASTROM Code*:. . . . . . . . . . . . . . . . . . . . . . . . . .
*FASTROM code name is assigned by STMicroelectronics.
FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
------------------|-----------------------|
FASTROM DEVICE: | 1K FASTROM |
------------------|-----------------------|
PDIP8 | [ ] |
SO8 | [ ] |
DFN8 | [ ] |
Conditioning (check only one option):
---------------------------------------------------------------------------
DIP package: [ ] Tube
SO package: [ ] Tape & Reel [ ] Tube
DFN package: [ ] Tape & Reel [ ] Tray (for ST7PLUSA5U6xxx and ST7PLUSA5U3xxx
only)
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _"
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Maximum character count:
PDIP8/SO8/DFN8 (8 char. max) : _ _ _ _ _ _ _ _
Temperature range [ ] -40°C to +85°C [ ] -40°C to +125°C
Clock Source Selection: [ ] External Clock
[ ] AWU RC oscillator
[ ] Internal RC oscillator
Sector 0 size: [ ] 0.5K [ ] 1K
Readout protection: [ ] Disabled [ ] Enabled
FLASH Write Protection: [ ] Disabled [ ] Enabled
LVD Reset [ ] Disabled [ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
Watchdog Selection: [ ] Software Activation [ ] Hardware Activation
Watchdog Reset on Halt: [ ] Disabled [ ] Enabled
Comments: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application:. . . . . . . . . . . . . . . . .
Notes:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Important note: Not all configurations are available. Refer to datasheet for
authorized option byte combinations.
Please download the latest version of this option list from:
http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list
Device configuration and ordering information ST7LITEUS2, ST7LITEUS5
128/136
14.3 Development tools
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
14.3.1 Starter kits
ST offers complete, affordable starter kits. Starter kits are complete, affordable
hardware/software tool packages that include features and samples to help you quickly start
developing your application.
14.3.2 Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The Cosmic C Compiler is available in a free version that outputs up to
16 Kbytes of code.
The range of hardware tools includes full-featured ST7-EMU3 series emulators, cost
effective ST7-DVP3 series emulators and the low-cost RLink in-circuit
debugger/programmer. These tools are supported by the ST7 Toolset from
STMicroelectronics, which includes the STVD7 integrated development environment (IDE)
with high-level language debugger, editor, project manager and integrated programming
interface.
14.3.3 Programming tools
During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the
RLink provide in-circuit programming capability for programming the Flash microcontroller
on your application board.
ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as
ST7 Socket Boards which provide all the sockets required for programming any of the
devices in a specific ST7 sub-family on a platform that can be used with any tool with in-
circuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
14.3.4 Order codes for development and programming tools
Ta bl e 8 0 below lists the ordering codes for the ST7LITEUSx development and programming
tools. For additional ordering codes for spare parts and accessories, refer to the online
product selector at www.st.com/mcu.
ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information
129/136
14.4 ST7 application notes
Table 80. Development tool order codes for the ST7LITEUSx family
Supported
products
In-circuit Debugger, RLink
series(1) Emulator Programming tool
Starter kit
without demo
board
Starter kit with
Demo Board DVP series EMU series In-circuit
programmer
ST socket
boards and
EPBs
ST7FLITEUS2
ST7FLITEUS5 STX-RLINK(2) STFLITE-
SK/RAIS(2) ST7MDT10-
DVP3(3) ST7MDT10-
EMU3
STX-RLINK
ST7-
STICK(5)(4)
ST7SB10-
SU0(5)
1. Available from ST or from Raisonance, www.raisonance.com.
2. USB connection to PC.
3. Includes connection kit for Plastic DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection
guide for connection kit ordering information.
4. Parallel port connection to PC.
5. Add suffix /EU, /UK or /US for the power supply for your region.
Table 81. ST7 application notes
Identification Description
Application examples
AN1658 Serial numbering implementation
AN1720 Managing the readout protection in flash microcontrollers
AN1755 A high resolution/precision thermometer using ST7 and NE555
AN1756 Choosing a DALI Implementation strategy with ST7DALI
AN1812 A high precision, low cost, single supply ADC for positive and negative input voltages
Example drivers
AN 969 SCI communication between ST7 and PC
AN 970 SPI communication between ST7 and EEPROM
AN 971 I²C communication between ST7 and M24Cxx EEPROM
AN 972 ST7 software SPI master communication
AN 973 SCI software communication with a PC using ST72251 16-bit timer
AN 974 Real time clock with ST7 Timer Output Compare
AN 976 Driving a buzzer through ST7 timer PWM function
AN 979 Driving an analog keyboard with the ST7 ADC
AN 980 ST7 keypad decoding techniques, implementing wakeup on keystroke
AN1017 Using the ST7 universal serial bus microcontroller
AN1041 Using ST7 PWM signal to generate analog output (sinusoïd)
AN1042 ST7 routine for I²C slave mode management
Device configuration and ordering information ST7LITEUS2, ST7LITEUS5
130/136
AN1044 Multiple interrupt sources management for ST7 MCUs
AN1045 ST7 S/W implementation of I²C bus master
AN1046 UART emulation software
AN1047 Managing reception errors with the ST7 SCI peripherals
AN1048 ST7 software LCD driver
AN1078 PWM duty cycle switch implementing true 0% & 100% duty cycle
AN1082 Description of the ST72141 motor control peripherals registers
AN1083 ST72141 BLDC motor control software and flowchart example
AN1105 ST7 pCAN peripheral driver
AN1129 PWM management for BLDC motor drives using the ST72141
AN1130 An introduction to sensorless brushless DC motor drive applications with the ST72141
AN1148 Using the ST7263 for designing a USB mouse
AN1149 Handling Suspend mode on a USB mouse
AN1180 Using the ST7263 Kit to implement a USB game pad
AN1276 BLDC motor start routine for the ST72141 microcontroller
AN1321 Using the ST72141 motor control MCU in sensor mode
AN1325 Using the ST7 USB low-speed firmware V4.x
AN1445 Emulated 16-bit slave SPI
AN1475 Developing an ST7265X mass storage application
AN1504 Starting a PWM signal directly at high level using the ST7 16-bit timer
AN1602 16-bit timing operations using ST7262 or ST7263B ST7 USB MCUs
AN1633 Device firmware upgrade (DFU) implementation in ST7 non-USB applications
AN1712 Generating a high resolution sinewave using ST7 PWMART
AN1713 SMBus slave driver for ST7 I2C peripherals
AN1753 Software UART using 12-bit ART
AN1947 ST7MC PMAC sine wave motor control software library
General purpose
AN1476 Low cost power supply for home appliances
AN1526 ST7FLITE0 quick reference note
AN1709 EMC design for ST Microcontrollers
AN1752 ST72324 quick reference note
Product evaluation
AN 910 Performance benchmarking
AN 990 ST7 benefits vs industry standard
Table 81. ST7 application notes (continued)
Identification Description
ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information
131/136
AN1077 Overview of enhanced CAN controllers for ST7 and ST9 MCUs
AN1086 U435 can-do solutions for car multiplexing
AN1103 Improved B-EMF detection for low speed, low voltage with ST72141
AN1150 Benchmark ST72 vs PC16
AN1151 Performance comparison between ST72254 & PC16F876
AN1278 LIN (local interconnect network) solutions
Product migration
AN1131 Migrating applications from ST72511/311/214/124 to ST72521/321/324
AN1322 Migrating an application from ST7263 Rev.B to ST7263B
AN1365 Guidelines for migrating ST72C254 applications to ST72F264
AN1604 How to use ST7MDT1-TRAIN with ST72F264
AN2200 Guidelines for migrating ST7LITE1x applications to ST7FLITE1xB
Product optimization
AN 982 Using ST7 with ceramic resonator
AN1014 How to Minimize the ST7 power consumption
AN1015 Software techniques for improving microcontroller EMC performance
AN1040 Monitoring the Vbus signal for USB Self-powered devices
AN1070 ST7 checksum self-checking capability
AN1181 Electrostatic Discharge sensitive measurement
AN1324 Calibrating the RC oscillator of the ST7FLITE0 MCU using the mains
AN1502 Emulated data EEPROM with ST7 HDFLASH memory
AN1529 Extending the current & voltage capability on the ST7265 VDDF supply
AN1530 Accurate timebase for low-cost ST7 applications with internal RC oscillator
AN1605 Using an active RC to wakeup the ST7LITE0 from power saving mode
AN1636 Understanding and minimizing ADC conversion errors
AN1828 PIR (passive Infrared) detector using the ST7FLITE05/09/SUPERLITE
AN1946 Sensorless BLDC motor control and BEMF sampling methods with ST7MC
AN1953 PFC for ST7MC starter kit
AN1971 ST7LITE0 microcontrolled ballast
Programming and tools
AN 978 ST7 Visual Develop software key debugging features
AN 983 Key features of the Cosmic ST7 C-compiler package
AN 985 Executing code In ST7 RAM
AN 986 Using the indirect addressing mode with ST7
Table 81. ST7 application notes (continued)
Identification Description
Device configuration and ordering information ST7LITEUS2, ST7LITEUS5
132/136
AN 987 ST7 serial test controller programming
AN 988 Starting with ST7 assembly tool chain
AN1039 ST7 math utility routines
AN1071 Half duplex USB-to-serial bridge using the ST72611 USB microcontroller
AN1106 Translating assembly code from HC05 to ST7
AN1179 Programming ST7 Flash microcontrollers in remote ISP mode (In-situ programming)
AN1446 Using the ST72521 emulator to debug an ST72324 target application
AN1477 Emulated data EEPROM with Xflash memory
AN1527 Developing a USB smartcard reader with ST7SCR
AN1575 On-board programming methods for XFLASH and HDFLASH ST7 MCUs
AN1576 In-application programming (IAP) drivers for ST7 HDFLASH or XFLASH MCUs
AN1577 Device firmware upgrade (DFU) implementation for ST7 USB applications
AN1601 Software implementation for ST7DALI-EVAL
AN1603 Using the ST7 USB device firmware upgrade development kit (DFU-DK)
AN1635 ST7 customer ROM code release information
AN1754 Data logging program for testing ST7 applications via I2C
AN1796 Field updates for FLASH based ST7 applications using a PC comm port
AN1900 Hardware implementation for ST7DALI-EVAL
AN1904 ST7MC three-phase AC induction motor control software library
AN1905 ST7MC three-phase BLDC motor control software library
System optimization
AN1711 Software techniques for compensating ST7 ADC errors
AN1827 Implementation of SIGMA-DELTA ADC with ST7FLITE05/09
AN2009 PWM Management for 3-phase BLDC motor drives using the ST7FMC
AN2030 Back EMF detection during PWM on time by ST7MC
Table 81. ST7 application notes (continued)
Identification Description
ST7LITEUS2, ST7LITEUS5 Known limitations
133/136
15 Known limitations
External interrupt 2 (ei2)
Whatever the external interrupt sensitivity configured through EICR1 register, ei2 cannot exit
the MCU from Halt, Active-halt and AWUFH modes when a falling edge occurs.
Workaround
None
Revision history ST7LITEUS2, ST7LITEUS5
134/136
16 Revision history
Table 82. Document revision history
Date Revision Changes
06-Feb-06 1 Initial release
18-Apr-06 2
Removed references to 3% RC
Added note below Figure 4
Modified presentation of Section 4.3.1
Added notes to Section 6.2 (above Figure 9), replaced 8-bit calibration value to
10-bit calibration value and changed application note reference (AN2326
instead of AN1324)
Modifed Table 7: Clock register map and reset values and added bit 1 in the
description of CKCNTCSR register
Modified Figure 13 (added CKCNTCSR register)
Added note 2 to EICRx description
Modified caution in section 7.2 on page 25
Replaced VIT+(LVD) by VIT+(LVD) in Section : Monitoring the VDD main supply
Modified LVDRF bit description in Section 7.4.4: Register description
Replaced “oscillator” by “main oscillator” in the second paragraph of
Section 8.4.2: Halt mode
Added note 1 to Figure 23 and added note 5 to Figure 24
Modified Section 8.5: Auto-wakeup from Halt mode
Replaced bit 1 by bit 2 for AWUF bit in Section 8.5.1: Register description
Modified Section 9.1: Introduction. Modified Section : External interrupt
function.Updated Section 9.5: Interrupts. Modified Section Table 47.: Operating
conditions with low voltage detector (LVD).
Modified Table 48: Auxiliary Voltage Detector (AVD) Thresholds. Modified
Table 49: Voltage drop between AVD flag set and LVD reset generation.
Modified Table 50: Internal RC oscillator calibrated at 5 V. Modified Table 53:
Supply current. Modified Table 54: On-chip peripherals. Modified Tabl e 6 3:
General characteristics. Modified Table 64: Output driving current. Modified
Table 65: Asynchronous RESET pin characteristics. Modified Section 12.10:
ADC characteristics.
Added Figure 49. Modified Figure 61. Removed EMC protection circuitry in
Figure 62 (device works correctly without these components). Added
ECOPACK text in Section 13: Package characteristics. Modified first paragraph
in Section 14: Device configuration and ordering information. Modified
Ta b l e 7 9 . Modified conditioning option in option list. Modified Section 14.3:
Development tools. Added Section 14.4: ST7 application notes. Added
Section : . Added erratasheet at the end of the document.
ST7LITEUS2, ST7LITEUS5 Revision history
135/136
18-Sep-06 3
Modified description of AVD[1:0] bits in the AVDTRH register in Section 7.4.4
Modified description of CNTR[11:0] bits in Section 10.2.6: Register description
Modified values in Table 4 4
LVD and AVD tables updated, Ta b l e 4 7 , Ta bl e 4 8 and Ta b l e 4 9
Internal RC oscillator data modified in Ta b l e 5 0 and new table added Ta bl e 5 1
Typical data in Ta b l e 5 4 (on chip peripherals) modified
EMC characteristics updated, Section 12.7
RPU data corrected in Ta bl e 6 3 including additional notes
Output driving current table updated, Ta bl e 6 4
RON data corrected in Tabl e 6 5 .
Modified ADC accuracy tables in Section 12.10
Section : updated
Errata sheet removed from document
Notes modified for low voltage detector Section 7.4.1
Notes updated in Section 4.4 (I2C Interface)
Thermal characteristics table updated, Ta b l e 7 4
Modified option list on Section 14.2: Ordering information
Modified Section 14.3: Development tools
Modified text in Section :
26-Jan-07 4
Added -40°C to 125°C temperature range
Modified note on ei4 in Table 9: Interrupt mapping
Added note 3 to Section 7.3.2: External Interrupt Control register 2 (EICR2)
Added Figure 41 and Figure 40
Added a note to LVDRF in Section 7.4.4: Register description
Section 6.4.1: Introduction
Modified Ta b l e 47 and Tabl e 48
Modified Ta b l e 50Updated Ta b l e 5 3
Updated Ta b l e 6 4
Modified RAIN and ADC accuracy tables in Section 12.10: ADC characteristics
Modified Ta b l e 80
Modified Ta b l e 79
Modified option list on Figure 69: Option list
06-Feb-2009 5
Document reformatted.
Replaced ST7ULTRALITE by ST7LITEUS2 and ST7LITEUS5.
Removed limitations in user and in I2C mode from Section 15: Known
limitations, and added External interrupt 2 (ei2).
Added MCO on pin 3.
Updated Section 12.3.2: Operating conditions with low voltage detector (LVD),
Section 12.3.3: Auxiliary voltage detector (AVD) thresholds, Section 12.3.4:
Internal RC oscillator, Section 12.4: Supply current characteristics, and
Section 12.8.2: Output driving current characteristics.
Updated internal RC prescaler to add 500 KHz.
Updated ECOPACK text in Section 13.1: Package mechanical data. Added
PDIP16 silhouette on cover page, and updated Table 73: 16-pin plastic dual in-
line package, 300-mil width, package mechanical data and Figure 68: 16-pin
plastic dual in-line package, 300-mil width, package outline.
Changed order codes to die A version in Table 79: Supported order codes.
Removed soldering information section.
Updated option list.
Table 82. Document revision history (continued)
Date Revision Changes
ST7LITEUS2, ST7LITEUS5
136/136
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