tm
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
May 2007
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ00 Rev. 1.4
74ACTQ00
Quiet Series™ Quad 2-Input NAND Gate
Features
■
I
CC
reduced by 50%
■
Guaranteed simultaneous switching noise level and
dynamic threshold performance
■
Improved latch-up immunity
■
Outputs source/sink 24mA
■
Has TTL-compatible inputs
General Description
The ACTQ00 contains four 2-input NAND gates and
utilizes Fairchild FACT Quiet Series™ technology to
guarantee quiet output switching and improve dynamic
threshold performance FACT Quiet Series features
GTO™ output control and undershoot corrector in
addition to a split ground bus for superior ACMOS
performance.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Order Number
Package
Number Package Description
74ACTQ00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACTQ00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ00 Rev. 1.4 2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
I
IK
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
–20mA
+20mA
V
I
DC Input Voltage –0.5V to V
CC
+ 0.5V
I
OK
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
–20mA
+20mA
V
O
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
O
DC Output Source or Sink Current ±50mA
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin ±50mA
T
STG
Storage Temperature –65°C to +150°C
DC Latch-Up Source or Sink Current ±300mA
T
J
Junction Temperature 140°C
Symbol Parameter Rating
V
CC
Supply Voltage 4.5V to 5.5V
V
I
Input Voltage 0V to V
CC
V
O
Output Voltage 0V to V
CC
T
A
Operating Temperature –40°C to +85°C
∆
V
/
∆
t Minimum Input Edge Rate:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
125mV/ns
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ00 Rev. 1.4 3
DC Electrical Characteristics
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. Max number of outputs defined as (n). Data inputs are 0V to 3V. One output @ GND.
4. Max number of data inputs (n) switching. (n–1) inputs switching 0V to 3V. Input-under-test switching:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1MHz.
Symbol Parameter V
CC
(V) Conditions
T
A
=
+25°C T
A
=
–40°C to +85°C
UnitsTyp. Guaranteed Limits
V
IH
Minimum HIGH Level
Input Voltage
4.5 V
OUT
=
0.1V
or V
CC
– 0.1V
1.5 2.0 2.0 V
5.5 1.5 2.0 2.0
V
IL
Maximum LOW Level
Input Voltage
4.5 V
OUT
=
0.1V
or V
CC
– 0.1V
1.5 0.8 0.8 V
5.5 1.5 0.8 0.8
V
OH
Minimum HIGH Level
Output Voltage
4.5 I
OUT
=
–50µA 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
V
IN
=
V
IL
or V
IH
:
4.5 I
OH
=
–24mA 3.86 3.76
5.5 I
OH
=
–24mA
(1)
4.86 4.76
V
OL
Maximum LOW Level
Output Voltage
4.5 I
OUT
=
50µA 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
V
IN
=
V
IL
or V
IH
:
4.5 I
OL
=
24mA 0.36 0.44
5.5 I
OL
=
24mA
(1)
0.36 0.44
I
IN
Maximum Input
Leakage Current
5.5 V
I
=
V
CC
, GND ±0.1 ±1.0 µA
I
CCT
Maximum I
CC
/Input 5.5 V
I
=
V
CC
– 2.1V 0.6 1.5 mA
I
OLD
Minimum Dynamic
Output Current
(2)
5.5 V
OLD
=
1.65V Max. 75 mA
I
OHD
5.5 V
OHD
=
3.85V Min. –75 mA
I
CC
Maximum Quiescent
Supply Current
5.5 V
IN
=
V
CC
or GND 2.0 20.0 µA
V
OLP
Quiet Output Maximum
Dynamic V
OL
5.0 Figures 1 & 2
(3)
1.1 1.5 V
V
OLV
Quiet Output Minimum
Dynamic V
OL
5.0 Figures 1 & 2
(3)
–0.6 –1.2 V
V
IHD
Minimum HIGH Level
Dynamic Input Voltage
5.0
(4)
1.9 2.2 V
V
ILD
Maximum LOW Level
Dynamic Input Voltage
5.0
(4)
1.2 0.8 V
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ00 Rev. 1.4 4
AC Electrical Characteristics
Notes:
5. Voltage range 5.0 is 5.0V ± 0.5V.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol Parameter VCC (V)(5)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
UnitsMin. Typ. Max. Min. Max.
tPLH Propagation Delay,
Data to Output
5.0 2.0 7.5 2.0 8.0 ns
tPHL Propagation Delay,
Data to Output
5.0 2.0 7.5 2.0 8.0 ns
tOSHL, tOSLH Output to Output Skew(6) 5.0 0.5 1.0 1.0 ns
Symbol Parameter Conditions Typ. Units
CIN Input Capacitance VCC = OPEN 4.5 pF
CPD Power Dissipation Capacitance VCC = 5.0V 74 pF
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ00 Rev. 1.4 5
FACT™ Noise Characteristics
The setup of a noise characteristics measurement is
critical to the accuracy and repeatability of the tests. The
following is a brief description of the setup used to
measure the noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the word generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper
loading of the outputs and that the input levels are at
the correct voltage.
4. Set the HFS generator to toggle all but one output at
a frequency of 1MHz. Greater frequencies will
increase DUT heating and effect the results of the
measurement.
5. Set the HFS generator input levels at 0V LOW and
3V HIGH for ACT devices and 0V LOW and 5V HIGH
for AC devices. Verify levels with an oscilloscope.
Notes:
7. VOHV and VOLP are measured with respect to ground
reference.
8. Input pulses have the following characteristics:
f = 1MHz, tr = 3ns, tf = 3ns, skew < 150ps.
Figure 1. Quiet Output Noise Voltage Waveforms
VOLP/VOLV and VOHP/VOHV:
■Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually
be the furthest from the ground pin. Monitor the output
voltages using a 50Ω coaxial cable plugged into a
standard SMB type connector on the test fixture. Do
not use an active FET probe.
■Measure VOLP and VOLV on the quiet output during
the worst case transition for active and enable.
Measure VOHP and VOHV on the quiet output during
the worst case active and enable transition.
■Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
VILD and VIHD:
■Monitor one of the switching outputs using a 50Ω
coaxial cable plugged into a standard SMB type
connector on the test fixture. Do not use an active
FET probe.
■First increase the input LOW voltage level, VIL, until
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input LOW voltage level at
which oscillation occurs is defined as VILD.
■Next decrease the input HIGH voltage level.VIH until
the output begins to oscillate or steps out a mine of
2ns. Oscillation is defined as noise on the output LOW
level that exceeds VIL limits, or on output HIGH levels
that exceed VIH limits. The input HIGH voltage level at
which oscillation occurs is defined as VIHD.
■Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
Figure 2. Simultaneous Switching Test Circuit
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ00 Rev. 1.4 6
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ00 Rev. 1.4 7
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 4. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
74ACTQ00 Quiet Series™ Quad 2-Input NAND Gate
©1990 Fairchild Semiconductor Corporation www.fairchildsemi.com
74ACTQ00 Rev. 1.4 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.
ACEx®
Across the board. Around the world.™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
CTL™
Current Transfer Logic™
DOME™
E2CMOS™
EcoSPARK®
EnSigna™
FACT Quiet Series™
FACT®
FAST®
FASTr™
FPS™
FRFET®
GlobalOptoisolator™
GTO™
HiSeC™
i-Lo™
ImpliedDisconnect™
IntelliMAX™
ISOPLANAR™
MICROCOUPLER™
MicroPak™
MICROWIRE™
Motion-SPM™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR®
PACMAN™
PDP-SPM™
POP™
Power220®
Power247®
PowerEdge™
PowerSaver™
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
ScalarPump™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TCM™
The Power Franchise®
™
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyWire™
TruTranslation™
µSerDes™
UHC®
UniFET™
VCX™
Wire™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed Full Production
First Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete Not In Production This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I26
