Precision, Miniature MEMs IMU ADIS16477 Data Sheet FEATURES GENERAL DESCRIPTION Triaxial, digital gyroscope 125/sec, 500/sec, 2000/sec range models 2/hr in-run bias stability (ADIS16477-1) 0.15/hr angle random walk (ADIS16477-1 and ADIS16477-2) 0.1 axis-to-axis misalignment error Triaxial, digital accelerometer, 40 g 13 g in-run bias stability Triaxial, delta angle and delta velocity outputs Factory calibrated sensitivity, bias, and axial alignment Calibration temperature range: -40C to +85C SPI compatible data communications Programmable operation and control Automatic and manual bias correction controls Data ready indicator for synchronous data acquisition External sync modes: direct, pulse, scaled, and output On demand self test of inertial sensors On demand self test of flash memory Single-supply operation (VDD): 3.0 V to 3.6 V 2000 g mechanical shock survivability Operating temperature range: -40C to +105C The ADIS16477 is a precision, miniature MEMS inertial measurement unit (IMU) that includes a triaxial gyroscope and a triaxial accelerometer. Each inertial sensor in the ADIS16477 combines with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, linear acceleration (gyroscope bias), and point of percussion (accelerometer location). As a result, each sensor has dynamic compensation formulas that provide accurate sensor measurements over a broad set of conditions. The ADIS16477 provides a simple, cost effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The serial peripheral interface (SPI) and register structure provide a simple interface for data collection and configuration control. The ADIS16477 is available in a 44-ball, ball grid array (BGA) package that is approximately 11 mm x 15 mm x 11 mm. APPLICATIONS Navigation, stabilization, and instrumentation Unmanned and autonomous vehicles Smart agriculture/construction machinery Factory/industrial automation, robotics Virtual/augmented reality Internet of Moving Things FUNCTIONAL BLOCK DIAGRAM DR SELF TEST RST POWER MANAGEMENT I/O OUTPUT DATA REGISTERS TRIAXIAL GYROSCOPE TRIAXIAL ACCELEROMETER CONTROLLER CALIBRATION AND FILTERS GND CS SCLK SPI USER CONTROL REGISTERS DIN DOUT CLOCK ADIS16477 SYNC 15437-001 TEMPERATURE SENSOR VDD Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017-2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADIS16477 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Device Configuration ................................................................ 16 Applications ...................................................................................... 1 User Register Memory Map.......................................................... 17 General Description ......................................................................... 1 User Register Defintions ............................................................... 19 Functional Block Diagram .............................................................. 1 Gyroscope Data .......................................................................... 19 Revision History ............................................................................... 2 Delta Angles ................................................................................ 22 Specifications .................................................................................... 3 Delta Velocity ............................................................................. 23 Timing Specifications .................................................................. 5 Calibration .................................................................................. 25 Absolute Maximum Ratings ....................................................... 7 Applications Information ............................................................. 32 Thermal Resistance ...................................................................... 7 Assembly and Handling Tips ................................................... 32 ESD Caution.................................................................................. 7 Power Supply Considerations .................................................. 33 Pin Configuration and Function Descriptions ............................ 8 Serial Port Operation ................................................................. 33 Typical Performance Characteristics ........................................... 10 Digital Resolution of Gyroscopes and Accelerometers ........ 33 Theory of Operation ...................................................................... 12 Evaluation Tools......................................................................... 34 Introduction ................................................................................ 12 Tray Drawing .................................................................................. 36 Inertial Sensor Signal Chain ..................................................... 12 Packaging and Ordering Information ......................................... 37 Register Structure ....................................................................... 13 Outline Dimensions ................................................................... 37 Serial Peripheral Interface (SPI) ............................................... 14 Ordering Guide .......................................................................... 37 Data Ready (DR) ........................................................................ 14 Reading Sensor Data .................................................................. 15 REVISION HISTORY 4/2020--Rev. C to Rev. D Change to Logic Inputs Parameter, Table 1 ................................. 4 Changes to Endnote 1, Table 3 ....................................................... 7 5/2019--Rev. B to Rev. C Changes to Serial Peripheral Interface (SPI) Section ................ 14 Changes to Figure 32 ..................................................................... 15 Changes to Table 10 and Gyroscope Data Section .................... 19 Changes to Acceleration Data Section ........................................ 21 Added Accelerometer Data Formatting Section Header .......... 21 Deleted Accelerometer Resolution Header ................................ 21 Added Serial Port Operation Section, Maximum Throughput Section, Serial Port SCLK Underrun/Overrun Conditions Section, and Digital Resolution of Gyroscopes and Accelerometers Section ................................................................. 33 Moved Gyroscope Data Width (Digital Resolution) Section... 33 Moved Accelerometer Data Width (Digital Resolution) Section . 33 Moved Figure 52 and Figure 53.................................................... 35 Added Tray Drawing Section and Figure 54; Renumbered Sequentially ..................................................................................... 36 2/2019--Rev. A to Rev. B Changes to Table 1 ........................................................................... 3 Changes to Table 2 ........................................................................... 5 Changes to Figure 5 ..........................................................................6 Changes to Figure 11 ..................................................................... 10 Added Figure 12 and Figure 13; Renumbered Sequentially..... 10 Added Figure 14, Figure 15, Figure 16, and Figure 17 .............. 11 Changes to Figure 18, Figure 19, and Figure 20 ........................ 12 Changes to Figure 22 and Figure 23 ............................................ 13 Added Gyroscope Data Width (Digital Resolution) Section ... 19 Changes to Gyroscope Measurement Range/Scale Factor Section, Table 11, Table 12, Table 13, Table 17, Table 21, and Table 25 .... 20 Added Accelerometer Data Width (Digital Resolution) Section .............................................................................................. 21 Change to Calibration, Accelerometer Bias (XA_BIAS_LOW and XA_BIAS_HIGH) Section..................................................... 26 Change to Filter Control Register (FILT_CTRL) Section ........ 27 Changes to Direct Sync Mode Section and to Pulse Sync Mode Section .............................................................................................. 28 Changes to Sensor Self Test Section ............................................ 30 11/2017--Rev. 0 to Rev. A Changes to Table 1 ............................................................................3 Changes to Figure 26 ..................................................................... 14 10/2017--Revision 0: Initial Version Rev. D | Page 2 of 37 Data Sheet ADIS16477 SPECIFICATIONS Case temperature (TC) = 25C, VDD = 3.3 V, angular rate = 0/sec, dynamic range = 2000/sec 1 g, unless otherwise noted. Table 1. Parameter GYROSCOPES Dynamic Range Sensitivity Error over Temperature Repeatability 1 Misalignment Error Nonlinearity2 Bias Repeatability1 In-Run Bias Stability Angular Random Walk Error over Temperature Linear Acceleration Effect Vibration Rectified Error (VRE) Output Noise Rate Noise Density 3 dB Bandwidth Sensor Resonant Frequency ACCELEROMETERS3 Dynamic Range Sensitivity Error over temperature Repeatability1 Misalignment Error Nonlinearity Bias Repeatability1 In-Run Bias Stability Velocity Random Walk Error over Temperature Test Conditions/Comments Min ADIS16477-1 ADIS16477-2 ADIS16477-3 ADIS16477-1, 16-bit ADIS16477-2, 16-bit ADIS16477-3, 16-bit ADIS16477-1, 32-bit ADIS16477-2, 32-bit ADIS16477-3, 32-bit -40C TC +85C, 1 -40C TC +85C, 1 Axis to axis, -40C TC +85C, 1 ADIS16477-1, full scale (FS) = 125/sec ADIS16477-2, FS = 500/sec ADIS16477-3, FS = 2000/sec 125 500 2000 Typ Max Unit 160 40 10 10,485,760 2,621,440 655,360 0.3 0.3 0.1 0.2 0.2 0.25 /sec /sec /sec LSB//sec LSB//sec LSB//sec LSB//sec LSB//sec LSB//sec % % Degrees % FS % FS % FS 0.7 2 2.5 7 0.15 0.15 0.3 0.2 0.01 0.0005 0.07 0.08 0.17 0.003 0.003 0.007 550 66 /sec /hr /hr /hr /hr /hr /hr /sec /sec/g /sec/g2 /sec rms /sec rms /sec rms /sec/Hz rms /sec/Hz rms /sec/Hz rms Hz kHz 32-bit data format -40C TC +85C, 1 -40C TC +85C, 1 Axis to axis, -40C TC +85C, 1 Best fit straight line, 10 g Best fit straight line, 20 g Best fit straight line, 40 g 52,428,800 0.1 0.1 0.05 0.02 0.4 1.5 g LSB/g % % Degrees % FS % FS % FS -40C TC +85C, 1 1 1 -40C TC +85C, 1 6 13 0.037 3 mg g m/sec/hr mg -40C TC +85C, 1 ADIS16477-1, 1 ADIS16477-2, 1 ADIS16477-3, 1 ADIS16477-1, 1 ADIS16477-2, 1 ADIS16477-3, 1 -40C TC +85C, 1 Any direction, 1 Random vibration, 2 grms, 50 Hz to 2 kHz ADIS16477-1, 1 , no filtering ADIS16477-2, 1 , no filtering ADIS16477-3, 1 , no filtering ADIS16477-1, f = 10 Hz to 40 Hz ADIS16477-2, f = 10 Hz to 40 Hz ADIS16477-3, f = 10 Hz to 40 Hz Each axis 40 Rev. D | Page 3 of 37 ADIS16477 Parameter Output Noise Noise Density 3 dB Bandwidth Sensor Resonant Frequency TEMPERATURE SENSOR Scale Factor LOGIC INPUTS4 Input Voltage High, VIH Low, VIL RST Pulse Width Input Current Logic 1, IIH Logic 0, IIL All Pins Except RST RST Pin Input Capacitance, CIN DIGITAL OUTPUTS Output Voltage High, VOH Low, VOL FLASH MEMORY Data Retention6 FUNCTIONAL TIMES7 Power-On Start-Up Time Reset Recovery Time8 Factory Calibration Restore Flash Memory Backup Flash Memory Test Time Self Test Time9 CONVERSION RATE Initial Clock Accuracy Sync Input Clock POWER SUPPLY, VDD Power Supply Current10 Data Sheet Test Conditions/Comments No filtering f = 10 Hz to 40 Hz, no filtering Min Y-axis and z-axis X-axis Typ 2.3 100 600 5.65 5.25 Output = 0x0000 at 0C (5C) 0.1 Max C/LSB 2.0 0.8 V V s 10 A 10 A mA pF 1 VIH = 3.3 V VIL = 0 V 0.33 10 ISOURCE = 0.5 mA ISINK = 2.0 mA Endurance5 TJ = 85C Time until data is available 2.4 0.4 10000 20 252 193 142 72 32 14 2000 3 GLOB_CMD, Bit 7 = 1 (see Table 113) GLOB_CMD, Bit 1 = 1 (see Table 113) GLOB_CMD, Bit 3 = 1 (see Table 113) GLOB_CMD, Bit 4 = 1 (see Table 113) GLOB_CMD, Bit 2 = 1 (see Table 113) Operating voltage range Normal mode, VDD = 3.3 V 1 1.9 3.0 44 Unit mg rms g/Hz rms Hz kHz kHz 2.1 3.6 55 V V Cycles Years ms ms ms ms ms ms SPS % kHz V mA Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of high temperature operating life (HTOL) at 105C. This measurement is based on the deviation from a best fit linear model. All specifications associated with the accelerometers relate to the full-scale range of 8 g, unless otherwise noted. 4 The digital input/output signals use a 3.3 V system. 5 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at -40C, +25C, +85C, and +125C. 6 The data retention specification assumes a junction temperature (TJ) of 85C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ. 7 These times do not include thermal settling and internal filter response times, which may affect overall accuracy. 8 The RST line must be in a low state for at least 10 s to ensure a proper reset initiation and recovery. 9 The self test time can extend when using external clock rates lower than 2000 Hz. 10 Power supply current transients can reach 100 mA during initial startup or reset recovery. 2 3 Rev. D | Page 4 of 37 Data Sheet ADIS16477 TIMING SPECIFICATIONS TA = 25C, VDD = 3.3 V, unless otherwise noted. Table 2. Normal Mode Min Typ Max 0.1 2 16 24 200 Parameter fSCLK tSTALL tREADRATE tCS Description Serial clock Stall period between data Read rate Chip select to SCLK edge tDAV tDSU tDHD tSCLKR, tSCLKF tDR, tDF tSFS t1 DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise/fall times DOUT rise/fall times CS high after SCLK edge Input sync positive pulse width; pulse sync mode, MSC_CTRL = 101 (binary, see Table 105) Input sync to data ready valid transition Direct sync mode, MSC_CTRL = 001 (binary, see Table 105) Pulse sync mode, MSC_CTRL = 101 (binary, see Table 105) Data invalid time Input sync period2 tSTDR tNV t2 1 2 Burst Read Mode Min1 Typ Max 0.1 1 N/A 200 25 25 25 50 25 50 5 5 12.5 12.5 0 5 5 5 12.5 12.5 0 5 256 256 20 256 256 20 477 477 Timing Diagrams tSCLKR tSCLKF tCS 2 3 4 5 tDAV DOUT MSB DB14 A6 16 DB13 DB12 DB11 tDHD A5 DB10 DB2 DB1 LSB tDF A4 A3 A2 D2 D1 LSB Figure 2. SPI Timing and Sequence Diagram READRATE STALL 15437-003 R/W 15 tDR tDSU DIN 6 15437-002 SCLK tSFS 1 Figure 3. Stall Time and Data Rate Timing Diagram Rev. D | Page 5 of 37 ns ns ns ns ns ns s s s s s N/A means not applicable. This specification is rounded up from the cycle time that comes from the maximum input clock frequency (2100 Hz). CS Unit MHz s s ns ADIS16477 Data Sheet t2 tSTDR t1 DR tNV 15437-004 SYNC Figure 4. Input Clock Timing Diagram, Pulse Sync Mode, Register MSC_CTRL, Bits[4:2] = 101 (Binary) t2 t1 SYNC tNV tSTDR 15437-005 DR Figure 5. Input Clock Timing Diagram, Direct Sync Mode, Register MSC_CTRL, Bits[4:2] = 001 (Binary) Rev. D | Page 6 of 37 Data Sheet ADIS16477 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Mechanical Shock Survivability Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Calibration Temperature Range Operating Temperature Range Storage Temperature Range1 Barometric Pressure 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating 2000 g 2000 g -0.3 V to +3.6 V -0.3 V to VDD + 0.2 V -0.3 V to VDD + 0.2 V -40C to +85C -40C to +105C -65C to +150C 2 bar The ADIS16477 is a multichip module that includes many active components. The values in Table 4 identify the thermal response of the hottest component inside of the ADIS16477, with respect to the overall power dissipation of the module. This approach enables a simple method for predicting the temperature of the hottest junction, based on either ambient or case temperature. For example, when the ambient temperature is 70C, the hottest junction temperature (TJ) inside of the ADIS16477 is 76.7C. Extended exposure to temperatures that are lower than -40C or higher than +105C may adversely affect the accuracy of the factory calibration. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. TJ = JA x VDD x IDD + 70C TJ = 158.2C/W x 3.3 V x 0.044 A + 70C TJ = 93C Table 4. Package Characteristics Package Type ML-44-13 1 JA1 158.2C/W JC2 106.1C/W Device Weight 1.3 g JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. 3 Thermal impedance values come from direct observation of the hottest temperature inside of the ADIS16477, when it is attached to an FR4-08 PCB that has two metal layers and has a thickness of 0.063 inches. 2 ESD CAUTION Rev. D | Page 7 of 37 ADIS16477 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADIS16477 A B C D E F G H J K 1 2 PIN A1 3 4 5 6 7 PIN K8 Figure 7. Pin Assignments, Package Level View Figure 6. Pin Assignments, Bottom View Table 5. Pin Function Descriptions Pin No. A1 A2 A3 A4 A5 A6 A7 A8 B3 B4 B5 B6 C2 C3 C6 C7 D3 D6 E2 E3 E6 E7 F1 F3 F6 F8 G2 G3 G6 G7 H1 H3 H6 H8 Mnemonic GND GND GND GND GND GND GND GND GND GND GND GND GND DNC GND VDD GND VDD GND VDD GND GND GND RST GND GND GND CS DIN GND VDD DOUT SCLK GND 15437-007 BOTTOM VIEW OF PACKAGE 15437-006 PIN A8 8 Type Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Not applicable Supply Supply Supply Supply Supply Supply Supply Supply Supply Input Supply Supply Supply Input Input Supply Supply Output Input Supply Rev. D | Page 8 of 37 Description Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Do Not Connect Power Ground Power Supply Power Ground Power Supply Power Ground Power Supply Power Ground Power Ground Power Ground Reset Power Ground Power Ground Power Ground SPI, Chip Select SPI, Data Input Power Supply Power Supply SPI, Data Output SPI, Serial Clock Power Ground Data Sheet Pin No. J2 J3 J4 J5 J6 J7 K1 K3 K6 K8 ADIS16477 Mnemonic GND SYNC VDD VDD DR GND GND GND VDD GND Type Supply Input Supply Supply Output Supply Supply Supply Supply Supply Rev. D | Page 9 of 37 Description Power Ground Sync (External Clock) Power Supply Power Supply Data Ready Power Ground Power Ground Power Ground Power Supply Power Ground ADIS16477 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS X-AXIS Y-AXIS Z-AXIS 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) 0.001 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) 15437-011 0.001 15437-008 ALLAN DEVIATION (g) ALLAN DEVIATION (/hr) X-AXIS Y-AXIS Z-AXIS Figure 11. Accelerometer Allan Deviation, TC = 25C Figure 8. Gyroscope Allan Deviation, TC = 25C, ADIS16477-1 0.5 X-AXIS Y-AXIS Z-AXIS 0.4 ALLAN DEVIATION (/hr) SENSITIVITY ERROR (%) 0.3 0.2 0.1 + 1 0 -0.1 -0.2 - 1 -0.3 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) -0.5 -60 15437-009 0.001 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (C) 15437-112 -0.4 Figure 12. ADIS16477-1 Gyroscope Sensitivity Error vs. Ambient Temperature Figure 9. Gyroscope Allan Deviation, TC = 25C, ADIS16477-2 0.5 X-AXIS Y-AXIS Z-AXIS 0.4 ALLAN DEVIATION (/hr) SENSITIVITY ERROR (%) 0.3 0.2 + 1 0.1 0 -0.1 -0.2 - 1 -0.3 0.01 0.1 1 10 100 1000 10000 100000 INTEGRATION PERIOD (Seconds) Figure 10. Gyroscope Allan Deviation, TC = 25C, ADIS16477-3 -0.5 -60 15437-010 0.001 -40 -20 0 20 40 60 AMBIENT TEMPERATURE (C) 80 100 15437-113 -0.4 Figure 13. ADIS16477-2 Gyroscope Sensitivity Error vs. Ambient Temperature Rev. D | Page 10 of 37 ADIS16477 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 BIAS ERROR (/sec) 0.1 0 + 1 -0.1 -0.2 -0.3 0 -0.1 - 1 0 20 40 60 80 100 -0.5 -60 0.4 0.4 0.3 0.3 BIAS ERROR (/sec) 0.1 0 -0.1 - 1 -0.2 0.2 60 AMBIENT TEMPERATURE (C) 80 100 -0.5 -60 15437-115 40 Figure 15. ADIS16477-1 Gyroscope Bias Error vs. Ambient Temperature 80 100 - 1 -0.2 -0.4 20 60 + 1 -0.1 -0.4 0 40 0 -0.3 -20 20 0.1 -0.3 -40 0 Figure 16. ADIS16477-2 Gyroscope Bias Error vs. Ambient Temperature 0.5 + 1 -20 AMBIENT TEMPERATURE (C) 0.5 0.2 -40 15437-116 -20 15437-114 -40 Figure 14. ADIS16477-3 Gyroscope Sensitivity Error vs. Ambient Temperature -0.5 -60 -0.2 -0.4 AMBIENT TEMPERATURE (C) BIAS ERROR (/sec) 0.1 -0.3 - 1 -0.4 -0.5 -60 + 1 -40 -20 0 20 40 60 AMBIENT TEMPERATURE (C) 80 100 15437-117 SENSITIVITY ERROR (%) Data Sheet Figure 17. ADIS16477-3 Gyroscope Bias Error vs. Ambient Temperature Rev. D | Page 11 of 37 ADIS16477 Data Sheet THEORY OF OPERATION INTRODUCTION External Clock Options When using the factory default configuration for all user configurable control registers, the ADIS16477 initializes itself and automatically starts a continuous process of sampling, processing, and loading calibrated sensor data into its output registers at a rate of 2000 SPS. The ADIS16477 provides three different modes of operation that support the device using an external clock to control the internal processing rate (fSM in Figure 19 and Figure 20) through the SYNC pin. The MSC_CTRL register (see Table 105) provides the configuration options for these external clock modes in Bits[4:2]. Figure 18 provides the basic signal chain for the inertial sensors in the ADIS16477. This signal chain produces an update rate of 2000 SPS in the output data registers when it operates in internal clock mode (default, see Register MSC_CTRL, Bits[4:2] in Table 105). BARTLETT WINDOW FIR FILTER AVERAGING DECIMATING FILTER CALIBRATION OUTPUT DATA REGISTERS 15437-014 MEMS SENSORS Inertial Sensor Calibration The inertial sensor calibration function for the gyroscopes and the accelerometers has two components: factory calibration and user calibration (see Figure 21). FROM BARTLETT WINDOW FIR FILTER Gyroscope Data Sampling fSG = 4100Hz fSM = 2000Hz 15437-015 TO BARTLETT WINDOW FIR FILTER INTERNAL DATA REGISTER Figure 19. Gyroscope Data Sampling Accelerometer Data Sampling The three accelerometers produce linear acceleration measurements along the same orthogonal axes (x, y, and z) as the gyroscopes. Figure 20 shows the data sampling plan for each accelerometer when the ADIS16477 operates in internal clock mode (default, see Register MSC_CTRL, Bits[4:2] in Table 105). ADC 1 2 a(n) 2n=1 /2 2 x fSM = 4000Hz Figure 20. Accelerometer Data Sampling TO BARTLETT WINDOW FIR FILTER 15437-016 MEMS ACCELEROMETER TO AVERAGING DECIMATING FILTER Figure 21. Inertial Sensor Calibration Processing m13 X bX m23 Y bY m33 Z bZ l13 a XC l23 aYC l33 aZC XC m11 m12 YC m21 m22 m31 m32 ZC The three gyroscopes produce angular rate measurements around three orthogonal axes (x, y, and z). Figure 19 shows the data sampling plan for each gyroscope when the ADIS16477 operates in internal clock mode (default, see Register MSC_CTRL, Bits[4:2] in Table 105). Each gyroscope has an analog-to-digital converter (ADC) and sample clock (fSG) that drives data sampling at a rate of 4100 Hz (5%). The internal processor reads and processes this data from each gyroscope at a rate of 2000 Hz (fSM). ADC USER CALIBRATION The factory calibration of the gyroscope applies the following correction formulas to the data of each gyroscope: Figure 18. Signal Processing Diagram, Inertial Sensors MEMS GYROSCOPE FACTORY CALIBRATION 15437-017 INERTIAL SENSOR SIGNAL CHAIN l11 l12 l21 l22 l31 l32 where: XC, YC, and ZC are the gyroscope outputs (post calibration). m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and alignment correction. X, Y, and Z are the gyroscope outputs (precalibration). bX, bY, and bZ provide bias correction. l11, l12, l13, l21, l22, l23, l31, l32, and l33 provide linear g correction aXC, aYC, and aZC are the accelerometer outputs (post calibration). All of the correction factors in this relationship come from direct observation of the response of each gyroscope at multiple temperatures over the calibration temperature range (-40C TC +85C). These correction factors are stored in the flash memory bank, but they are not available for observation or configuration. Register MSC_CTRL, Bit 7 (see Table 105) provides the only user configuration option for the factory calibration of the gyroscopes: an on/off control for the linear g compensation. See Figure 44 for more details on the user calibration options available for the gyroscopes. Rev. D | Page 12 of 37 Data Sheet ADIS16477 0 p32 FROM MEMS SENSOR 1 N (n) Nn = 1 1 N (n) Nn = 1 TO FACTORY CALIBRATION Figure 22. Bartlett Window FIR Filter Signal Path where: aXC, aYC, and aZC are the accelerometer outputs (post calibration). m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and alignment correction. aX, aY, and aZ are the accelerometer outputs (precalibration). bX, bY, and bZ provide bias correction. p12, p13, p21, p23, p31 and p32 provide a point of percussion alignment correction (see Figure 47). 2XC, 2YC, and 2ZC are the square of the gyroscope outputs (post calibration). All of the correction factors in this relationship come from direct observation of the response of each accelerometer at multiple temperatures, over the calibration temperature range (-40C TC +85C). These correction factors are stored in the flash memory bank, but they are not available for observation or configuration. MSC_CTRL, Bit 6 (see Table 105) provides the only user configuration option for the factory calibration of the accelerometers: an on/off control for the point of percussion, alignment function. See Figure 45 for more details on the user calibration options available for the accelerometers. Averaging/Decimating Filter The second digital filter averages multiple samples together to produce each register update. In this type of filter structure, the number of samples in the average is equal to the reduction in the update rate for the output data registers. The DEC_RATE register (see Table 109) provides the configuration controls for this filter. FROM USER CALIBRATION 1 N (n) N n =1 /N TO OUTPUT REGISTERS Figure 23. Averaging/Decimating Filter Diagram REGISTER STRUCTURE All communication between the ADIS16477 and an external processor involves either reading the contents of an output register or writing configuration/command information to a control register. The output data registers include the latest sensor data, error flags, and identification information. The control registers include sample rate, filtering, calibration, and diagnostic options. Each user accessible register has two bytes (upper and lower), each of which has its own unique address. See Table 8 for a detailed list of all user registers, along with their addresses. TRIAXIAL GYROSCOPE TRIAXIAL ACCELLEROMETER TEMPERATURE SENSOR SENSOR SIGNAL PROCESSING OUTPUT REGISTERS CONTROLLER CONTROL REGISTERS Figure 24. Basic Operation of the ADIS16477 Rev. D | Page 13 of 37 15437-020 p12 15437-019 0 p21 p31 m13 a X b X m23 aY bY m33 a Z bZ 2 p13 XC 2 p23 YC 2 0 ZC The Bartlett window finite impulse response (FIR) filter (see Figure 22) contains two averaging filter stages, in a cascade configuration. The FILT_CTRL register (see Table 101) provides the configuration controls for this filter. SPI a XC m11 m12 aYC m21 m22 a m31 m32 ZC Bartlett Window FIR Filter 15437-018 The factory calibration of the accelerometer applies the following correction formulas to the data of each accelerometer: ADIS16477 Data Sheet DATA READY (DR) The SPI provides access to the user registers (see Table 8). Figure 25 shows the most common connections between the ADIS16477 and a SPI master device, which is often an embedded processor that has a SPI-compatible interface. In this example, the SPI master uses an interrupt service routine to collect data every time the data ready (DR) signal pulses. The factory default configuration provides users with a DR signal on the DR pin (see Table 5), which pulses when the output data registers are updating. Connect the DR pin to a pin on the embedded processor, which triggers data collection, on the second edge of this pulse. The MSC_CTRL register, Bit 0 (see Table 105), controls the polarity of this signal. In Figure 26, Register MSC_CTRL, Bit 0 = 1, which means that data collection must start on the rising edges of the DR pulses. Additional information on the ADIS16477 SPI can be found in the Serial Port Operation section of this data sheet. I/O LINES ARE COMPATIBLE WITH 3.3V LOGIC LEVELS +3.3V VDD 15437-022 SERIAL PERIPHERAL INTERFACE (SPI) DR ACTIVE INACTIVE Figure 26. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default) ADIS16477 SCLK SCLK MOSI DIN MISO DOUT DR 15437-021 IRQ During the start-up and reset recovery processes, the DR signal may exhibit some transient behavior before data production begins. Figure 27 shows an example of the DR behavior during startup, and Figure 28 and Figure 29 provide examples of the DR behavior during recovery from reset commands. TIME THAT VDD > 3V VDD Figure 25. Electrical Connection Diagram PULSING INDICATES DATA PRODUCTION Table 6. Generic SPI Master Pin Names and Functions Mnemonic SS SCLK MOSI MISO IRQ Function Slave select Serial clock Master output, slave input Master input, slave output Interrupt request DR START-UP TIME Figure 27. Data Ready Response During Startup SOFTWARE RESET COMMAND GLOB_CMD[7] = 1 Embedded processors typically use control registers to configure their serial ports for communicating with SPI slave devices such as the ADIS16477. Table 7 provides a list of settings that describe the SPI protocol of the ADIS16477. The initialization routine of the master processor typically establishes these settings using firmware commands to write them into the control registers. DR PULSING RESUMES DR RESET RECOVERY TIME Figure 28. Data Ready Response During Reset (Register GLOB_CMD, Bit 7 = 1) Recovery Table 7. Generic Master Processor SPI Settings Processor Setting Master SCLK 2 MHz1 SPI Mode 3 MSB First Mode 16-Bit Mode 1 15437-023 CS 15437-024 SS RST PIN RELEASED Description ADIS16477 operates as slave Maximum serial clock rate CPOL = 1 (polarity), CPHA = 1 (phase) Bit sequence, see Figure 30 for coding Shift register and data length RST DR PULSING RESUMES DR A burst mode read requires this value to be 1 MHz (see Table 2 for more information). Rev. D | Page 14 of 37 RESET RECOVERY TIME Figure 29. Data Ready Response During Reset (RST = 0) Recovery 15437-025 SYSTEM PROCESSOR SPI MASTER Data Sheet ADIS16477 CS DIN R/W D15 DOUT A6 A5 A4 A3 A2 A1 A0 DC7 D14 D13 D12 D11 D10 D9 D8 D7 DC6 DC5 D6 DC4 D5 D4 DC3 DC2 D3 D2 R/W DC1 DC0 D1 D0 D15 A6 A5 D14 D13 NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0. 2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE FOR OTHER DEVICES. 15437-026 SCLK Figure 30. SPI Communication Bit Sequence 1 CS 2 3 11 SCLK DIN DIAG_STAT DOUT XGYRO_OUT 15437-027 0x6800 CHECKSUM Figure 31. Burst Read Sequence CS SCLK DIN DOUT HIGH-Z HIGH-Z DOUT = 0100 0000 0101 1101 = 0x405D = 16477 (PROD_ID) 15437-028 DIN = 0x7200 = 0111 0010 0000 0000 Figure 32. SPI Signal Pattern Showing a Read of the PROD_ID Register Burst Read Function Reading a single register requires two 16-bit cycles on the SPI: one to request the contents of a register and another to receive those contents. The 16-bit command code (see Figure 30) for a read request on the SPI has three parts: the read bit (R/W = 0), either address of the register, [A6:A0], and eight don't care bits, [DC7:DC0]. Figure 33 shows an example that includes two register reads in succession. This example starts with DIN = 0x0C00, to request the contents of the Z_GYRO_LOW register, and follows with 0x0E00, to request the contents of the Z_GYRO_OUT register. The sequence in Figure 33 also shows full duplex mode of operation, which means that the ADIS16477 can receive requests on DIN while also transmitting data out on DOUT within the same 16-bit SPI cycle. The burst read function provides a way to read a batch of output data registers, using a continuous stream of bits, at a rate of up to 1 MHz (SCLK). This method does not require a stall time between each 16-bit segment (see Figure 3). As shown in Figure 31, start this mode by setting DIN = 0x6800, and then read each of the registers in the sequence out of DOUT while keeping CS low for the entire 176-bit sequence. DIN DOUT 0x0C00 0x0E00 NEXT ADDRESS Z_GYRO_LOW Z_GYRO_OUT 15437-029 READING SENSOR DATA Figure 33. SPI Read Example Figure 32 provides an example of the four SPI signals when reading the PROD_ID register (see Table 121) in a repeating pattern. This pattern can be helpful when troubleshooting the SPI interface setup and communications because the signals are the same for each 16-bit sequence, except during the first cycle. The sequence of registers (and checksum value) in the burst read response depends on which sample clock mode that the ADIS16477 is operating in (Register MSC_CTRL, Bits[4:2], see Table 105). In all clock modes, except when operating in scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010), the burst read response includes the following registers and value: DIAG_STAT, X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_ OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, DATA_ CNTR, and the checksum value. In these cases, use the following formula to verify the checksum value, treating each byte in the formula as an independent, unsigned, 8-bit number: Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] + X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] + Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] + Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] + X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] + Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] + Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] + TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] + DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0] Rev. D | Page 15 of 37 ADIS16477 Data Sheet When operating in scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010), the burst read response includes the following registers and value: DIAG_STAT, X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, TIME_STAMP, and the checksum value. In this case, use the following formula to verify the checksum value, treating each byte in the formula as an independent, unsigned, 8-bit number. Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] + X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] + Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] + Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] + X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] + Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] + Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] + TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] + TIME_STAMP, Bits[15:8] + TIME_STAMP, Bits[7:0] Memory Structure Figure 35 provides a functional diagram for the memory structure of the ADIS16477. The flash memory bank contains the operational code, unit specific calibration coefficients and user configuration settings. During initialization (power application or reset recover), this information loads from the flash memory into the static random access memory (SRAM), which supports all normal operation, including register access through the SPI port. Writing to a configuration register using the SPI updates the SRAM location of the register but does not automatically update its settings in the flash memory bank. The manual flash memory update command (Register GLOB_CMD, Bit 3, see Table 113) provides a convenient method for saving all of these settings to the flash memory bank at one time. A yes in the flash backup column of Table 8 identifies the registers that have storage support in the flash memory bank. MANUAL FLASH BACKUP Each configuration register contains 16 bits (two bytes). Bits[7:0] contain the low byte, and Bits[15:8] contain the high byte of each register. Each byte has its own unique address in the user register map (see Table 8). Updating the contents of a register requires writing to both of its bytes in the following sequence: low byte first, high byte second. There are three parts to coding a SPI command (see Figure 30) that write a new byte of data to a register: the write bit (R/W = 1), the address of the byte, [A6:A0], and the new data for that location, [DC7:DC0]. Figure 34 shows a coding example for writing 0x0004 to the FILT_CTRL register (see Table 101). In Figure 34, the 0xDC04 command writes 0x04 to Address 0x5C (lower byte) and the 0xDD00 command writes 0x00 to Address 0x5D (upper byte). CS DIN 0xDC04 0xDD00 15437-030 SCLK Figure 34. SPI Sequence for Writing 0x0004 to FILT_CTRL Rev. D | Page 16 of 37 NONVOLATILE FLASH MEMORY VOLATILE SRAM SPI ACCESS (NO SPI ACCESS) START-UP RESET Figure 35. SRAM and Flash Memory Diagram 15437-031 DEVICE CONFIGURATION Data Sheet ADIS16477 USER REGISTER MEMORY MAP Table 8. User Register Memory Map (N/A Means Not Applicable) Name Reserved DIAG_STAT X_GYRO_LOW X_GYRO_OUT Y_GYRO_LOW Y_GYRO_OUT Z_GYRO_LOW Z_GYRO_OUT X_ACCL_LOW X_ACCL_OUT Y_ACCL_LOW Y_ACCL_OUT Z_ACCL_LOW Z_ACCL_OUT TEMP_OUT TIME_STAMP Reserved DATA_CNTR X_DELTANG_LOW X_DELTANG_OUT Y_DELTANG_LOW Y_DELTANG_OUT Z_DELTANG_LOW Z_DELTANG_OUT X_DELTVEL_LOW X_DELTVEL_OUT Y_DELTVEL_LOW Y_DELTVEL_OUT Z_DELTVEL_LOW Z_DELTVEL_OUT Reserved XG_BIAS_LOW XG_BIAS_HIGH YG_BIAS_LOW YG_BIAS_HIGH ZG_BIAS_LOW ZG_BIAS_HIGH XA_BIAS_LOW XA_BIAS_HIGH YA_BIAS_LOW YA_BIAS_HIGH ZA_BIAS_LOW ZA_BIAS_HIGH Reserved FILT_CTRL RANG_MDL MSC_CTRL UP_SCALE R/W N/A R R R R R R R R R R R R R R R N/A R R R R R R R R R R R R R N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R R/W R/W Flash Backup N/A No No No No No No No No No No No No No No No N/A No No No No No No No No No No No No No N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A Yes No Yes Yes Address 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A, 0x2B 0x2C, 0x2D 0x2E, 0x2F 0x30, 0x31 0x32, 0x33 0x34, 0x35 0x36, 0x37 0x38, 0x39 0x3A, 0x3B 0x3C to 0x3F 0x40, 0x41 0x42, 0x43 0x44, 0x45 0x46, 0x47 0x48, 0x49 0x4A, 0x4B 0x4C, 0x4D 0x4E, 0x4F 0x50, 0x51 0x52, 0x53 0x54, 0x55 0x56, 0x57 0x58 to 0x5B 0x5C, 0x5D 0x5E, 0x5F 0x60, 0x61 0x62, 0x63 Default N/A 0x0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 N/A 0x0000 N/A1 0x00C1 0x07D0 DEC_RATE R/W Yes 0x64, 0x65 0x0000 Rev. D | Page 17 of 37 Register Description Reserved Output, system error flags Output, x-axis gyroscope, low word Output, x-axis gyroscope, high word Output, y-axis gyroscope, low word Output, y-axis gyroscope, high word Output, z-axis gyroscope, low word Output, z-axis gyroscope, high word Output, x-axis accelerometer, low word Output, x-axis accelerometer, high word Output, y-axis accelerometer, low word Output, y-axis accelerometer, high word Output, z-axis accelerometer, low word Output, z-axis accelerometer, high word Output, temperature Output, time stamp Reserved New data counter Output, x-axis delta angle, low word Output, x-axis delta angle, high word Output, y-axis delta angle, low word Output, y-axis delta angle, high word Output, z-axis delta angle, low word Output, z-axis delta angle, high word Output, x-axis delta velocity, low word Output, x-axis delta velocity, high word Output, y-axis delta velocity, low word Output, y-axis delta velocity, high word Output, z-axis delta velocity, low word Output, z-axis delta velocity, high word Reserved Calibration, offset, gyroscope, x-axis, low word Calibration, offset, gyroscope, x-axis, high word Calibration, offset, gyroscope, y-axis, low word Calibration, offset, gyroscope, y-axis, high word Calibration, offset, gyroscope, z-axis, low word Calibration, offset, gyroscope, z-axis, high word Calibration, offset, accelerometer, x-axis, low word Calibration, offset, accelerometer, x-axis, high word Calibration, offset, accelerometer, y-axis, low word Calibration, offset, accelerometer, y-axis, high word Calibration, offset, accelerometer, z-axis, low word Calibration, offset, accelerometer, z-axis, high word Reserved Control, Bartlett window FIR filter Measurement range (model specific) identifier Control, input/output and other miscellaneous options Control, scale factor for input clock, pulse per second (PPS) mode Control, decimation filter (output data rate) ADIS16477 Name NULL_CNFG GLOB_CMD Reserved FIRM_REV FIRM_DM FIRM_Y PROD_ID SERIAL_NUM USER_SCR_1 USER_SCR_2 USER_SCR_3 FLSHCNT_LOW FLSHCNT_HIGH 1 Data Sheet R/W R/W W N/A R R R R R R/W R/W R/W R R Flash Backup Yes No N/A No No No No No Yes Yes Yes No No Address 0x66, 0x67 0x68, 0x69 0x6A to 0x6B 0x6C, 0x6D 0x6E, 0x6F 0x70, 0x71 0x72, 0x73 0x74, 0x75 0x76, 0x77 0x78, 0x79 0x7A, 0x7B 0x7C, 0x7D 0x7E, 0x7E Default 0x070A N/A N/A N/A N/A N/A 0x405D N/A N/A N/A N/A N/A N/A See Table 102 for the default value in this register, which is model specific. Rev. D | Page 18 of 37 Register Description Control, bias estimation period Control, global commands Reserved Identification, firmware revision Identification, date code, day and month Identification, date code, year Identification, device number Identification, serial number User Scratch Register 1 User Scratch Register 2 User Scratch Register 3 Output, flash memory write cycle counter, lower word Output, flash memory write cycle counter, upper word Data Sheet ADIS16477 USER REGISTER DEFINTIONS clears them. If an error condition persists, the flag (bit) automatically returns to an alarm value of 1. Status/Error Flag Indicators (DIAG_STAT) Table 9. DIAG_STAT Register Definition Access R GYROSCOPE DATA Flash Backup No Table 10. DIAG_STAT Bit Assignments Bits [15:8] 7 6 5 4 3 2 1 0 Description Reserved. Clock error. A 1 indicates that the internal data sampling clock (fSM, see Figure 19 and Figure 20) does not synchronize with the external clock, which only applies when using scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010, see Table 105). When this error occurs, adjust the frequency of the clock signal on the SYNC pin to operate within the appropriate range. Memory failure. A 1 indicates a failure in the flash memory test (Register GLOB_CMD, Bit 4, see Table 113), which involves a comparison between a cyclic redundancy check (CRC) calculation of the present flash memory and a CRC calculation from the same memory locations at the time of initial programming (during the production process). If this error occurs, repeat the same test. If this error persists, replace the ADIS16477 device. Sensor failure. A 1 indicates failure of at least one sensor, at the conclusion of the self test (Register GLOB_CMD, Bit 2, see Table 113). If this error occurs, repeat the same test. If this error persists, replace the ADIS16477. Motion, during the execution of this test, can cause a false failure. Standby mode. A 1 indicates that the voltage across VDD and GND is <2.8 V, which causes data processing to stop. When VDD 2.8 V for 250 ms, the ADIS16477 reinitializes itself and starts producing data again. SPI communication error. A 1 indicates that the total number of SCLK cycles is not equal to an integer multiple of 16. When this error occurs, repeat the previous communication sequence. Persistence in this error may indicate a weakness in the SPI service that the ADIS16477 is receiving from the system it is supporting. Flash memory update failure. A 1 indicates that the most recent flash memory update (Register GLOB_CMD, Bit 3, see Table 113) failed. If this error occurs, ensure that VDD 3 V and repeat the update attempt. If this error persists, replace the ADIS16477. Data path overrun. A 1 indicates that one of the data paths experienced an overrun condition. If this error occurs, initiate a reset using the RST pin (see Table 5, Pin F3) or Register GLOB_CMD, Bit 7 (see Table 113). See the Serial Port Operation section for more details on conditions that may cause this bit to be set to 1. Reserved The gyroscopes in the ADIS16477 measure the angular rate of rotation around three orthogonal axes (x, y, and z). Figure 36 shows the orientation of each gyroscope axis, along with the direction of rotation that produces a positive response in each of their measurements. Z Z X Y X Y PIN A8 15437-032 Default 0x0000 PIN K1 Figure 36. Gyroscope Axis and Polarity Assignments Each gyroscope has two output data registers. Figure 37 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis gyroscope measurements. This format also applies to the y- and z-axes. Additional information on the precision and resolution of the accelerometers can be found in the Digital Resolution of Gyroscopes and Accelerometers section of this data sheet. X_GYRO_OUT BIT 15 X_GYRO_LOW BIT 0 BIT 15 BIT 0 X-AXIS GYROSCOPE DATA 15437-033 Addresses 0x02, 0x03 Figure 37. Gyroscope Output Data Structure Gyroscope Measurement Range/Scale Factor Table 11 provides the measurement range (MAX) and scale factor (KG) for the gyroscope in each ADIS16477 model. Table 11. Gyroscope Measurement Range and Scale Factors Model ADIS16477-1 ADIS16477-2 ADIS16477-3 The DIAG_STAT register (see Table 9 and Table 10) provides error flags for monitoring the integrity and operation of the ADIS16477. Reading this register causes all of its bits to return to 0. The error flags in DIAG_STAT are sticky, meaning that, when they raise to a 1, they remain there until a read request Rev. D | Page 19 of 37 Range, MAX (/sec) 125 500 2000 Scale Factor, KG (LSB//sec) 160 40 10 ADIS16477 Data Sheet Table 20. Y_GYRO_OUT Register Definition Gyroscope Data Formatting Table 12 and Table 13 offer various numerical examples that demonstrate the format of the rotation rate data in both 16-bit and 32-bit formats. Table 12. 16-Bit Gyroscope Data Format Examples Rotation Rate +MAX +2/KG +1/KG 0/sec -1/KG -2/KG -MAX Decimal +20,000 +2 +1 0 -1 -2 -20,000 Hex 0x4E20 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xB1E0 Binary 0100 1110 0010 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1011 0001 1110 0000 Table 13. 32-Bit Gyroscope Data Format Examples Rotation Rate (/sec) +MAX +2/(KG x 216) +1/(KG x 216) 0 -1/(KG x 216) -2/(KG x 216) -MAX Decimal +1,310,720,000 +2 +1 0 -1 -2 -1,310,720,000 Hex 0x4E200000 0x00000002 0x00000001 0x0000000 0xFFFFFFFF 0xFFFFFFFE 0xB1E00000 Addresses 0x0A, 0x0B Default Not applicable Access R Flash Backup No Table 21. Y_GYRO_OUT Bit Definitions Bits [15:0] Description Y-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG) The Y_GYRO_LOW (see Table 18 and Table 19) and Y_GYRO_ OUT (see Table 20 and Table 21) registers contain the gyroscope data for the y-axis. Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT) Table 22. Z_GYRO_LOW Register Definition Addresses 0x0C, 0x0D Default Not applicable Access R Flash Backup No Table 23. Z_GYRO_LOW Bit Definitions Bits [15:0] Description Z-axis gyroscope data; additional resolution bits Table 24. Z_GYRO_OUT Register Definition Addresses 0x0E, 0x0F Default Not applicable Access R Flash Backup No Table 25. Z_GYRO_OUT Bit Definitions X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT) Bits [15:0] Table 14. X_GYRO_LOW Register Definition Addresses 0x04, 0x05 Default Not applicable Access R Flash Backup No Table 15. X_GYRO_LOW Bit Definitions Bits [15:0] Description X-axis gyroscope data; additional resolution bits Default Not applicable Access R Flash Backup No Table 17. X_GYRO_OUT Bit Definitions Bits [15:0] The Z_GYRO_LOW (see Table 22 and Table 23) and Z_GYRO_ OUT (see Table 24 and Table 25) registers contain the gyroscope data for the z-axis. Acceleration Data Table 16. X_GYRO_OUT Register Definition Addresses 0x06, 0x07 Description Z-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG) The accelerometers in the ADIS16477 measure both dynamic and static (response to gravity) acceleration along the same three orthogonal axes that define the axes of rotation for the gyroscopes (x, y, and z). Figure 38 shows the orientation of each accelerometer axis, along with the direction of acceleration that produces a positive response in each of their measurements. Description X-axis gyroscope data; high word; twos complement, 0/sec = 0x0000, 1 LSB = 1/KG (See Table 11 for KG) Z az The X_GYRO_LOW (see Table 14 and Table 15) and X_GYRO_ OUT (see Table 16 and Table 17) registers contain the gyroscope data for the x-axis. Default Not applicable Access R Table 19. Y_GYRO_LOW Bit Definitions Bits [15:0] X Flash Backup No Description Y-axis gyroscope data; additional resolution bits ax ay Y 15437-034 Table 18. Y_GYRO_LOW Register Definition Addresses 0x08, 0x09 PIN K1 PIN A8 Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT) Figure 38. Accelerometer Axis and Polarity Assignments Each accelerometer has two output data registers. Figure 39 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis accelerometer measurements. This format also applies to the y- and z-axes. Rev. D | Page 20 of 37 Data Sheet ADIS16477 Additional information on the precision and resolution of the accelerometers can be found in the Digital Resolution of Gyroscopes and Accelerometers section of this data sheet. X_ACCL_LOW BIT 15 BIT 0 BIT 15 BIT 0 X-AXIS ACCELEROMETER DATA 15437-035 X_ACCL_OUT Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT) Table 32. Y_ACCL_LOW Register Definition Addresses 0x14, 0x15 Default Not applicable Access R Flash Backup No Table 33. Y_ACCL_LOW Bit Definitions Bits [15:0] Figure 39. Accelerometer Output Data Structure Description Y-axis accelerometer data; additional resolution bits Accelerometer Data Formatting Table 26 and Table 27 offer various numerical examples that demonstrate the format of the linear acceleration data in both 16-bit and 32-bit formats. Table 34. Y_ACCL_OUT Register Definition Table 26. 16-Bit Accelerometer Data Format Examples Table 35. Y_ACCL_OUT Bit Definitions Acceleration +40 g +2.5 mg +1.25 mg 0 mg -1.25 mg -2.5 mg -40 g Bits [15:0] Decimal +32,000 +2 +1 0 -1 -2 -32,000 Hex 0x7D00 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8300 Binary 0111 1101 0000 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0011 0000 0000 Addresses 0x16, 0x17 Default Not applicable Access R Flash Backup No Description Y-axis accelerometer data, high word; twos complement, 40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg The Y_ACCL_LOW (see Table 32 and Table 33) and Y_ACCL_ OUT (see Table 34 and Table 35) registers contain the accelerometer data for the y-axis. Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT) Table 36. Z_ACCL_LOW Register Definition Table 27. 32-Bit Accelerometer Data Format Examples Acceleration +40 g +1.25/215 mg +1.25/216 mg 0 -1.25/216 mg -1.25/215 mg -40 g Decimal +2,097,152,000 +2 +1 0 -1 -2 -2,097,152,000 Addresses 0x18, 0x19 Hex 0x7D000000 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x83000000 Default Not applicable Access R Flash Backup No Table 37. Z_ACCL_LOW Bit Definitions Bits [15:0] Description Z-axis accelerometer data; additional resolution bits Table 38. Z_ACCL_OUT Register Definition Addresses 0x1A, 0x1B Default Not applicable Access R Flash Backup No X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT) Table 39. Z_ACCL_OUT Bit Definitions Table 28. X_ACCL_LOW Register Definition Addresses 0x10, 0x11 Default Not applicable Access R Flash Backup No Table 29. X_ACCL_LOW Bit Definitions Bits [15:0] Description X-axis accelerometer data; additional resolution bits Bits [15:0] The Z_ACCL_LOW (see Table 36 and Table 37) and Z_ACCL_ OUT (see Table 38 and Table 39) registers contain the accelerometer data for the z-axis. Table 30. X_ACCL_OUT Register Definition Addresses 0x12, 0x13 Default Not applicable Access R Flash Backup No Table 31. X_ACCL_OUT Bit Definitions Bits [15:0] Description Z-axis accelerometer data, high word; twos complement, 40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg Description X-axis accelerometer data, high word; twos complement, 40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg The X_ACCL_LOW (see Table 28 and Table 29) and X_ACCL_ OUT (see Table 30 and Table 31) registers contain the accelerometer data for the x-axis. Rev. D | Page 21 of 37 ADIS16477 Data Sheet Internal Temperature (TEMP_OUT) Data Update Counter (DATA_CNTR) Table 40. TEMP_OUT Register Definition Addresses 0x1C, 0x1D Default Not applicable Access R Table 45. DATA_CNTR Register Definition Flash Backup No Addresses 0x22, 0x23 Default Not applicable Access R Table 41. TEMP_OUT Bit Definitions Table 46. DATA_CNTR Bit Definitions Bits [15:0] Bits [15:0] Description Temperature data; twos complement, 1 LSB = 0.1C, 0C = 0x0000 The TEMP_OUT register (see Table 40 and Table 41) provides a coarse measurement of the temperature inside of the ADIS16477. This data is most useful for monitoring relative changes in the thermal environment. Table 42. TEMP_OUT Data Format Examples Temperature (C) +105 +25 +0.2 +0.1 +0 +0.1 +0.2 -40 Decimal +1050 +250 +2 +1 0 -1 -2 -400 Hex 0x041A 0x00FA 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xFE70 Binary 0000 0100 0001 1010 0000 0000 1111 1010 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1111 1110 0111 0000 Flash Backup No Description Data update counter, offset binary format When the ADIS16477 goes through its power-on sequence or when it recovers from a reset command, DATA_CNTR (see Table 45 and Table 46) starts with a value of 0x0000 and increments every time new data loads into the output registers. When the DATA_CNTR value reaches 0xFFFF, the next data update causes it to wrap back around to 0x0000, where it continues to increment every time new data loads into the output registers. DELTA ANGLES In addition to the angular rate of rotation (gyroscope) measurements around each axis (x, y, and z), the ADIS16477 also provides delta angle measurements that represent a calculation of angular displacement between each sample update. Z Z Time Stamp (TIME_STAMP) Table 43. TIME_STAMP Register Definition Default Not applicable Access R X Y PIN K1 PIN A8 Figure 40. Delta Angle Axis and Polarity Assignments Table 44. TIME_STAMP Bit Definitions Bits [15:0] X Y Flash Backup No 15437-036 Addresses 0x1E, 0x1F Description Time from the last pulse on the SYNC pin; offset binary format, 1 LSB = 49.02 s The TIME_STAMP register (see Table 43 and Table 44) works in conjunction with scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010, see Table 105). The 16-bit number in TIME_ STAMP contains the time associated with the last sample in each data update relative to the most recent edge of the clock signal in the SYNC pin. For example, when the value in the UP_SCALE register (see Table 107) represents a scale factor of 20, DEC_RATE = 0, and the external SYNC rate = 100 Hz, the following time stamp sequence results: 0 LSB, 10 LSB, 21 LSB, 31 LSB, 41 LSB, 51 LSB, 61 LSB, 72 LSB, ..., 194 LSB for the 20th sample, which translates to 0 s, 490 s, ..., 9510 s, the time from the first SYNC edge. The delta angle outputs represent an integration of the gyroscope measurements and use the following formula for all three axes (xaxis displayed): x , n D D 1 1 x , n D d x , n D d 1 2 fS d 0 where: D is the decimation rate (DEC_RATE + 1, see Table 109). fS is the sample rate. d is the incremental variable in the summation formula. X is the x-axis rate of rotation (gyroscope). n is the sample time, prior to the decimation filter. When using the internal sample clock, fS is equal to a nominal rate of 2000 SPS. For better precision in this measurement, measure the internal sample rate (fS) using the data ready signal on the DR pin (DEC_RATE = 0x0000, see Table 108), divide each delta angle result (from the delta angle output registers) by the data ready frequency and multiply it by 2000. Each axis of the delta angle measurements has two output data registers. Figure 41 shows how these two registers combine to support a 32-bit, twos complement data format for the x-axis delta angle measurements. This format also applies to the y- and z-axes. Rev. D | Page 22 of 37 Data Sheet ADIS16477 BIT 15 The Y_DELTANG_LOW (see Table 52 and Table 53) and Y_DELTANG_OUT (see Table 54 and Table 55) registers contain the delta angle data for the y-axis. X_DELTANG_LOW BIT 0 BIT 15 BIT 0 X-AXIS DELTA ANGLE DATA 15437-037 X_DELTANG_OUT Z-Axis Delta Angle (Z_DELTANG_LOW and Z_DELTANG_OUT) Figure 41. Delta Angle Output Data Structure Delta Angle Measurement Range Table 56. Z_DELTANG_LOW Register Definitions Table 47 shows the measurement range and scale factor for each ADIS16477 model. Addresses 0x2C, 0x2D Default Not applicable Access R Flash Backup No Table 47. Delta Angle Measurement Range and Scale Factor Model ADIS16477-1BMLZ ADIS16477-2BMLZ ADIS16477-3BMLZ Table 57. Z_DELTANG_LOW Bit Definitions Measurement Range, MAX () 360 720 2160 Bits [15:0] Description Z-axis delta angle data; low word Table 58. Z_DELTANG_OUT Register Definitions X-Axis Delta Angle (X_DELTANG_LOW and X_DELTANG_OUT) Addresses 0x2E, 0x2F Table 48. X_DELTANG_LOW Register Definitions Table 59. Z_DELTANG_OUT Bit Definitions Addresses 0x24, 0x25 Bits [15:0] Default Not applicable Access R Flash Backup No Table 49. X_DELTANG_LOW Bit Definitions Bits [15:0] Table 50. X_DELTANG_OUT Register Definitions Default Not applicable Access R The X_DELTANG_LOW (see Table 48 and Table 49) and X_DELTANG_OUT (see Table 50 and Table 51) registers contain the delta angle data for the x-axis. Y-Axis Delta Angle (Y_DELTANG_LOW and Y_DELTANG_OUT) Table 52. Y_DELTANG_LOW Register Definitions Default Not applicable Access R Flash Backup No Table 53. Y_DELTANG_LOW Bit Definitions Bits [15:0] Description Y-axis delta angle data; low word Table 54. Y_DELTANG_OUT Register Definitions Addresses 0x2A, 0x2B Default Not applicable Access R Flash Backup No Table 60. 16-Bit Delta Angle Data Format Examples Delta Angle () MAX x (215-1)/215 +MAX/214 +MAX/215 0 -MAX/215 -MAX/214 -MAX Decimal +32,767 +2 +1 0 -1 -2 -32,768 Hex 0x7FFF 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8000 Binary 0111 1111 1110 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 Table 61. 32-Bit Delta Angle Data Format Examples Delta Angle () +MAX x (231 - 1)/231 +MAX/230 +MAX/231 0 -MAX/231 -MAX/230 -MAX Decimal +2,147,483,647 +2 +1 0 -1 -2 -2,147,483,648 Hex 0x7FFFFFFF 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x80000000 DELTA VELOCITY Table 55. Y_DELTANG_OUT Bit Definitions Bits [15:0] Description Z-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 47 for MAX) Table 60 and Table 61 show various numerical examples that demonstrate the format of the delta angle data in both 16-bit and 32-bit formats. Description X-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 47 for MAX) Addresses 0x28, 0x29 Flash Backup No Delta Angle Resolution Flash Backup No Table 51. X_DELTANG_OUT Bit Definitions Bits [15:0] Access R The Z_DELTANG_LOW (see Table 56 and Table 57) and Z_DELTANG_OUT (see Table 58 and Table 59) registers contain the delta angle data for the z-axis. Description X-axis delta angle data; low word Addresses 0x26, 0x27 Default Not applicable Description Y-axis delta angle data; twos complement, 0 = 0x0000, 1 LSB = MAX/215 (see Table 47 for MAX) In addition to the linear acceleration measurements along each axis (x, y, and z), the ADIS16477 also provides delta velocity measurements that represent a calculation of linear velocity change between each sample update. Rev. D | Page 23 of 37 ADIS16477 Data Sheet Z Table 65. X_DELTVEL_OUT Bit Definitions Bits [15:0] VZ The X_DELTVEL_LOW (see Table 62 and Table 63) and X_DELTVEL_OUT (see Table 64 and Table 65) registers contain the delta velocity data for the x-axis. X VX VY 15437-038 PIN K1 PIN A8 Y Y-Axis Delta Velocity (Y_DELTVEL_LOW and Y_DELTVEL_OUT) Figure 42. Delta Velocity Axis and Polarity Assignments The delta velocity outputs represent an integration of the acceleration measurements and use the following formula for all three axes (x-axis displayed): Vx , n D D 1 1 a x , n D d a x , n D d 1 2 fS d 0 Access R Flash Backup No Bits [15:0] Description Y-axis delta velocity data; twos complement, 400 m/sec range, 0 m/sec = 0x0000; 1 LSB = 400 m/sec / 215 = ~0.01221 m/sec The Y_DELTVEL_LOW (see Table 66 and Table 67) and Y_DELTVEL_OUT (see Table 68 and Table 69) registers contain the delta velocity data for the y-axis. Z-Axis Delta Velocity (Z_DELTVEL_LOW and Z_DELTVEL_OUT) Table 70. Z_DELTVEL_LOW Register Definition Addresses 0x38, 0x39 Default Not applicable Access R Flash Backup No Table 71. Z_DELTVEL_LOW Bit Definitions 15437-039 BIT 0 Bits [15:0] Access R Addresses 0x3A, 0x3B Flash Backup No Table 64. X_DELTVEL_OUT Register Definition Flash Backup No Default Not applicable Access R Flash Backup No Table 73. Z_DELTVEL_OUT Bit Definitions Bits [15:0] Description X-axis delta velocity data; additional resolution bits Access R Description Z-axis delta velocity data; additional resolution bits Table 72. Z_DELTVEL_OUT Register Definition Table 63. X_DELTVEL_LOW Bit Definitions Default Not applicable Default Not applicable Table 69. Y_DELTVEL_OUT Bit Definitions Table 62. X_DELTVEL_LOW Register Definition Addresses 0x32, 0x33 Flash Backup No Description Y-axis delta velocity data; additional resolution bits Addresses 0x36, 0x37 X-Axis Delta Velocity (X_DELTVEL_LOW and X_DELTVEL_OUT) Bits [15:0] Access R Table 68. Y_DELTVEL_OUT Register Definition Figure 43. Delta Angle Output Data Structure Default Not applicable Default Not applicable X_ DELTVEL_LOW BIT 0 BIT 15 X-AXIS DELTA VELOCITY DATA Addresses 0x30, 0x31 Addresses 0x34, 0x35 Bits [15:0] When using the internal sample clock, fS is equal to a nominal rate of 2000 SPS. For better precision in this measurement, measure the internal sample rate (fS) using the data ready signal on the DR pin (DEC_RATE = 0x0000, see Table 108), divide each delta angle result (from the delta angle output registers) by the data ready frequency and multiply it by 2000. Each axis of the delta velocity measurements has two output data registers. Figure 43 shows how these two registers combine to support 32-bit, twos complement data format for the delta velocity measurements along the x-axis. This format also applies to the y- and z-axes. X_ DELTVEL_OUT Table 66. Y_DELTVEL_LOW Register Definition Table 67. Y_DELTVEL_LOW Bit Definitions where: x is the x-axis. n is the sample time, prior to the decimation filter. D is the decimation rate (DEC_RATE + 1, see Table 109). fS is the sample rate. d is the incremental variable in the summation formula. aX is the x-axis acceleration. BIT 15 Description X-axis delta velocity data; twos complement, 400 m/sec range, 0 m/sec = 0x0000; 1 LSB = 400 m/sec / 215 = ~0.01221 m/sec Description Z-axis delta velocity data; twos complement, 400 m/sec range, 0 m/sec = 0x0000; 1 LSB = 400 m/sec / 215 = ~0.01221 m/sec The Z_DELTVEL_LOW (see Table 70 and Table 71) and Z_DELTVEL_OUT (see Table 72 and Table 73) registers contain the delta velocity data for the z-axis. Rev. D | Page 24 of 37 Data Sheet ADIS16477 Table 74 and Table 75 offer various numerical examples that demonstrate the format of the delta velocity data in both 16-bit and 32-bit formats. Table 74. 16-Bit Delta Velocity Data Format Examples Velocity (m/sec) +400 x (215 - 1)/215 +400/214 +400/215 0 -400/215 -400/214 -400 Decimal +32,767 +2 +1 0 -1 -2 -32,768 Hex 0x7FFF 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8000 Binary 0111 1111 1111 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 Table 75. 32-Bit Delta Velocity Data Format Examples Velocity (m/sec) +400 x (231 - 1)/231 +400/230 +400/231 0 -400/231 -400/230 -400 Decimal +2,147,483,647 +2 +1 0 -1 -2 +2,147,483,648 Hex 0x7FFFFFFF 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x80000000 CALIBRATION The signal chain of each inertial sensor (accelerometers and gyroscopes) includes the application of unique correction formulas, which are derived from extensive characterization of bias, sensitivity, alignment, response to linear acceleration (gyroscopes), and point of percussion (accelerometer location) over a temperature range of -40C to +85C, for each ADIS16477. These correction formulas are not accessible, but users do have the opportunity to adjust the bias for each sensor individually through user accessible registers. These correction factors follow immediately after the factory derived correction formulas in the signal chain, which processes at a rate of 2000 Hz when using the internal sample clock. Calibration, Gyroscope Bias (XG_BIAS_LOW and XG_BIAS_HIGH) Table 76. XG_BIAS_LOW Register Definition Addresses 0x40, 0x41 Default 0x0000 Access R/W Access R/W XG_BIAS_LOW Calibration, Gyroscope Bias (YG_BIAS_LOW and YG_BIAS_HIGH) Table 80. YG_BIAS_LOW Register Definition Addresses 0x44, 0x45 Default 0x0000 Access R/W Flash Backup Yes Table 81. YG_BIAS_LOW Bit Definitions Bits [15:0] Description Y-axis gyroscope offset correction; lower word Table 82. YG_BIAS_HIGH Register Definition Addresses 0x46, 0x47 Default 0x0000 Access R/W Flash Backup Yes Table 83. YG_BIAS_HIGH Bit Definitions Bits [15:0] Description Y-axis gyroscope offset correction factor, upper word The YG_BIAS_LOW (see Table 80 and Table 81) and YG_BIAS_ HIGH (see Table 82 and Table 83) registers combine to allow users to adjust the bias of the y-axis gyroscopes. The data format examples in Table 12 also apply to the YG_BIAS_HIGH register, and the data format examples in Table 13 apply to the 32-bit combination of the YG_BIAS_LOW and YG_BIAS_HIGH registers. These registers influence the y-axis gyroscope measurements in the same manner that the XG_BIAS_LOW and XG_BIAS_HIGH registers influence the x-axis gyroscope measurements (see Figure 44). Default 0x0000 Access R/W Flash Backup Yes Table 85. ZG_BIAS_LOW Bit Definitions Bits [15:0] Flash Backup Yes Description Z-axis gyroscope offset correction; lower word Table 86. ZG_BIAS_HIGH Register Definition Addresses 0x4A, 0x4B Table 79. XG_BIAS_HIGH Bit Definitions Bits [15:0] X_GYRO_LOW Figure 44. User Calibration Signal Path, Gyroscopes Addresses 0x48, 0x49 Table 78. XG_BIAS_HIGH Register Definition Default 0x0000 XG_BIAS_HIGH X_GYRO_OUT Table 84. ZG_BIAS_LOW Register Definition Description X-axis gyroscope offset correction; lower word Addresses 0x42, 0x43 FACTORY CALIBRATION AND FILTERING X-AXIS GYRO Calibration, Gyroscope Bias (ZG_BIAS_LOW and ZG_BIAS_HIGH) Flash Backup Yes Table 77. XG_BIAS_LOW Bit Definitions Bits [15:0] The XG_BIAS_LOW (see Table 76 and Table 77) and XG_BIAS_ HIGH (see Table 78 and Table 79) registers combine to allow users to adjust the bias of the x-axis gyroscopes. The data format examples in Table 12 also apply to the XG_BIAS_HIGH register, and the data format examples in Table 13 apply to the 32-bit combination of the XG_BIAS_LOW and XG_BIAS_HIGH registers. See Figure 44 for an illustration of how these two registers combine and influence the x-axis gyroscope measurements. 15437-040 Delta Velocity Resolution Description X-axis gyroscope offset correction factor, upper word Rev. D | Page 25 of 37 Default 0x0000 Access R/W Flash Backup Yes ADIS16477 Data Sheet Table 87. ZG_BIAS_HIGH Bit Definitions Table 93. YA_BIAS_LOW Bit Definitions Bits [15:0] Bits [15:0] Description Z-axis gyroscope offset correction factor, upper word The ZG_BIAS_LOW (see Table 84 and Table 85) and ZG_BIAS_ HIGH (see Table 86 and Table 87) registers combine to allow users to adjust the bias of the z-axis gyroscopes. The data format examples in Table 12 also apply to the ZG_BIAS_HIGH register, and the data format examples in Table 13 apply to the 32-bit combination of the ZG_BIAS_LOW and ZG_BIAS_HIGH registers. These registers influence the z-axis gyroscope measurements in the same manner that the XG_BIAS_LOW and XG_BIAS_HIGH registers influence the x-axis gyroscope measurements (see Figure 44). Description Y-axis accelerometer offset correction; lower word Table 94. YA_BIAS_HIGH Register Definition Addresses 0x52, 0x53 Default 0x0000 Access R/W Flash Backup Yes Table 95. YA_BIAS_HIGH Bit Definitions Bits [15:0] Description Y-axis accelerometer offset correction, upper word Table 89. XA_BIAS_LOW Bit Definitions The YA_BIAS_LOW (see Table 92 and Table 93) and YA_BIAS_HIGH (see Table 94 and Table 95) registers combine to allow users to adjust the bias of the y-axis accelerometers. The data format examples in Table 26 also apply to the YA_BIAS_HIGH register, and the data format examples in Table 27 apply to the 32-bit combination of the YA_BIAS_LOW and YA_BIAS_HIGH registers. These registers influence the yaxis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 45). Bits [15:0] Calibration, Accelerometer Bias (ZA_BIAS_LOW and ZA_BIAS_HIGH) Calibration, Accelerometer Bias (XA_BIAS_LOW and XA_BIAS_HIGH) Table 88. XA_BIAS_LOW Register Definition Addresses 0x4C, 0x4D Default 0x0000 Access R/W Flash Backup Yes Description X-axis accelerometer offset correction; lower word Table 90. XA_BIAS_HIGH Register Definition Table 96. ZA_BIAS_LOW Register Definition Addresses 0x4E, 0x4F Addresses 0x54, 0x55 Default 0x0000 Access R/W Flash Backup Yes Default 0x0000 Access R/W Table 91. XA_BIAS_HIGH Bit Definitions Table 97. ZA_BIAS_LOW Bit Definitions Bits [15:0] Bits [15:0] Description X-axis accelerometer offset correction, upper word The XA_BIAS_LOW (see Table 88 and Table 89) and XA_BIAS_ HIGH (see Table 90 and Table 91) registers combine to allow users to adjust the bias of the x-axis accelerometers. The data format examples in Table 26 also apply to the XA_BIAS_HIGH register, and the data format examples in Table 27 apply to the 32-bit combination of the XA_BIAS_LOW and XA_BIAS_HIGH registers. See Figure 45 for an illustration of how these two registers combine and influence the x-axis accelerometer measurements. Flash Backup Yes Description Z-axis accelerometer offset correction; lower word Table 98. ZA_BIAS_HIGH Register Definition Addresses 0x56, 0x57 Default 0x0000 Access R/W Flash Backup Yes Table 99. ZA_BIAS_HIGH Bit Definitions Bits [15:0] Description Z-axis accelerometer offset correction, upper word Calibration, Accelerometer Bias (YA_BIAS_LOW and YA_BIAS_HIGH) The ZA_BIAS_LOW (see Table 96 and Table 97) and ZA_BIAS_ HIGH (see Table 98 and Table 99) registers combine to allow users to adjust the bias of the z-axis accelerometers. The data format examples in Table 26 also apply to the ZA_BIAS_HIGH register, and the data format examples in Table 27 apply to the 32bit combination of the ZA_BIAS_LOW and ZA_BIAS_HIGH registers. These registers influence the z-axis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 45). Table 92. YA_BIAS_LOW Register Definition Filter Control Register (FILT_CTRL) Addresses 0x50, 0x51 Table 100. FILT_CTRL Register Definition XA_BIAS_HIGH X_ACCL_OUT X_ACCL_LOW 15437-041 FACTORY CALIBRATION AND FILTERING X-AXIS ACCL XA_BIAS_LOW Figure 45. User Calibration Signal Path, Accelerometers Default 0x0000 Access R/W Flash Backup Yes Addresses 0x5C, 0x5D Rev. D | Page 26 of 37 Default 0x0000 Access R/W Flash Backup Yes Data Sheet ADIS16477 Table 101. FILT_CTRL Bit Definitions Bits [15:3] [2:0] Description Not used Filter Size Variable B, number of taps in each stage; N = 2B The FILT_CTRL register (see Table 100 and Table 101) provides user controls for the Bartlett window FIR filter (see Figure 22), which contains two cascaded averaging filters. For example, use the following sequence to set Register FILT_CTRL, Bits[2:0] = 100, which sets each stage to have 16 taps: 0xCC04 and 0xCD00. Figure 46 provides the frequency response for several settings in the FILT_CTRL register. Bits [4:2] 1 0 0 -20 MAGNITUDE (dB) -40 Description SYNC function setting 111 = reserved (do not use) 110 = reserved (do not use) 101 = pulse sync mode 100 = reserved (do not use) 011 = output sync mode 010 = scaled sync mode 001 = direct sync mode 000 = internal clock mode (default) SYNC polarity (input or output) 1 = rising edge triggers sampling 0 = falling edge triggers sampling DR polarity 1 = active high when data is valid 0 = active low when data is valid -60 Point of Percussion -80 -100 -140 0.001 N=2 N=4 N = 16 N = 64 0.01 0.1 1 FREQUENCY (f/fS 15437-042 -120 Figure 46. Bartlett Window, FIR Filter Frequency Response (Phase Delay = N Samples) Register MSC_CTRL, Bit 6 (see Table 105) offers an on/off control for the point of percussion alignment function, which maps the accelerometer sensors to the corner of the package that is closest to Pin A1 (see Figure 47). The factory default setting in the MSC_CTRL register activates this function. To turn this function off while retaining the rest of the factory default settings in the MSC_CTRL register, set Register MSC_CTRL, Bit 6 = 0, using the following command sequence on the DIN pin: 0xE081, then 0xE100. Range Identifier (RANG_MDL) Table 102. RANG_MDL Register Definition Default Not applicable Access R Flash Backup No PIN A8 PIN A1 Table 103. RANG_MDL Bit Definitions Bits [15:3] [3:2] [1:0] Description Not used Gyroscope measurement range 00 = 125/sec (ADIS16477-1BMLZ) 01 = 500/sec (ADIS16477-2BMLZ) 10 = reserved 11 = 2000/sec (ADIS16477-3BMLZ) Reserved, binary value = 11 Figure 47. Point of Percussion Reference Point Linear Acceleration Effect on Gyroscope Bias Register MSC_CTRL, Bit 7 (see Table 105) provides an on/off control for the linear g compensation in the signal calibration routines of the gyroscope. The factory default contents in the MSC_CTRL register enable this compensation. To turn the compensation off, set Register MSC_CTRL, Bit 7 = 0, using the following sequence on the DIN pin: 0xE04, then 0xEF00. Miscellaneous Control Register (MSC_CTRL) Internal Clock Mode Table 104. MSC_CTRL Register Definition Addresses 0x60, 0x61 Default 0x00C1 Access R/W Flash Backup Yes Table 105. MSC_CTRL Bit Definitions Bits [15:8] 7 6 5 POINT OF PERCUSSION 15437-043 Addresses 0x5E, 0x5F Description Not used Linear g compensation for gyroscopes (1 = enabled) Point of percussion alignment (1 = enabled) Not used, always set to zero Register MSC_CTRL, Bits[4:2] (see Table 105), provide five different configuration options for controlling the clock (fSM; see Figure 19 and Figure 20), which controls data acquisition and processing for the inertial sensors. The default setting for Register MSC_CTRL, Bits[4:2] is 000 (binary), which places the ADIS16477 in the internal clock mode. In this mode, an internal clock controls inertial sensor data acquisition and processing at a nominal rate of 2000 Hz. In this mode, each accelerometer data update comes from an average of two data samples (sample rate = 4000 Hz). Rev. D | Page 27 of 37 ADIS16477 Data Sheet Output Sync Mode When Register MSC_CTRL, Bits[4:2] = 011, the ADIS16477 operates in output sync mode, which is the same as internal clock mode with one exception, the SYNC pin pulses when the internal processor collects data from the inertial sensors. Figure 48 provides an example of this signal. GYROSCOPE AND ACCELEROMETER DATA ACQUISITION ACCELEROMETER DATA ACQUISITION external clock scale factor, KECSF, (from the UP_SCALE register, see Table 106 and Table 107) and the frequency of the clock signal on the SYNC pin. For example, when using a 1 Hz input signal, set UP_SCALE = 0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of 2000 SPS for the inertial sensors and their signal processing. Use the following sequence on the DIN pin to configure UP_SCALE for this scenario: 0xE2D0, then 0xE307. Table 106. UP_SCALE Register Definition SYNC 500s Addresses 0x62, 0x63 15437-044 250s Default 0x07D0 Access R/W Flash Backup Yes Table 107. UP_SCALE Bit Definitions Figure 48. Sync Output Signal, Register MSC_CTRL, Bits[4:2] = 011 Bits [15:0] Direct Sync Mode When Register MSC_CTRL, Bits[4:2] = 001, the ADIS16477 operates in direct sync mode. The signal on the SYNC pin directly controls the sample clock. In this mode, the internal processor collects gyroscope data samples on the rising edge of the clock signal (SYNC pin) and collects accelerometer data samples on both rising and falling edges of the clock signal. The internal processor averages both accelerometer samples (from rising and falling edges of the clock signal) together to produce a single data sample. Therefore, when operating the ADIS16477 in this mode, the clock signal (SYNC pin) must have a duty cycle of 50% and a frequency that is within the range of 1900 Hz to 2100 Hz. The ADIS16477 is capable of operating when the clock frequency (SYNC pin) is less than 1900 Hz, but with risk of performance degradation, especially when tracking dynamic inertial conditions (including vibration). Pulse Sync Mode When operating in pulse sync mode (Register MSC_CTRL, Bits[4:2] = 101), the internal processor only collects accelerometer samples on the leading edge of the clock signal, which enables the use of a narrow pulse width (see Table 2) in the clock signal on the SYNC pin. Using pulse sync mode also lowers the bandwidth on the inertial sensors to 370 Hz. When operating in pulse sync mode, the ADIS16477 provides the best performance when the frequency of the clock signal (SYNC pin) is within the range of 1000 Hz to 2100 Hz. The ADIS16477 is capable of operating when the clock frequency (SYNC pin) is less than 1000 Hz, but with risk of performance degradation, especially when tracking dynamic inertial conditions (including vibration). Scaled Sync Mode When Register MSC_CTRL, Bits[4:2] = 010, the ADIS16477 operates in scaled sync mode that supports a frequency range of 1 Hz to 128 Hz for the clock signal on the SYNC pin. This mode of operation is particularly useful when synchronizing the data processing with a PPS signal from a global positioning system (GPS) receiver or with a synchronization signal from a video processing system. When operating in scaled sync mode, the frequency of the sample clock is equal to the product of the Description KECSF; binary format Decimation Filter (DEC_RATE) Table 108. DEC_RATE Register Definition Addresses 0x64, 0x65 Default 0x0000 Access R/W Flash Backup Yes Table 109. DEC_RATE Bit Definitions Bits [15:11] [10:0] Description Don't care Decimation rate, binary format, maximum = 1999 The DEC_RATE register (see Table 108 and Table 109) provides user control for the averaging decimating filter, which averages and decimates the gyroscope and accelerometer data; it also extends the time that the delta angle and the delta velocity track between each update. When the ADIS16477 operates in internal clock mode (see Register MSC_CTRL, Bits [4:2], in Table 105), the nominal output data rate is equal to 2000/(DEC_RATE + 1). For example, set DEC_RATE = 0x0013 to reduce the output sample rate to 100 SPS (2000 / 20), using the following DIN pin sequence: 0xE413, then 0xE500. Data Update Rate in External Sync Modes When using the input sync option, in scaled sync mode (Register MSC_CTRL, Bits[4:2] = 010, see Table 105), the output data rate is equal to (fSYNC x KECSF)/(DEC_RATE + 1) where: fSYNC is the frequency of the clock signal on the SYNC pin. KESCF is the value from the UP_SCALE register (see Table 107). When using direct sync mode and pulse sync mode, KESCF = 1. Continuous Bias Estimation (NULL_CNFG) Table 110. NULL_CNFG Register Definition Addresses 0x66, 0x67 Rev. D | Page 28 of 37 Default 0x070A Access R/W Flash Backup Yes Data Sheet ADIS16477 Table 111. NULL_CNFG Bit Definitions Flash Memory Test Bits [15:14] 13 12 11 10 9 8 [7:4] [3:0] Use the following DIN sequence to set Register GLOB_CMD, Bit 4 = 1, which tests the flash memory: 0xE810, then 0xE900. The command performs a CRC computation on the flash memory (excluding user register locations) and compares it to the original CRC value, which comes from the factory configuration process. If the current CRC value does not match the original CRC value, Register DIAG_STAT, Bit 6 (see Table 10), rises to 1, indicating a failing result. Description Not used Z-axis accelerometer bias correction enable (1 = enabled) Y-axis accelerometer bias correction enable (1 = enabled) X-axis accelerometer bias correction enable (1 = enabled) Z-axis gyroscope bias correction enable (1 = enabled) Y-axis gyroscope bias correction enable (1 = enabled) X-axis gyroscope bias correction enable (1 = enabled) Not used Time base control (TBC), range: 0 to 12 (default = 10); tB = 2TBC/2000, time base; tA = 64 x tB, average time The NULL_CNFG register (see Table 110 and Table 111) provides the configuration controls for the continuous bias estimator (CBE), which associates with the bias correction update command in Register GLOB_CMD, Bit 0 (see Table 113). Register NULL_ CNFG, Bits[3:0], establishes the total average time (tA) for the bias estimates and Register NULL_CNFG, Bits[13:8], provide the on/off controls for each sensor. The factory default configuration for the NULL_CNFG register enables the bias null command for the gyroscopes, disables the bias null command for the accelerometers, and sets the average time to ~32 sec. Global Commands (GLOB_CMD) Table 112. GLOB_CMD Register Definition Addresses 0x68, 0x69 Default Not applicable Access W Flash Backup No Table 113. GLOB_CMD Bit Definitions Bits [15:8] 7 [6:5] 4 3 2 1 0 Description Not used Software reset Not used Flash memory test Flash memory update Sensor self test Factory calibration restore Bias correction update Flash Memory Update Use the following DIN sequence to set Register GLOB_CMD, Bit 3 = 1, which triggers a backup of all user configurable registers in the flash memory: 0xE808, then 0xE900. Register DIAG_STAT, Bit 2 (see Table 10) identifies success (0) or failure (1) in completing this process. Sensor Self Test Use the following DIN sequence to set Register GLOB_CMD, Bit 2 = 1, which triggers the self test routine for the inertial sensors: 0xE804 and 0xE900. The self test routine uses the following steps to validate the integrity of each inertial sensor: 1. Measure the output on each sensor. 2. Activate an internal stimulus on the mechanical elements of each sensor to move them in a predictable manner and create an observable response in the sensors. 3. Measure the output response on each sensor. 4. Deactivate the internal stimulus on each sensor. 5. Calculate the difference between the sensor measurements from Step 1 (stimulus is off) and from Step 3 (stimulus is on). 6. Compare the difference with internal pass and fail criteria. 7. Report the pass and fail result to Register DIAG_STAT, Bit 5 (see Table 10). Motion, during the execution of this test, can indicate a false failure. Factory Calibration Restore The GLOB_CMD register (see Table 112 and Table 113) provides trigger bits for several operations. Write a 1 to the appropriate bit in GLOB_CMD to start a particular function. During the execution of these commands, data production stops, pulsing stops on the DR pin, and the SPI interface does not respond to requests. Table 1 provides the execution time for each GLOB_CMD command. Use the following DIN sequence to set Register GLOB_CMD, Bit 1 = 1 to restore the factory default settings for the MSC_ CTRL, DEC_RATE, and FILT_CTRL registers and to clear all user configurable bias correction settings: 0xE802, then 0xE900. Executing this command results in writing 0x0000 to the following registers: XG_BIAS_LOW, XG_BIAS_HIGH, YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_ HIGH, XA_BIAS_LOW, XA_BIAS_HIGH, YA_BIAS_LOW, YA_BIAS_HIGH, ZA_BIAS_LOW, and ZA_BIAS_HIGH. Software Reset Bias Correction Update Use the following DIN sequence to set Register GLOB_CMD, Bit 7 = 1, which triggers a reset: 0xE880, then 0xE900. This reset clears all data, and then restarts data sampling and processing. This function provides a firmware alternative to toggling the RST pin (see Table 5, Pin F3). Use the following DIN pin sequence to set Register GLOB_CMD, Bit 0 = 1 to trigger a bias correction, using the correction factors from the CBE (see Table 111): 0xE801, then 0xE900. Rev. D | Page 29 of 37 ADIS16477 Data Sheet Firmware Revision (FIRM_REV) Table 114. FIRM_REV Register Definition Addresses 0x6C, 0x6D Default Not applicable Access R Flash Backup No Table 115. FIRM_REV Bit Definitions Bits [15:0] Description Firmware revision, binary coded decimal (BCD) format The FIRM_REV register (see Table 114 and Table 115) provides the firmware revision for the internal firmware. This register uses a BCD format, where each nibble represents a digit. For example, if FIRM_REV = 0x0104, the firmware revision is 1.04. The PROD_ID register (see Table 120 and Table 121) contains the numerical portion of the device number (16,477). See Figure 32 for an example of how to use a looping read of this register to validate the integrity of the communication. Serial Number (SERIAL_NUM) Table 122. SERIAL_NUM Register Definition Addresses 0x74, 0x75 Default Not applicable Access R Flash Backup No Table 123. SERIAL_NUM Bit Definitions Bits [15:0] Description Lot specific serial number Scratch Registers (USER_SCR_1 to USER_SCR_3) Firmware Revision Day and Month (FIRM_DM) Table 124. USER_SCR_1 Register Definition Table 116. FIRM_DM Register Definition Addresses 0x6E, 0x6F Default Not applicable Access R Flash Backup No Addresses 0x76, 0x77 Default Not applicable Access R/W Flash Backup Yes Table 125. USER_SCR_1 Bit Definitions Table 117. FIRM_DM Bit Definitions Bits [15:8] [7:0] Bits [15:0] Description Factory configuration month, BCD format Factory configuration day, BCD format Table 126. USER_SCR_2 Register Definition The FIRM_DM register (see Table 116 and Table 117) contains the month and day of the factory configuration date. Register FIRM_DM, Bits[15:8], contain digits that represent the month of the factory configuration. For example, November is the 11th month in a year and is represented by Register FIRM_DM, Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:0], contain the day of factory configuration. For example, the 27th day of the month is represented by Register FIRM_DM, Bits[7:0] = 0x27. Firmware Revision Year (FIRM_Y) Default Not applicable Access R Flash Backup No Table 119. FIRM_Y Bit Definitions Bits [15:0] Addresses 0x78, 0x79 Description Factory configuration year, BCD format The FIRM_Y register (see Table 118 and Table 119) contains the year of the factory configuration date. For example, the year, 2017, is represented by FIRM_Y = 0x2017. Bits [15:0] Access R Description User defined Addresses 0x7A, 0x7B Bits [15:0] Default Not applicable Access R/W Flash Backup Yes Description User defined The USER_SCR_1 (see Table 124 and Table 125), USER_SCR_2 (see Table 126 and Table 127), and USER_SCR_3 (see Table 128 and Table 129) registers provide three locations for the user to store information. For nonvolatile storage, use the manual flash memory update command (Register GLOB_CMD, Bit 3, see Table 113), after writing information to these registers. Flash Backup No Table 121. PROD_ID Bit Definitions Bits [15:0] Flash Backup Yes Table 128. USER_SCR_3 Register Definition Table 120. PROD_ID Register Definition Default 0x405D Access R/W Table 127. USER_SCR_2 Bit Definitions Product Identification (PROD_ID) Addresses 0x72, 0x73 Default Not applicable Table 129. USER_SCR_3 Bit Definitions Table 118. FIRM_Y Register Definition Addresses 0x70, 0x71 Description User defined Description Product identification = 0x405D Rev. D | Page 30 of 37 Data Sheet ADIS16477 Flash Memory Endurance Counter (FLSHCNT_LOW and FLSHCNT_HIGH) Table 130. FLSHCNT_LOW Register Definition Default Not applicable Access R Flash Backup No Table 131. FLSHCNT_LOW Bit Definitions 600 Description Flash memory write counter, low word Table 132. FLSHCNT_HIGH Register Definition Addresses 0x7E, 0x7F Default Not applicable Access R Flash Backup No RETENTION (Years) Bits [15:0] Table 133. FLSHCNT_HIGH Bit Definitions Bits [15:0] 450 300 150 Description Flash memory write counter, high word 0 The FLSHCNT_LOW (see Table 130 and Table 131) and FLSHCNT_HIGH (see Table 132 and Table 133) registers combine to provide a 32-bit, binary counter that tracks the number of flash memory write cycles. In addition to the 30 40 55 70 85 100 125 JUNCTION TEMPERATURE (C) Figure 49. Flash Memory Retention Rev. D | Page 31 of 37 135 150 15437-045 Addresses 0x7C, 0x7D number of write cycles, the flash memory has a finite service lifetime, which depends on the junction temperature. Figure 49 provides guidance for estimating the retention life for the flash memory at specific junction temperatures. The junction temperature is approximately 7C above the case temperature. ADIS16477 Data Sheet APPLICATIONS INFORMATION ASSEMBLY AND HANDLING TIPS PCB Layout Suggestions Package Attributes Figure 51 shows an example of the pad design and layout for the ADIS16477 on a PCB. This example uses a solder mask opening, with a diameter of 0.73 mm, around a metal pad that has a diameter of 0.56 mm. When using a material for the system PCB, which has similar thermal expansion properties as the substrate material of the ADIS16477, the system PCB can also use the solder mask to define the pads that support attachment to the balls of the ADIS16477. The coefficient of thermal expansion (CTE) in the substrate of the ADIS16477 is approximately 14 ppm/C. The ADIS16477 is a multichip module package that has a 44-ball BGA interface. This package has three basic attributes that influence its handling and assembly to the PCB of the system: the lid, the substrate, and the BGA pattern. The material of the lid is a liquid crystal polymer (LCP), and its nominal thickness is 0.5 mm. The substrate is a laminate composition that has a nominal thickness of 1.57 mm. The solder ball material is SAC305, and each ball has a nominal diameter of 0.75 mm (0.15 mm). The BGA pattern follows an 8 x 10 array, with 36 unpopulated positions, which simplifies the escape pattern for the power, ground, and signal traces on the system PCB. 0.73 (MASK OPENING) 0.56 (COPPER PAD) Assembly Tips When developing a process to attach the ADIS16477 to a PCB, consider the following guidelines and insights: The ADIS16477 is capable of supporting solder reflow attachment processes, which are in accordance with J-STD-020E. Limit device exposure to one pass through the solder reflow process (no rework). The hole in the top of the lid (see Figure 50) provides venting and pressure relief during the assembly process of the ADIS16477. Keep this hole clear of obstruction while attaching the ADIS16477 to a PCB. 1.27 ALL DIMENSIONS IN MILLIMETERS 15437-047 1.27 Figure 51. Recommend PCB Pattern, Solder Mask Defined Pads Underfill 15437-046 OPENING IN PACKAGE LID Figure 50. Pressure Relief Hole Use no clean flux to avoid exposing the device to cleaning solvents, which can penetrate the inside of the ADIS16477 through the hole in the lid and be difficult to remove. When the assembly process requires the use of liquids that can reach the hole in the lid, use a temporary seal to prevent entrapment of those liquids inside the cavity. Manage moisture exposure prior to the solder reflow processing, in accordance with J-STD-033, Moisture Sensitivity Level 5. Avoid exposing the ADIS16477 to mechanical shock survivability that exceeds the maximum rating of 2000 g (see Table 3). In standard PCB processing, high speed handling equipment and panel separation processes often present the most risk of introducing harmful levels of mechanical shock survivability. Underfill can be a useful technique in managing certain threats to the integrity of the solder joints of the ADIS16477, including peeling stress and extended exposure to vibration. When selecting underfill material and developing an application and curing process, ensure that the material fills the gap between each surface (the ADIS16477 substrate and system PCB) and adheres to both surfaces. The ADIS16477 does not require the use of underfill materials in applications that do not anticipate exposure to these types of mechanical stresses and when the CTE of the system PCB is close to the same value as the CTE of the substrate of the ADIS16477 (~14 ppm/C). Process Validation and Control These guidelines provide a starting point for developing a process for attaching the ADIS16477 to a system PCB. Because each system and situation may present unique requirements for this attachment process, ensure that the process supports optimal solder joint integrity, verify that the final system meets all environmental test requirements, and establish observation and control strategies for all key process attributes (for example, peak temperatures, dwell times, and ramp rates). Rev. D | Page 32 of 37 Data Sheet ADIS16477 POWER SUPPLY CONSIDERATIONS The ADIS16477 contains 6 F of decoupling capacitance across the VDD and GND pins. When the VDD voltage rises from 0 V to 3.3 V, the charging current for this capacitor bank imposes the following current profile (in amperes): I DD t C dVDD dVDD t 6 10 6 dt dt where: IDD(t) is the current demand on the VDD pin during the initial power supply ramp, with respect to time. C is the internal capacitance across the VDD and GND pins (6 F). VDD(t) is the voltage on the VDD pin, with respect to time. For example, if VDD follows a linear ramp from 0 V to 3.3 V, in 66 s, the charging current is 300 mA for that timeframe. The ADIS16477 also contains embedded processing functions that present transient current demands during initialization or reset recovery operations. During these processes, the peak current demand reaches 250 mA and occurs at a time that is approximately 40 ms after VDD reaches 3.0 V (or ~40 ms after initiating a reset sequence). SERIAL PORT OPERATION Accelerometer Data Width (Digital Resolution) section for more information. Serial Port SCLK Underrun/Overrun Conditions The serial port operates in 16-bit segments, and it is critical that the number of SCLK cycles be equal to an integer multiple of 16 when the CS pin is low. Failure to meet this condition causes the serial port controller inside of the ADIS16477 to be unable to correctly receive and respond to new requests. If too many SCLK cycles are received before the CS pin is deasserted, the user can recover serial port operation by asserting CS, providing 17 rising edges on the SCLK line, deasserting CS, and then attempting to correctly read the PROD_ID (or other read-only) register on the ADIS16477. The user should repeat these steps up to a maximum of 15 times until the correct data is read. If CS is deasserted before enough SCLK cycles are received, the user must either power cycle or issue a hard reset (using the RST pin) to regain SPI port access. DIGITAL RESOLUTION OF GYROSCOPES AND ACCELEROMETERS Gyroscope Data Width (Digital Resolution) Maximum Throughput When operating with the maximum output data (DEC_RATE = 0x0000, as described in Table 109), the maximum SCLK rate (defined in Table 2) and minimum stall time, the SPI port can support up to 12, 16-bit register reads in between each pulse of the data ready signal. Attempting to read more than 12 registers can result in a datapath overrun error in the DIAG_STAT register (see Table 10). The serial port stall time (tSTALL) to meet these requirements must be no more than 10% greater than the minimum specification for tSTALL in Table 2. The number of allowable registers reads between each pulse on the data ready line increases proportionally with the decimation rate (set by the DEC_RATE register, see Table 109). For example, when the decimation rate equals 3 (DEC_RATE = 0x0002), the SPI is able to support up to 36 register reads, assuming maximum SCLK rate and minimum stall times in the protocol. Decreasing the SCLK rate and increasing the stall time lowers the total number of register reads supported by the ADIS16477 before a datapath overrun error occurs. This limitation of reading 12, 16-bit registers does not impact the ability of the user to access the full precision of the gyroscopes and accelerometers if the factory default settings of DEC_RATE = 0x0000 and FILT_CTRL = 0x0000 are used. In this case, the data width for the gyroscope and accelerometer data is 16 bits, and application processors can acquire all relevant information through the X_GYRO_OUT, Y_GYRO_ OUT, Z_GYRO_OUT, X_ACCEL_OUT, Y_ACCEL_OUT, and Z_ACCEL_OUT registers. Thirty-two bit reads of the sensor data do not provide additional precision in this case. See the Gyroscope Data Width (Digital Resolution) section and the The decimation filter (DEC_RATE register, see Table 109) and Bartlett window filter (FILT_CTRL register, see Table 101) have direct influence over the total number of bits in the output data registers, which contain relevant information. When using the factory default settings (DEC_RATE = 0x0000, FILT_CTRL = 0x0000) for these filters, the gyroscope data width is 16 bits, which means that application processors can acquire all relevant information through the X_GYRO_OUT, Y_GYRO_OUT, and Z_GYRO_OUT registers. The X_GYRO_LOW, Y_GYRO_LOW, and Z_GYRO_LOW registers capture the bit growth that comes from each accumulation operation in the decimation and Bartlett window filters. When using these filters (DEC_RATE 0x0000 and/or FILT_CTRL 0x0000), the data width increases by one bit every time the number of summations (in a filter stage) increases by a factor of two. For example, when DEC_RATE = 0x0007, the decimation filter adds eight (7 + 1 = 8, see Table 109) successive samples together, which causes the data width to increase by 3 bits (log28 = 3). When FILT_CTRL = 0x0002, both stages in the Bartlett window filter use four (22 = 4, see Table 101) summation operations, which increases the data width by 2 bits (log24 = 2). When using both DEC_RATE = 0x0007 and FILT_CTRL = 0x0002, the total bit growth is 7 bits, which increases the overall data width to 23 bits. Accelerometer Data Width (Digital Resolution) The decimation filter (DEC_RATE register, see Table 109) and Bartlett window filter (FILT_CTRL register, see Table 101) have direct influence over the total number of bits in the output data registers, which contain relevant information. When using the factory default settings (DEC_RATE = 0x0000, FILT_CTRL Rev. D | Page 33 of 37 ADIS16477 Data Sheet = 0x0000) for these filters, the accelerometer data width is 20 bits. The X_ACCL_OUT, Y_ACCL_OUT, and Z_ACCL_OUT registers contain the most significant 16 bits of this data, while the remaining (least significant) bits are in the upper 4 bits of the X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW registers. Since the total noise (0.6 mg rms, see Table 1) in the accelerometer data (DEC_RATE = 0x0000, FILT_CTRL = 0x0000) is greater than the 16-bit quantization noise (0.25 mg / 120.5 = 0.072 mg), application processors can acquire all relevant information through the X_ACCL_OUT, Y_ACCL_OUT, and Z_ACCL_OUT registers. This enables applications to preserve optimal performance, while using the burst read (see Figure 31), which only provides 16-bit data for the accelerometers. EVALUATION TOOLS The X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW registers also capture the bit growth that comes from each accumulation operation in the decimation and Bartlett window filters. When using these filters (DEC_RATE 0x0000 and/or FILT_CTRL 0x0000), the data width increases by one bit every time the number of summations (in a filter stage) increases by a factor of two. For example, when DEC_RATE = 0x0001, the decimation filter adds two (1 + 1 = 2, see Table 109) successive samples together, which causes the data width to increase by 1 bit (log22 = 1). When FILT_CTRL = 0x0001, both stages in the Bartlett window filter add two (21 = 2, see Table 101) successive samples together, which increases the data width by 1 bit (log22 = 1) as well. When using both DEC_RATE = 0x0001 and FILT_CTRL = 0x0001, the total bit growth is 3 bits, which increases the overall data width to 23 bits. The electrical interface (J1) on each breakout board comes from a dual row, 2 mm pitch, 16-pin interface, which supports standard ribbon cabling (1 mm pitch). Table 135 provides the J1 pin assignments, which support direct connection with an embedded processor board, using standard ribbon cables. Although each case may present its own set of sensitivities (such as electromagnetic interference (EMI)), these boards can typically support reliable communication over ribbon cables up to 20 cm in length. Breakout Boards The ADIS16477 has three difference breakout boards, which provide a simple way to connect an ADIS16477 model and an existing embedded processor platform. Table 134 provides a list of the model numbers for each breakout board, along with the ADIS16477 model that is on each breakout board. Table 134. Breakout Board Models Breakout Board Model ADIS16477-1/PCBZ ADIS16477-2/PCBZ ADIS16477-3/PCBZ ADIS16477 Model ADIS16477-1BMLZ ADIS16477-2BMLZ ADIS16477-3BMLZ Table 135. J1 Pin Assignments, Breakout Board J1 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal RST SCLK CS DOUT NC DIN GND GND GND VDD VDD VDD DR SYNC NC NC Function Reset SPI SPI SPI No connect SPI Ground Ground Ground Power, 3.3 V Power, 3.3 V Power, 3.3 V Data ready Input clock No connect No connect Figure 52 provides a top level view of the breakout board, including dimensional locations for all the key mechanical features, such as the mounting holes and the 16-pin header. Figure 53 provides an electrical schematic for this breakout board. For additional information, refer to the ADIS1647x/PCB Wiki Guide. Rev. D | Page 34 of 37 Data Sheet ADIS16477 30.07mm J1 11/14/16 * 16.99mm 5.125mm TFD1 ADIS1647X/PCB BREAKOUT BOARD 08-045113rA ML/BEL 33.25mm TFD2 16.26mm 3.625mm 6.03mm 15437-048 5.125mm Figure 52. Top Level View of the Breakout Board VDD DUT1 K6 VDD J5 VDD J4 VDD C7 VDD D6 VDD H1 VDD GND D3 F3 RST GND F6 G6 DIN CS G3 GND NC RST VDD GND SCLK E3 H6 DOUT CS J6 DR J3 SYNC VDD SCLK DOUT DR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RST SCLK DOUT CS SYNC DIN K8 K3 K1 J7 J2 H8 G7 G2 F8 F1 E7 E6 E2 C6 C2 GND GND VDD SYNC DR NC GND J1 HIROSE A3-16-PA-2SV(71) 15437-049 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VDD H3 DIN ADIS16477AMLZ A1 A2 A3 A4 A5 A6 A7 A8 B8 B3 B4 B5 B6 C3 GND Figure 53. Breakout Board Schematic PC-Based Evaluation, EVAL-ADIS2 In addition to supporting quick prototype connections between the ADIS16477 and an embedded processing system, J1 on the breakout board also connects directly to J1 on the EVAL-ADIS2 evaluation system. When used in conjunction with the IMU Evaluation Software for the EVAL-ADISX Platforms, the EVAL-ADIS2 provides a simple, functional test platform that allows users to configure and collect data from the ADIS16477 models. Rev. D | Page 35 of 37 ADIS16477 Data Sheet TRAY DRAWING The ADIS16477 parts are shipped in the tray shown in Figure 54. 322.60 REF 315.00 112.25 112.00 111.75 92.10 135.90 16.00 BSC 12.70 TOP VIEW 22.00 BSC 11.95 BSC 14.50 BSC DETAIL C 272.05 271.80 271.55 DETAIL A 0.76 R 4.75 DETAIL C DETAIL B 2.50 3.80 21.40 SIDE VIEW 2.54 1.30 17.90 34.30 25.40 255.30 30 1 3.50 B A DETAIL B A 15.43 15.35 15.27 11.10 NOTES: 1. MATERIAL IS MPPO. 2. TOLERANCES ARE x.x = 0.25 x.xx = 0.13 UNLESS OTHERWISE SPECITIED. 3. ESD - SURFACE RESISTIVITY 105 TO 1011 /SQ. 11.43 11.35 11.27 7.90 SECTION A-A C 3.00 x 0.45 DETAIL A B Figure 54. Drawing of Shipping Tray Rev. D | Page 36 of 37 SECTION B-B 15437-100 2.00 Data Sheet ADIS16477 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 11.25 11.00 10.75 1.270 BSC 1.055 BSC A1 BALL CORNER INDICATOR 1.785 BSC 1.270 BSC 15.25 15.00 14.75 0.900 O 0.750 0.600 TOP VIEW BOTTOM VIEW END VIEW 11.350 11.000 *10.475 0.90 MAX *Including Lable Thickness PKG-005267 06-22-2017-B SEATING PLANE Figure 55. 44-Ball Ball Grid Array Module [BGA] (ML-44-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADIS16477-1BMLZ ADIS16477-2BMLZ ADIS16477-3BMLZ ADIS16477-1/PCBZ ADIS16477-2/PCBZ ADIS16477-3/PCBZ 1 Temperature Range -40C to +105C -40C to +105C -40C to +105C Package Description 44-Ball Ball Grid Array Module [BGA] 44-Ball Ball Grid Array Module [BGA] 44-Ball Ball Grid Array Module [BGA] ADIS16477-1 Breakout Board ADIS16477-2 Breakout Board ADIS16477-3 Breakout Board Package Option ML-44-1 ML-44-1 ML-44-1 Z = RoHS Compliant Part. (c)2017-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15437-4/20(D) www.analog.com/ADIS16477 Rev. D | Page 37 of 37