REVISIONS LTR DESCRIPTION A DATE (YR-MO-DA) APPROVED 06-10-26 Raymond Monnin Boilerplate update, part of 5 year review. ksr THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV SHEET REV STATUS REV A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Kenneth S. Rice STANDARD MICROCIRCUIT DRAWING Charles Reusing APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY Michael A. Frye DRAWING APPROVAL DATE MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2K X 8 STATIC RAM (SRAM), MONOLITHIC SILICON 89-10-16 AMSC N/A REVISION LEVEL A SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 . 1 OF 5962-89690 13 5962-E009-07 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89690 01 J A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 02 1/ 1/ Circuit function Acess time 2K X 8 CMOS SRAM 2K X 8 CMOS SRAM 25 ns 20 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter J K L X Y Z 3 Descriptive designator GDIP1-T24 or CDIP2-T24 GDFP2-F24 or CDFP3-F24 GDIP3-T24 or CDIP4-T24 CQCC1-N32 See Figure 1 CQCC3-N28 CQCC1-N28 Terminals Package style 24 24 24 32 24 28 28 dual-in-line package flat package dual-in-line package rectangular chip carrier package rectangular chip carrier package rectangular chip carrier package rectangular chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 2/ Supply voltage range (VCC) -----------------------------------Input voltage range 2/ -----------------------------------------Output voltage range in high impedance state ---------Output current----------------------------------------------------Storage temperature range-----------------------------------Power dissipation, (PD) ---------------------------------------Lead temperature (soldering, 10 seconds) ---------------Junction temperature (TJ) ------------------------------------Thermal resistance, junction-to-case (JC):. Cases J, K, L, X, Z, and 3-----------------------------Case Y ------------------------------------------------------ -0.5 V dc to 7 V dc 0.5 V to VCC +0.5 V -0.5 V dc to 7 V dc 20 mA -65C to +150C 864 mW +275C +175C See MIL-STD-1835 20C/W 1.4 Recommended operating conditions. Supply voltage range (VCC) -----------------------------------High level Input voltage range (VIH) ------------------------Low level Input voltage range (VIL) 3/ ---------------------Case operating temperature range (TC) -------------------- 4.5 V dc minimum to 5.5 V dc maximum 2.2 V dc minimum to VCC + 0.5 V dc maximum -0.5 V dc minimum to 0.8 V dc maximum -55C to +125C 1/ Generic numbers are listed on the Standardized Military Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103. 2/ All voltages are with respect to GND. 3/ VIL (minimum) of -3 V dc for short pulse durations of 20 ns or less. Prolonged operation at VIL levels below -1 V dc will result in excessive currents that may damage the device. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MILPRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MILPRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.2 Truth table. The truth table shall be as specified on figure 3. 3.2.3 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and figure 1. 3.2.4 Load circuit and switching waveforms. The load circuit and switching waveforms shall be as specified on figure 4. 3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 3 TABLE I. Electrical performance characteristics. Test Operating supply current Standby power supply current TTL Standby power supply current CMOS Input leakage current, any input Off-state output leakage current Output high voltage Output low voltage Input capacitance 5/ Output capacitance 5/ Read cycle time Symbol ICC1 ICC2 ICC3 IILK IOLK VOH VOL CIN COUT tAVAV Conditions -55C < TC < +125C 4.5 V < VCC < 5.5 V VSS = 0 V unless otherwise specified 1/ 2/ 3/ 4/ tAVAV = tAVAV (minimum), VCC = 5.5 V, CE = VIL, all other inputs at VIL CE VIH, all other inputs VIL or VIH, VCC = 5.5 V, f = 0 MHz CE (VCC - 0.2 V), f = 0 Mhz, VCC = 5.5 V, all other inputs < 0.2 V or > (VCC -0.2 V) VCC = 5.5 V, VIN = 0 V to 5.5 V, VCC = 5.5 V VIN = 0 V to 5.5 V, IOUT = -4.0 mA, VCC = 4.5 V, VIL = 0.8 V, VIH = 2.2 V IOUT = 8 mA, VCC = 4.5 V, VIL = 0.8 V, VIH = 2.2 V VIN = 0 V, f = 1.0 Mhz, TA = +25C, see 4.3.1c VOUT= 0 V, f = 1 Mhz, TA = +25C, see 4.3.1c Group A Device subgroups type 1,2,3 01 02 1,2,3 01 02 1,2,3 All 1,2,3 All 1,2,3 All 1,2,3 All 1,2,3 All 4 All 4 All 9, 10 11 01 02 Limits Min Max 135 150 45 50 20 -10 10 -10 10 2.4 0.4 8 8 25 20 Unit mA mA mA A A V V pF pF ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 4 TABLE I. Electrical performance characteristics - Continued. 0 0 ns ns Address to WE setup time tAVWL 9, 10, 11 01 02 Address to CE setup time tAVEL See footnotes at end of table. 9, 10, 11 01, 02 Conditions -55C < TC < +125C 4.5 V < VCC < 5.5 V VSS = 0 V unless otherwise specified 1/ 2/ 3/ 4/ STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Device type 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 01 02 Unit ns ns ns ns ns ns ns ns ns ns DSCC FORM 2234 APR 97 Group A subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Limits Min Max 25 20 0 0 0 0 16 15 0 0 25 20 15 15 0 0 20 15 20 15 Symbol Address access time tAVQV Output hold after address tAVQX change Output enable to output tOLQX active 5/ 6/ Output enable access tOLQV time Chip enable to output tELQX active 5/ 6/ Chip enable access time tELQV Chip enable to output tEHQZ in high Z 5/ 6/ Write recovery time tWHAV Chip enable to end of tELWH write Address valid to end of tAVWH write Test 0 SIZE 5962-89690 A REVISION LEVEL A SHEET 5 TABLE I. Electrical performance characteristics - Continued. Symbol Output enable to output tOHQZ in high Z 5/ 6/ Write enable pulse width tWLWH Data setup to end of write tDVWH Data hold after end of writetWHDX Chip enable pulse width tELEH during write Write enable pulse setup tWLEH time Write enable to output tWLQZ in high Z 5/ 6/ Test Group A subgroups 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Conditions -55C < TC < +125C 4.5 V < VCC < 5.5 V VSS = 0 V unless otherwise specified 1/ 2/ 3/ 4/ Device type 01 02 01 02 01 02 01 02 01 02 01 02 01 02 Limits Min Max 16 15 20 15 15 12 0 0 20 15 20 15 15 15 Unit ns ns ns ns ns ns ns 1/ All voltages referenced to VSS. 2/ Negative undershoots to a minimum of -0.3 V are allowed with a maximum of 50 ns pulse width. 3/ AC measurements assume transition time < 5 ns and input level are from VSS to 3.0 V. Output load is specified on figure 4. Reference timing levels are 1.5 V. 4/ For timing waveforms, see figure 4. 5/ Tested initially and after any design and or process changes which may affect this parameters, and therefore shall be guaranteed to the limits specified in table I. Transition measured 500 mV from steady-state value. 6/ This parameter measured 500 mV from steady-state output voltage. Load capacitance is 5.0 pF, see figure 4. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 6 NOTES: 1. Dimensions are in inches. 2. Metric equivalents are given for general information only. FIGURE 1. Case outline Y (24-terminal, .308" x .408" x .078"), rectangular chip carrier package. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 7 Device types Case outlines 01and 02 J,K,L,Y Terminal number 3, Z X Terminal Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 VSS I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CE A10 A7 A6 A5 A4 A3 A2 NC NC A1 A0 I/O 1 I/O 2 I/O 3 VSS I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 NC NC NC A7 A6 A5 A4 A3 A2 A1 A0 NC I/O 0 I/O 1 I/O 2 VSS NC I/O 3 I/O 4 20 OE CE I/O 5 21 22 NC NC A10 I/O 6 I/O 7 23 24 WE A9 A8 VCC OE A10 25 --- WE OE 26 27 28 29 30 31 32 --------------- A9 A8 VCC --------- WE NC A9 A8 NC NC VCC CE FIGURE 2. Terminal connections. Inputs CE H L L L Mode Power Standby Read Read Write Standby Active Active Active I/O WE OE X H H L X L H X I/O 0 - I/O 7 HI - Z Data output HI - Z Data input FIGURE 3. Truth table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 8 NOTES: 1. tr and tf 5 ns. 2. All switching characteristics and timing requirements assume test conditions as depicted in configuration (a) and configuration (b) with timing references of 1.5 V (50% reference point) as shown in the subsequent timing diagrams. FIGURE 4. Load circuit and switching waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 9 NOTE: When WE is high, address is valid prior to or simultaneously with the high-to-low transition of CE . FIGURE 4. Load circuit and switching waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 10 NOTES: 1. CE or WE must be high during address transitions. 2. The internal write time of the memory if defined by the overlap of CE low and WE low. Both signals must be low to initiate a write, and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. Data I/O pins enter high-impedance state, as shown when CE is held low during write. FIGURE 4. Load circuit and switching waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 11 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MILSTD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and COUT measurement) shall be measured only for the initial test and after process or design changes which may affect capacitance. Sample size is fifteen devices with no failures and all input and output terminals tested. d. Subgroups 7 and 8 tests shall include verification of the truth table. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 12 TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (per method 5005, table I) Interim electrical parameters (method 5004) --- Final electrical test parameters (method 5004) Group A test requirements (method 5005) 1/ 2/ 3/ 1*, 2, 3, 7*, 8A, 8B, 9, 10,11 1,2,3,4**,(7,8A,8B)***, 9, 10,11 Groups C and D end-point electrical parameters (method 5005) 2, 3, 7, 8A, 8B 1/ * indicates PDA applies to subgroups 1 and 7. 2/ ** see 4.3.1c. 3/ *** see 4.3.1d. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MILHDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89690 A REVISION LEVEL A SHEET 13 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 06-10-26 Approved sources of supply for SMD 5962-89690 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar part number 2/ 5962-8969001JA 61772 3/ 0C7V7 IDT6116SA25DB CY6116A-25DMB QP6116A-25DMB 5962-8969001KA 3/ 3/ 0C7V7 3DTT2 IDT6116SA25EB CY7C128A-25KMB QP7C128A-25KMB P4C116-25FMB 5962-8969001LA 3/ 3/ 61772 3DTT2 3/ 0C7V7 SMJ68CE16-25JDM CY7C128A-25DMB IDT6116SA25TDB P4C116-25DMB MT5C1608C-25883C QP7C128A-25DMB 5962-8969001XA 3/ 3/ 3/ CY6117A-25LMB IDT6116SA25L32B SMJ68CE16-25FGM 5962-8969001YA 3/ 3/ 3DTT2 0C7V7 IDT6116SA25L24B CY7C128A-25LMB P4C116-25LMB QP7C128A-25LMB 5962-89690013A 3/ 3/ 0C7V7 3DTT2 CY6116A-25LMB IDT6116SA25L28B QP6116A-25LMB P4C116-25L28MB 5962-8969001ZA 3/ 5962-8969002JA 61772 3/ 0C7V7 IDT6116SA20DB CY6116A-20DMB QP6116A-20DMB 5962-8969002KA 3/ 3/ 0C7V7 3DTT2 IDT6116SA20EB CY7C128A-20KMB QP7C128A-20KMB P4C116-20FMB 5962-8969002LA 3/ 61772 3DTT2 3/ 0C7V7 CY7C128A-20DMB IDT6116SA20TDB P4C116-20DMB MT5C1608C-20883C QP7C128A-20DMB See footnotes at end of table. Page 1 of 2 MT5C1608EC-25883C STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued. Standard microcircuit drawing PIN 1/ Vendor CAGE number 5962-8969002XA 3/ 3/ CY6117A-20LMB IDT6116SA20L32B 5962-8969002YA 3/ 3/ 3DTT2 0C7V7 IDT6116SA20L24B CY7C128A-20LMB P4C116-20LMB QP7C128A-20LMB 5962-8969002ZA 3/ MT5C1608EC-20883C 5962-89690023A 3/ 3/ 3/ 0C7V7 3DTT2 CY6116A-20LMB IDT6116SA20L28B MT5C1608EC-20883C QP6116A-20LMB P4C116-20L28MB Vendor similar part number 2/ 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution: Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source. Vendor CAGE number Vendor name and address 0C7V7 QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 3DTT2 Pyramid Semiconductor Corporation 1340 Bordeaux Drive Sunnyvale, CA 94089 61772 Integrated Device Technology, Inc. 2975 Stender Way Santa Clara, CA 95054 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. Page 2 of 2