LTC2311-12 12-Bit + Sign, 5Msps Differential Input ADC with Wide Input Common Mode Range Description Features n n n n n n n n n n n n n 5Msps Throughput Rate 0.25LSB INL (Typ), 1LSB INL Guaranteed Guaranteed 12-Bit, No Missing Codes 8VP-P Differential Inputs with Wide Input Common Mode Range 73dB SNR (Typ) at fIN = 2.2MHz -85dB THD (Typ) at fIN = 2.2MHz Guaranteed Operation -40C to 125C Single 3.3V or 5V Supply Low Drift (20ppm/C Max) 2.048V or 4.096V Internal Reference with 1.25V External Reference Input 1.8V to 2.5V I/O Voltages CMOS or LVDS SPI-Compatible Serial I/O Power Dissipation 50mW at VDD = 5V (Typ) Small 16-Lead (4mm x 5mm) MSOP Package Applications n n n n n n n High Speed Data Acquisition Systems Communications Remote Data Acquisition Imaging Optical Networking Automotive Multiphase Motor Control The LTC(R)2311-12 is a low noise, high speed 12-bit + sign successive approximation register (SAR) ADC with differential inputs and wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC231112 has an 8VP-P differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. The LTC2311-12 achieves 0.25LSB INL typical, no missing codes at 12 bits and 73dB SNR typical. The LTC2311-12 has an onboard low drift (20ppm/C max) 2.048V or 4.096V temperature compensated reference and provides an external 1.25V buffered reference input. The LTC2311-12 also has a high speed SPI-compatible serial interface that supports CMOS or LVDS. The fast 5Msps throughput with one-cycle latency makes the LTC2311-12 ideally suited for a wide variety of high speed applications. The LTC2311-12 dissipates only 50mW with a 5V supply and offers nap and sleep modes to reduce the power consumption for further power savings during inactive periods. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application IN+, IN - DIFFERENTIAL VDD REFOUT 25 BIPOLAR AIN+ REFIN 47pF UNIPOLAR 25 10F SDO SCK AIN- CMOS/LVDS 0V 0V 10F LTC2311-12 0V 0V 0 1F AMPLITUDE (dBFS) ARBITRARY 16k Point FFT fSMPL = 5Msps, fIN = 2.2MHz 3.3V OR 5V DIFFERENTIAL INPUTS NO CONFIGURATION REQUIRED GND LVDS OR CMOS CONFIGURABLE I/O SNR = 73.3dB THD = -85dB -20 SINAD = 73.1dB SFDR = 91dB -40 -60 -80 -100 -120 -140 CNV OVDD 1.8V TO 2.5V 0 0.5 1 1.5 FREQUENCY (MHz) 2 2.5 231112 TA01b 1F 231112 TA01a 231112f For more information www.linear.com/LTC2311-12 1 LTC2311-12 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) Supply Voltage (VDD)...................................................6V Supply Voltage (OVDD).................................................3V Analog Input Voltage AIN+, AIN - (Note 3).................... -0.3V to (VDD + 0.3V) REFIN, REFOUT........................ -0.3V to (VDD + 0.3V) CNV (Note 15)........................... -0.3V to (VDD + 0.3V) Digital Input Voltage (Note 3)........................... (GND - 0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3)........................... (GND - 0.3V) to (OVDD + 0.3V) Power Dissipation................................................200mW Operating Temperature Range LTC2311C.................................................. 0C to 70C LTC2311I...............................................-40C to 85C LTC2311H........................................... -40C to 125C Storage Temperature Range................... -65C to 150C Order Information TOP VIEW GND REFIN REFOUT VDD GND AIN+ AIN- GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 17 GND SCK+ SCK- SDO+ SDO- OVDD GND CMOS/LVDS CNV MSE PACKAGE 16-LEAD (4mm x 5mm) PLASTIC MSOP TJMAX = 150C, JA = 40C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB http://www.linear.com/product/LTC2311-12#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2311CMSE-12#PBF LTC2311CMSE-12#TRPBF 231112 16-Lead Plastic MSOP 0C to 70C LTC2311IMSE-12#PBF LTC2311IMSE-12#TRPBF 231112 16-Lead Plastic MSOP -40C to 85C LTC2311HMSE-12#PBF LTC2311HMSE-12#TRPBF 231112 16-Lead Plastic MSOP -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (AIN+) (Note 5) MIN l TYP 0 MAX UNITS VDD V VIN- Absolute Input Range (AIN-) (Note 5) l 0 VDD V VIN+ - VIN- Input Differential Voltage Range VIN = VIN+ - VIN- l -REFOUT REFOUT V VCM Common Mode Input Range VIN = (VIN+ + VIN-)/2 l 0 VDD V l -1 1 A IIN Analog Input DC Leakage Current CIN Analog Input Capacitance CMRR Input Common Mode Rejection Ratio VIHCNV CNV High Level Input Voltage l VILCNV CNV Low Level Input Voltage l VINCNV CNV Input Current fIN = 2.2MHz VIN = 0V to VDD l 10 pF 85 dB 1.3 -10 V 0.3 V 10 A 231112f 2 For more information www.linear.com/LTC2311-12 LTC2311-12 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS MIN MAX UNITS Resolution 12 Bits No Missing Codes l 12 Bits l -1 0.25 1 LSB l -0.99 0.2 0.99 LSB l -2 0 2 Transition Noise INL Integral Linearity Error DNL Differential Linearity Error BZE Bipolar Zero-Scale Error 0.3 (Note 6) (Note 7) Bipolar Zero-Scale Error Drift FSE TYP l LSBRMS 0.002 Bipolar Full-Scale Error VREFOUT = 4.096V (REFIN Grounded) (Note 7) Bipolar Full-Scale Error Drift VREFOUT = 4.096V (REFIN Grounded) l -4 1 LSB LSB/C 4 15 LSB ppm/C Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and AIN = -1dBFS (Notes 4, 8). MIN TYP SINAD SYMBOL PARAMETER Signal-to-(Noise + Distortion) Ratio fIN = 2.2MHz, VREFOUT = 4.096V, Internal Reference fIN = 2.2MHz, VREFOUT = 5V, External Reference CONDITIONS l 70.5 73 73.2 dB dB SNR Signal-to-Noise Ratio fIN = 2.2MHz, VREFOUT = 4.096V, Internal Reference fIN = 2.2MHz, VREFOUT = 5V, External Reference l 71 73.3 73.5 dB dB THD Total Harmonic Distortion fIN = 2.2MHz, VREFOUT = 4.096V, Internal Reference fIN = 2.2MHz, VREFOUT = 5V, External Reference l SFDR Spurious Free Dynamic Range fIN = 2.2MHz, VREFOUT = 4.096V, Internal Reference fIN = 2.2MHz, VREFOUT = 5V, External Reference l -3dB Input Linear Bandwidth SNR - SINAD 3dB -85 -85 79 MAX -79 UNITS dB dB 90 90 dB dB 10 MHz Aperture Delay 500 ps Aperture Jitter 1 psRMS 3 ns Transient Response Full-Scale Step Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS VREFOUT REFOUT Output Voltage 4.75V < VDD < 5.25V 3.13V < VDD < 3.47V REFOUT Input Voltage IREFOUT MIN TYP MAX UNITS l l 4.082 2.042 4.096 2.048 4.110 2.054 V V 4.75V < VDD < 5.25V, REFIN = 0V (Note 5) 3.13V < VDD < 3.47V, REFIN = 0V (Note 5) l l 0.5 0.5 VDD VDD V V REFOUT Temperature Coefficient (Note 14) l 20 ppm/C REFOUT Short-Circuit Current VDD = 5.25V, Forcing Output to GND l 30 mA 3 REFOUT Line Regulation VDD = 4.75V to 5.25V 0.3 mV/V REFOUT Load Regulation IREFOUT < 2mA 0.5 mV/mA REFOUT Input Resistance (External Reference Mode) REFIN = 0V 60 k REFOUT Input Current (External Reference Mode) REFIN = 0V, REFOUT = 4.096V (Note 10) 700 A 231112f For more information www.linear.com/LTC2311-12 3 LTC2311-12 Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VREFIN REFIN Output Voltage 3.13V < VDD < 3.47V 4.75V < VDD < 5.25V l l 1.245 1.245 1.25 1.25 1.255 1.255 V V REFIN Input Voltage 3.13V < VDD < 3.47V (Note 5) 4.75V < VDD < 5.25V (Note 5) l l 1 1 1.85 1.45 V V REFIN Short-Circuit Current VDD = 5.25V, Forcing Output to GND l 250 A 3.13V < VDD < 3.47V 4.75V < VDD < 5.25V l l 0.5 0.5 V V VIL (VREFIN) REFIN Low Level Input Voltage (External Reference Mode) Digital Inputs And Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Digital Inputs and Outputs VIH High Level Input Voltage l VIL Low Level Input Voltage l IIN Digital Input Current CIN Digital Input Capacitance VOH 0.8 * OVDD VIN = 0V to OVDD l -10 High Level Output Voltage IO = -500A l OVDD - 0.2 VOL Low Level Output Voltage IO = 500A l l V 0.2 * OVDD V 10 A 5 IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD ISOURCE Output Source Current VOUT = 0V ISINK Output Sink Current VOUT = OVDD pF V 0.2 -10 10 V A -10 mA 10 mA LVDS Digital Inputs and Outputs VID LVDS Differential Input Voltage 100 Differential Termination, OVDD = 2.5V l 240 600 mV VIS LVDS Common Mode Input Voltage 100 Differential Termination, OVDD = 2.5V l 1 1.45 V VOD LVDS Differential Output Voltage 100 Differential Load, LVDS Mode, OVDD = 2.5V l 100 225 300 mV VOS LVDS Common Mode Output Voltage 100 Differential Load, LVDS Mode, OVDD = 2.5V l 0.85 1.2 1.4 V VOD_LP Low Power LVDS Differential Output Voltage 100 Differential Load, Low Power, LVDS Mode, OVDD = 2.5V l 50 125 200 mV VOS_LP Low Power LVDS Common Mode Output Voltage 100 Differential Load, Low Power, LVDS Mode, OVDD = 2.5V l 0.9 1.2 1.4 V 231112f 4 For more information www.linear.com/LTC2311-12 LTC2311-12 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS MIN 5V Operation 3.3V Operation MAX UNITS l l 4.75 3.13 TYP 5.25 3.47 V V l 1.71 2.63 V VDD Supply Voltage OVDD Supply Voltage IVDD Supply Current 5Msps Sample Rate (AIN+ = AIN- = 0V) l 8.8 12 mA INAP Nap Mode Current Conversion Done (IVDD) l 2.4 3.5 mA ISLEEP Sleep Mode Current VDD = 3.3V, Sleep Mode (IVDD + IOVDD) l 0.1 10 A l 1.1 1.5 mA CMOS I/O Mode IOVDD Supply Current 5Msps Sample Rate (CL = 5pF) PD_3.3V Power Dissipation VDD = 3.3V 5Msps Sample Rate (AIN+ = AIN- = 0V) 27 mW PD_5V Nap Mode VDD = 3.3V Conversion Done (IVDD + IOVDD) 7.5 mW Sleep Mode VDD = 3.3V Sleep Mode (IVDD + IOVDD) 0.3 W Power Dissipation VDD = 5V 5Msps Sample Rate (AIN+ = AIN- = 0V) l Nap Mode VDD = 5V Conversion Done (IVDD + IOVDD) l Sleep Mode VDD = 5V Sleep Mode (IVDD + IOVDD) l l 2.5 50 65 mW 12 18 mW 0.5 30 W 3.5 mA LVDS I/O Mode IOVDD Supply Current 5Msps Sample Rate (RL = 100) PD_3.3V Power Dissipation VDD = 3.3V 5Msps Sample Rate (AIN+ = AIN- = 0V) PD_5V 33 mW Nap Mode VDD = 3.3V Conversion Done (IVDD + IOVDD) 14 mW Sleep Mode VDD = 3.3V Sleep Mode (IVDD + IOVDD) 0.3 W Power Dissipation VDD = 5V 5Msps Sample Rate (AIN+ = AIN- = 0V) l 58 65 mW Nap Mode VDD = 5V Conversion Done (IVDD + IOVDD) l 18 25 mW Sleep Mode VDD = 5V Sleep Mode (IVDD + IOVDD) l 0.5 20 W ADC Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 5 Msps CMOS, LVDS I/O Modes fSMPL Maximum Sampling Frequency l tCYC Time Between Conversions (Note 11) l 200 tACQ Acquisition Time (Note 11) l 38.1 1000000 ns ns tCONV Conversion Time l 161.9 ns tCNVH CNV High Time l 25 ns tDCNVSCKL SCK Quiet Time from CNV (Note 11) l 10 ns tDSCKLCNVH SCK Delay Time to CNV (Note 11) l 20 ns (Notes 12, 13) tSCK SCK Period l 9.4 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns 231112f For more information www.linear.com/LTC2311-12 5 LTC2311-12 ADC Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C (Note 4). SYMBOL PARAMETER CONDITIONS tDSCKSDOV SDO Data Valid Delay from SCK CL = 5pF (Note 11) l tHSDO SDO Data Remains Valid Delay from SCK CL = 5pF (Note 11) l tDCNVSDOV SDO Data Valid Delay from CNV CL = 5pF (Note 11) l tDCNVSDOZ Bus Relinquish Time After CNV (Note 11) l tWAKE REFOUT Wake-Up Time CREFOUT = 10F Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground, or above VDD or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground, or above VDD or OVDD, without latch-up. Note 4: VDD = 5V, OVDD = 2.5V, REFOUT = 4.096V, fSMPL = 5MHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero error is the offset voltage measured from -0.5LSB when the output code flickers between 0 0000 0000 0000 and 1 1111 1111 1111. Full-scale bipolar error is the worst-case of -FS or +FS MIN TYP MAX 4 7.4 2 UNITS ns ns 2.5 10 5 ns 5 ns ms untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale 4.096V input with REFOUT = 4.096V. Note 9: When REFOUT is overdriven, the internal reference buffer must be turned off by setting REFIN = 0V. Note 10: fSMPL = 5MHz, IREFOUT varies proportionally with sample rate. Note 11: Guaranteed by design, not subject to test. Note 12: Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V. Note 13: tSCK of 9.4ns minimum allows a shift clock frequency up to 105MHz for falling edge capture. Note 14: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 15: CNV is driven from a low jitter digital source, typically at OVDD logic levels. This input pin has a TTL style input that will draw a small amount of current. 0.8 * OVDD tWIDTH 0.2 * OVDD tDELAY tDELAY 0.8 * OVDD 0.8 * OVDD 0.2 * OVDD 0.2 * OVDD 50% 50% 231112 F01 Figure 1. Voltage Levels for Timing Specifications 231112f 6 For more information www.linear.com/LTC2311-12 LTC2311-12 Typical Performance Characteristics 4.096V, fSMPL = 5Msps, unless otherwise noted. Integral Nonlinearity vs Output Code TA = 25C, VDD = 5V, OVDD = 2.5V, REFOUT = Differential Nonlinearity vs Output Code DC Histogram for 64k Samples 50000 1.0 1.0 = 0.3 45000 0 35000 COUNTS DNL ERROR (LSB) INL ERROR (LSB) 40000 0.5 0.5 0 25000 20000 15000 -0.5 -0.5 30000 10000 5000 -1.0 -4096 -2048 0 2048 OUTPUT CODE -1.0 -4096 4096 -2048 0 2048 OUTPUT CODE 16k Point FFT, fSMPL = 5Msps, fIN = 2.2MHz -80 -100 -120 0.5 1 1.5 FREQUENCY (MHz) 2 73.8 -85 73.6 SNR 73.4 SINAD 0 0.5 2 2.5 73 3.3 231112 G07 2 72 71 70 69 67 2.5 -20 SINAD AMPLITUDE (dBFS) SNR,SINAD (dBFS) 2.1 2.3 2.5 2.7 2.9 3.1 INPUT COMMON MODE (V) 1 1.5 FREQUENCY (MHz) 0 68 1.9 0.5 8k Point FFT, IMD, fSMPL = 5Msps, AIN+ = 100kHz, AIN- = 2.2MHz SNR -85 1.7 0 231112 G06 74 THD -100 -100 SNR, SINAD vs Reference Voltage, fIN = 500kHz -80 THD, SFDR (dBFS) 1 1.5 FREQUENCY (MHz) 231112 G05 THD, SFDR vs Input Common Mode (100kHz to 2.2MHz) -95 SFDR -95 231112 G04 -90 2 THD -90 73.2 73.0 2.5 SFDR 1 -80 THD, SFDR (dBFS) SNR, SINAD LEVEL (dBFS) AMPLITUDE (dBFS) -60 0 CODE THD, SFDR Input Frequency (100kHz to 2.2MHz) 74.0 SNR = 73.3dB THD = -85dB -20 SINAD = 73.1dB SFDR = 91dB -40 -1 231112 G03 SNR, SINAD vs Input Frequency (100kHz to 2.2MHz) 0 0 -2 231112 G02 231112 G01 -140 0 4096 -40 -60 -80 -100 -120 0.5 1 1.5 2 2.5 3 3.5 VREF (V) 4 4.5 5 231112 G08 -140 0 0.5 1 1.5 FREQUENCY (MHz) 2 2.5 231112 G09 231112f For more information www.linear.com/LTC2311-12 7 LTC2311-12 Typical Performance Characteristics TA = 25C, VDD = 5V, OVDD = 2.5V, REFOUT = 4.096V, fSMPL = 5Msps, unless otherwise noted. Offset Error vs Temperature Gain Error vs Temperature CMRR vs Input Frequency 0.10 1.0 -80 -83 0.05 0 -86 CMRR (dB) GAIN ERROR (LSB) OFFSET ERROR (LSB) 0.5 0 -0.05 -0.5 -89 -92 -95 -98 -101 -1.0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 -0.10 -50 -25 0 25 50 75 TEMPERATURE (C) 708 200 100 0 -100 -200 -300 -400 IREFOUT vs Temperature, VREF = 4.096V -25 0 25 50 75 TEMPERATURE (C) 100 125 0.5 1 1.5 FREQUENCY (MHz) 2 2.5 231112 G12 REFOUT Output Load Regulation 706 4.0965 704 4.0960 702 4.0955 700 4.0950 698 4.0945 -500 -600 -50 0 4.0970 VREF (V) 2.048V 4.096V REFERENCE CURRENT (A) REFOUT ERROR (ppm, NORMALIZED TO 25C) REFOUT Output vs Temperature 300 -104 125 231112 G11 231112 G10 400 100 696 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 231112 G14 231112 G13 Supply Current vs Sample Frequency 1.5 10 4.0940 0 0.5 1 1.5 REFOUT LOAD CURRENT (mA) 2 231112 G15 OVDD Current vs SCK Frequency, CLOAD = 10pF OVDD CURRENT (mA) SUPPLY CURRENT (mA) 9 8 8 7 1.0 0.5 6 5 0 1 2 3 4 SAMPLE FREQUENCY (Msps) 5 0 0 10 20 30 40 50 60 70 80 90 100 110 SCK FREQUENCY (MHz) 231112 G16 231112 G17 231112f 8 For more information www.linear.com/LTC2311-12 LTC2311-12 Pin Functions GND (Pins 1, 5, 8, 11): Ground. These pins and the exposed pad (Pin 17) must be tied directly to a solid ground plane. REFIN (Pin 2): Reference Buffer 1.25V Input/Output. An onboard buffer nominally outputs 1.25V to this pin. This pin should be decoupled closely to the pin (no vias) with a 10F (X5R, 0805 size) ceramic capacitor. The internal buffer driving this pin may be overdriven with an external reference. The REFIN pin, when pulled to GND disables the REFOUT pin buffer allowing an external reference to drive REFOUT directly. REFOUT (Pin 3): Reference Buffer Output. An onboard buffer nominally outputs 4.096V to this pin. This pin should be decoupled closely to the pin (no vias) with a 10F (X5R, 0805 size) ceramic capacitor. The internal buffer driving this pin may be disabled by grounding the REFIN pin. If the buffer is disabled, an external reference may drive this pin in the range of 1.25V to VDD. VDD (Pin 4): Power Supply. Bypass VDD to GND with a 1F ceramic capacitor close to the VDD pin. AIN+, AIN- (Pins 6, 7): Analog Differential Input Pins. Fullscale range (AIN+ to AIN-) is REFOUT voltage. These pins can be driven from VDD to GND. CNV (Pin 9): Convert Input. This pin, when high, defines the sampling phase. When this pin is driven low, the conversion phase is initiated and output data is clocked out. This input pin is a TTL style input typically driven at OVDD levels with a low jitter pulse, but it is bound to VDD levels. This pin is unaffected by the CMOS/LVDS pin. CMOS/LVDS (Pin 10): I/O mode select. Ground this pin to enable CMOS mode, tie to OVDD to enable LVDS mode. Float this pin to enable low power LVDS mode. OVDD (Pin 12): I/O Interface Digital Power. The range of OVDD is 1.71V to 2.5V. This supply is nominally set to the same supply as the host interface (CMOS: 1.8V or 2.5V, LVDS: 2.5V). Bypass OVDD to GND with a 1F ceramic capacitor close to the OVDD pin. Exposed Pad (Pin 17): Ground. Solder this pad to ground. CMOS I/O Mode SDO+ (Pin 14): Serial Data Output. The conversion result is shifted MSB first on each falling edge of SCK. The result is output on SDO+. The logic level is determined by OVDD. Do not connect SDO-. (Pin 13) SCK+ (Pin 16): Serial Data Clock Input. The falling edge of this clock shifts the conversion result MSB first onto the SDO pins. Drive SCK+ with a single-ended clock. The logic level is determined by OVDD. Do not connect SCK-. (Pin 15) LVDS I/O Mode SDO+, SDO- (Pins 14, 13): Serial Data Output. The conversion result is shifted MSB first on each falling edge of SCK. The result is output differentially on SDO+ and SDO-. These pins must be differentially terminated by an external 100 resistor at the receiver (FPGA). SCK+, SCK- (Pins 16, 15): Serial Data Clock Input. The falling edge of this clock shifts the conversion result MSB first onto the SDO pins. Drive SCK+ and SCK- with a differential clock. These pins must be differentially terminated by an external 100 resistor at the receiver (ADC). 231112f For more information www.linear.com/LTC2311-12 9 LTC2311-12 Functional Block Diagram CMOS I/O Mode 4 6 7 VDD AIN+ AIN- LDO + 13-BIT SAR ADC S/H - LVDS/CMOS TRI-STATE SERIAL OUTPUT GND 1, 5, 8, 11, 17 3 2 9 REFOUT SDO+ 14 OVDD 12 1.25V REF G CMOS/LVDS 10 REFIN CNV TIMING CONTROL LOGIC LVDS/CMOS RECEIVERS SCK+ 16 231112 BDa LVDS I/O Mode 4 6 7 VDD AIN+ AIN- LDO + 13-BIT SAR ADC S/H - LVDS/CMOS TRI-STATE SERIAL OUTPUT GND 1, 5, 8, 11, 17 3 2 9 REFOUT SDO+ SDO- 14 13 OVDD 12 G 1.25V REF CMOS/LVDS 10 REFIN CNV TIMING CONTROL LOGIC LVDS/CMOS RECEIVERS SCK+ SCK - 16 15 231112 BDb 231112f 10 For more information www.linear.com/LTC2311-12 LTC2311-12 Timing Diagram CMOS, LVDS I/O Modes ACQUISITION CONVERSION AND READOUT ACQUISITION CNV SCK HI-Z SDO B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 HI-Z 231112 TD SERIAL DATA BITS B[12:0] CORRESPOND TO PREVIOUS CONVERSION 231112f For more information www.linear.com/LTC2311-12 11 LTC2311-12 Applications Information The LTC2311-12 is a low noise, high speed 12-bit + sign successive approximation register (SAR) ADC with differential inputs and a wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC231112 has an 8VP-P differential input range, making it ideal for applications which require a wide dynamic range. The LTC2311-12 achieves 0.25LSB INL typical, no missing codes at 12 bits and 73dB SNR typical. The LTC2311-12 has an onboard reference buffer and low drift (20ppm/C max) 4.096V temperature-compensated reference. The LTC2311-12 also has a high speed SPIcompatible serial interface that supports CMOS or LVDS. The fast 5Msps throughput with one-cycle latency makes the LTC2311-12 ideally suited for a wide variety of high speed applications. The LTC2311-12 dissipates only 50mW operating at a 5V supply. Nap and sleep modes are also provided to reduce the power consumption of the LTC231112 during inactive periods for further power savings. ADC provides 12 bits of resolution across this reduced span, with the additional benefit of digitizing over and underrange conditions, as shown in Table 1. The LTC2311-12 digitizes the full-scale voltage of 2 * REFOUT into 213 levels, resulting in an LSB size of 1mV with REFOUT = 4.096V. The ideal transfer function is shown in Figure 2. The output data is in 2's complement format. When driven by fully differential inputs, the transfer function spans 213 codes. When driven by pseudo differential inputs, the transfer function spans 212 codes. OUTPUT CODE (TWO'S COMPLEMENT) OVERVIEW 0 1111 1111 1111 0 1111 1111 1110 0 0000 0000 0001 0 0000 0000 0000 1 1111 1111 1111 1LSB = 2 * REFOUT 8192 1 0000 0000 0001 1 0000 0000 0000 CONVERTER OPERATION -1LSB 0 1LSB -REFOUT The LTC2311-12 operates in two phases. During the acquisition phase, the sample capacitor is connected to the analog input pins AIN+ and AIN - to sample the differential analog input voltage, as shown in Figure 3. A falling edge on the CNV pin initiates a conversion. During the conversion phase, the 13-bit CDAC is sequenced through a successive approximation algorithm for each input SCK pulse, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g., VREFOUT/2, VREFOUT/4 ... VREFOUT/8192) using a differential comparator. At the end of conversion, the CDAC output approximates the sampled analog input. The ADC control logic then prepares the 13-bit digital output code for serial transfer. The MSB of the 13-bit two's complement output indicates the sign of the differential analog input voltage. TRANSFER FUNCTION The LTC2311-12 transfer function provides 13 bits of resolution across the full span of 2 * REFOUT, as shown in Figure 2. If the analog input spans less than this fullscale, such as in the case of pseudo-differential drive, the REFOUT -1LSB INPUT VOLTAGE (V) 231112 F02 Figure 2. LTC2311-12 Transfer Function VDD RON 15 AIN+ CIN 10pF BIAS VOLTAGE VDD AIN- RON 15 CIN 10pF 231112 F03 Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2311-12 231112f 12 For more information www.linear.com/LTC2311-12 LTC2311-12 Applications Information MIN CODE MAX CODE Fully -REFOUT to Differential +REFOUT 1 0000 0000 0000 0 1111 1111 1111 nals, with no configuration required. The wide common mode input range relaxes the accuracy requirements of any signal conditioning circuits prior to the analog inputs. Pseudo-REFOUT/2 to Differential +REFOUT/2 Bipolar 11 000 0000 0000 00 111 1111 1111 Pseudo-Differential Bipolar Input Range Psuedo0 to REFOUT Differential Unipolar 0 0000 0000 0000 Table 1: Code Ranges for the Analog Input Operational Modes MODE SPAN (VIN+ - VIN-) 0 1111 1111 1111 Analog Input The differential inputs of the LTC2311-12 provide great flexibility to convert a wide variety of analog signals with no configuration required. The LTC2311-12 digitizes the difference voltage between the AIN+ and AIN - pins while supporting a wide common mode input range. The analog input signals can have an arbitrary relationship to each other, provided that they remain between VDD and GND. The LTC2311-12 can also digitize more limited classes of analog input signals such as pseudo-differential unipolar/ bipolar and fully differential with no configuration required. The analog inputs of the LTC2311-12 can be modeled by the equivalent circuit shown in Figure 3. The back-toback diodes at the inputs form clamps that provide ESD protection. In the acquisition phase, 10pF (CIN) from the sampling capacitor in series with approximately 15 (RON) from the on-resistance of the sampling switch is connected to the input. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the ADC sampler. The inputs of the ADC core draw a small current spike while charging the CIN capacitors during acquisition. The pseudo-differential bipolar configuration represents driving one of the analog inputs at a fixed voltage, typically VREF /2, and applying a signal to the other AIN pin. In this case the analog input swings symmetrically around the fixed input yielding bipolar two's complement output codes with an ADC span of half of full-scale. This configuration is illustrated in Figure 4, and the corresponding transfer function in Figure 5. The fixed analog input pin need not be set at VREF /2, but at some point within the VDD rails allowing the alternate input to swing symmetrically around this voltage. If the input signal (AIN+ - AIN -) swings beyond REFOUT/2, valid codes will be generated by the ADC and must be clamped by the user, if necessary. VREF 0V LT1819 VREF + - 0V 25 VREF LTC2311-12 AIN+ 47pF 10k VREF /2 10k 1F + - 25 VREF /2 REFOUT REFIN AIN- SDO SCK CNV 10F 10F TO CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) 231112 F04 Figure 4. Pseudo-Differential Bipolar Application Circuit ADC CODE (2's COMPLEMENT) Single-Ended Signals 4095 Single-ended signals can be directly digitized by the LTC2311-12. These signals should be sensed pseudodifferentially for improved common mode rejection. By connecting the reference signal (e.g., ground sense) of the main analog signal to the other AIN pin, any noise or disturbance common to the two signals will be rejected by the high CMRR of the ADC. The LTC2311-12 flexibility handles both pseudo-differential unipolar and bipolar sig- 2048 -VREF -VREF /2 -2048 -4096 0 VREF /2 VREF AIN (AIN+ - AIN-) DOTTED REGIONS AVAILABLE 231112 F05 Figure 5. Pseudo-Differential Bipolar Transfer Function 231112f For more information www.linear.com/LTC2311-12 13 LTC2311-12 Applications Information Pseudo-Differential Unipolar Input Range complement output codes with an ADC span of half of full-scale. This configuration is illustrated in Figure 6, and the corresponding transfer function in Figure 7. If the input signal (AIN+ - AIN -) swings negative, valid codes will be generated by the ADC and must be clamped by the user, if necessary. The pseudo-differential unipolar configuration represents driving one of the analog inputs at ground and applying a signal to the other AIN pin. In this case, the analog input swings between ground and VREF yielding unipolar two's VREF 0V LT1818 VREF + - 0V LTC2311-12 25 AIN+ REFIN 47pF 25 REFOUT AIN- SDO SCK CNV 10F 10F TO CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) 231112 F06 Figure 6. Pseudo-Differential Unipolar Application Circuit ADC CODE (2's COMPLEMENT) 4095 2048 -VREF -VREF /2 -2048 -4096 0 VREF /2 VREF AIN (AIN+ - AIN-) DOTTED REGIONS AVAILABLE 231112 F07 Figure 7. Pseudo-Differential Unipolar Transfer Function 231112f 14 For more information www.linear.com/LTC2311-12 LTC2311-12 Applications Information Single-Ended-to-Differential Conversion Fully-Differential Inputs While single-ended signals can be directly digitized as previously discussed, single-ended to differential conversion circuits may also be used when higher dynamic range is desired. By producing a differential signal at the inputs of the LTC2311-12, the signal swing presented to the ADC is maximized, thus increasing the achievable SNR. To achieve the best distortion performance of the LTC2311-12, we recommend driving a fully-differential signal through LT1819 amplifiers configured as two unity-gain buffers, as shown in Figure 9. This circuit achieves the full data sheet THD specification of -85dB at input frequencies up to 2.2MHz. A fully-differential input signal can span the maximum full-scale of the ADC, up to REFOUT. The common mode input voltage can span the entire supply range up to VDD, limited by the input signal swing. The fully-differential configuration is illustrated in Figure 10, with the corresponding transfer function illustrated in Figure 11. The LT(R)1819 high speed dual operational amplifier is recommended for performing single-ended-to-differential conversions, as shown in Figure 8. In this case, the first amplifier is configured as a unity-gain buffer and the single-ended input signal directly drives the high impedance input of this amplifier. VREF 200 VREF LT1819 0V VREF /2 + - VREF + - VREF 0V VREF 0V 0V 200 0V LT1819 VREF + - 0V 0V 0V VREF 0V ADC CODE (2's COMPLEMENT) 4095 LTC2311-12 25 25 + - 0V Figure 9. LT1819 Buffering a Fully-Differential Signal Source AIN+ REFOUT REFIN VREF + - VREF 231112 F09 47pF VREF + - 231112 F08 Figure 8. Single-Ended to Differential Driver VREF LT1819 0V AIN- SDO SCK CNV 2048 10F 10F -VREF TO CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) 0 VREF /2 VREF AIN (AIN+ - AIN-) -2048 -4096 231112 F10 Figure 10. Fully-Differential Application Circuit -VREF /2 231112 F11 Figure 11. Fully-Differential Transfer Function 231112f For more information www.linear.com/LTC2311-12 15 LTC2311-12 Applications Information INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance inputs of the LTC2311-12 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC inputs draw a current spike at the start of the acquisition phase. For best performance, a buffer amplifier should be used to drive the analog inputs of the LTC2311-12. The amplifier provides low output impedance to minimize gain error and allow for fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the ADC inputs, which draw a small current spike during acquisition. Input Filtering The noise and distortion of the buffer amplifier and signal source must be considered since they add to the ADC noise and distortion. Noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. The simple 1-pole RC lowpass filter shown in Figure 12 is sufficient for many applications. SINGLE-ENDED INPUT SIGNAL 3.3nF BW = 1MHz SINGLE-ENDED TO DIFFERENTIAL DRIVER ADC REFERENCE Internal Reference The LTC2311-12 has an on-chip, low noise, low drift (20ppm/C max), temperature compensated bandgap reference that is internally buffered and is available at REFIN (Pin 2). The internal reference buffer gains the REFIN pin voltage (1.25V) to REFOUT (pin 3) and is 4.096V for a 5V supply and 2.048V for 3.3V supply. Bypass REFOUT to GND with a 10F (X5R, 0805 size) ceramic capacitor. The 10F capacitor should be soldered as close as possible to the REFOUT pin to minimize wiring inductance. The REFIN pin produces a 1.25V precision reference which should also be bypassed with a 10F (X5R, 0805 size) ceramic capacitor. The REFIN pin may be overdriven with an external precision reference as shown in Figure 13a. 5V TO 13.2V IN+ LTC2311 IN- 50 High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. 0.1F LTC6655-1.25V VIN VOUT_F SHDN VOUT_S REFIN 10F LTC2311-12 231114 F12 REFOUT 10F Figure 12. Input Signal Chain GND Sampling switch on-resistance (RON) and the sample capacitor (CIN) form a second lowpass filter that limits the input bandwidth to the ADC core to 110MHz. A buffer amplifier with a low noise density must be selected to minimize the degradation of the SNR over this bandwidth. 231112 F13a Figure 13a. LTC2311-12 with an External REFIN Voltage 231112f 16 For more information www.linear.com/LTC2311-12 LTC2311-12 Applications Information Table 1. Internal Reference with Internal Buffer FULLY DIFFERENTIAL VDD REFIN REFOUT INPUT RANGE 4.096V 5V 1.25V 4.096V UNIPOLAR INPUT RANGE BIPOLAR INPUT RANGE 0V to 4.096V 2.048V 3.3V 1.25V 0V to 2.048V 1.024V 2.048V 2.048V REFIN 0.1F Table 2. External Reference with Internal Buffer REFIN FULLY (OVERDIFFERENTIAL VDD DRIVEN) REFOUT INPUT RANGE 5V 1V 3.3V 3.3V 1.25V 3.3V 4.096V 4.096V UNIPOLAR INPUT RANGE 0V to 3.3V 1.65V 0V to 4.096V 2.048V 4.7V 4.7V 0V to 4.7V 2.35V 1V 1.65V 1.65V 0V to 1.65V 0.825V 1.25V 2.048V 2.048V 0V to 2.048V 1.024V 1.85 3V 3V 0V to 3V 1.5V Table 3. External Reference Unbuffered 5V 3.3V LTC6655-4.096 VIN VOUT_F SHDN VOUT_S REFOUT 10F BIPOLAR INPUT RANGE 1.45V VDD REFIN LTC2311-12 5V TO 13.2V REFOUT FULLY DIFFERENTIAL INPUT RANGE UNIPOLAR INPUT RANGE BIPOLAR INPUT RANGE 0V 0.5V 0.5V 0V to 0.5V 0.25V 0V 5V 5V 0V to 5V 2.5V 0V 0.5V 0.5V 0V to 0.5V 0.25V 0V 3.3V 3.3V 0V to 3.3V 1.65V External Reference The internal reference buffer can also be overdriven from 1.25V to 5V with an external reference at REFOUT as shown in Figure 13b. In this configuration, REFIN must be grounded to disable the internal reference buffer. A 55k internal resistance loads the REFOUT pin when the reference buffer is disabled. To maximize the input signal swing and corresponding SNR, the LTC6655-5 is recommended when overdriving REFOUT. The LTC6655-5 offers the same small size, accuracy, drift and extended temperature range as the LTC6655-4.096. By using a 5V reference, a higher SNR can be achieved. We recommend bypassing the LTC6655-5 with a 10F ceramic capacitor (X5R, 0805 size) as close as possible to the REFOUT pin. GND 231112 F13b Figure 13b. LTC2311-12 with an External REFOUT Voltage Internal Reference Buffer Transient Response The REFOUT pin of the LTC2311-12 draws charge (QCONV) from the external bypass capacitors during each conversion cycle. If the internal reference buffer is overdriven, the external reference must provide all of this charge with a DC current equivalent to IREFOUT = QCONV/tCYC. Thus, the DC current draw of REFOUT depends on the sampling rate and output code. In applications where a burst of samples is taken after idling for long periods, as shown in Figure 14 , IREFOUT quickly goes from approximately ~75A to a maximum of 700A for REFOUT = 5V at 5Msps. This step in DC current draw triggers a transient response in the external reference that must be considered since any deviation in the voltage at REFOUT will affect the accuracy of the output code. Due to the one-cycle conversion latency, the first conversion result at the beginning of a burst sampling period will be invalid. If an external reference is used to buffer/drive the REFOUT pin, the fast settling LTC6655 reference is recommended. CNV IDLE PERIOD 231112 F14 Figure 14. CNV Waveform Showing Burst Sampling 231112f For more information www.linear.com/LTC2311-12 17 LTC2311-12 Applications Information 0 AMPLITUDE (dBFS) OUTPUT CODE 4000 2667 1333 -60 -80 -100 -120 0 -5000 SNR = 73.3dB THD = -85dB -20 SINAD = 73.1dB SFDR = 91dB -40 100 0 TIME (ns) 200 -140 0 0.5 1 1.5 FREQUENCY (MHz) 2.5 231112 F16 231112 F15 Figure 15. Transient Response of the LTC2311-12 2 Figure 16. 16k Point FFT of the LTC2311-12 DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Fast Fourier transform (FFT) techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. The LTC2311-12 provides guaranteed tested limits for both AC distortion and noise measurements. The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 16 shows that the LTC2311-12 achieves a typical SNR of greater than 73dB at a 5MHz sampling rate with a 2.2MHz input. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is bandlimited to frequencies from above DC and below half the sampling frequency. Figure 16 shows that the LTC2311-12 achieves a typical SINAD of 73dB at a 5MHz sampling rate with a 2.2MHz input. Total Harmonic Distortion (THD) Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL /2). THD is expressed as: THD= 20log V22 + V32 + V42 +...+ VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. The THD specifications for the LTC2311-12 consider the first seven harmonics (i.e. N=7). Figure 16 shows that the LTC2311-12 achieves a typical THD of -85dB at a 5MHz sampling rate with a 2.2MHz input. 231112f 18 For more information www.linear.com/LTC2311-12 LTC2311-12 Applications Information POWER CONSIDERATIONS TIMING AND CONTROL The LTC2311-12 requires two power supplies: the 5V power supply (VDD), and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2311-12 to communicate with any digital logic operating between 1.8V and 2.5V. When using LVDS I/O, the OVDD supply must be set to 2.5V. CNV Timing Power Supply Sequencing The LTC2311-12 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC231112 has a power-on-reset (POR) circuit that will reset the LTC2311-12 at initial power-up or whenever the power supply voltage drops below 2V. Once the supply voltage re-enters the nominal supply voltage range, the POR will reinitialize the ADC. No conversions should be initiated until 10ms after a POR event to ensure the reinitialization period has ended. Any conversions initiated before this time will produce invalid results. 10 SUPPLY CURRENT (mA) 9 8 8 7 6 5 0 1 2 3 4 SAMPLE FREQUENCY (Msps) 5 231112 F17 The LTC2311-12 sampling and conversion is controlled by CNV. A rising edge on CNV will start sampling and the falling edge starts the conversion and readout process. The conversion process is timed by the SCK input clock. For optimum performance, CNV should be driven by a clean low jitter signal. The Typical Application at the back of the data sheet illustrates a recommended implementation to reduce the relatively large jitter from an FPGA CNV pulse source. Note the low jitter input clock times the falling edge of the CNV signal. The rising edge jitter of CNV is much less critical to performance. The typical pulse width of the CNV signal is 38.1ns at a 5Msps conversion rate. SCK Serial Data Clock Input The falling edge of this clock shifts the conversion result MSB first onto the SDO pins. A 105MHz external clock must be applied at the SCK pin to achieve 5Msps throughput. Nap/Sleep Modes Nap mode is a method to save power without sacrificing power-up delays for subsequent conversions. Sleep mode has substantial power savings, but a power-up delay is incurred to allow the reference and power systems to become valid. To enter nap mode on the LTC2311-12, the SCK signal must be held high or low and a series of two CNV pulses must be applied. This is the case for both CMOS and LVDS modes. The second rising edge of CNV initiates the nap state. The nap state will persist until either a single rising edge of SCK is applied, or further CNV pulses are applied. The SCK rising edge will put the LTC2311-12 back into the operational (full-power) state. When in nap Figure 17. Power Supply Current of the LTC2311-12 Versus Sampling Rate 231112f For more information www.linear.com/LTC2311-12 19 LTC2311-12 Applications Information mode, two additional pulses will put the LTC2311-12 in sleep mode. When configured for CMOS I/O operation, a single rising edge of SCK can return the LTC2311-12 into operational mode. A 10ms delay is necessary after exiting sleep mode to allow the reference buffer to recharge the external filter capacitor. In LVDS mode, exit sleep mode by supplying a fifth CNV pulse. The fifth pulse will return the LTC2311-12 to operational mode, and further SCK pulses will keep the part from re-entering nap and sleep modes. The fifth SCK pulse also works in CMOS mode as a method to exit sleep. In the absence of SCK pulses, repetitive CNV pulses will cycle the LTC2311-12 between operational, nap and sleep modes indefinitely. Refer to the timing diagrams in Figure 18, Figure 19, Figure 20 and Figure 21 for more detailed timing information about sleep and nap modes. CNV 1 DIGITAL INTERFACE The LTC2311-12 features a serial digital interface that is simple and straightforward to use. The flexible OVDD supply allows the LTC2311-12 to communicate with any digital logic operating between 1.8V and 2.5V. A 105MHz external clock must be applied at the SCK pin to achieve 5Msps throughput. In addition to a standard CMOS SPI interface, the LTC231112 provides an optional LVDS SPI interface to support low noise digital design. The CMOS/LVDS pin is used to select the digital interface mode. The falling edge of SCK outputs the conversion result MSB first on the SDO pins. In CMOS mode, use the SDO+ pin as the serial data output and the SCK+ pin as the serial clock input. Do not connect the SDO- and SCK- pins as they have internal pull-downs to GND. 2 FULL POWER MODE NAP MODE SCK HOLD STATIC HIGH OR LOW WAKE ON 1ST SCK EDGE SDO Z Z 231112 F18 Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK REFOUT REFOUT RECOVERY 4.096V 4.096V tWAKE CNV 1 2 3 4 NAP MODE SCK SLEEP MODE FULL POWER MODE HOLD STATIC HIGH OR LOW WAKE ON 1ST SCK EDGE SDO Z Z Z Z 231112 F19 Figure 19. CMOS Mode SLEEP and WAKE Using SCK 231112f 20 For more information www.linear.com/LTC2311-12 LTC2311-12 Applications Information REFOUT REFOUT RECOVERY 4.096V 4.096V tWAKE CNV 1 2 3 4 NAP MODE SCK WAKE ON 5TH CSB EDGE 5 SLEEP MODE FULL POWER MODE HOLD STATIC HIGH OR LOW Z SDO Z Z Z Z 231112 F20 Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV tDSCKLCNVH tCNVH CNV tDCNVSCKL SCK HI-Z SDO 1 2 tSCKL 3 4 5 tSCKH 6 7 8 9 tDCNVSDOZ tSCK 10 11 12 13 14 tDCNVSDOV B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 HI-Z tDSCKSDOV tHSDO tCONV tTHROUGHPUT 231112 F21 SERIAL DATA BITS B[12:0] CORRESPOND TO PREVIOUS CONVERSION Figure 21. LTC2311-12 Timing Diagram, CMOS, LVDS I/O Modes 231112f For more information www.linear.com/LTC2311-12 21 LTC2311-12 Applications Information In LVDS mode, use the SDO+/SDO- pins as a differential output. These pins must be differentially terminated by an external 100 resistor at the receiver (FPGA). The SCK+/ SCK- pins are a differential input and must be terminated differentially by an external 100 resistor at the receiver (ADC), see Figure 22. A single solid ground plane is used. Bypass capacitors to the supplies are placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. The analog input traces are screened by ground. BOARD LAYOUT For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer to the DC2425, the evaluation kit for the LTC2311-12. Reference Design To obtain the best performance from the LTC2311-12, a four layer printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals adjacent to analog signals or underneath the ADC. LTC2311-12 FPGA OR DSP 2.5V OVDD SDO+ 100 SDO- 2.5V SCK+ CMOS/LVDS 100 SCK- + - + - CNV 231112 F22 Figure 22. LTC2311-12 Using the LVDS Interface 231112f 22 For more information www.linear.com/LTC2311-12 LTC2311-12 Package Description Please refer to http://www.linear.com/product/LTC2311-12#packaging for the most recent package drawings. MSE Package 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev F) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 0.102 (.112 .004) 5.10 (.201) MIN 2.845 0.102 (.112 .004) 0.889 0.127 (.035 .005) 8 1 1.651 0.102 (.065 .004) 1.651 0.102 3.20 - 3.45 (.065 .004) (.126 - .136) 0.305 0.038 (.0120 .0015) TYP 16 0.50 (.0197) BSC 4.039 0.102 (.159 .004) (NOTE 3) RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 0.12 REF DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE 0.280 0.076 (.011 .003) REF 16151413121110 9 DETAIL "A" 0 - 6 TYP 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 1234567 8 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.86 (.034) REF 0.1016 0.0508 (.004 .002) MSOP (MSE16) 0213 REV F 231112f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC2311-12 23 LTC2311-12 Typical Application Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop VCC 0.1F 50 1k NC7SVUO4P5X MASTER_CLOCK VCC 1k D PRE NC7SV74KBX Q CLR CONV CONV ENABLE CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) CNV SCK LTC2311-12 GND CMOS/LVDS SDO NC7SVUO4P5X 10 231112 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2311-14 14-Bit +Sign, 5Msps, Differential Input ADC with Wide Input Common Mode Range 3.3V/5V Supply, 50mW, 20ppm/C Max Internal Reference, Flexible Inputs, 4mm x 5mm 16-Lead MSOP Package LTC2311-16 16-Bit, 5Msps, Differential Input ADC with Wide Input Common Mode Range 3.3V/5V Supply, 50mW, 20ppm/C Max Internal Reference, Flexible Inputs, 4mm x 5mm 16-Lead MSOP Package ADCs LTC2323-16/LTC2323-14/ 16-/14-/12-Bit, 5Msps, Simultaneous Sampling LTC2323-12 Dual ADCs 3.3V/5V Supply, 40mW/Ch, 20ppm/C Max Internal Reference, Flexible Inputs, 4mm x 5mm QFN-28 Package LTC1407/LTC1407-1 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V Supply, 2-Channel Differential, 1.5Msps per Channel Throughput, Unipolar/Bipolar Inputs, 14mW, MSOP Package LTC2314-14 14-Bit, 4.5Msps Serial ADC 3V/5V Supply, 18mW/31mW, 20ppm/C Max Internal Reference, Unipolar Inputs, 8-Lead TSOT-23 Package LTC2321-16/LTC2321-14/ 16-/14-/12-Bit, 2Msps, Simultaneous Sampling LTC2321-12 Dual ADCs 3.3V/5V Supply, 33mW/Ch, 10ppmC Max Internal Reference, Flexible Inputs, 4mm x 5mm QFN-28 Package LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, LTC2367-16/LTC2364-16 Low Power ADC 2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 5V Input Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm x 3mm DFN-16 Packages LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, LTC2377-16/LTC2376-16 Low Power ADC 2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC, Pin-Compatible Family in MSOP-16 and 4mm x 3mm DFN-16 Packages DACs LTC2632 Dual 12-/10-/8-Bit, SPI VOUT DACs with Internal Reference 2.7V to 5.5V Supply Range, 10ppm/C Reference, External REF Mode, Rail-to-Rail Output, 8-Pin ThinSOTTM Package LTC2602/LTC2612/ LTC2622 Dual 16-/14-/12-Bit SPI VOUT DACs with External Reference 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead MSOP Package LTC6655 Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LTC6652 Precision Low Drift, Low Power Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package References Amplifiers LT1818/LT1819 400MHz, 2500V/s, 9mA Single/Dual Operational Amplifiers LT1806 325MHz, Single, Rail-to-Rail Input and Output, Low -80dBc Distortion at 5MHz, 3.5nV/Hz Input Noise Voltage, Distortion, Low Noise Precision Op Amps 9mA Supply Current, Unity-Gain Stable LT6200 165MHz, Rail-to-Rail Input and Output, 0.95nV/Hz Low Noise, Low Distortion, Unity-Gain Stable Low Noise, Op Amp Family -85dBc Distortion at 5MHz, 6nV/Hz Input Noise Voltage, 9mA Supply Current, Unity-Gain Stable 231112f 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2311-12 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2311-12 LT 0716 * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2016