TS68C429AMFB/C - Atmel Corporation

Features

•8 Independent Receivers (Rx)

•3 Independent Transmitters (Tx)

•Full TS68K Family Microprocessor Interface Compatibility

•16-bit Data-bus

•ARINC 429 Interface: “1” and “0” Lines, RZ Code

•Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s

•Multi Label Capability

•Parity Control: Odd, Even, No Parity, Interrupt Capability

•Independent Programmable Frequency for Rx and Tx Channels

•8 Messages FIFO per Tx Channel

•Independent Interrupt Request Line for Rx and Tx Functions

•Vectored Interrupts

•Daisy Chain Capability

•Direct Addressing of all Registers

•Test Modes Ca pab ility

•20 MHz Operating Frequency

•Self-test Capabil ity for Receive r Labe l Memories and Trans mit FiFO

•Low Power: 400 mW

Description

The TS68C429A is an ARINC 429 controller. It is an enhanced version of the EF 4442

and it is des igned to be connec ted to the new 16- or 32-bi t microproc essors, espe-

cially these of the Atmel TS68K family.

Screening

• MIL-S TD -8 83, cl as s B

• DESC Drawing 5962-955180

•Atmel Standards

Application Note

• A detailed application note is available “AN 68C429A” on request.

R suffix

PGA 84

Ceramic Pin Grid Array

F suffix

CQFP 1 3 2

Ceramic Quad Flat Pack

CMOS

ARINC 429

Multichannel

Receiver/

Transmitter

(MRT)

TS68C429A

Rev. 2120A–H I REL –0 8/0 2

2TS68C429A 2120A–HIREL–08/02

Hardware Overview The TS 68C429A is a h igh p erforma nce ARINC 429 c ontroll er d esigned to i nter face pri-

mary to the Atmel TS68K family microprocessor in a straight forward fashion (see

“Application Notes” on page 33). It can be connected to any TS68K processor family

with an asynchronous bus with some additional logic in some cases.

As shown in Figure 1, the TS68C429A is divided into five main blocks, the microproces-

sor interface unit (MIU), the logical control unit (LCU), the interrupt control unit (ICU), the

receiver channel unit (RCU) and the transmitter channel unit (TCU).

• The MIU handles the interface protocol of the host processor. Through this unit, the

host sees the TS68C429A as a set of registers.

• The LCU controls the internal data flow and initializes the TS68C429A.

• The ICU manages one interrupt line for the RCU and one for the TCU. Each of

these two parts has a daisy chain capability. All channels have a dedicated vectored

interrupt answer. Receiver channels priority is programmable.

• The RCU is composed of 8 ARINC receiver channels made of:

– a serial to parallel converter to translate the two serial signals (the “1” and “0”

in RZ code) into two 16-bit words,

– a memory to store the valid labels,

– a control logic to check the validity of the received message,

– a buffer to keep the last valid received message.

• The TCU is composed of three ARINC transmitter channels made of:

– a parallel to serial converter to translate the messages into two serial signals

(the “1” and “0” in RZ code),

– a FIFO memory to store eight 32-bit ARINC messages,

– a control logic to synchronize the message transmitter (parity, gap, speed,

etc.).

• Test facility: Rx inputs can be internally connected to TX3 output.

• Self-test facility: The receiver control label matrix and transmitter FIFO can be

tested. This self-test can be used to verify the integrity of the TS68C429A

memories.

TS68C429A

2120A–HIREL–08/02

Figure 1. Simplified Block Diagram

4TS68C429A 2120A–HIREL–08/02

Package See “Package Mechanical Data” on page 40 and “Terminal Connections” on page 41.

Figure 1. Signal Description

Pin Name Type Function

A0-8 I Address bus. The add ress bu s is used to select one of the internal registers during a processor

read or write cycle.

D0-15 I/O This bi-d irectiona l bus is used to re ceive data from or transmit d ata to an intern al register during a

process or re ad or write cyc le. Du ring an in terru pt ac k now l edg e cy cl e, th e ve cto r number is given

on the lower data bus (D0 - D7).

CS I Chip select (active low). This input is used to select the chip for internal register access.

LDS I Lower data strobe. This input (active low) validates lower data during R/W access (D0-D7).

UDS I Upper data strobe. This input (active low) validates upper data during R/W access (D8-D15).

R/W I Read/write. This input defines a data transfer as a read (high) or a write (low) cycle.

DTACK O Data transfer acknowledge. If t he bus cycle is a processor rea d, the chip a s serts DTACK to

indicate that the information on the data bus is valid. If the bus cycle is a processor write, DTACK

acknowl edges the a cceptanc e of the data b y the MRT . DTACK will be asserted during chi p select

access (CS asserted) or interrup t acknowle dge cycle (IACKTX or IACKRK asserted).

IRQTX O Interrupt transmit request. This open drain output signals to the processor that an interrupt is

pending from the transmission part of the MRT. There are 6 causes that can generate an

inter rupt requ es t (2 per chann el: FIFO empty and end of transmissi on).

IACKTX I Interrupt transmit acknowledge. If IRQTX is active, the MRT will begin an interrupt acknowledge

cycle. The MRT will generate a vector number to the processor which is the highest priority

channel requesting interrupt service.

IEITX I Interrupt transmit enable in. This input, together with IEOTX signal, provides a daisy chained

interrupt structure for a vectored scheme. IEITX (active low) indicates that no higher priority

device is requesting interrupt service.

IEOTX O Interrupt transmit enable out. This output, together with IEITX signal, provides a daisy chained

interrupt structure for a vectored interrupt scheme. IEOTX (active low) indicates to lower priority

devices that neither the TS68C429A nor any highest priority peripheral is requesting an interrupt.

IRQRX O Interrupt transmit request. This open drain output signals to the processor that an interrupt is

pending from the receiving part of the chip. There are 9 causes that can generate an interrupt

request (1 per channel: valid message received, and 1 for bad parity on a received message).

IACKRX I Interrupt receive acknowledge. Same function as IACKTX but for receiver part.

IEIRX I Interrupt receive enable in. Same function as IEITX but for receiver part.

IEORX I Interrupt receive enable out. Same function as IEOTX but for receiver part.

TX1H O Transmission “1” line of the channel 1.

TX1L O Transmission “0” line of the channel 1.

TX2H O Transmission “1” line of the channel 2.

TX2L O Transmission “0” line of the channel 2.

TX3H O Transmission “1” line of the channel 3.

TX3L O Transmission “0” line of the channel 3.

RX1H I Rec ei vi ng “1” line of the chann el 1.

RX1L I Rec ei vi ng “0” line of the chann el 1.

RX2H I Rec ei vi ng “1” line of the chann el 2

TS68C429A

2120A–HIREL–08/02

RX2L I Rec ei vi ng “0” line of the chann el 2.

RX3H I Rec ei vi ng “1” line of the chann el 3.

RX3L I Rec ei vi ng “0” line of the chann el 3.

RX4H I Rec ei vi ng “1” line of the chann el 4.

RX4L I Rec ei vi ng “0” line of the chann el 4.

RX5H I Rec ei vi ng “1” line of the chann el 5.

RX5L I Rec ei vi ng “0” line of the chann el 5.

RX6H I Rec ei vi ng “1” line of the chann el 6.

RX6L I Rec ei vi ng “0” line of the chann el 6.

RX7H I Rec ei vi ng “1” line of the chann el 7.

RX7L I Rec ei vi ng “0” line of the chann el 7.

RX8H I Rec ei vi ng “1” line of the chann el 8.

RX8L I Rec ei vi ng “0” line of the chann el 8.

RESET I This input (active low) will initialize the TS68C429A registers.

VCC/GND I These inputs supply power to the chip. The VCC is powered at +5 volts and GND is the ground

connection.

CLK-SYS I The clock input is a single-phase signal used for internal timing of processor interface.

CLK-ARINC I This input provides the timing clock to synchronize received/transmitted messaged.

Figure 1. Signal Description (Continued)

Pin Name Type Function

6TS68C429A 2120A–HIREL–08/02

Figure 2 illustrates the functional signal groups.

Figure 2. Functional Signal Groups Diagram

Scope This drawing describes the specified requirements for the ARINC multi channel

receiver/transmitter, in compliance either with MIL-STD-863 class B or SMD drawing.

Applicable

Documents

MIL-STD-883 1. MIL-STD-883: test methods and procedures for electronics

2. MIL -S TD- 385 35: gene r al speci fi cat ion s for microc i rcui ts .

3. MIL-STD-1835 microcircu it case outlines.

4. DESC/SMD.

Requirements

General The micro circuits are in acc ordance w ith the app licable doc ument and as specifie d

herein.

TS68C429A

2120A–HIREL–08/02

Design and Construction

Terminal Connections Depending on the package, the terminal connections is detail ed in “Terminal Connec-

tions” on page 41.

Package The circuits are packaged in a hermetically sealed ceramic package which is conform to

case outlines of MIL-STD 1835 (when defined):

• PGA 84,

• CQFP 132.

The precise case outlines are described at the end of this specification (“Package

Mechanical Data” on page 40) and into MIL-STD-1835.

Special Recommended

Conditions for CMOS Devices •CMOS Latch-up

The CMOS cell i s basically compo sed of two complementar y transistors (a P-channe l

and an N -cha nne l), an d, i n the ste ady s tate , onl y one tra ns istor is tu rn ed-on . T he a ct ive

P-channel transistor sources current when the output is a logic high and presents a high

impedance when the output is a logic low. Thus the overall result is extremely low power

consum ption be cause t here is n o power loss thr ough the active P -channel transi stor.

Also since only once transistor is determined by leakage currents.

Because the basic CMOS cell is c omposed of two complementary transistors, a para-

sitic semiconductor controlled rectifier (SCR) formed and may be triggered when an

input e xceeds the supp ly vo ltage. The SCR that is fo rmed by th is hig h input cause s the

device to become “latched” in a mode that may result in excessive current drain and

eventual destruction of the device. Although the device is implemented with input pro-

tection diodes, care should be exercised to ensure that the maximum input voltages

specification is not exceeded from voltage transients; others may require no additional

circuitry.

•CMOS/TTL Levels

The TS 68C429 A does n’t sat isfy tot ally t he input/o utpu t drive requir ements of TTL log ic

device s, see Tabl e 4.

Electrical Characteristics

Table 1. Absolute Maximum Ratings

Symbol Parameter Test Conditions Min Max Unit

VCC Supply Voltage -0.3 +7.0 V

VIInput Voltage -0.3 +7.0 V

Pdmax Max Power Dissipation 400 mW

Tcase O pe rati ng Tem pera ture M suffix -55 +125 °C

V suffix -40 +85 °C

Tstg Storage Temperature -55 +150 °C

TjJunction Temperature +160 °C

Tleads Lead Temperature Max 5 sec. soldering +270 °C

8TS68C429A 2120A–HIREL–08/02

This device contains protective circuitry against damage due to high static voltages or

electrical fields: however, it is advised that normal precautions be taken to avoid applica-

tion of any volt ag es higher than maximum -rat ed v ol tage s to this high- i mpe dan ce ci rcui t.

Reliability of operation is enhanced if unused inputs are tied to an appropriate logic volt-

age level (e.g., either GND or VCC).

Figure 3. Clock Input Timing Diagram

Note: Timing measurements are referenced to and from a low of 0.8-volt and a high voltage of

2.25 volts, unless otherwise noted. The voltage swing through this range should start

outside and pass through the range such that the rise or fall will be linear between

0.8-volt and 2.25 volts.

Unless otherwise stated, all voltages are referenced to the reference terminal.

Table 2. Recommended Condition of Use

Symbol Parameter Test conditions Min Max Units

VCC Supply Voltage 4.5 5.5 V

VIL Low Level Input Voltage -0.5 0.8 V

VIH High Level Input Voltage 2.25 5.8 V

Tcase O pe rati ng Tem pera ture M suffix -55 +125 °C

V suffix -40 +85 °C

CLOutput Loa din g Ca pac ita nc e 130 pF

tr(c) Clock Rise Time (See Figure 3) 5 ns

tf(c) Clock Fall Time (See Figure 3) 5 ns

fcClock System Frequency

(See Figure 3) 0.5 20 MHz

Table 3. Thermal Characteristics

Package Symbol Parameter Value Unit

PGA 68 θJ-A Thermal Resistance Junction-to- ambient 28 °C/W

θJ-C Thermal Resistance Junction-to-case 2 °C/W

CQFP 132 θJ-A Thermal Resistance Junction-to- ambient 27 °C/W

θJ-C Thermal Resistance Junction-to-case 3 °C/W

0.8V

2.25V

tcyc

tCL tCH

tCF

tCR

TS68C429A

2120A–HIREL–08/02

Power Considera tions The average ch ip- junc ti on tempe ra ture, T J, in °C can be obtained from:

TJ = TA + (PD ⋅ θJA)(1)

TA = Ambient Temperature, °C

θJA = Package Thermal Resistance, Junction-to-Ambient, °C/W

PD = PINT + PI/O

PINT = ICC x VCC, Watts—Chip Internal Power

PI/O = Power Dissipation on Input and Output Pins—User Determined

For most app li cations PI/O < PINT and can be neglected.

An approximate relationship between PD and TJ (if PI/O is neglected ) is:

PD = K: (TJ + 273) (2)

Solving equations (1) and (2) for K gives:

K = PD ⋅ (TA + 273) + θJA ⋅ PD2(3)

where K is a constant pertaining to the particular part K can be determined from equa-

tion (3) by measuring PD (at equilibriu m) for a known TA. Using this value of K, the

values of PD and TJ can be obta ined b y solving equatio ns (1) and ( 2) iterat ively f or any

value of TA.

The tot al the rmal resis tance of a pack age ( θJA) can be separated into two components,

θJC and θCA, representing the barrier to heat flow from the semiconductor junction to the

package (case), surface (θJC) and from the case to the outside ambient (θCA). These

terms are related by the equation:

θJA = θJC + θCA (4)

θJC is device related and cannot be influenced by the user. However, θCA is user depen-

dent and can be minimized by such thermal management techniques as heat sinks,

ambien t air cooling and ther mal convecti on. Thus, good the rmal managem ent on the

part of the user can significantly reduce θCA so th at θJA approximately equals θJC. Substi-

tution of θJC for θJA in equation (1) will result in a lower semiconductor junction

temperature.

Mechanical and

Environment The microcircuits shall meet all mechanical environmental requirements of either MIL-

STD-883 for class B devices or DESC devices.

Marking The document where are defined the marking are identified in the related reference doc-

uments. Each microcircuit are legibly and permanently marked with the following

information as minimum:

•Atmel logo

• Manufacturer’s part number

• Class B identification

• Date-code of inspection lot

• ESD identifier if available

• Country of manufacturing

10 TS68C429A 2120A–HIREL–08/02
Quality Conformance 
Inspection
DESC/MIL-STD-883 Is in ac cordan ce with M IL-M-38 510 and  method 50 05 of M IL-STD-8 83. Grou p A and B
inspections are performed on each production lot. Group C and D inspections are per-
formed on  a periodic basis.
Electrical 
Characteristics
General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the
relevant measurement conditions are given below:
• Table 4, Table 5: Static electrical characteristics for the electrical variants.
• Table 6, Table 7, Table 8: Dynamic electrical characteristics.
For static characteristics (Table 4, Table 5), test methods refer to IEC 748-2 method
number, wher e exis tin g.
For dynamic characteristics (T able 6, Table 7, Tabl e 8), test methods refer t o clause 5.5
of this specification.
Note: 1. IDD is measured with all I/O pins at 0V, all input pins at 0V except signals CS, IACKxx, LDS, UDS at 5V and CLK-SYS and
CLK-ARINC which run at tcyc mini.
Table 4.  DC Electrical Characteristics
With -5 5°C ≤ Tcase ≤ +125°C or -40° ≤ Tcase ≤ +85°C; VCC = 5V ± 10% .
Symbol Parameter Min Max Unit
VIH Input High Voltage 2.25 VCC + 0.3 V
VIL Input Low Voltage -0.5 0.8 V
VOH Output Hi gh Vo lta ge (except IR QRX, IRQTX: open drain out puts) 2.7 V
VOL Output Low Volta ge 0.5 V
IOH Output Source Current (except IRQRX, 
IRQTX: open drain outputs) (Vout = 2.7V) -8 mA
IOL Output Sink  Current  (Vout = 0.5V) 8 mA
ILI Input Leakage Current  (Vin = 0 to VCC) ±20 µA
IDD Dynamic Current(1) (Tcase = Tmin ⋅ VDD
= Vmax)65 mA
Table 5.  Capacitance (TA = 25°C)
Symbol Parameter Max Unit
Cin Input Capacitance 10 pF
Cout HI-Z Output Capacitance 20 pF

TS68C429A

2120A–HIREL–08/02

Clock Timing

Note: 1. tcyc A ≥ 4 x tcyc S.

AC Electrical

Characteristics With VCC = 5 VDC ± 10% VSS = 0 VDC.

IEIxx, IEOxx, IACKxx, must be understood as generic signals (xx = RX and TX).

Figure 4. Read Cycle

Notes: 1. LDS/UDS can be asserted on the next or previous CLK-SYS period after CS goes low but (4) must be met for the next

period.

2. The cycle ends when the first of CS, LDS/UDS goe s high .

Table 6. Clock System (CLK SYS)

Symbol Parameter Min Max Unit

tcyc S Clock Period 50 2000 ns

tCLS, tCHS Cloc k Puls e Width 20 ns

tcrS, tcfS Rise and Fall Times 5 ns

Table 7. Clock ARINC (CLK ARINC)

Symbol Parameter Min Max Unit

tcyc ACycle Time

(1) 200 8000 ns

tCLA, tCHA Cloc k Puls e Width 240 ns

tcrA, tcfA Rise and Fall Times 5 ns

12 TS68C429A 2120A–HIREL–08/02

Figure 5. Write Cycle

3. LDS/UDS can be asserted on the same or previous CLK-SYS period as CS but (3) and (4) must be met.

Figure 6. Interrupt Cycle (IEIxx = 0)

Notes: 1. If UDS = 1, D15-D8 stay hi-z else D15-D8 drive the bus with a stable unknown value.

2. If IEOxx goes low, neithe r vecto r nor DT ACK are gene rated, e lse IEO xx stays inactive and a vector is generated (D7-D0 and

DTACK).

TS68C429A

2120A–HIREL–08/02

Figure 7. Interrupt Cycle (IEIxx = 1)

Notes: 1. If UDS = 1, D15-D8 stay hi-z else D15-D8 drive the bus with a stable unknown value.

2. If IEOxx goes low, neithe r vecto r nor DT ACK are gene rated, e lse IEO xx stays inactive and a vector is generated (D7-D0 and

DTACK).

Table 8. Timing Characteristic

Number Symbol Parameter Min Max T/G(1) Unit

AVCSL Address valid to CS low 0 - T ns

RWVCSL R/W valid to CS low 0 - T ns

DIVDSL Data in valid to LDS/UDS low 0 - T ns

SVCL CS, LDS/UDS, IACKxx valid to CLK-SYS low 5 - T ns

CLDKL CLK-SYS low to DTACK low - 45 T ns

CLDOV CLK-SYS low to data out valid - 50 T ns

DKLDOV DTACK low to data out valid - 10 G ns

SHDKH CS or LDS/UDS or IACKxx high to DTACK high - 35 G ns

SHDXZ CS or LDS/UDS or IACKxx high to DTACK hi-z - 50 G ns

10 tSHDOZ CS or LDS/UDS or IACKxx high to data out hi-z - 25 G ns

11 tILIOL IEIxx or IACKxx low to IEOxx low - 35 T ns

12 tIKHIOH IACKxx high to IEOxx high - 40 T ns

13 tIILDKL IEIxx low to DTACK low - 40 T ns

14 tIILDOV IEIxx low to data out valid - 45 T ns

15 tSH CS, IACKxx, LDS/UDS inactive time 15 - T ns

16 tDKLSH DTACK low to CS or LDS/UDS or IACKxx high 0 - G ns

17 tSHAH CS or LDS/UDS high to address hold time 0 - G ns

14 TS68C429A 2120A–HIREL–08/02

Note: 1. T/G = Tested/Guaranteed.

Functional

Description

Receiver Channel Unit

(RCU)

Overview The RCU is composed of 8 ARINC receiver channels and has per channel:

• a serial to parallel converter to translate the two serial signals in two 16-bit words.

• a memory to store the authorized labels,

• a control logic to check the validity of the received message.

• a buffer to keep the last valid received message.

Inputs Each receiver channel has two input lines, receiving line high (RxiH) and receiving line

low (RXiL) which are not directly compatible with the bipolar modulated ARINC line. This

ARINC three-level state sig nals (“HIG H”, “NULL”, “ LOW”) s hould be demulti plexed to

generate the two RZ lines according to Figure 8.

Figure 8.

Description Each channel h as a test mo de in which th e input sign als (RXiH , RXiL), are i nternally

connected to the third Transmit Channel Lines. This selection is done by programming

the Test bit in the receiver control register (see “Registe r Description” on page 17)

except this difference, the TS68C429A behaves exactly the same manner in the two

modes. The receiver channel block diagram is given in Figure 9.

ARINC signals being asynchronous, the RCU first rebuilds the received clock in order to

transf er the d ata with in the sh ift-re gister and whe n the Gap- contr oller ha s detec ted the

end of the message, tests the message validity according to the criteria listed hereafter.

18 tSHRWI CS or LDS/UDS high to R/W invalid 0 - G ns

19 tDKLDIH DTACK low to data in hold time 0 - G ns

20 tSHDOH CS or LDS/UDS or IACKxx high data out hold

time 0-Gns

Table 8. Timing Characteristic (Continued)

Number Symbol Parameter Min Max T/G(1) Unit

TS68C429A

2120A–HIREL–08/02

To detect the end of the mess age, the Gap-Cont roller wai ts for a Gap after the last

received bit. To do so, at eac h CLK ARINC cy cle, a counter is incremented and c om-

pared to the c ontent of th e Gap-Reg ister whi ch has th e user progr ammed v alue. If bo th

values are equal, the counter is stopped and an internal end of message signal is gener-

ated. Thi s counter is rese ted on the fal ling edge of the r ebuil t clock . Figur e 9 shows th e

gap detection principle.

When the end of message is detected, the TS68C429A verifies the following points:

• the number of received bits must be 32,

• if requested the message parity (see “Register Description” on page 17) is

compared to the parity bit of the message,

• the message label must be equal to one of the label stored in the Label Control

Matrix,

• the Buffer is empty (that is: the last message has been read). The corresponding bit

in the Status-register (see logical interface unit), has been cleared,

• when all four conditions are met, the message is transferred from the Shift-register

to the Buffer and the corresponding bit is set in the Status-register. If the interrupt

mode is enabled (see “General Circuit Control” on page 24) the IRQRX line is

activated.

If not, reception of a new message is enabled, see Note.

If only the message parity is incorrect, an interrupt can be generated (see “Register

Description” on page 17).

The Buffer is seen as two 16-bit word registers, the Most Significant Word of the mes-

sage (MSW) is contained in the lower address, the Less Significant Word of the

message (LSW) is contained in the upper address. The MSW should be read first

because reading the LSW will release the buffer and allow transfer of a new message

from the Shift-r egi st er.

16 TS68C429A 2120A–HIREL–08/02

Figure 9. Receiver Channel Block Diagram

Note: A valid message is stored in the Shift-Reg. until a new message arrives and so may be transferred to the message buffer as

soon as the buffer is “freed”.

TS68C429A

2120A–HIREL–08/02

Figure 10.

a) receiver control

b) gap register

c) message buffer

d) label control matrix

•Register Control Register

This read/write register controls the function of the related receiver channel:

End of msg

Synchro counter

Gap register

CLK-ARINC

Rebuilt clock

18 TS68C429A 2120A–HIREL–08/02

The lowest va lue will give the highest priori ty. If two channel s have the same priority,

one of them will never be able to send its interrupt vector to the microprocessor. Each

channel must have a unique channel priority order.

Figure 11.

1514131211109876543210

Channel enable

Test mode

Label control

Label control matrix write enable

Parity control

Not used

Wrong parity

Not used

Channel priority order

USD access LDS access

Table 9. Register Control Register Description

Bit Function Comments

Bit 15 Channel enable 0: channel is out of service

1: channel is in service

Bit 14 Test mode 0: external ARINC lines as input (normal operation)

1: third transmitter lines as input (test mode)

Bit 13 Label control 0: no control, all the labels are accepted

1: automatic check of the label according to the label control matrix

Bit 12 LCMWE label co ntrol matrix

write enable 0: receiving mode (write to the matrix are disabled)

1: programmation mode for labels control matrix

Bit 11 Parity control 0: even parity check

1: odd parity check

Bit 10 Parity control 0: parity check is disable

1: parity check is enable

Bit 9 Not used

Bit 8 Not used

Bit 7 Wrong parity: this feature is

enabled only if the self-test

0: receiv ed mes sage parit y is corr ect if read, reset w rong w rong pari ty flag i f writte n.

1: an incorrect received message parity has been detected (the corresponding

message is lost) (set by hardware).

Bit 6 Not used

TS68C429A

2120A–HIREL–08/02

•Gap Register (Figure 12)

The gap register i s acc ess ibl e fo r w ritin g op er ations on ly . It c on tai ns the v alue o n wh ic h

the gap counte r will be stopped and wi ll generate the end of the message signal (see

“Inputs” on page 14). The value is interpreted as a multiple of the CLK ARINC period.

Figure 12. Gap Register Description

The value of the gap register must be chosen so as to generate the end of the message

before the minimal gap as defined in the ARINC-429 norm.

•Message Buffer

The Bu ffer is ma de of two 16-bit reg isters, th e Most S ignificant Word of the mess age

(MSW) is contained in the lower address register, the Least Significant Word of the mes-

sage (LSW) is contained in the upper address register. For correct behavior, the MSW

must be read before the LSW. They are accessible in read mode only and 16-bit access

is mandatory.

•Label Control Matrix

The label control matrix is a 256 x 1 bit memory. There is one memory per channel.

The address is driven by the incoming label, the output data is used to v alidate this

incoming message label (see Figure 13). To program this matrix, the LCMWE (label

control matrix write enable) bit of the receiver-control-register should be set to “1” to

allow the access. At this time, the address is driven by the external address bus and the

data are written from the data bus D7 to D0 (one per channel according to Figure 14).

Any wri te to a matrix o n whic h the LC MWE i s not set will n ot hav e any e ffect. Th e labe l

control m atr ix c an be wr itten or r ea d in by te a nd wor d mod e. In word m ode , th e state of

D15-D8 is unknown. After complete programming of the matrix, the LCMWE bit should

be reset to “0” to allow normal receiving mode. A “1” in the memory means that this label

is allowed and a “0” means that this label must be ignored.

Bit 5 Not used

Bit 4 Not used

Bit 0 to 3 Channel priority: order The lowest value will give the highest priority. Each channel must have a unique

channel priority order.

If sev eral messa ges are pending, the inter rupt v ector will accoun t for high est priori ty

channel.

Table 9. Register Control Register Description

Bit Function Comments

20 TS68C429A 2120A–HIREL–08/02

Figure 13. Label Control Matrix

Figure 14.

Transmitter Channel

Unit (TCU)

Overview The TCU is composed of three ARINC transmit channels and has per channel:

• a parallel to serial converter to translate the messages into two serial signals,

• a FIFO memory to store eight 32-bit ARINC messages,

• a control logic to synchronize the message transmitter (parity, gap, speed...).

Outputs Each transmitter channel has two output lines, Transmit line High (TXiH) and Transmit

line Low (TXiL) which are not directly compatible with the bipolar modulated ARINC line.

These RZ format lines should be translated by an outside device into ARINC three-level

state signa l acc ordi ng to Figur e 15.

TS68C429A

2120A–HIREL–08/02

Figure 15. Transmitter Channel Unit Outputs

Description The block diagr am of a transmit chan nel is given is give n in Figure 16. On ly the third

channel can be switched to internal lines for test mode, otherwise the channels are iden-

tical. The selection of this test mode is done by programming the test bit in the

transmitter -control-reg ister (s ee “Regi ster Desc ription” on page 1 7). In this test mod e

the lines TX3H and TX3L are not driven, they are both kept at “0”.

The transmit frequency is generated by dividing the ARINC clock signal (CLK ARINC)

by the va lue contai ned in the fr equency reg ister. Thi s divided cl ock synch ronize s the

shift register which sends the 32-bit word on the lines TXiH and TXiL.

The parity is computed and if requested (see “Register Description” on page 17) the par-

ity bit (32nd bit of the message) is modified to have an odd number of “1” in the 32-bit

message for odd parity or an even number of “1” in the 32-bit message for even parity.

A gap con tro l bl oc k gene r ates a ga p be twee n the se nt me ss ag es . The v al ue of this ga p

is defined by the 5 bits “transmission gap” of the transmitter-control-register, it is given in

number of ARINC bit (see “Register Description” on page 17).

A FIFO control block manages the messages to be sent. Up to 8 messages can be writ-

ten into the FIFO. The FIFO is seen as a two 16-bit memory words, the Most Significant

Word of t he m es sa ge (MS W ) is writte n in the lower add ress , th e Le as t Si gnifi ca nt W or d

of the mess ag e ( LS W) is written in th e up per ad dr es s. Th e MS W s ho uld be written fir st.

The acces s to the FI FO is 16 bi ts mand ator y . The num ber of me ssages within the FIFO

is indicated by a counter that can be read through the transmitter-control-register. This

counter is incremented when the LSW is written and decremented when the message is

transfe rred to the shi ft- regi ste r. The “ Reset FIFO” bi t is us ed to c ancel me ss ag es wi thi n

the FIFO. If a transmission is on going, the entire message will be sent. The “reset

FIFO” bit remains active until written at 1 by the microprocessor. When the transmitter is

disable during a transmission, the out going message is lost.

When the F IFO is em pty , a b it is s et in t he s tatu s-r egi st er ( see “ Ge neral Cir cui t Con tro l”

on page 24). If the int er ru pt mo de is ena bled (see “Gene r al Ci rcui t Cont rol” on pag e 24)

the IRQTX lin e is activ ate d.

When the transmitter FIFO is empty and when no transmission is on going, the first write

access to the FIFO has to be preceded by the following sequence: disable and enable

transmission (see Figure 36: First FIFO access).

22 TS68C429A 2120A–HIREL–08/02

Figure 16. Transmitter Channel Block Diagram

• the frequency register,

• the transmitter control register,

• the FIFO.

•The Frequency Register

The frequency register is only accessible for writing operations by the user and contains

the frequency divider.

Figure 17. Frequency Register

TS68C429A

2120A–HIREL–08/02

The trans m is sion fr equ ency c an be com puted by di v iding th e CLK A RINC fr equ ency by

the frequency register value.

The frequency register must be loaded with a value greater or equal to 2.

•The Transmitter Control Register

The transmitter control register is accessible for reading and writing operations.

Figure 18. Transmitter Control Register

Table 10. Transmission Control Register Description

Bit Function Comments

Bit 15 Enable transmission - 0: channel out of service (stops on going transmission)

- 1: channel in service

- 1 to 0: transition is not allowed at the same time as an 1 to 0 transition of the bit 4

- when t he transm itter FIFO i s empty and when no transmissi on is on going, the first

write access to the FIFO has to be preceded by the following sequence: reset to 0

and then set to 1

Bit 14 Test (only 3rd channel) 0: normal operating

1: test, output are only driven on internal lines for input testing

Bit 13 to 12 Not used

Bus 11 Parity control 0: even parity calculation

1: odd parity calculation

Bit 10 Parity control 0: parity disable, Bit 32 of the message stays unchanged

1: parity enable. Bit 32 of the message will be forced by parity control

Bit 9 to 5 Transmission gap “transmission gap” which is the delay between two 32-bit ARINC messages (in

ARINC bit)

Bit 4 Reset FIFO - write a 0 in this bit reset the FIFO counter

- this bit must be set to 1 before any write in the transmit buffer.

- 1 to 0: transition is not allowed at the same time as an 1 to 0 transition of the bit 15

Bit 3 to 0 Number of msg these four bits indicate the available space within the FIFO

24 TS68C429A 2120A–HIREL–08/02

•FIFO

The FIFO is seen as two 16-bit words . The Most Signific ant Word (MSW) must be writ-

ten first. The Least Significant Word (LSW) write increments the FIFO counter.

Before any write, the user should verify that the FIFO is not full. If the FIFO is full, any

write to the FIFO will be lost.

General Circuit Control

Logical Control Unit (LCU) The LCU mainly distributes the clocks and reset within the MRT. The reset signal, active

low is an asy nc hro n ous s ign al . Wh en i t oc cu rs, a ll regis te rs are r es et t o z ero exce pt the

Label-Control-Matrix which is not initialized and the Status-Register which is set to FC00

(hex). Reset duration must be greater than 4 clk-cyc periods.

The LCU co ntains the St atus-reg ister . This read/wr ite regis ter indica tes the sta te of the

interna l op erati ons . It i s als o th e im age of the pen din g i nter rupt s i f the y ar e not m as ked.

Clearin g a bit “RX- Channel-i” wi ll cancel the receiv ed message and r elease the Mes-

sage-buffer for reception of a ne w message. The “ End of TX on channel-i” Is set only

when the in volved channel FI FO is empty. The form at of the Status-R egister is give n

below.

Figure 19. Status Register

TS68C429A

2120A–HIREL–08/02

Microprocessor Interface Unit

(MIU) This interface which is directly compatible with the Atmel TS68K family is based on an

asynch ro nou s data trans fer.

The data exchange is mandatory on 16 bits for access to the FIFO messages (transmit-

ter) and to the message buffer (receiver). For other access it can be on byte on D0-D7

with LDS assertion or an D8-D15 with UDS assertion.

Figure 20 and Figure 21 show the read and write flow chart.

Figure 20. Read Cycle Flow Chart

Table 11. Description of LCU Status Register

Bit Function Comments

Bit 15, 13, 11 FIFO channel 3, 2, 1 empty 0: FIFO not empty

1: FIFO empty

Bit 14, 12, 10 End of transmission on channel 3, 2,

10: Tr ansmission occurs

1: No transmission actually

Bit 8 RX wrong parity. This feature is

available only if self-test register bit 0

is set to 1. This bit must be reset to 0

by user when needed.

0: No wrong parity received

1: At least one receiver has received a message with wrong

parity (set by hardw are).

Bit 7, 6, 5, 4, 3, 2, 1, 0 Receiving channe l 8, 7, 6, 5, 4, 3, 2 , 1 0: Waiting for mes sa ge

1: Received c orrect message

26 TS68C429A 2120A–HIREL–08/02

Figure 21. Write Cycle Flow Chart

Interrupt Control Unit (ICU) •Daisy Chain

The ICU is compos ed of 2 interrup t blocks with a dais y chain capabilit y (transm itter and

receiver blocks). The daisy chain allows more than one circuit to be connected on the

same in terrupt lin e. Figure 22 s hows the use of a dai sy chain. IRQ xx, IACKxx , IEIxx,

IEOxx must be understood as generic signals. They are IRQTX, IACKTX, IEITX, IEOTX

for the transmitter block and IRQRX, IACKRX, IEIRX, IEORX for the receiver block.

If IEIxx = 0, no higher device have an interrupt pending on the same line so the interrupt

is requested and the IEOxx is forced high to dis able lowest devices to generate inte r-

rupt. If IEIx x = 1, it waits for the c ondition IEIx x = 0. When IEIxx is tied high, IEO xx is

forced hig h.

The dais y chains can be used to progr am a priority be tween receiv ers and tra nsmitters

interrupts when only one interrupt level is needed. An example is given in “Microproces-

sor Interface” on page 33.

TS68C429A

2120A–HIREL–08/02

Figure 22. Interrupt Control Unit Daisy Chain Use

•Vectored Interrupt

They are 15 poss ibilities to generate an i nterrupt and two lines to ha ndle them. To be

more efficient, a unique vector number for each cause is given to the microprocessor as

an answer to an IRQ. Figure 23 shows the interrupt acknowledge sequence flow chart.

Figure 23. Interrupt Acknowledge Sequence Flow Chart

28 TS68C429A 2120A–HIREL–08/02

•Register Description

Any internal status change that induces a bit to be set in the status-register will generate

an interrup t if thi s c ause is ena ble d by the Mas k-register and if no hi ghe st pri ority ca use

is already activated or pending.

For the receiver blocks, the priority is programmable (see interrupt vector number

description). For the transmitter block, the End-of-transmission has higher priority than

FIFO-empty and channel 1 has higher priority than channel 2 that has higher priority

than channel 3.

The RX wrong parity bit can be set only if self-test register bit 0 is set to 1.

The user has to check which receiver has it receiver control register bit 7 set to 1.

At the end of the interrupt procedure, the user must reset RX wrong parity bit to 0.

RX wrong parity is the highest interrupt priority source for the receiver part of the MRT.

•The Mask Register

The mas k regi st er is acc ess ibl e for r ead ing and wr it ing oper a tion s. The mas k reg ister is

used to disable interrupt source. The bit order is the same as in the status register. A “0”

indicates that this source is disable, a “1” enables an interrupt for this source.

Figure 24. Mask Register

•The Base Register

The base register is only accessible for writing operations by the user. The base register

must be progr ammed at the init ializati on ph ase. It conta ins the base for the v ector gen-

eration during an interrupt acknowle dge. This allo ws the use of seve ral peripherals. If

not programmed interrupt vector is set to $OF.

TS68C429A

2120A–HIREL–08/02

Figure 25. Base Regis ter

•The Interrupt Vector Number

Durin g a n in terr upt ackn owle dge cycl e, a n 8- bit vecto r n umber is pres ent ed to th e mic ro-

processor on D0-D7 lines. This vector number corresponds to the interrupt source

requesting service. The format of this number is given below.

Figure 26.

Self-test Descriptio n A self-test has bee n implemented for th e receiver control l abel matrix RAM and the

transmi tter FIF O. T his te st can be u sed to gua ran tee t he g ood behav ior of th e di fferen t

MRT’s mem ories .

30 TS68C429A 2120A–HIREL–08/02

The self-t est reg ister can be split in three par ts :

1. bit 0: Used to enable receiver wrong parity detection. This bit has been imple-

mented to guarantee compatibility with previous designs:

0: Receiver wrong parity detection disable,

1: Receiver wrong parity detection enable.

2. Self-test command:

bit 5: Receiver test clock mode:

0: If CLK-SYS is less or equal to 10 MHz,

1: If CLK-SYS is higher than 10 MHz.

bit 6: Star t transmit ter self-tes t if a 0 to 1 transitio n is programm ed (before a new

self-test, the user must reprogram this bit to 0).

bit 7: Start receiver Label Control Matrix self-test if a 0 to 1 transition is programmed

(before a new self-test, the user must reprogram this bit to 0).

3. Self-test result:

bit 8: 0: Transmitter 1 self-test is running,

1: End of Transmitter 1 self-test.

bit 9: 0: Transmitter 2 self-test is running,

1: End of Transmitter 2 self-test.

bit 10: 0: Transmitter 3 self-test is running,

1: End of Transmitter 3 self-test.

bit 11: Result of Transmitter 1 self-test:

0: (if bit 8 is set to 1) self-test pass,

1: Self-test fail.

bit 12: Request of Transmitter 2 self-test:

0: (if bit 9 is set to 1) self-test pass,

TS68C429A

2120A–HIREL–08/02

1: Self-test fail.

bit 13: Result of Transmitter 3 self-test:

0: (if bit 10 is set to 1) self-test pass,

1: Self-test fail.

bit 14: 0: Receiver Label Control Matrix self-test is running,

1: End of receiver Label Control Matrix self-test.

bit 15: Result of receiver LCM self-test:

0: (if bit 14 is set to 1) self-test pass,

1: Self-test fail.

Self -t e s t U se The self-test destroys the content of the tested memory. So, it could be used after sys-

tem re set, duri ng system init ializa tion. Only one self-t est (trans mitters and rec eivers)

can be pe r formed after a res et . If t he s el f- tes t m ust be rest ar ted, the re se t m ust be ac ti-

vated (then released) before the new self-test start.

To program the self-test:

1. If the receiver self-test will be used:

set to 1 LCMWE bits (for all receivers).

2. If receiver self-test will be used and CLK-SYS is > 10 MHz:

set to self-test register bit 5.

3. Start s elf-test:

set to 1 self-test register bit 6 for Transmitter test,

set to 1 self-test register bit 7 for Receiver RAM test.

At this point, self-test is running. The test duration is:

710 CLK-SYS periods for Transmitter self-test,

2820 CLK-SYS periods for Receiver RAM test if self-test register bit 5 is 0,

5640 CLK-SYS periods for Receiver RAM test if self-test register bit 5 is 1.

To read the self-test result, the user must:

1. poll the self-test register and wait for an end of test set to 1 (bits 8 to 10, bit 14)

then,

2. read the self-test register again to have a valid result on bits 11, 12, 13, 15

according to the tests which end at point 1.

Memory MAP

Address Access Register

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Rece iving channel 1

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Rece iving channel 2

32 TS68C429A 2120A–HIREL–08/02

MRT address 2CH to 3FH and 44H to FFH do not generate DTACK signal (illegal

address).

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Rece iving channel 3

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Rece iving channel 4

10H

11H

12H

13H

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Rece iving channel 5

14H

15H

16H

17H

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Rece iving channel 6

18H

19H

1AH

1BH

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Rece iving channel 7

1CH

1DH

1EH

1FH

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Rece iving channel 8

20H

21H

22H

23H

R/W

Transmit-control-register

Frequency-register

Messag e-FIFO MSW

Message-FIF O LSW

Transmission channel 1

24H

25H

26H

27H

R/W

Transmit-control-register

Frequency-register

Messag e-FIFO MSW

Message-FIF O LSW

Transmission channel 2

28H

29H

2AH

2BH

R/W

Transmit-control-register

Frequency-register

Messag e-FIFO MSW

Message-FIF O LSW

Transmission channel 3

40H R/W Status-register

41H

42H

43H

R/W

Mask-register

Base-register

Self-test register

100H to 1FFH R/W Label-control-matrix Receiving channels 1-8

Memory MAP (Continued)

Address Access Register

TS68C429A

2120A–HIREL–08/02

Application Notes (for additional details order the AN 68C429A)

Microproces sor Inte rfac e

Figure 28. Typical Interface with TS68000

(*) This kind of application can also work with an independant clk

34 TS68C429A 2120A–HIREL–08/02

Figure 29. Typical Interface with 68020/CPU 32 Core Microcontrollers

TS68C429A

2120A–HIREL–08/02

Figure 30. Typical Interface with 68302

In this example, receiver interrupts have a higher priority than transmitter interrupts.

36 TS68C429A 2120A–HIREL–08/02

Programs Flow-chart

Figure 31. Initialization after Reset Flow-chart

TS68C429A

2120A–HIREL–08/02

Figure 32. Receiver without Interrupt Flow-chart

Figure 33. Receiver with Interrupt Flow-chart

IT START

Read "MSW"

Read "LSW"

IT END

38 TS68C429A 2120A–HIREL–08/02

Figure 34. Transmitter without Interrupt Flow-chart

Figure 35. Transmitter with Interrupt Flow-chart

TS68C429A

2120A–HIREL–08/02

Figure 36. First FIFO Access

Preparation for

Delivery

Packaging Microcircuits are prepared for delivery in accordance with MIL-I-38535 or DESC.

Certific ate of Compl iance Atme l offers a cer tificate of compli ance with each shipment of parts, affi rming the pr od-

ucts are in compliance either with MIL-STD-883 or DESC and guaranteeing the

parameters not tested at temperature extremes for the entire temperature range.

Handling MOS devices must be handled with certain precautions to avoid damage due to accu-

mulation of static charge. Input protection devices have been designed in the chip to

minimize the effect of this static buildup. However, the following handling practices are

recommended:

• Devices should be handled on benches with conductive and grounded surfaces.

• Ground test equipment, tools and operator.

• Do not handle devices by the leads.

• Store devices in conductive foam or carriers.

• Avoid use of plastic, rubber, or silk in MOS areas.

• Maintain relative humidity above 50 percent if practical.

40 TS68C429A 2120A–HIREL–08/02

Package Mechanical

Data

PGA 84

CQFP 132

TS68C429A

2120A–HIREL–08/02

Terminal

Connections

84-lead PGA Assignment

132-lead CQFP

Assignment

42 TS68C429A 2120A–HIREL–08/02

Ordering Information

Standard Product

Atmel Part Number Norms Package Temperature Range

Tc (°C) Detailed Qualification

TS68C429AMR Atmel Standard 84-lead PGA -55/+125 Atmel internal

TS68C429AMF Atmel Standard 132-lead CQFP -55/+125 Atmel internal

TS68C429AVR Atmel Standard 84-lead PGA -40/+85 Atmel internal

TS68C429AVF Atmel Standard 132-lead CQFP -40/+85 Atmel internal

HI-REL Products

Atmel Part Number Norms Package Temperature Range

Tc (°C) Detailed Qualification

TS68C429AMRB /C MIL-STD-883 84-lead P GA -55/+125 Atmel internal

TS68C429AMFB /C MIL-STD -883 132-lead CQFP -55/+125 Atmel internal

TS68C429ADESCxx DESC 84-lead PGA -55/+125 Atmel internal

TS68C429ADESCxx DESC 132-lead CQFP -55/+125 Atmel internal

TS68C429A M R 1 B/C

Part number

Temperature range:

M: -55°C/+125°C

V: -40°C/+85°C

Package:

R = PGA 84

F = CQFP132

Screening:

B/C = MIL-STD-883 Class B

- = internal

Lead finish

1: Hot solder dip

-: Gold

Printed on recycled paper.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Term s and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this docum ent, reserves the right to change devices or specifications detailed herein at any time w ithout notice, and does

not make any commitment to update t he information contained herein. No licenses to patents or other intellectual property of At mel are granted

by the Company in connec tion with the sale of Atmel p roducts, expres sly or by implication. At mel’s pr oduct s are not aut horized for use as crit ical

components in life s upport devic es or syst ems.

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