PIC16C5X EPROM/ROM-Based 8-Bit CMOS Microcontroller Series Pin Diagrams Devices Included in this Data Sheet PIC16C54 PIC16CR54 PIC16C55 PIC16C56 PIC16C57 PDIP, SOIC, Windowed CERDIP High-Performance RISC CPU Features * Only 33 single word instructions to learn * All instructions are single cycle (200 ns) except for program branches which are two-cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle Device PIC16C54 18 18 28 18 28 I/O 12 12 20 12 20 EPROM/ ROM RAM 512 512 25 25 512 1K 2K 24 25 72 * 12-bit wide instructions * 8-bit wide data path * Seven or eight special function hardware registers * Two-level deep hardware stack * Direct, indirect and relative addressing modes for data and instructions Peripheral Features * 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler * Power-On Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Selectable oscillator options: - RC: Low-cost RC oscillator - XT: Standard crystal/resonator - HS: High-speed crystal/resonator - LP: Power saving, low frequency crystal *1 18 RA1 RA3 2 17 RA0 T0CKI 3 16 OSC1/CLKIN MCLR/VPP 4 15 OSC2/CLKOUT VSS 5 14 VDD RB0 6 13 RB7 RB1 7 12 RB6 RB2 8 11 RB5 RB3 9 10 RB4 PDIP, SOIC, Windowed CERDIP *1 28 MCLR/VPP VDD 2 27 OSC1/CLKIN N/C 3 26 OSC2/CLKOUT VSS 4 25 RC7 N/C 5 24 RC6 RA0 6 23 RC5 RA1 7 22 RC4 RA2 8 21 RC3 RA3 9 20 RC2 RB0 10 19 RC1 RB1 11 18 RC0 RB2 12 17 RB7 RB3 13 16 RB6 RB4 14 15 RB5 T0CKI PIC16C55 PIC16C57 PIC16CR54 PIC16C55 PIC16C56 PIC16C57 Pins RA2 PIC16C54 PIC16CR54 PIC16C56 * * * * * CMOS Technology * Low-power, high-speed CMOS EPROM/ROM technology * Fully static design * Wide-operating voltage range: - EPROM Commercial/Industrial 2.5V to 6.25V - ROM Commercial/Industrial 2.0V to 6.25V - EPROM/ROM Automotive 2.5V to 6.0V * Low-power consumption - < 2 mA typical @ 5.0V, 4 MHz - 15 A typical @ 3.0V, 32 kHz - < 3 A typical standby current (with WDT disabled) @ 3.0V, 0C to 70C The PIC16CR54 is not recommended for new designs. The PIC16CR54A is recommended, as found in the Enhanced PIC16C5X data sheet. 1995 Microchip Technology Inc. DS30015M-page 1 This document was created with FrameMaker 4 0 4 PIC16C5X Pin Diagrams (con't) SSOP 20 19 18 17 16 15 14 13 12 11 RA1 RA0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4 VSS T0CKI VDD VDD RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 VSS *1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16C55 PIC16C57 *1 2 3 4 5 6 7 8 9 10 PIC16C54 PIC16CR54 PIC16C56 RA2 RA3 T0CKI MCLR/VPP VSS VSS RB0 RB1 RB2 RB3 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/VPP OSC1/CLKIN OSC2/CLKOUT RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 RB7 RB6 RB5 Table of Contents 1.0 General Description .............................................................................................................................................3 2.0 PIC16C5X Device Varieties.................................................................................................................................5 3.0 Architectural Overview.........................................................................................................................................7 4.0 Memory Organization ........................................................................................................................................13 5.0 I/O Ports.............................................................................................................................................................21 6.0 Timer0 Module and TMR0 Register...................................................................................................................23 7.0 Special Features of the CPU .............................................................................................................................27 8.0 Instruction Set Summary ...................................................................................................................................39 9.0 Development Support ........................................................................................................................................51 10.0 Electrical Characteristics - PIC16C54/55/56/57.................................................................................................57 11.0 DC and AC Characteristics - PIC16C54/55/56/57 .............................................................................................71 12.0 Electrical Characteristics - PIC16CR54 .............................................................................................................79 13.0 DC and AC Characteristics - PIC16CR54 .........................................................................................................91 14.0 Packaging Information .....................................................................................................................................101 Appendix A: Compatibility................................................................................................................................115 Appendix B: What's New .................................................................................................................................115 Appendix C: What's Changed..........................................................................................................................116 Appendix D: PIC16/17 Microcontrollers...........................................................................................................117 Index ................................................................................................................................................................125 List of Examples ..............................................................................................................................................126 List of Figures ..................................................................................................................................................126 List of Tables ...................................................................................................................................................127 Connecting to Microchip BBS ..........................................................................................................................129 Access to the Internet ......................................................................................................................................129 Reader Response............................................................................................................................................130 PIC16C54/55/56/57 Product Identification System..........................................................................................131 PIC16CR54 Product Identification System ......................................................................................................131 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. To assist you in the use of this document, Appendix B contains a list of new information in this data sheet, while Appendix C contains information that has changed DS30015M-page 2 1995 Microchip Technology Inc. PIC16C5X 1.0 GENERAL DESCRIPTION The PIC16C5X from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EPROM/ROM-based CMOS microcontrollers. This family is pin and software compatible with the Enhanced PIC16C5X family of devices. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (200 ns) except for program branches which take two cycles. The PIC16C5X delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The PIC16C5X products are equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost-saving RC oscillator. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability. 1.1 Applications The PIC16C5X series fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. The EPROM technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through- hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the PIC16C5X series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of "glue" logic in larger systems, coprocessor applications). The UV erasable CERDIP packaged versions are ideal for code development, while the cost effective One Time Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in OTP microcontrollers while benefiting from the OTP's flexibility. The PIC16C5X products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a `C' compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM PC-AT and compatible machines. 1995 Microchip Technology Inc. DS30015M-page 3 This document was created with FrameMaker 4 0 4 PIC16C5X TABLE 1-1: PIC16C5X FAMILY OF DEVICES Memory Peripherals Features PIC16C54 og Da ta 20 512 20 512 -- 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP 20 -- 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP PIC16CR54A 20 -- 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP PIC16CR54B(1) 20 -- 512 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP PIC16C55 20 512 -- 24 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP PIC16C56 20 1K -- 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP PIC16CR56(1) 20 -- 1K 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP PIC16C57 20 2K -- 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP PIC16CR57A 20 -- 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP PIC16CR57B(1) 20 -- 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP PIC16C58A 20 2K -- 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP PIC16CR58A 20 -- 2K 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP PIC16CR58B(1) 20 -- 2K 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP PIC16C54A PIC16CR54 (2) -- RA M RO RO M M EP M ax im um Fr eq ue nc y Pr of O pe ra tio n (M H z) ra (w m M M o e rd m em s) o or Ti ry y m (b er y M te od s) ul e( s I/O ) Pi ns Vo lta ge Ra ng Nu e m (V be ol ro ts ) fI ns tru Pa ct io ck ns ag es Clock 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP Legend: Grayed boxes: Devices NOT covered in this data sheet All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. Note 1: Please contact your local sales office for availability of these devices. 2: Not recommended for new designs. DS30015M-page 4 1995 Microchip Technology Inc. PIC16C5X 2.0 PIC16C5X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16C5X Product Identification System at the back of this data sheet to specify the correct part number. For the PIC16C5X family of devices, there are two device types, as indicated in the device number: 1. 2. 2.1 C, as in PIC16C54. These devices have EPROM program memory and operate over the standard voltage range. CR, as in PIC16CR54. These devices have ROM program memory and operate over the standard voltage range. UV Erasable Devices The UV erasable versions, offered in CERDIP packages, are optimal for prototype development and pilot programs. UV erasable devices can be programmed for any of the four oscillator configurations. Microchip's PICSTART and PRO MATE programmers both support programming of the PIC16C5X. Third party programmers also are available; refer to the Third Party Guide for a list of sources. 2.2 One-Time-Programmable (OTP) Devices 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration bit options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround-Production (SQTP) Devices Microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry code, password or ID number. 2.5 Read Only Memory (ROM) Devices Microchip offers masked ROM versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products. The availability of OTP devices is especially useful for customers expecting frequent code changes and updates. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must be programmed. 1995 Microchip Technology Inc. DS30015M-page 5 This document was created with FrameMaker 4 0 4 PIC16C5X NOTES: DS30015M-page 6 1995 Microchip Technology Inc. PIC16C5X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C5X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C5X uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200 ns @ 20 MHz) except for program branches. The PIC16C54/CR54/C55 address 512 x 12 program memory, the PIC16C56 addresses 1K x 12, and the PIC16C57 addresses 2K x 12 of program memory. All program memory is internal. The PIC16C5X can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC16C5X has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16C5X simple yet efficient. In addition, the learning curve is reduced significantly. The PIC16C5X device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1 and Table 3-2. 1995 Microchip Technology Inc. DS30015M-page 7 This document was created with FrameMaker 4 0 4 PIC16C5X FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM 9-11 9-11 EPROM/ROM 512 X 12 TO 2048 X 12 T0CKI PIN STACK 1 CONFIGURATION WORD STACK 2 "DISABLE" "OSC SELECT" PC WATCHDOG TIMER 12 "CODE PROTECT" 2 OSCILLATOR/ TIMING & CONTROL INSTRUCTION REGISTER WDT TIME OUT 9 12 OSC1 OSC2 MCLR CLKOUT WDT/TMR0 PRESCALER 8 "SLEEP" INSTRUCTION DECODER 6 "OPTION" OPTION REG. DIRECT ADDRESS DIRECT RAM ADDRESS FROM W 5 5-7 LITERALS 8 STATUS TMR0 W FSR 8 8 DATA BUS ALU FROM W FROM W 4 4 "TRIS 5" 8 "TRIS 6" TRISA PORTA 4 RA3:RA0 DS30015M-page 8 GENERAL PURPOSE REGISTER FILE (SRAM) 24, 25 or 72 Bytes TRISB FROM W 8 PORTB 8 RB7:RB0 8 "TRIS 7" TRISC 8 PORTC 8 RC7:RC0 (28 Pin Devices Only) 1995 Microchip Technology Inc. PIC16C5X TABLE 3-1: PIC16C54/CR54/C56 PINOUT DESCRIPTION Name DIP, SOIC No. SSOP No. I/O/P Type Input Levels RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 T0CKI 17 18 1 2 6 7 8 9 10 11 12 13 3 19 20 1 2 7 8 9 10 11 12 13 14 3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL ST MCLR/VPP 4 4 I ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD to avoid unintended entering of programming mode. OSC1/CLKIN 16 18 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 17 O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. VDD 14 15,16 P -- Positive supply for logic and I/O pins. VSS 5 5,6 P -- Ground reference for logic and I/O pins. Description Bi-directional I/O port Bi-directional I/O port Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input 1995 Microchip Technology Inc. DS30015M-page 9 PIC16C5X TABLE 3-2: PIC16C55/C57 PINOUT DESCRIPTION Name DIP, SOIC No. SSOP No. I/O/P Type Input Levels RA0 RA1 RA2 RA3 6 7 8 9 5 6 7 8 I/O I/O I/O I/O TTL TTL TTL TTL Bi-directional I/O port RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 10 11 12 13 14 15 16 17 9 10 11 12 13 15 16 17 I/O I/O I/O I/O I/O I/O I/O I/O TTL TTL TTL TTL TTL TTL TTL TTL Bi-directional I/O port RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 18 19 20 21 22 23 24 25 18 19 20 21 22 23 24 25 I/O I/O I/O I/O I/O I/O I/O I/O TTL TTL TTL TTL TTL TTL TTL TTL Bi-directional I/O port T0CKI 1 2 I ST Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP 28 28 I ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD to avoid unintended entering of programming mode. OSC1/CLKIN 27 27 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 26 26 O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. VDD 2 3,4 P -- Positive supply for logic and I/O pins. VSS 4 1,14 P -- Ground reference for logic and I/O pins. N/C 3,5 -- -- -- Unused, do not connect Description Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input DS30015M-page 10 1995 Microchip Technology Inc. PIC16C5X Clocking Scheme/Instruction Cycle 3.1 3.2 The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1. Instruction Flow/Pipelining An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase clock Q3 Q4 PC PC OSC2/CLKOUT (RC mode) EXAMPLE 3-1: PC+1 Fetch INST (PC) Execute INST (PC-1) PC+2 Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) INSTRUCTION PIPELINE FLOW 1. MOVLW 55h 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA, BIT3 Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. 1995 Microchip Technology Inc. DS30015M-page 11 PIC16C5X NOTES: DS30015M-page 12 1995 Microchip Technology Inc. PIC16C5X 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization FIGURE 4-3: The PIC16C54, PIC16CR54 and PIC16C55 have a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space (Figure 4-1). The PIC16C56 has a 10-bit program counter capable of addressing a 1K x 12 program memory space (Figure 4-2). The PIC16C57 has an 11-bit program counter capable of addressing a 2K x 12 program memory space (Figure 4-3). Accessing a location above the physically implemented address will cause a wraparound. PC<10:0> 11 CALL, RETLW Stack Level 1 Stack Level 2 000h On-chip Program Memory (Page 0) 0FFh 100h 1FFh 200h User Memory Space The reset vector for the PIC16C54/CR54/C55 is at 1FFh, at 3FFh for the PIC16C56, and at 7FFh for the PIC16C57. FIGURE 4-1: PIC16C57 PROGRAM MEMORY MAP AND STACK PIC16C54/CR54/C55 PROGRAM MEMORY MAP AND STACK On-chip Program Memory (Page 1) 2FFh 300h 3FFh 400h On-chip Program Memory (Page 2) 4FFh 500h PC<8:0> 5FFh 600h 9 CALL, RETLW On-chip Program Memory (Page 3) Stack Level 1 Stack Level 2 6FFh 700h Reset Vector 7FFh User Memory Space 000h FIGURE 4-2: On-chip Program Memory 0FFh 100h Reset Vector 1FFh PIC16C56 PROGRAM MEMORY MAP AND STACK PC<9:0> 10 CALL, RETLW User Memory Space 000h 0FFh 100h 1FFh 200h On-chip Program Memory (Page 1) Reset Vector Data Memory Organization Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers. The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. Stack Level 1 Stack Level 2 On-chip Program Memory (Page 0) 4.2 2FFh 300h 3FFh For the PIC16C54, PIC16CR54 and PIC16C56, the register file is composed of seven special function registers and 25 general purpose registers (Figure 4-4). For the PIC16C55, the register file is composed of eight special function registers and 24 general purpose registers (Figure 4-5). For the PIC16C57, up to 48 additional general purpose registers may be addressed using a banking scheme (Figure 4-6). 4.2.1 GENERAL PURPOSE REGISTER FILE The register file is accessed either directly or indirectly through the file select register FSR (Section 4.7). 1995 Microchip Technology Inc. DS30015M-page 13 This document was created with FrameMaker 4 0 4 PIC16C5X FIGURE 4-4: PIC16C54/CR54/C56 REGISTER FILE MAP FIGURE 4-5: File Address PIC16C55 REGISTER FILE MAP File Address 00h INDF(1) 00h INDF(1) 01h TMR0 01h TMR0 02h PCL 02h PCL 03h STATUS 03h STATUS 04h FSR 04h FSR 05h PORTA 05h PORTA 06h PORTB 06h PORTB 07h PORTC 07h 08h General Purpose Registers 0Fh 10h 1Fh 1Fh Note 1: Not a physical register. See Section 4.7 FIGURE 4-6: General Purpose Registers 0Fh 10h Note 1: Not a physical register. See Section 4.7 PIC16C57 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 01h TMR0 02h PCL 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h PORTC 08h General Purpose Register 0Fh 10h General Purpose Registers 1Fh Bank 0 40h 20h 60h Addresses map back to addresses in Bank 0. 2Fh 30h General Purpose Registers 4Fh 50h 3Fh 5Fh Bank 1 6Fh 70h General Purpose Registers General Purpose Registers 7Fh Bank 2 Bank 3 Note 1: Not a physical register. See Section 4.7 DS30015M-page 14 1995 Microchip Technology Inc. PIC16C5X 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). TABLE 4-1: Address The special registers can be classified into two sets. The special function registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on MCLR and WDT Reset N/A TRIS I/O control registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 --11 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111 03h STATUS 0001 1xxx 000q quuu 04h FSR 1xxx xxxx 1uuu uuuu 05h PORTA -- -- -- -- RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 06h (2) 07h PA2 PA1 PA0 TO PD Z DC C Indirect data memory address pointer Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5 for an explanation of how to access these bits. 2: File address 07h is a general purpose register on the PIC16C54/CR54/C56. 1995 Microchip Technology Inc. DS30015M-page 15 PIC16C5X 4.3 STATUS Register This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bits for program memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. FIGURE 4-7: R/W-0 PA2 bit7 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect STATUS bits, see Table 8-2, Instruction Set Summary. STATUS REGISTER (ADDRESS:03h) R/W-0 PA1 6 R/W-0 PA0 5 R-1 TO 4 R-1 PD 3 R/W-x Z 2 R/W-x DC 1 R/W-x C bit0 R = Readable bit W = Writable bit - n = Value at POR reset bit 7: PA2: This bit unused at this time. Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. bit 6-5: PA1:PA0: Program page preselect bits (PIC16C56 and PIC16C57 only) 00 = Page 0 (000h - 1FFh) - PIC16C56 and PIC16C57 01 = Page 1 (200h - 3FFh) - PIC16C56 and PIC16C57 10 = Page 2 (400h - 5FFh) - PIC16C57 11 = Page 3 (600h - 7FFh) - PIC16C57 Each page is 512 bytes. Using the PA1:PA0 bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF 1 = A carry occurred 1 = A borrow did not occur 0 = A carry did not occur 0 = A borrow occurred DS30015M-page 16 RRF or RLF Load bit with LSb or MSb 1995 Microchip Technology Inc. PIC16C5X 4.4 OPTION Register The OPTION register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<5:0> bits. FIGURE 4-8: U-0 -- bit7 OPTION REGISTER U-0 -- 6 W-1 T0CS 5 W-1 T0SE 4 W-1 PSA 3 W-1 PS2 2 bit 7-6: Unimplemented. bit 5: T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1995 Microchip Technology Inc. W-1 PS1 1 W-1 PS0 bit0 W = Writable bit U = Unimplemented bit - n = Value at POR reset DS30015M-page 17 PIC16C5X 4.5 Program Counter As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> (Figure 4-9, Figure 4-10 and Figure 4-11). For the PIC16C56 and PIC16C57, a page number must be supplied as well. Bit5 of the STATUS register provides this to bit9 of the PC for the PIC16C56 (Figure 4-10). Bit5 and bit6 of the STATUS register provide page information to bit9 and bit10 of the PC for the PIC16C57 (Figure 4-11). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-9, Figure 4-10 and Figure 4-11). Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5. For the PIC16C56 and PIC16C57, a page number again must be supplied. Bit5 of the STATUS register provides this to bit9 of the PC for the PIC16C56 (Figure 4-10). Bit5 and bit6 of the STATUS register provide page information to bit9 and bit10 of the PC for the PIC16C57 (Figure 4-11). Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). FIGURE 4-9: FIGURE 4-10: LOADING OF PC BRANCH INSTRUCTIONS - PIC16C56 GOTO Instruction 9 8 7 0 PC PCL Instruction Word PA0 7 0 STATUS CALL or Modify PCL Instruction 9 8 7 0 PC PCL Instruction Word Reset to '0' PA0 7 0 STATUS FIGURE 4-11: LOADING OF PC BRANCH INSTRUCTIONS PIC16C57 GOTO Instruction 10 9 8 7 0 PC PCL Instruction Word 2 LOADING OF PC BRANCH INSTRUCTIONS PIC16C54/CR54/C55 PA1:PA0 7 0 STATUS GOTO Instruction 8 7 0 CALL or Modify PCL Instruction PCL PC 10 9 8 7 0 PC PCL Instruction Word Instruction Word CALL or Modify PCL Instruction 8 7 PC 0 PCL 2 Reset to `0' PA1:PA0 7 0 STATUS Reset to '0' DS30015M-page 18 Instruction Word 1995 Microchip Technology Inc. PIC16C5X For the RETLW instruction, the PC is loaded with the Top Of Stack (TOS) contents. All of the devices covered in this data sheet have only two stacks. Each stack has the same bit width as the device PC. 4.5.1 PAGING CONSIDERATIONS - PIC16C56/57 If the Program Counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. However, the page preselect bits in the STATUS register will not be updated. Therefore, the next GOTO, CALL, or Modify PCL instruction will return the program to the page specified by the page preselect bits (PA0 or PA1:PA0). For example, a NOP at location 1FFh (page 0) increments the PC to 200h (page 1). A GOTO xxx at 200h will return the program to address xxxh on page 0 (assuming that PA1:PA0 are clear). To prevent this, the page preselect bits must be updated under program control. 4.5.2 4.6 Stack PIC16C5X devices have a 9-bit, 10-bit or 11-bit wide, two-level hardware push/pop stack (Figure 4-1, Figure 4-2 and Figure 4-3 respectively). A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL's are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW's are executed, the stack will be filled with the address previously stored in level 2. Note: The W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. EFFECTS OF RESET The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page (i.e., the reset vector). The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is pre-selected. Therefore, upon a RESET, a GOTO instruction at the reset vector location will automatically cause the program to jump to page 0. If an inadequate RESET occurs (i.e., POR conditions are not met, a brown-out occurs, etc.), page preselect bits in the STATUS register will not be cleared. Therefore, it is good programming practice to include the following code before the GOTO instruction at the reset vector location: BSF STATUS BSF FSR 1995 Microchip Technology Inc. DS30015M-page 19 PIC16C5X 4.7 Indirect Data Addressing; INDF and FSR Registers EXAMPLE 4-2: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. EXAMPLE 4-1: movlw movwf clrf incf btfsc goto NEXT INDIRECT ADDRESSING * * * * Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 06) * A read of the INDR register now will return the value of 0Ah. HOW TO CLEAR RAM USING INDIRECT ADDRESSING 0x10 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next CONTINUE : ;YES, continue The FSR is either a 5-bit (PIC16C54/CR54/C55/C56) or 7-bit (PIC16C57) wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The last two bits, FSR<6:5>, are also used on the PIC16C57 for direct addressing (Figure 4-12). Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. PIC16C54/CR54/C55/C56: Do not use banking. FSR<6:5> are unimplemented and read as '1's. A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2. PIC16C57: FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = bank 0, 01 = bank 1, 10 = bank 2, 11 = bank 3). FIGURE 4-12: DIRECT/INDIRECT ADDRESSING Direct Addressing (FSR) 6 5 4 bank select location select Indirect Addressing (opcode) 0 6 5 4 bank 00 01 10 (FSR) 0 location select 11 00h Addresses map back to addresses in Bank 0. Data Memory(1) 0Fh 10h 1Fh Bank 0 3Fh Bank 1 5Fh Bank 2 7Fh Bank 3 Note 1: For register map detail see Section 4.2. DS30015M-page 20 1995 Microchip Technology Inc. PIC16C5X 5.0 I/O PORTS 5.5 As with any other register, the I/O registers can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin's input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers (TRISA, TRISB, TRISC) are all set. 5.1 PORTA PORTA is a 4-bit I/O register. Only the low order 4 bits are used (RA3:RA0). Bits 7-4 are unimplemented and read as '0's. 5.2 The equivalent circuit for an I/O port pin is shown in Figure 5-1. All ports may be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB, TRISC) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output. FIGURE 5-1: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN PORTB Data Bus PORTB is an 8-bit I/O register (PORTB<7:0>). 5.3 I/O Interfacing D PORTC WR Port PIC16C55/C57: 8-bit I/O register. Q Data Latch CK VDD Q P PIC16C54/CR54/C56: General purpose register. 5.4 W Reg TRIS Registers D TRIS `f' I/O pin(1) Q TRIS Latch The output driver control registers are loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. Note: N CK VSS Q Reset A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. RD Port Note 1: I/O pins have protection diodes to VDD and VSS. The TRIS registers are "write-only" and are set (output drivers disabled) upon RESET. TABLE 5-1: Address SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I/O control registers (TRISA, TRISB, TRISC) Value on Power-On Reset Value on MCLR and WDT Reset 1111 1111 1111 1111 N/A TRIS 05h PORTA -- -- -- -- RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h(1) PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu Legend: Shaded boxes = unimplemented, read as `0', - = unimplemented, read as '0', x = unknown, u = unchanged Note 1: File address 07h is a general purpose register on the PIC16C54/CR54/C56. 1995 Microchip Technology Inc. DS30015M-page 21 This document was created with FrameMaker 4 0 4 PIC16C5X 5.6 I/O Programming Considerations 5.6.1 BI-DIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip. FIGURE 5-2: EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT ;Initial PORT Settings ; PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- ---------BCF PORTB, 7 ;01pp pppp 11pp pppp BCF PORTB, 6 ;10pp pppp 11pp pppp MOVLW 03Fh ; TRIS PORTB ;10pp pppp 10pp pppp ; ;Note that the user may have expected the pin ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High). 5.6.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched MOVWF PORTB PC + 1 MOVF PORTB,W PC + 2 PC + 3 NOP NOP RB7:RB0 Port pin written here Instruction executed DS30015M-page 22 MOVWF PORTB (Write to PORTB) Port pin sampled here MOVF PORTB,W (Read PORTB) This example shows a write to PORTB followed by a read from PORTB. Data setup time = (0.25 TCY - TPD) where: TCY = instruction cycle. TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic. NOP 1995 Microchip Technology Inc. PIC16C5X 6.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1. The Timer0 module has the following features: * 8-bit timer/counter register, TMR0 - Readable and writable * 8-bit software programmable prescaler * Internal or external clock select - Edge select for external clock The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler. Figure 6-1 is a simplified block diagram of the Timer0 module, while Figure 6-2 shows the electrical structure of the Timer0 input. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-3 and Figure 6-4). The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 6-1: A summary of registers associated with the Timer0 module is found in Table 6-1. TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 1 1 T0CKI pin Programmable Prescaler(2) T0SE(1) 0 8 Sync with Internal Clocks TMR0 reg PSout (2 cycle delay) Sync 3 T0CS(1) PSA(1) PS2, PS1, PS0(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-6). FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN RIN T0CKI pin (1) VSS N (1) Schmitt Trigger Input Buffer VSS Note 1: ESD protection circuits 1995 Microchip Technology Inc. DS30015M-page 23 This document was created with FrameMaker 4 0 4 PIC16C5X FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch PC PC+1 MOVWF TMR0 T0 Timer0 T0+1 Instruction Executed FIGURE 6-4: PC+3 T0+2 NT0 NT0 Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 PC+4 PC+5 MOVF TMR0,W NT0 NT0+1 Read TMR0 reads NT0 + 1 Read TMR0 reads NT0 PC+6 MOVF TMR0,W NT0+2 Read TMR0 reads NT0 + 2 TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 PC PC+1 MOVWF TMR0 Instruction Fetch Instruction Execute PC+3 PC+4 PC+5 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 PC+6 MOVF TMR0,W NT0+1 NT0 Write TMR0 executed TABLE 6-1: PC+2 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W T0+1 T0 Timer0 Address PC+2 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 T0 Read TMR0 reads NT0 + 1 REGISTERS ASSOCIATED WITH TIMER0 Name 01 TMR0 N/A OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 - 8-bit real-time clock/counter -- -- T0CS T0SE PSA Value on Power-On Reset Value on MCLR and WDT Reset xxxx xxxx uuuu uuuu PS2 PS1 PS0 --11 1111 --11 1111 Legend: Shaded cells: Unimplemented bits, - = unimplemented, x = unknown, u = unchanged, DS30015M-page 24 1995 Microchip Technology Inc. PIC16C5X Using Timer0 with an External Clock 6.1 When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. FIGURE 6-5: 6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing. TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Prescaler Output (2) Q1 Q2 Q3 Q4 Small pulse misses sampling (1) External Clock/Prescaler Output After Sampling (3) Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 1995 Microchip Technology Inc. DS30015M-page 25 PIC16C5X 6.2 Prescaler following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 6.1.2). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. EXAMPLE 6-1: CLRF TMR0 CLRWDT MOVLW 'xxxx1xxx' OPTION The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. EXAMPLE 6-2: CHANGING PRESCALER (WDTTIMER0) CLRWDT SWITCHING PRESCALER ASSIGNMENT MOVLW 'xxxx0xxx' The prescaler assignment is fully under software control (i.e., it can be changed "on the fly" during program execution). To avoid an unintended device RESET, the FIGURE 6-6: ;Clear TMR0 ;Clears WDT and ;prescaler ;Select new prescale ;value To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's. 6.2.1 CHANGING PRESCALER (TIMER0WDT) ;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source OPTION BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = Fosc/4) Data Bus 0 T0CKI pin 1 8 M U X 1 M U X 0 Sync 2 Cycles TMR0 reg T0SE T0CS 0 Watchdog Timer 1 M U X PSA 8-bit Prescaler 8 8 - to - 1MUX PS2:PS0 PSA WDT Enable bit 1 0 MUX PSA WDT Time-Out Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register. DS30015M-page 26 1995 Microchip Technology Inc. PIC16C5X 7.0 SPECIAL FEATURES OF THE CPU The SLEEP mode is designed to offer a very low current power-down mode. The user can wake up from SLEEP through external reset or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC16C5X family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are: * * * * * * * * 7.1 Configuration Bits The PIC16C5X configuration word consists of 12 bits, 4 of which are implemented. Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit and one bit is the code protection bit (Figure 7-1). Oscillator selection Reset Power-On Reset (POR) Device Reset Timer (DRT) Watchdog Timer (WDT) SLEEP Code protection ID locations OTP, QTP or ROM devices have the oscillator configuration programmed at the factory and these parts are tested accordingly (see "Product Identification System" on the inside back cover). The PIC16C5X has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18 ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. With this timer on-chip, most applications need no external reset circuitry. FIGURE 7-1: CONFIGURATION WORD FOR PIC16C54/CR54/C55/C56/C57 -- -- -- -- -- -- -- -- CP bit11 10 9 8 7 6 5 4 3 WDTE FOSC1 FOSC0 2 1 bit0 Register: Address(1): CONFIG FFFh bit 11-4: Unimplemented: Read as '0'. bit 3: CP: Code protection bit 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Refer to the PIC16C5X Programming Specifications (literature number DS30190) to determine how to access the configuration word. 1995 Microchip Technology Inc. DS30015M-page 27 This document was created with FrameMaker 4 0 4 PIC16C5X 7.2 Oscillator Configurations 7.2.1 OSCILLATOR TYPES TABLE 7-1: The PIC16C5X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes: * * * * LP: XT: HS: RC: 7.2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR / CERAMIC RESONATORS In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 7-2). The PIC16C5X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin (Figure 7-3). FIGURE 7-2: CRYSTAL OPERATION OR CERAMIC RESONATOR (HS, XT OR LP OSC CONFIGURATION) C1(1) OSC1 PIC16C5X SLEEP XTAL RS(2) RF(3) OSC2 To internal logic C2(1) Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen (approx. value = 10 M). FIGURE 7-3: Osc Type CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC16C54/55/56/57 Resonator Freq Cap. Range C1 XT Cap. Range C2 Y R A 455 kHz 68-100 pF 68-100 pF 2.0 MHz 15-33 pF 15-33 pF 4.0 MHz 10-22 pF 10-22 pF HS 8.0 MHz 10-22 pF 10-22 pF 16.0 MHz 10 pF 10 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. PR TABLE 7-2: Osc Type E I M I L N CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC16C54/55/56/57 Resonator Freq Cap.Range C1 Cap. Range C2 32 kHz(1) 15 pF 15 pF 200-300 pF 15-30 pF 100 kHz 100-200 pF 15-30 pF 200 kHz 15-100 pF 15-30 pF 455 kHz 15-30 pF 15-30 pF 1 MHz 15 pF 15 pF 2 MHz 15 pF 15 pF 4 MHz HS 4 MHz 15 pF 15 pF 8 MHz 15 pF 15 pF 20 MHz 15 pF 15 pF Note 1: For VDD > 4.5V, C1 = C2 30pF is recommended. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. LP XT EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 PIC16C5X Clock from ext. system Open DS30015M-page 28 OSC2 1995 Microchip Technology Inc. PIC16C5X TABLE 7-3: Osc Type CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC16CR54 Resonator Freq Cap. Range C1 Cap. Range C2 Data not available at this time. TABLE 7-4: Osc Type CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC16CR54 Resonator Freq Cap.Range C1 Cap. Range C2 32 kHz(1) 15-33 pF 15-33 pF 100 kHz 15-33 pF 15-33 pF 200 kHz 15-30 pF 15-30 pF 68-100 pF 68-100 pF XT 100 kHz 15-30 pF 15-30 pF 200 kHz 15-47 pF 15-47 pF 1 MHz 15-47 pF 15-47 pF 2 MHz 15-47 pF 15-47 pF 4 MHz HS 4 MHz 15-47 pF 15-47 pF 8 MHz 15-47 pF 15-47 pF 20 MHz 15-47 pF 15-47 pF Note 1: For VDD < 2.5V, C1 = C2 15-33pF is recommended. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. LP PR IM L E R A IN Y 7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 7-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. FIGURE 7-4: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To Other Devices PIC16C5X 10k 74AS04 4.7k CLKIN 74AS04 10k XTAL 10k 20 pF 20 pF Figure 7-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region. FIGURE 7-5: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT 330 To Other Devices 330 74AS04 74AS04 PIC16C5X 74AS04 CLKIN 0.1 F XTAL 1995 Microchip Technology Inc. DS30015M-page 29 PIC16C5X 7.2.4 7.3 RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 7-6 shows how the R/C combination is connected to the PIC16C5X. For Rext values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. Reset PIC16C5X devices may be reset in one of the following ways: * * * * * Power-On Reset (POR) MCLR reset (normal operation) MCLR wake-up reset (from SLEEP) WDT reset (normal operation) WDT wake-up reset (from SLEEP) Table 7-5 shows these reset conditions for the PCL and STATUS registers. Some registers are not affected in any reset condition. Their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-On Reset (POR), MCLR or WDT reset. A MCLR or WDT wake-up from SLEEP also results in a device reset, and not a continuation of operation before SLEEP. The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different reset conditions (Section 7.7). These bits may be used to determine the nature of the reset. Table 7-6 lists a full description of reset states of all registers. Figure 7-7 shows a simplified block diagram of the on-chip reset circuit. The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. The oscillator frequency, divided by four, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic. FIGURE 7-6: RC OSCILLATOR MODE VDD Rext OSC1 N Cext Internal clock PIC16C5X VSS Fosc/4 OSC2/CLKOUT DS30015M-page 30 1995 Microchip Technology Inc. PIC16C5X TABLE 7-5: RESET CONDITIONS FOR SPECIAL REGISTERS PCL Addr: 02h Condition STATUS Addr: 03h 1111 1111 Power-On Reset 1111 1111 MCLR reset (normal operation) 1111 1111 MCLR wake-up (from SLEEP) 1111 1111 WDT reset (normal operation) 1111 1111 WDT wake-up (from SLEEP) Legend: u = unchanged, x = unknown, - = unimplemented read as '0'. Note 1: TO and PD bits retain their last value until one of the other reset conditions occur. 2: The CLRWDT instruction will set the TO and PD bits. TABLE 7-6: 0001 1xxx 000u uuuu(1) 0001 0uuu 0000 1uuu(2) 0000 0uuu RESET CONDITIONS FOR ALL REGISTERS Register W TRIS OPTION INDF TMR0 PCL(1) Address N/A N/A N/A 00h 01h 02h Power-On Reset MCLR or WDT Reset xxxx xxxx uuuu uuuu 1111 1111 1111 1111 --11 1111 --11 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 03h 0001 1xxx 000q quuu 04h 05h 06h 07h 1xxx xxxx 1uuu uuuu ---- xxxx ---- uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu STATUS(1) FSR PORTA PORTB PORTC(2) xxxx xxxx General Purpose 08-7Fh register files Legend: u = unchanged, x = unknown, - = unimplemented, read as '0', q = see tables in Section 7.7 for possible values. Note 1: See Table 7-5 for reset value for specific conditions. 2: General purpose register file on the PIC16C54/CR54/C56. FIGURE 7-7: uuuu uuuu SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-Up Detect POR (Power-On Reset) VDD MCLR/VPP pin WDT Time-out RESET On-Chip RC OSC 8-bit Asynch Ripple Counter (Start-Up Timer) S Q R Q CHIP RESET 1995 Microchip Technology Inc. DS30015M-page 31 PIC16C5X 7.4 Power-On Reset (POR) The PIC16C5X family incorporates on-chip Power-On Reset (POR) circuitry which provides an internal chip reset for most power-up situations. To use this feature, the user merely ties the MCLR/VPP pin (Figure 7-8) to VDD. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure 7-7. FIGURE 7-8: RIN MCLR pin The Power-On Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on-chip reset signal. A power-up example where MCLR is not tied to VDD is shown in Figure 7-10. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset TDRT msec after MCLR goes high. In Figure 7-11, the on-chip Power-On Reset feature is being used (MCLR and VDD are tied together). The VDD is stable before the start-up timer times out and there is no problem in getting a proper reset. However, Figure 7-12 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses a high on the MCLR/VPP pin, and when the MCLR/VPP pin (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. On-chip POR is guaranteed to work if the rate of rise of VDD is no slower than 0.05V/ms and VDD starts from 0V. If the on-chip POR time delay is too short for low frequency crystals/resonators (which require much longer than 18 ms to start-up and stabilize) or for high frequency crystals/resonators (which have to reach a higher VDD voltage for operation), we recommend that external RC circuits be used to achieve longer POR delay times (Figure 7-9). DS30015M-page 32 ELECTRICAL STRUCTURE OF MCLR/VPP PIN N (1) (1) Schmitt Trigger Input Buffer VSS VSS Note 1: ESD protection circuits FIGURE 7-9: VDD EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD D R R1 MCLR C PIC16C5X * External Power-On Reset circuit is required only if VDD power-up is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. * R < 40 k is recommended to make sure that voltage drop across R does not exceed 0.2V (max leakage current spec on MCLR/VPP pin is 5 A). A larger voltage drop will degrade VIH level on MCLR/VPP pin. * R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR pin breakdown due to ESD or EOS. 1995 Microchip Technology Inc. PIC16C5X FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min. 1995 Microchip Technology Inc. DS30015M-page 33 PIC16C5X 7.5 Device Reset Timer (DRT) The Device Reset Timer (DRT) provides a fixed 18 ms nominal time-out on reset. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET for approximately 18 ms after the voltage on the MCLR/VPP pin has reached a logic high (VIHMC) level. Thus, external RC networks connected to the MCLR input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications. The Device Reset time delay will vary from chip to chip due to VDD, temperature, and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake the PIC16C5X from SLEEP mode automatically. 7.6 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer reset. The WDT can be permanently disabled by programming the configuration bit WDTE as a '0' (Section 7.1). 7.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, time-out a period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs. 7.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset. DS30015M-page 34 1995 Microchip Technology Inc. PIC16C5X FIGURE 7-13: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 6-6) 0 M U X 1 Watchdog Timer Postscaler Postscaler 8 - to - 1 MUX PS2:PS0 PSA WDT Enable EPROM Bit To Timer0 (Figure 6-6) 1 0 MUX PSA Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register. WDT Time-out TABLE 7-7: Address SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FFFh(1) Config. Word(2) -- -- -- -- CP N/A OPTION -- -- T0CS T0SE PSA Bit 2 Bit 1 Bit 0 WDTE FOSC1 FOSC0 PS2 PS1 PS0 Value on Power-On Reset Value on MCLR and WDT Reset ---- uuuu ---- uuuu --11 1111 --11 1111 Legend: Shaded boxes = Not used by Watchdog Timer, - = unimplemented, read as '0', u = unchanged Note 1: Refer to the PIC16C5X Programming Specifications (literature number DS30190) to determine how to access the configuration word. 2: Only the first 8 bits of the Configuration Word are shown. Reset values (for POR, MCLR and WDT) for bits 12:8 are unimplemented, read as '0'. Initial values of bits 3:0 = 1111. 1995 Microchip Technology Inc. DS30015M-page 35 PIC16C5X 7.7 Time-Out Sequence and Power Down Status Bits (TO/PD) The TO and PD bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) reset, or a MCLR or WDT wake-up reset. TABLE 7-8: TO/PD STATUS AFTER RESET TO PD 1 1 Power-up (POR) u u 1 0 MCLR reset (normal operation)(1) MCLR wake-up reset (from SLEEP) WDT reset (normal operation) WDT wake-up reset (from SLEEP) 0 1 0 0 RESET was caused by 7.8 Reset on Brown-Out A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC16C5X devices when a brown-out occurs, external brown-out protection circuits may be built (Figure 7-14 and Figure 7-15). FIGURE 7-14: BROWN-OUT PROTECTION CIRCUIT 1 VDD VDD 33k 10k Legend: u = unchanged Note 1: The TO and PD bits maintain their status (u) until a reset occurs. A low-pulse on the MCLR input does not change the TO and PD status bits. These STATUS bits are only affected by events listed in Table 7-9. TABLE 7-9: MCLR 40k PIC16C5X This circuit will activate reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). EVENTS AFFECTING TO/PD STATUS BITS Event Power-up WDT Time-out SLEEP instruction CLRWDT instruction TO PD 1 1 0 u 1 0 1 1 Remarks No effect on PD Legend: u = unchanged A WDT time-out will occur regardless of the status of the TO bit. A SLEEP instruction will be executed, regardless of the status of the PD bit. Table 7-8 reflects the status of TO and PD after the corresponding event. FIGURE 7-15: BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD R1 Q1 MCLR R2 40k Table 7-5 lists the reset conditions for the special function registers, while Table 7-6 lists the reset conditions for all the registers. PIC16C5X This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD * DS30015M-page 36 R1 R1 + R2 = 0.7V 1995 Microchip Technology Inc. PIC16C5X 7.9 Power-Down Mode (SLEEP) A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 7.9.1 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR/VPP pin low. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the MCLR/VPP pin must be at a logic high level (VIHMC). 7.9.2 WAKE-UP FROM SLEEP 7.10 The program memory can be code protected by selecting the code protect option when programming the device. In a code protected mode, the configuration word will not be protected, allowing reading of all bits. For EPROM devices, program memory locations 40h and above cannot be further programmed. However, the first 64 locations, 00h-3Fh, may be programmed. These locations are not considered "secure". 7.11 1. 2. An external reset input on MCLR/VPP pin. A Watchdog Timer time-out reset (if WDT was enabled). ID Locations Four memory locations are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the lower four bits of the ID locations and always program the upper eight bits as '1's. Note: The device can wake-up from SLEEP through one of the following events: Code Protection Microchip will assign a unique pattern number for QTP and SQTP requests and for ROM devices. This pattern number will be unique and traceable to the submitted code. Both of these events cause a device reset. The TO and PD bits can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The WDT is cleared when the device wakes from sleep, regardless of the wake-up source. 1995 Microchip Technology Inc. DS30015M-page 37 PIC16C5X NOTES: DS30015M-page 38 1995 Microchip Technology Inc. PIC16C5X 8.0 INSTRUCTION SET SUMMARY Each PIC16C5X instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16C5X instruction set summary in Table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator is used to specify which one of the 32 file registers is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is '0', the result is placed in the W register. If 'd' is '1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Figure 8-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where 'h' signifies a hexadecimal digit. FIGURE 8-1: Byte-oriented file register operations 11 OPCODE FIELD DESCRIPTIONS Field Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0 (store result in W) d = 1 (store result in file register 'f') Default is d = 1 label Label name TOS Top of Stack PC Program Counter WDT Watchdog Timer Counter TO Time-Out bit PD Power-Down bit dest [ ] Options Contents Assigned to <> Register bit field 4 0 f (FILE #) Bit-oriented file register operations 11 OPCODE 8 7 5 4 b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 8 7 OPCODE 0 k (literal) k = 8-bit immediate value Literal and control operations - GOTO instruction 11 9 8 OPCODE 0 k (literal) k = 9-bit immediate value Destination, either the W register or the specified register file location ( ) italics 5 d d = 0 for destination W d = 1 for destination f f = 5-bit file register address Description f 6 OPCODE For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. TABLE 8-1: GENERAL FORMAT FOR INSTRUCTIONS In the set of User defined term (font is courier) 1995 Microchip Technology Inc. DS30015M-page 39 This document was created with FrameMaker 4 0 4 PIC16C5X TABLE 8-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f,d f,d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d 12-Bit Opcode Description Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract W from f Swap f Exclusive OR W with f Cycles MSb LSb Status Affected Notes 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z None Z None Z Z None None C C C,DC,Z None Z 1,2,4 2,4 4 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff None None None None 2,4 2,4 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk Z None TO, PD None Z None None None TO, PD None Z 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set LITERAL AND CONTROL OPERATIONS ANDLW CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW k k k k k k k k - f k AND literal with W Call subroutine Clear Watchdog Timer Unconditional branch Inclusive OR Literal with W Move Literal to W Load OPTION register Return, place Literal in W Go into standby mode Load TRIS register Exclusive OR Literal to W 1 3 Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except forGOTO. (Section 4.5) 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: The instruction TRIS f, where f = 5, 6, or 7 causes the contents of the W register to be written to the tristate latches of PORTA, B or C, respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS30015M-page 40 1995 Microchip Technology Inc. PIC16C5X ADDWF Add W and f Syntax: [ label ] ADDWF Syntax: [ label ] ANDWF Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (W) + (f) (dest) Operation: (W) .AND. (f) (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 0001 11df ANDWF f,d ffff AND W with f Encoding: 0001 f,d 01df ffff Description: Add the contents of the W register and register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. Description: The contents of the W register are AND'ed with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: ADDWF Example: ANDWF FSR, 0 Before Instruction W = FSR = W = FSR = 0x17 0xC2 After Instruction After Instruction W = FSR = W = FSR = 0xD9 0xC2 ANDLW And literal with W Syntax: [ label ] ANDLW k Operands: 0 k 255 Operation: (W).AND. (k) (W) Status Affected: Z 1110 Description: kkkk 1 Cycles: 1 Example: ANDLW 0x5F Before Instruction W = 0xA3 After Instruction W kkkk The contents of the W register are AND'ed with the eight-bit literal 'k'. The result is placed in the W register. Words: = 1 Before Instruction 0x17 0xC2 Encoding: FSR, 0x17 0x02 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 31 0b7 Operation: 0 (f<b>) Status Affected: None Encoding: 0100 bbbf f,b ffff Description: Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Example: BCF FLAG_REG, 7 Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47 0x03 1995 Microchip Technology Inc. DS30015M-page 41 PIC16C5X BSF Bit Set f BTFSS Bit Test f, Skip if Set Syntax: [ label ] BSF Syntax: [ label ] BTFSS f,b Operands: 0 f 31 0b7 Operands: 0 f 31 0b<7 Operation: 1 (f<b>) Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 0101 f,b bbbf ffff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Example: BSF FLAG_REG, Encoding: FLAG_REG = 0x8A Words: 1 Cycles: 1(2) Example: HERE FALSE TRUE BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b Operands: 0 f 31 0b7 Before Instruction Operation: skip if (f<b>) = 0 After Instruction Status Affected: None Encoding: 0110 * * PC bbbf ffff Description: If bit 'b' in register 'f' is 0 then the next instruction is skipped. If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and an NOP is executed instead, making this a 2 cycle instruction. Words: 1 Cycles: 1(2) Example: HERE FALSE TRUE BTFSC GOTO ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and an NOP is executed instead, making this a 2 cycle instruction. Before Instruction FLAG_REG = 0x0A bbbf Description: 7 After Instruction 0111 If FLAG<1> PC if FLAG<1> PC BTFSS GOTO * FLAG,1 PROCESS_CODE = address (HERE) = = = = 0, address (FALSE); 1, address (TRUE) FLAG,1 PROCESS_CODE * * * Before Instruction PC = address (HERE) = = = = 0, address (TRUE); 1, address(FALSE) After Instruction if FLAG<1> PC if FLAG<1> PC DS30015M-page 42 1995 Microchip Technology Inc. PIC16C5X CALL Subroutine Call CLRW Clear W Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 k 255 Operands: None Operation: (PC) + 1 Top of Stack; k PC<7:0>; (STATUS<6:5>) PC<10:9>; 0 PC<8> Operation: 00h (W); 1Z Status Affected: Z Status Affected: None Encoding: Description: 1001 kkkk kkkk Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two cycle instruction. 1 Cycles: 2 Example: HERE CALL After Instruction address (THERE) address (HERE + 1) CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 31 Operation: 00h (f); 1Z Status Affected: Z Description: 0000 The W register is cleared. Zero bit (Z) is set. Words: 1 Cycles: 1 Example: CLRW Before Instruction W = 0x5A 0000 f 1 Cycles: 1 Example: CLRF 011f FLAG_REG = 0x5A = = 0x00 1 After Instruction FLAG_REG Z CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD Status Affected: TO, PD Description: Before Instruction FLAG_REG 0x00 1 Encoding: ffff The contents of register 'f' are cleared and the Z bit is set. Words: = = THERE address (HERE) Encoding: 0100 Description: W Z Before Instruction PC = TOS = 0000 After Instruction Words: PC = Encoding: 1995 Microchip Technology Inc. 0000 0000 0100 The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set. Words: 1 Cycles: 1 Example: CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter WDT prescale TO PD = = = = 0x00 0 1 1 DS30015M-page 43 PIC16C5X COMF Complement f Syntax: [ label ] COMF Operands: 0 f 31 d [0,1] Operation: (f) (dest) Status Affected: Z Encoding: 0010 f,d 01df ffff Description: The contents of register 'f' are complemented. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: COMF = 0x13 After Instruction REG1 W = = Decrement f Syntax: [ label ] DECF f,d Operands: 0 f 31 d [0,1] Operation: (f) - 1 (dest) Status Affected: Z Description: 0000 1 Cycles: 1 Example: DECF Before Instruction = = 0x01 0 After Instruction CNT Z = = [ label ] DECFSZ f,d Operands: 0 f 31 d [0,1] Operation: (f) - 1 d; Status Affected: None Encoding: Description: 0010 skip if result = 0 11df ffff The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded and an NOP is executed instead making it a two cycle instruction. Words: 1 Cycles: 1(2) Example: HERE DECFSZ GOTO CONTINUE * * * CNT, 1 LOOP Before Instruction PC = address (HERE) After Instruction 11df CNT if CNT PC if CNT PC CNT, = = = = CNT - 1; 0, address (CONTINUE); 0, address (HERE+1) ffff Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: CNT Z Syntax: 0x13 0xEC DECF Encoding: Decrement f, Skip if 0 REG1,0 Before Instruction REG1 DECFSZ GOTO Unconditional Branch Syntax: [ label ] Operands: 0 k 511 Operation: k PC<8:0>; STATUS<6:5> PC<10:9> Status Affected: None 1 Encoding: 101k GOTO k kkkk kkkk Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a two cycle instruction. Words: 1 Cycles: 2 Example: GOTO THERE 0x00 1 After Instruction PC = DS30015M-page 44 address (THERE) 1995 Microchip Technology Inc. PIC16C5X INCF Increment f IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 k 255 Operation: (f) + 1 (dest) (W) .OR. (k) (W) Operation: Status Affected: Z Status Affected: Z Encoding: Description: Words: INCF f,d Encoding: 0010 10df ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. 1 Cycles: 1 Example: INCF CNT, = = 1101 kkkk kkkk Description: The contents of the W register are OR'ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: IORLW 0x35 Before Instruction 1 W Before Instruction CNT Z IORLW k = 0x9A After Instruction 0xFF 0 W Z = = 0xBF 0 After Instruction CNT Z = = 0x00 1 IORWF Inclusive OR W with f Syntax: [ label ] Operands: 0 f 31 d [0,1] IORWF f,d INCFSZ Increment f, Skip if 0 Syntax: [ label ] Operands: 0 f 31 d [0,1] Operation: (W).OR. (f) (dest) Status Affected: Z Operation: (f) + 1 (dest), skip if result = 0 Encoding: Status Affected: None Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Example: IORWF Encoding: Description: 0011 INCFSZ f,d 11df ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, then the next instruction, which is already fetched, is discarded and an NOP is executed instead making it a two cycle instruction. 0001 00df ffff RESULT, 0 Before Instruction RESULT = W = 0x13 0x91 After Instruction Words: 1 Cycles: 1(2) Example: HERE INCFSZ GOTO CONTINUE * * * CNT, LOOP 1 RESULT = W = Z = 0x13 0x93 0 Before Instruction PC = address (HERE) After Instruction CNT if CNT PC if CNT PC = = = = CNT + 1; 0, address (CONTINUE); 0, address (HERE +1) 1995 Microchip Technology Inc. DS30015M-page 45 PIC16C5X MOVF Move f Syntax: [ label ] Operands: 0 f 31 d [0,1] Operation: (f) (dest) Status Affected: Z Encoding: 0010 Description: MOVF f,d MOVWF Move W to f Syntax: [ label ] Operands: 0 f 31 Operation: (W) (f) Status Affected: None Encoding: 00df ffff The contents of register 'f' is moved to destination 'd'. If 'd' is 0, destination is the W register. If 'd' is 1, the destination is file register 'f'. 'd' is 1 is useful to test a file register since status flag Z is affected. Description: 1 Cycles: 1 Example: MOVF 1 Cycles: 1 Example: MOVWF TEMP_REG W FSR, TEMP_REG = = 0xFF 0x4F = = 0x4F 0x4F After Instruction 0 TEMP_REG W value in FSR register NOP No Operation MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: No operation Operation: k (W) Status Affected: None Status Affected: None Encoding: Encoding: 1100 Description: ffff Move data from the W register to register 'f'. Words: After Instruction = 001f f Before Instruction Words: W 0000 MOVWF MOVLW k kkkk kkkk Description: 0000 NOP 0000 0000 No operation. The eight bit literal 'k' is loaded into the W register. The don't cares will assemble as 0s. Words: 1 Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A DS30015M-page 46 1995 Microchip Technology Inc. PIC16C5X OPTION Load OPTION Register RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] RLF Operands: None Operands: Operation: (W) OPTION 0 f 31 d [0,1] Status Affected: None Operation: See description below Status Affected: C Encoding: 0000 OPTION 0000 0010 Description: The content of the W register is loaded into the OPTION register. Words: 1 Cycles: 1 Example Encoding: Description: OPTION 0011 = After Instruction 0x07 RETLW Return with Literal in W Syntax: [ label ] Operands: 0 k 255 Operation: k (W); TOS PC Status Affected: None Encoding: 1000 Description: Cycles: 2 Example: CALL TABLE ;W contains ;table offset ;value. * ;W now has table * ;value. * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction 0x07 After Instruction W = 1 Example: RLF value of k8 REG1,0 Before Instruction REG1 C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 kkkk 1 = Cycles: REG1 W C Words: W 1 After Instruction The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction. TABLE Words: RETLW k kkkk ffff register 'f' C 0x07 OPTION = 01df The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. Before Instruction W f,d RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 31 d [0,1] Operation: See description below Status Affected: C Encoding: Description: 0011 RRF f,d 00df ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. C Words: 1 Cycles: 1 Example: RRF register 'f' REG1,0 Before Instruction REG1 C = = 1110 0110 0 After Instruction REG1 W C 1995 Microchip Technology Inc. = = = 1110 0110 0111 0011 0 DS30015M-page 47 PIC16C5X SLEEP Enter SLEEP Mode SUBWF Subtract W from f Syntax: [label] Syntax: [label] Operands: None Operands: Operation: 00h WDT; 0 WDT prescaler; 1 TO; 0 PD 0 f 31 d [0,1] Operation: (f) - (W) (dest) Status Affected: C, DC, Z Status Affected: TO, PD Encoding: Description: SLEEP 0000 Description: 0000 0011 Time-out status bit (TO) is set. The power down status bit (PD) is cleared. The WDT and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See section on SLEEP for more details. Words: 1 Cycles: 1 Example: SLEEP Encoding: 0000 SUBWF f,d 10df ffff Subtract (2's complement method) the W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example 1: SUBWF REG1, 1 Before Instruction REG1 W C = = = 3 2 ? After Instruction REG1 W C = = = 1 2 1 ; result is positive Example 2: Before Instruction REG1 W C = = = 2 2 ? After Instruction REG1 W C = = = 0 2 1 ; result is zero Example 3: Before Instruction REG1 W C = = = 1 2 ? After Instruction REG1 W C DS30015M-page 48 = = = FF 2 0 ; result is negative 1995 Microchip Technology Inc. PIC16C5X SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [label] Operands: 0 f 31 d [0,1] Operands: 0 k 255 (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) Operation: Operation: (W) .XOR. k (W) Status Affected: Z Status Affected: None Encoding: XORLW k 1111 kkkk kkkk Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Words: 1 Example: XORLW Cycles: 1 Example SWAPF Encoding: Description: 0011 10df ffff Before Instruction REG1, W 0 = = 0xB5 After Instruction Before Instruction REG1 0xAF W 0xA5 = 0x1A After Instruction REG1 W = = 0xA5 0X5A XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 f 31 d [0,1] f,d TRIS Load TRIS Register Syntax: [ label ] TRIS Operation: (W) .XOR. (f) (dest) Operands: f = 5, 6 or 7 Status Affected: Z Operation: (W) TRIS register f Encoding: Status Affected: None Encoding: 0000 0000 f 0001 Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. TRIS register 'f' (f = 5, 6, or 7) is loaded with the contents of the W register Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example XORWF TRIS PORTA Before Instruction W = = REG,1 Before Instruction 0XA5 After Instruction TRISA ffff Description: 0fff Description: Example 10df 0XA5 REG W 0xAF 0xB5 After Instruction REG W 1995 Microchip Technology Inc. = = = = 0x1A 0xB5 DS30015M-page 49 PIC16C5X NOTES: DS30015M-page 50 1995 Microchip Technology Inc. PIC16C5X 9.0 DEVELOPMENT SUPPORT 9.1 Development Tools The PIC16/17 microcontrollers are supported with a full range of hardware and software development tools: * * * * * * * * * PICMASTER Real-Time In-Circuit Emulator PRO MATE Universal Programmer PICSTART Low-Cost Prototype Programmer PICDEM-1 Low-Cost Demonstration Board PICDEM-2 Low-Cost Demonstration Board MPASM Assembler MPSIM Software Simulator C Compiler (MP-C) Fuzzy logic development system (fuzzyTECH-MP) 9.2 The PICMASTER Universal Emulator System consists primarily of four major components: * * * * Host-Interface Card Emulator Control Pod Target-Specific Emulator Probe PC-Host Emulation Control Software The Windows operating system allows the developer to take full advantage of the many powerful features and functions of the PICMASTER system. PICMASTER High Performance Universal In-Circuit Emulator with MPLAB IDE PICMASTER emulation can operate in one window, while a text editor is running in a second window. The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC16C5X, PIC16CXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. A PICMASTER System configuration is shown in Figure 9-1. Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new PIC16C5X, PIC16CXX and PIC17CXX microcontrollers. FIGURE 9-1: The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and better) machine platform and the Microsoft Windows 3.x environment was chosen to best make these features available to you, the end user. PC-Host Emulation Control software takes full advantage of Dynamic Data Exchange (DDE), a feature of Windows. DDE allows data to be dynamically transferred between two or more Windows programs. With this feature, data collected with PICMASTER can be automatically transferred to a spreadsheet or database program for further analysis. Under Windows, as many as four PICMASTER emulators can be run simultaneously from the same PC making development of multi-microcontroller systems possible (e.g., a system containing a PIC16CXX processor and a PIC17CXX processor). The PICMASTER probes specifications are shown in Table 9-1. PICMASTER SYSTEM CONFIGURATION 5 VDC Windows 3.x PC Bus In-Line Power Supply (Optional) 90 - 250 VAC Power Switch Power Connector Interchangeable Emulator Probe PC-Interface Common Interface Card PC Compatible Computer PICMASTER Emulator Pod Logic Probes 1995 Microchip Technology Inc. DS30015M-page 51 This document was created with FrameMaker 4 0 4 PIC16C5X TABLE 9-1: PICMASTER PROBE SPECIFICATION TABLE 9-1: PICMASTER PROBE SPECIFICATION PROBE Devices PIC16C54 PICMASTER PROBE PROBE-16D Maximum Frequency Operating Voltage 20 MHz 4.5V - 5.5V PROBE Devices PIC16C65 PICMASTER PROBE Maximum Frequency Operating Voltage PROBE-16F 10 MHz 4.5V - 5.5V 10 MHz 4.5V - 5.5V PIC16C54A PROBE-16D 20 MHz 4.5V - 5.5V PIC16C65A PROBE-16F(1) PIC16CR54 PROBE-16D 20 MHz 4.5V - 5.5V PIC16C620 PROBE-16H 10 MHz 4.5V - 5.5V PIC16CR54A PROBE-16D(1) 20 MHz 4.5V - 5.5V PIC16C621 PROBE-16H 10 MHz 4.5V - 5.5V PIC16CR54B PROBE-16D(1) 20 MHz 4.5V - 5.5V PIC16C622 PROBE-16H 10 MHz 4.5V - 5.5V 10 MHz 4.5V - 5.5V PIC16C55 PIC16CR55 PIC16C56 PIC16CR56 PIC16C57 PIC16CR57A PROBE-16D PROBE-16D (1) 20 MHz 4.5V - 5.5V PIC16C70 20 MHz 4.5V - 5.5V PIC16C71 10 MHz 4.5V - 5.5V (1) PROBE-16D 20 MHz 4.5V - 5.5V PIC16C71A PROBE-16B 10 MHz 4.5V - 5.5V 20 MHz 4.5V - 5.5V PIC16C72 PROBE-16F(1) 10 MHz 4.5V - 5.5V PROBE-16D 20 MHz 4.5V - 5.5V PIC16C73 PROBE-16F 10 MHz 4.5V - 5.5V PROBE-16F(1) 10 MHz 4.5V - 5.5V PROBE-16D (1) 20 MHz 4.5V - 5.5V PIC16C73A 20 MHz 4.5V - 5.5V PIC16C74 PROBE-16D 20 MHz 4.5V - 5.5V PIC16C74A PIC16CR58A PROBE-16D 20 MHz 4.5V - 5.5V 20 MHz PIC16CR58B PROBE-16B PROBE-16D(1) PIC16C58A PIC16CR57B PROBE-16B (1) PROBE-16D PROBE-16D (1) PROBE-16F 10 MHz 4.5V - 5.5V PROBE-16F(1) 10 MHz 4.5V - 5.5V PIC16C83 PROBE-16C 10 MHz 4.5V - 5.5V 4.5V - 5.5V PIC16C84 PROBE-16C 10 MHz 4.5V - 5.5V PIC16C61 PROBE-16G 10 MHz 4.5V - 5.5V PIC17C42 PROBE-17B 20 MHz 4.5V - 5.5V PIC16C62 PROBE-16E 10 MHz 4.5V - 5.5V PIC17C43 PROBE-17B 20 MHz 4.5V - 5.5V PROBE-16E (1) 10 MHz 4.5V - 5.5V PIC17C44 PROBE-17B 20 MHz 4.5V - 5.5V PROBE-16E (1) 10 MHz 4.5V - 5.5V Note 1: This PICMASTER probe can be used to functionally emulate the device listed in the previous column. Contact your Microchip sales office for details. PIC16C62A PIC16CR62 PIC16C63 10 MHz 4.5V - 5.5V PROBE-16E 10 MHz 4.5V - 5.5V PIC16C64A PROBE-16E(1) 10 MHz 4.5V - 5.5V PIC16CR64 (1) 10 MHz 4.5V - 5.5V PIC16C64 PROBE-16F (1) PROBE-16E DS30015M-page 52 1995 Microchip Technology Inc. PIC16C5X 9.3 PRO MATE Universal Programmer The PRO MATE Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. The PRO MATE has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE can read, verify or program PIC16C5X, PIC16CXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode. In PC-hosted mode, the PRO MATE connects to the PC via one of the COM (RS-232) ports. PC based user-interface software makes using the programmer simple and efficient. The user interface is full-screen and menu-based. Full screen display and editing of data, easy selection of bit configuration and part type, easy selection of VDD min, VDD max and VPP levels, load and store to and from disk files (Intel hex format) are some of the features of the software. Essential commands such as read, verify, program and blank check can be issued from the screen. Additionally, serial programming support is possible where each part is programmed with a different serial number, sequential or random. The PRO MATE has a modular "programming socket module". Different socket modules are required for different processor types and/or package types. PRO MATE supports all PIC16C5X, PIC16CXX and PIC17CXX processors. 9.4 PICSTART Low-Cost Development System The PICSTART programmer is an easy to use, very low-cost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. A PC-based user interface software makes using the programmer simple and efficient. The user interface is full-screen and menu-based. PICSTART is not recommended for production programming. 1995 Microchip Technology Inc. 9.5 PICDEM-1 Low-Cost PIC16/17 Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE or PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. 9.6 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM-2 is a simple demonstration board that supports the PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE programmer or PICSTART-16C, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad. DS30015M-page 53 PIC16C5X 9.7 MPLAB Integrated Development Environment Software The MPLAB Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator (available soon) * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * edit your source files (either assembly or "C") * one touch assemble (or compile) and download to PIC16/17 tools (automatically updates all project information) * debug using: - source files - absolute listing file * transfer data dynamically via DDE (soon to be replaced by OLE) * run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator (available soon) allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. DS30015M-page 54 9.8 MPASM Assembler The MPASM Cross Assembler is a PC-hosted symbolic assembler. It supports all microcontroller series including the PIC16C5X, PIC16CXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from the Microchip Universal Emulator System (PICMASTER). MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemble source code shorter and more maintainable. * Data Directives are those that control the allocation of memory and provide a way to refer to data items symbolically (i.e., by meaningful names). * Control Directives control the MPASM listing display. They allow the specification of titles and sub-titles, page ejects and other listing control. This eases the readability of the printed output file. * Conditional Directives permit sections of conditionally assembled code. This is most useful where additional functionality may wished to be added depending on the product (less functionality for the low end product, then for the high end product). Also this is very helpful in the debugging of a program. * Macro Directives control the execution and data allocation within macro body definitions. This makes very simple the re-use of functions in a program as well as between programs. 1995 Microchip Technology Inc. PIC16C5X 9.9 MPSIM Software Simulator The MPSIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPSIM fully supports symbolic debugging using MP-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 9.10 9.11 fuzzyTECH-MP Fuzzy Logic Development System fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for implementing more complex systems. Both versions include Microchip's fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation. 9.12 Development Systems For convenience, the development tools are packaged into comprehensive systems as listed in Table 9-2. MP-C C Compiler The MP-C Code Development System is a complete 'C' compiler and integrated development environment for Microchip's PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the PICMASTER Universal Emulator memory display (PICMASTER emulator software versions 1.13 and later). The MP-C Code Development System is supplied directly by Byte Craft Limited of Waterloo, Ontario, Canada. If you have any questions, please contact your regional Microchip FAE or Microchip technical support personnel at (602) 786-7627. TABLE 9-2: Item DEVELOPMENT SYSTEM PACKAGES Name System Description 1. PICMASTER System PICMASTER In-Circuit Emulator, PRO MATE Programmer, Assembler, Software Simulator, Samples and your choice of Target Probe. 2. PICSTART System PICSTART Low-Cost Prototype Programmer, Assembler, Software Simulator and Samples. 3. PRO MATE System PRO MATE Universal Programmer, full featured stand-alone or PC-hosted programmer, Assembler, Simulator 1995 Microchip Technology Inc. DS30015M-page 55 PIC16C5X NOTES: DS30015M-page 56 1995 Microchip Technology Inc. PIC16C54/55/56/57 10.0 PIC16C5X ELECTRICAL CHARACTERISTICS - PIC16C54/55/56/57 Absolute Maximum Ratings Ambient Temperature under bias ........................................................................................................... -55C to +125C Storage Temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................... 0V to +7.5V Voltage on MCLR with respect to VSS(2) ......................................................................................................... 0V to +14V Voltage on all other pins with respect to VSS ................................................................................. -0.6V to (VDD + 0.6V) Total Power Dissipation(1) ....................................................................................................................................800 mW Max. Current out of VSS pin ..................................................................................................................................150 mA Max. Current into VDD pin .......................................................................................................................................50 mA Max. Current into an input pin (T0CKI only) ....................................................................................................................500 A Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................20 mA Output Clamp Current, IOK (V0 < 0 or V0 > VDD).............................................................................................................20 mA Max. Output Current sunk by any I/O pin................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................20 mA Max. Output Current sourced by a single I/O port (PORTA, B or C).......................................................................40 mA Max. Output Current sunk by a single I/O port (PORTA, B or C) ............................................................................50 mA Note 1: Power Dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50 to 100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1995 Microchip Technology Inc. DS30015M-page 57 This document was created with FrameMaker 4 0 4 PIC16C5X TABLE 10-1: PIC16C54/55/56/57 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS (RC, XT & 10) AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) OSC PIC16C5X-RC RC VDD: IDD: IPD: Freq: 3.0 V to 6.2 V 3.3 mA max. at 5. V 9 A max. at 3.0 V, WDT dis 4 MHz max. XT VDD: IDD: IPD: Freq: 3.0V to 6.25V 1.8 mA typ. at 5.5V 0.6 A typ. at 3.0V WDT dis 4 MHz max. HS VDD: IDD: IPD: Freq: 4.5V to 5.5V 9.0 mA typ. at 5.5V 0.6 A typ. at 3.0V WDT dis 20 MHz max. LP VDD: IDD: IPD: Freq: 2.5V to 6.25V 15 A typ. at 3.0V 0.6 A typ. at 3.0V, WDT dis 40 kHz max. VDD: IDD: IPD: Freq: PIC16C5X-XT PIC16C5X-10 N/A N/A 3.0V to 6.25V 3.3 mA max. at 5.5V 9 A max. at 3.0V, WDT dis 4 MHz max. N/A VDD: IDD: IPD: Freq: 2.5V to 6.25V 15 A typ. at 3.0V 0.6 A typ. at 3.0V, WDT dis 40 kHz max. N/A VDD: IDD: IPD: Freq: 4.5V to 5.5V 10 mA max. at 5.5V 9 A max. at 3.0V, WDT dis 10 MHz max. VDD: IDD: IPD: Freq: 2.5V to 6.25V 15 A typ. at 3.0V 0.6 A typ. at 3.0V, WDT dis 40 kHz max. The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended that the user select the device type from information in unshaded sections. TABLE 10-2: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS (HS, LP & JW) AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) OSC PIC16C5X-HS PIC16C5X-LP N/A RC N/A XT HS VDD: IDD: IPD: Freq: 4.5V to 5.5V 20 mA max. at 5.5V 9 A max. at 3.0V, WDT dis 20 MHz max. LP VDD: IDD: IPD: Freq: 2.5V to 6.25V 15 A typ. at 3.0V 0.6 A typ. at 3.0V, WDT dis 40 kHz max. VDD: IDD: IPD: Freq: PIC16C5X/JW N/A VDD: IDD: IPD: Freq: 3.0V to 6.25V 3.3 mA max. at 5.5V 9 A max. at 3.0V, WDT dis 4 MHz max. N/A VDD: IDD: IPD: Freq: 3.0V to 6.25V 3.3 mA max. at 5.5V 9 A max. at 3.0V, WDT dis 4 MHz max. N/A VDD: IDD: IPD: Freq: 4.5V to 5.5V 20 mA max. at 5.5V 9 A max. at 3.0V, WDT dis 20 MHz max. VDD: IDD: IPD: Freq: 2.5V to 6.25V 32 A max. at 32 kHz, 3.0V 9 A max. at 3.0V, WDT dis 40 kHz max. 2.5V to 6.25V 32 A max. at 32 kHz, 3.0V 9 A max. at 3.0V, WDT dis 40 kHz max. The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended that the user select the device type from information in unshaded sections. DS30015M-page 58 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 10.1 DC Characteristics: PIC16C5X-RC, XT, 10, HS, LP (Commercial) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C Sym Min Typ(1) Max Units Conditions 6.25 6.25 5.5 5.5 6.25 V V V V V FOSC = DC to 4 MHz FOSC = DC to 4 MHz FOSC = DC to 10 MHz FOSC = DC to 20 MHz FOSC = DC to 40 kHz Supply Voltage PIC16C5X-RC PIC16C5X-XT PIC16C5X-10 PIC16C5X-HS PIC16C5X-LP VDD RAM Data Retention Voltage(2) VDR 1.5* V Device in SLEEP Mode VDD Start Voltage to ensure Power-On Reset VPOR VSS V See Section 7.4 for details on Power-On Reset VDD Rise Rate to ensure Power-On Reset SVDD V/ms See Section 7.4 for details on Power-On Reset Supply Current(3) PIC16C5X-RC(4) PIC16C5X-XT PIC16C5X-10 PIC16C5X-HS 3.0 3.0 4.5 4.5 2.5 0.05* IDD PIC16C5X-LP Power Down Current(5) 1.8 1.8 4.8 4.8 9.0 15 3.3 3.3 10 10 20 32 mA mA mA mA mA A FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.0V, WDT disabled 4.0 0.6 12 9 A A VDD = 3.0V, WDT enabled VDD = 3.0V, WDT disabled IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in k. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 1995 Microchip Technology Inc. DS30015M-page 59 PIC16C5X 10.2 PIC16C54/55/56/57 DC Characteristics: PIC16C5XI-RC, XT, 10, HS, LP (Industrial) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C Sym Min Typ(1) Max Units Conditions 6.25 6.25 5.5 5.5 6.25 V V V V V FOSC = DC to 4 MHz FOSC = DC to 4 MHz FOSC = DC to 10 MHz FOSC = DC to 20 MHz FOSC = DC to 40 kHz Supply Voltage PIC16C5XI-RC PIC16C5XI-XT PIC16C5XI-10 PIC16C5XI-HS PIC16C5XI-LP VDD RAM Data Retention Voltage(2) VDR 1.5* V Device in SLEEP mode VDD Start Voltage to ensure Power-On Reset VPOR VSS V See Section 7.4 for details on Power-On Reset VDD Rise Rate to ensure Power-On Reset SVDD V/ms See Section 7.4 for details on Power-On Reset Supply Current(3) PIC16C5XI-RC(4) PIC16C5XI-XT PIC16C5XI-10 PIC16C5XI-HS 3.0 3.0 4.5 4.5 2.5 0.05* IDD PIC16C5XI-LP Power Down Current(5) 1.8 1.8 4.8 4.8 9.0 19 3.3 3.3 10 10 20 40 mA mA mA mA mA A FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V FOSC = 32 kHz, Vdd = 3.0V, WDT disabled 5.0 0.6 14 12 A A VDD = 3.0V, WDT enabled VDD = 3.0V, WDT disabled IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in k. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30015M-page 60 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 10.3 DC Characteristics: PIC16C5XE-RC, XT, 10, HS, LP (Automotive) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C Sym Min Typ (1) Max Units Conditions 6.0 6.0 5.5 5.5 6.0 V V V V V FOSC = DC to 4 MHz FOSC = DC to 4 MHz FOSC = DC to 10 MHz FOSC = DC to 16 MHz FOSC = DC to 40 kHz Supply Voltage PIC16C5XE-RC PIC16C5XE-XT PIC16C5XE-10 PIC16C5XE-HS PIC16C5XE-LP VDD RAM Data Retention Voltage(2) VDR 1.5* V Device in SLEEP mode VDD Start Voltage to ensure Power-On Reset VPOR VSS V See Section 7.4 for details on Power-On Reset VDD rise rate to ensure Power-On Reset SVDD V/ms See Section 7.4 for details on Power-On Reset Supply Current(3) PIC16C5XE-RC(4) PIC16C5XE-XT PIC16C5XE-10 PIC16C5XE-HS 3.25 3.25 4.5 4.5 2.5 0.05* IDD PIC16C5XE-LP Power Down Current(5) 1.8 1.8 4.8 4.8 9.0 25 3.3 3.3 10 10 20 55 mA mA mA mA mA A FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 16 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.25V, WDT disabled 5.0 0.8 22 18 A A VDD = 3.25V, WDT enabled VDD = 3.25V, WDT disabled IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in k. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 1995 Microchip Technology Inc. DS30015M-page 61 PIC16C5X 10.4 PIC16C54/55/56/57 DC Characteristics: PIC16C5X-RC, XT, 10, HS, LP (Commercial) PIC16C5XI-RC, XT, 10, HS, LP (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3. DC Characteristics All Pins Except Power Supply Pins Characteristic Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) VIL Input High Voltage I/O ports VIH MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) Hysteresis of Schmitt Trigger inputs Input Leakage Current(2,3) I/O ports VHYS Min Typ(1) Max Units VSS VSS VSS VSS VSS 0.2 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD V V V V V 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD VDD VDD VDD VDD VDD VDD VDD V V V V V V V 0.15VDD* MCLR -3 -3 Output Low Voltage I/O ports OSC2/CLKOUT VOL Output High Voltage I/O ports(3) OSC2/CLKOUT VOH VDD - 0.7 VDD - 0.7 PIC16C5X-RC only(4) PIC16C5X-XT, 10, HS, LP For all VDD(5) 4.0V < VDD 5.5V(5) VDD > 5.5V PIC16C5X-RC only(4) PIC16C5X-XT, 10, HS, LP For VDD 5.5V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, PIC16C5X-XT, 10, HS, LP 0.5 +1 A 0.5 0.5 0.5 +5 +3 +3 A A A A 0.6 0.6 V V IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, PIC16C5X-RC V V IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, PIC16C5X-RC -5 T0CKI OSC1 Pin at hi-impedance V IIL -1 Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. DS30015M-page 62 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 10.5 DC Characteristics: PIC16C5X-RC, XT, 10, HS, LP (Automotive) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3. DC Characteristics All Pins Except Power Supply Pins Characteristic Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) VIL Input High Voltage I/O ports VIH MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) Hysteresis of Schmitt Trigger inputs Input Leakage Current (2,3) I/O ports VHYS Min Typ(1) Max Units Vss Vss Vss Vss Vss 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD V V V V V 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD VDD VDD VDD VDD VDD VDD VDD V V V V V V V 0.15VDD* MCLR -3 -3 Output Low Voltage I/O ports OSC2/CLKOUT VOL Output High Voltage I/O ports(3) OSC2/CLKOUT VOH VDD - 0.7 VDD - 0.7 PIC16C5X-RC only(4) PIC16C5X-XT, 10, HS, LP For all VDD(5) 4.0V < VDD 5.5V(5) VDD > 5.5 V PIC16C5X-RC only(4) PIC16C5X-XT, 10, HS, LP For VDD 5.5 V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, PIC16C5X-XT, 10, HS, LP 0.5 +1 A 0.5 0.5 0.5 +5 +3 +3 A A A A 0.6 0.6 V V IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, PIC16C5X-RC V V IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, PIC16C5X-RC -5 T0CKI OSC1 Pin at hi-impedance V IIL -1 Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. 1995 Microchip Technology Inc. DS30015M-page 63 PIC16C5X 10.6 PIC16C54/55/56/57 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time drt device reset timer io I/O port Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low T Time mc osc os t0 wdt MCLR oscillator OSC1 T0CKI watchdog timer P R V Z Period Rise Valid Hi-impedance FIGURE 10-1: LOAD CONDITIONS - PIC16C54/55/56/57 Pin CL = 50 pF for all pins except OSC2 CL VSS DS30015M-page 64 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 10.7 Timing Diagrams and Specifications FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C54/55/56/57 Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 AC Characteristics Parameter No. Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Sym FOSC Characteristic External CLKIN Frequency(2) Oscillator Frequency(2) Min Typ(1) Max Units DC -- 4 MHz RC osc mode DC -- 4 MHz XT osc mode DC -- 10 MHz 10 MHz mode DC -- 20 MHz HS osc mode (Com/Indust) DC -- 16 MHz HS osc mode (Automotive) DC -- 40 kHz LP osc mode DC -- 4 MHz RC osc mode 0.1 -- 4 MHz XT osc mode 4 -- 10 MHz 10 MHz mode 4 -- 20 MHz HS osc mode (Com/Indust) 4 -- 16 MHz HS osc mode (Automotive) DC -- 40 kHz LP osc mode Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. 1995 Microchip Technology Inc. DS30015M-page 65 PIC16C5X TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 (CON'T) AC Characteristics Parameter No. 1 PIC16C54/55/56/57 Sym TOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Characteristic External CLKIN Period(2) Oscillator Period(2) 2 3 4 TCY Instruction Cycle Time(3) TosL, TosH Clock in (OSC1) Low or High Time TosR, TosF Clock in (OSC1) Rise or Fall Time Min Typ(1) Max Units 250 -- -- ns RC osc mode 250 -- -- ns XT osc mode 100 -- -- ns 10 MHz mode 50 -- -- ns HS osc mode (Com/Indust) 62.5 -- -- ns HS osc mode (Automotive) 25 -- -- s LP osc mode 250 -- -- ns RC osc mode 250 -- 10,000 ns XT osc mode 100 -- 250 ns 10 MHz mode 50 -- 250 ns HS osc mode (Com/Indust) 62.5 -- 250 ns HS osc mode (Automotive) 25 -- -- s LP osc mode -- 4/FOSC -- -- 50* -- -- ns XT oscillator 20* -- -- ns HS oscillator 2* -- -- s LP oscillator -- -- 25* ns XT oscillator -- -- 25* ns HS oscillator -- -- 50* ns LP oscillator Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS30015M-page 66 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57 Q1 Q4 Q2 Q3 OSC1 10 11 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 17 I/O Pin (output) 15 New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 10-4: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57 AC Characteristics Parameter No. Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Min Typ(1) Max Units TosH2ckL OSC1 to CLKOUT(2) -- 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(2) -- 15 30** ns 12 TckR CLKOUT rise time(2) -- 5 15** ns TckF CLKOUT fall time(2) -- 5 15** ns TckL2ioV CLKOUT to Port out valid(2) -- -- 40** ns 15 TioV2ckH Port in valid before CLKOUT(2) 0.25 TCY+30* -- -- ns 16 TckH2ioI Port in hold after CLKOUT(2) 0* -- -- ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(3) -- -- 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) TBD -- -- ns 19 TioV2osH Port input valid to OSC1 (I/O in setup time) TBD -- -- ns 20 TioR Port output rise time(3) -- 10 25** ns TioF Port output fall time(3) -- 10 25** ns 10 13 14 21 Sym Characteristic * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 3: See Figure 10-1 for loading conditions. 1995 Microchip Technology Inc. DS30015M-page 67 PIC16C5X PIC16C54/55/56/57 FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C54/55/56/57 VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. TABLE 10-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Parameter No. Sym Characteristic Min Typ(1) Max Units 30 TmcL MCLR Pulse Width (low) 100* -- -- ns VDD = 5.0V 31 Twdt Watchdog Timer Time-out Period (No Prescaler) 9* 18* 30* ms VDD = 5.0V (Commercial) 32 TDRT Device Reset Timer Period 9* 18* 30* ms VDD = 5.0V (Commercial) 34 TioZ I/O Hi-impedance from MCLR Low -- -- 100* ns Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30015M-page 68 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57 T0CKI 40 41 42 TABLE 10-6: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3 Parameter Sym Characteristic No. 40 Min Tt0H T0CKI High Pulse Width - No Prescaler - With Prescaler 41 Tt0L T0CKI Low Pulse Width - No Prescaler - With Prescaler 42 Tt0P T0CKI Period Typ(1) Max Units Conditions 0.5 TCY + 20* -- -- ns 10* -- -- ns 0.5 TCY + 20* -- -- ns 10* -- -- ns 20 or TCY + 40* N -- -- ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1995 Microchip Technology Inc. DS30015M-page 69 PIC16C5X PIC16C54/55/56/57 NOTES: DS30015M-page 70 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 11.0 DC AND AC CHARACTERISTICS - PIC16C54/55/56/57 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively, where is standard deviation. FIGURE 11-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FOSC FOSC (25C) Frequency normalized to +25C 1.10 Rext 10 k Cext = 100 pF 1.08 1.06 1.04 1.02 1.00 0.98 VDD = 5.5 V 0.96 0.94 VDD = 3.5 V 0.92 0.90 0.88 0 10 20 25 30 40 50 60 70 T(C) TABLE 11-1: RC OSCILLATOR FREQUENCIES Cext 20 pF Average Fosc @ 5 V, 25C Rext 3.3 k 5k 10 k 100 k 100 pF 3.3 k 5k 10 k 100 k 300 pF 3.3 k 5.0 k 10 k 160 k The frequencies are measured on DIP packages. 4.973 MHz 3.82 MHz 2.22 MHz 262.15 kHz 1.63 MHz 1.19 MHz 684.64 kHz 71.56 kHz 660 kHz 484.1 kHz 267.63 kHz 29.44 kHz 27% 21% 21% 31% 13% 13% 18% 25% 10% 14% 15% 19% The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5 V. 1995 Microchip Technology Inc. DS30015M-page 71 This document was created with FrameMaker 4 0 4 PIC16C5X PIC16C54/55/56/57 FIGURE 11-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20PF FIGURE 11-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF 5.5 1.8 R = 3.3k R = 3.3k 5.0 1.6 4.5 1.4 R = 5k 3.5 FOSC (MHz) R = 5k 1.2 FOSC (MHz) 4.0 3.0 1.0 0.8 R = 10k R = 10k 2.5 0.6 2.0 0.4 Measured on DIP Packages, T = 25C Measured on DIP Packages, T = 25C 0.2 1.5 R = 100k 0.0 3.0 1.0 4.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 4.5 5.0 5.5 6.0 VDD (Volts) R = 100k 0.5 0.0 3.0 3.5 6.0 FIGURE 11-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF 800 700 R = 3.3k 600 R = 5k FOSC (kHz) 500 400 R = 10k 300 200 Measured on DIP Packages, T = 25C 100 R = 100k 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30015M-page 72 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 11-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED FIGURE 11-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED 2.5 20 18 2.0 16 14 T = 25C T = 25C 12 IPD (A) IPD (A) 1.5 1.0 10 8 6 0.5 4 2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 11-6: MAXIMUM IPD vs. VDD, WATCHDOG DISABLED 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 11-8: MAXIMUM IPD vs. VDD, WATCHDOG ENABLED 60 100 50 +125C 10 +85C 40 +70C -55C IPD (mA) 0C +85C 30 1 -55C IPD (A) -40C +125C -40C +70C 20 0C 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (Volts) 0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 6.0 6.5 7.0 IPD, with WDT enabled, has two components: The leakage current which increases with higher temperature and the operating current of the WDT logic which increases with lower temperature. At -40C, the latter dominates explaining the apparently anomalous behavior. 1995 Microchip Technology Inc. DS30015M-page 73 PIC16C5X PIC16C54/55/56/57 FIGURE 11-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD 2.00 1.80 to -40C Max ( VTH (Volts) 1.60 +85C ) 5C) 1.40 2 Typ (+ 1.20 85C) + 0C to 1.00 4 Min (- 0.80 0.60 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.5 5.0 6.0 FIGURE 11-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD 4.5 5C) 4.0 3.5 max VIH, VIL (Volts) VIH 3.0 +8 C to (-40 VIH 2.5 VIH min C +25 C) +85 o t C (-40 typ 2.0 C to +85C) VIL max (-40 VIH typ +25C 1.5 1.0 5C) 0.5 VIL min (-40C to +8 0.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 5.5 6.0 Note: These input pins have Schmitt Trigger input buffers. FIGURE 11-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs. VDD 3.4 3.2 3.0 2.8 VTH (Volts) 2.6 Max 2.4 2.2 o C t (-40 C) +85 C) +25 ( Typ C) 85 2.0 Min 1.8 o+ C t 0 4 (- 1.6 1.4 1.2 1.0 2.5 DS30015M-page 74 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 11-12: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK, 25C) 10 IDD (mA) 1.0 0.1 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0.01 10k 100k 1M External Clock Frequency (Hz) 10M 100M FIGURE 11-13: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK, -40C TO +85C) 10 IDD (mA) 1.0 0.1 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0.01 10k 100k 1M 10M 100M External Clock Frequency (Hz) 1995 Microchip Technology Inc. DS30015M-page 75 PIC16C5X PIC16C54/55/56/57 FIGURE 11-14: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK -55C TO +125C) 10 IDD (mA) 1.0 0.1 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0.01 10k 100k 1M External Clock Frequency (Hz) FIGURE 11-15: WDT TIMER TIME-OUT PERIOD vs. VDD 10M 100M FIGURE 11-16: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD 50 9000 45 8000 40 7000 35 6000 30 gm (A/V) WDT period (ms) Max -40C Max +85C 25 5000 Typ +25C 4000 Max +70C 20 3000 Typ +25C Min +85C 15 2000 MIn 0C 10 100 MIn -40C 5 0 2 DS30015M-page 76 3 4 5 VDD (Volts) 6 7 2 3 4 5 VDD (Volts) 6 7 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 FIGURE 11-17: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD FIGURE 11-19: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD 45 2500 40 Max -40C Max -40C 2000 35 30 gm (A/V) gm (A/V) 1500 25 Typ +25C 20 Typ +25C 1000 15 Min +85C 500 10 Min +85C 5 0 2 0 2 3 4 5 VDD (Volts) 6 3 7 FIGURE 11-18: IOH vs. VOH, VDD = 3 V 4 5 6 7 VDD (Volts) FIGURE 11-20: IOH vs. VOH, VDD = 5 V 0 0 Min +85C -5 -10 -10 IOH (mA) IOH (mA) Min +85C Typ +25C -20 Typ +25C -15 Max -40C -30 Max -40C -20 -40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -25 0 0.5 1.0 1.5 2.0 VOH (Volts) 1995 Microchip Technology Inc. 2.5 3.0 VOH (Volts) DS30015M-page 77 PIC16C5X PIC16C54/55/56/57 FIGURE 11-21: IOL vs. VOL, VDD = 3 V FIGURE 11-22: IOL vs. VOL, VDD = 5 V 90 45 80 Max -40C 40 35 70 30 60 25 50 Max -40C IOL (mA) IOL (mA) Typ +25C Typ +25C 20 40 Min +85C 30 15 Min +85C 10 20 5 10 0 0.0 TABLE 11-2: 0.5 1.0 1.5 2.0 VOL (Volts) 2.5 3.0 0 0.0 0.5 1.5 2.0 2.5 3.0 VOL (Volts) INPUT CAPACITANCE FOR PIC16C54/56 TABLE 11-3: INPUT CAPACITANCE FOR PIC16C55/57 Typical Capacitance (pF) Pin 18L PDIP 18L SOIC RA port 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account. DS30015M-page 78 1.0 Typical Capacitance (pF) Pin 28L PDIP (600 mil) 28L SOIC RA port 5.2 4.8 RB port 5.6 4.7 RC port 5.0 4.1 MCLR 17.0 17.0 OSC1 6.6 3.5 OSC2/CLKOUT 4.6 3.5 T0CKI 4.5 3.5 All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account. 1995 Microchip Technology Inc. PIC16CR54 12.0 PIC16C5X ELECTRICAL CHARACTERISTICS - PIC16CR54 Absolute Maximum Ratings Ambient Temperature under bias ........................................................................................................... -55C to +125C Storage Temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS(2) .........................................................................................................0 to +14.0V Voltage on all other pins with respect to VSS ................................................................................ -0.6 V to (VDD + 0.6V) Total Power Dissipation(1) ....................................................................................................................................800 mW Max. Current out of VSS pin ..................................................................................................................................150 mA Max. Current into VDD pin .......................................................................................................................................50 mA Max. Current into an input pin (T0CKI only) ....................................................................................................................500 A Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................20 mA Output Clamp Current, IOK (V0 < 0 or V0 > VDD).............................................................................................................20 mA R FO E C R O NO NE MM T W E DE ND SI ED G NS Max. Output Current sunk by any I/O pin................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................20 mA Max. Output Current sourced by a single I/O port (PORTA or B)............................................................................40 mA Max. Output Current sunk by a single I/O port (PORTA or B).................................................................................50 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL) Note 2: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus, a series resistor of 50 to 100 should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss. NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1995 Microchip Technology Inc. DS30015M-page 79 This document was created with FrameMaker 4 0 4 PIC16C5X TABLE 12-1: PIC16CR54 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) OSC PIC16CR54-RC PIC16CR54-XT PIC16CR54-10 PIC16CR54-HS PIC16CR54-LP RC VDD: 2.5V to 6.25V IDD: 3.6 mA max at 6.0V IPD: 6 A max at 2.5V, WDT dis Freq: 4 MHz max N/A N/A N/A N/A N/A N/A N/A XT N/A VDD: 2.5V to 6.25V IDD: 3.6 mA max at 6.0V IPD: 6 A max at 2.5V, WDT dis Freq: 4 MHz max HS LP N/A N/A VDD: 4.5V to 5.5V IDD: 20 mA max at 5.5V IPD: 6 A max at 2.5V, WDT dis Freq: 20 MHz max N/A R FO E C R O NO NE MM T W E N DE D SI ED G NS N/A VDD: 4.5V to 5.5V IDD: 10 mA max at 5.5V IPD: 6 A max at 2.5V, WDT dis Freq: 10 MHz max N/A N/A N/A VDD: 2.0V to 6.25V IDD: 20 A max at 32 kHz, 2.0V IPD: 6 A max at 2.5V, WDT dis Freq: 200 kHz max The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended that the user select the device type from information in unshaded sections. DS30015M-page 80 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 12.1 DC Characteristics: PIC16CR54-RC, XT, HS, LP (Commercial) PIC16CR54I-RC, XT, HS, LP (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) DC Characteristics Power Supply Pins Characteristic Sym Min Typ(1) Max Units Conditions 6.25 6.25 5.5 5.5 6.25 V V V V V FOSC = DC to 4 MHz FOSC = DC to 4 MHz FOSC = DC to 10 MHz FOSC = DC to 20 MHz FOSC = DC to 200 kHz Supply Voltage PIC16CR54-RC PIC16CR54-XT PIC16CR54-10 PIC16CR54-HS PIC16CR54-LP VDD RAM Data Retention Voltage(2) VDR 1.5* V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR VSS V See Section 7.4 for details on Power-on Reset VDD Rise Rate to ensure Power-on Reset SVDD V/ms See Section 7.4 for details on Power-on Reset 2.5 2.5 4.5 4.5 2.0 R FO E C R O NO NE MM T W E DE ND SI ED G NS Supply Current(3) PIC16CR54-RC(4), XT PIC16CR54-10 PIC16CR54-HS PIC16CR54-LP 0.05* Power-Down Current Commercial(5) Power-Down Current Industrial(5) IDD 2.0 0.8 90 4.8 4.8 9.0 10.0 3.6 1.8 350 10 10 20 20 70 mA mA A mA mA mA A A FOSC = 4 MHz, VDD = 6.0V FOSC = 4 MHz, VDD = 3.0V FOSC = 200 kHz, VDD = 2.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 20 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 2.0V FOSC = 32 kHz, VDD = 6.0V 1 2 3 5 6 8* 15 25 A A A A VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled 1 2 3 3 5 8 10* 20* 18 45 A A A A A VDD = 2.5V, WDT disabled VDD = 4.0V, WDT disabled VDD = 4.0V, WDT enabled VDD = 6.0V, WDT disabled VDD = 6.0V, WDT enabled IPD IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in k. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 1995 Microchip Technology Inc. DS30015M-page 81 PIC16C5X 12.2 PIC16CR54 DC Characteristics: PIC16CR54E-RC, XT, HS, LP (Automotive) DC Characteristics Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C Sym Min Typ(1) Max Units Conditions 6.0 6.0 5.5 5.5 6.0 V V V V V FOSC = DC to 4 MHz FOSC = DC to 4 MHz FOSC = DC to 10 MHz FOSC = DC to 16 MHz FOSC = DC to 200 kHz Supply Voltage PIC16CR54E-RC PIC16CR54E-XT PIC16CR54E-10 PIC16CR54E-HS PIC16CR54E-LP VDD RAM Data Retention Voltage(2) VDR 1.5* V Device in SLEEP mode VDD Start Voltage to ensure Power-on Reset VPOR VSS V See Section 7.4 for details on Power-on Reset VDD Rise Rate to ensure Power-on Reset SVDD V/ms See Section 7.4 for details on Power-on Reset 3.25 3.25 4.5 4.5 2.5 PIC16CR54E-LP IDD R FO E C R O NO NE MM T W E N DE D SI ED G NS Supply Current(3) PIC16CR54E-RC(4) PIC16CR54E-XT PIC16CR54E-10 PIC16CR54E-HS 0.05* Power-Down Current(5) 1.8 1.8 4.8 4.8 9.0 25 3.3 3.3 10 10 20 55 mA mA mA mA mA A FOSC = 4 MHz, VDD = 5.5V FOSC = 4 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 10 MHz, VDD = 5.5V FOSC = 16 MHz, VDD = 5.5V FOSC = 32 kHz, VDD = 3.25V, WDT disabled 5 0.8 22 18 A A VDD = 3.25V, WDT enabled VDD = 3.25V, WDT disabled IPD * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in k. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS30015M-page 82 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 12.3 DC Characteristics: PIC16CR54-RC, XT, HS, LP (Commercial) PIC16CR54I-RC, XT, HS, LP (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) -40C TA +85C (industrial) Operating Voltage VDD range is described in Section 12.1. DC Characteristics All Pins Except Power Supply Pins Characteristic Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) VIL Input High Voltage I/O ports VIH Hysteresis of Schmitt Trigger inputs Input Leakage Current(2,3) I/O ports MCLR T0CKI OSC1 Typ(1) Max Units VSS VSS VSS VSS VSS 0.20 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD V V V V V 2.0 0.6 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.85 VDD VDD VDD VDD VDD VDD VDD V V V V V V Conditions Pin at hi-impedance PIC16CR54-RC only(4) PIC16CR54-XT, 10, HS, LP VDD = 3.0V to 5.5V(5) Full VDD range(5) R FO E C R O NO NE MM T W E DE ND SI ED G NS MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) Min VHYS 0.15VDD* V IIL -1 Output Low Voltage I/O ports OSC2/CLKOUT Vol Output High Voltage(3,4) I/O ports OSC2/CLKOUT VOH VDD -0.5 VDD -0.5 0.5 0.5 0.5 For VDD 5.5 V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, PIC16CR54-XT, 10, HS, LP +1 A +5 +5 +3 A A A A 0.5 0.5 V V IOL = 10 mA, VDD = 6.0V IOL = 1.9 mA, VDD = 6.0V V V IOH = -4.0 mA, VDD = 6.0V IOH = -0.8 mA, VDD = 6.0V -5 -3 -3 PIC16CR54-RC only(4) PIC16CR54-XT, 10, HS, LP * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. 1995 Microchip Technology Inc. DS30015M-page 83 PIC16C5X 12.4 PIC16CR54 DC Characteristics: PIC16CR54E-RC, XT, HS, LP (Automotive) DC Characteristics All Pins Except Power Supply Pins Characteristic Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C Operating Voltage VDD range is described in Section 12.2. Sym Input Low Voltage I/O ports MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) VIL Input High Voltage I/O ports VIH Hysteresis of Schmitt Trigger inputs Input Leakage Current(2,3) I/O ports MCLR T0CKI OSC1 Typ(1) Max Units Vss Vss Vss Vss Vss 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD V V V V V 0.45 VDD 2.0 0.36 VDD 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD VDD VDD VDD VDD VDD VDD VDD V V V V V V V Conditions Pin at hi-impedance PIC16CR54E-RC only(4) PIC16CR54E-XT, 10, HS, LP For all VDD(5) 4.0V < VDD 5.5V(5) VDD > 5.5V R FO E C R O NO NE MM T W E N DE D SI ED G NS MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) Min VHYS 0.15VDD* V IIL -1 Output Low Voltage I/O ports OSC2/CLKOUT Vol Output High Voltage (3) I/O ports OSC2/CLKOUT VOH VDD -0.7 VDD -0.7 For VDD 5.5 V VSS VPIN VDD, Pin at hi-impedance VPIN = VSS + 0.25V VPIN = VDD VSS VPIN VDD VSS VPIN VDD, PIC16CR54E-XT, 10, HS, LP 0.5 +1 A 0.5 0.5 0.5 +5 +3 +3 A A A A 0.6 0.6 V V IOL = 8.7 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V, PIC16CR54-RC V V IOH = -5.4 mA, VDD = 4.5V IOH = -1.0 mA, VDD = 4.5V, PIC16CR54-RC -5 -3 -3 PIC16CR54E-RC only(4) PIC16CR54E-XT, 10, HS, LP * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is defined as coming out of the pin. 4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 5: The user may use the better of the two specifications. DS30015M-page 84 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 12.5 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer S F Fall H High I L R FO E C R O NO NE MM T W E DE ND SI ED G NS Uppercase letters and their meanings: P Period R Rise Invalid (Hi-impedance) V Valid Low Z Hi-impedance FIGURE 12-1: LOAD CONDITIONS Pin CL = 50 pF for all pins except OSC2 CL VSS 1995 Microchip Technology Inc. 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 DS30015M-page 85 PIC16C5X 12.6 PIC16CR54 Timing Diagrams and Specifications FIGURE 12-2: EXTERNAL CLOCK TIMING - PIC16CR54 Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 12-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54 Parameter No. Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 12.1 and Section 12.2 R FO E C R O NO NE MM T W E N DE D SI ED G NS AC Characteristics Sym FOSC Characteristic External CLKIN Frequency(2) Oscillator Frequency(2) Min Typ(1) Max Units DC -- 4 MHz RC osc mode DC -- 4 MHz XT osc mode DC -- 10 MHz 10 MHz mode DC -- 20 MHz HS osc mode (Com/Indust) DC -- 16 MHz HS osc mode (Automotive) DC -- 200 kHz LP osc mode DC -- 4 MHz RC osc mode 0.1 -- 4 MHz XT osc mode 4 -- 10 MHz 10 MHz mode 4 -- 20 MHz HS osc mode (Com/Indust) 4 -- 16 MHz HS osc mode (Automotive) DC -- 200 kHz LP osc mode Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS30015M-page 86 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 TABLE 12-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54 (CON'T) AC Characteristics Parameter No. 1 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 12.1 and Section 12.2 Sym TOSC Characteristic External CLKIN Period(2) 2 3 4 Typ(1) Max Units 250 -- -- ns RC osc mode 250 -- -- ns XT osc mode 100 -- -- ns 10 MHz mode 50 -- -- ns HS osc mode (Com/Indust) 62.5 -- -- ns HS osc mode (Automotive) 5 -- -- s LP osc mode 250 -- -- ns RC osc mode 250 -- 10,000 ns XT osc mode 100 -- 250 ns 10 MHz mode 50 -- 250 ns HS osc mode (Com/Indust) 62.5 -- 250 ns HS osc mode (Automotive) 5 -- -- s LP osc mode -- 4/FOSC -- -- 50* -- -- ns XT oscillator 20* -- -- ns HS oscillator 2* -- -- s LP oscillator -- -- 25* ns XT oscillator -- -- 25* ns HS oscillator -- -- 50* ns LP oscillator Conditions R FO E C R O NO NE MM T W E DE ND SI ED G NS Oscillator Period(2) Min TCY Instruction Cycle Time(3) TosL, TosH Clock in (OSC1) Low or High Time TosR, TosF Clock in (OSC1) Rise or Fall Time * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. 1995 Microchip Technology Inc. DS30015M-page 87 PIC16C5X PIC16CR54 FIGURE 12-3: CLKOUT AND I/O TIMING - PIC16CR54 Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 12 18 16 14 I/O Pin (input) 15 17 I/O Pin (output) New Value R FO E C R O NO NE MM T W E N DE D SI ED G NS Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54 AC Characteristics Parameter No. Sym Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 12.1 and Section 12.2 Characteristic Min Typ(1) Max Units TosH2ckL OSC1 to CLKOUT(2) -- 15 30** ns TosH2ckH OSC1 to CLKOUT(2) -- 15 30** ns TckR CLKOUT rise time(2) -- 5 15** ns 13 TckF CLKOUT fall time(2) -- 5 15** ns 14 TckL2ioV CLKOUT to Port out valid(2) -- -- 40** ns TioV2ckH Port in valid before CLKOUT(2) 0.25 TCY+30* -- -- ns TckH2ioI Port in hold after CLKOUT(2) 0* -- -- ns 10 11 12 15 16 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(3) -- -- 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) TBD -- -- ns 19 TioV2osH Port input valid to OSC1 (I/O in setup time) TBD -- -- ns 20 TioR Port output rise time(3) -- 10 25** ns TioF Port output fall time(3) -- 10 25** ns 21 * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 3: See Figure 12-1 for loading conditions. DS30015M-page 88 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 FIGURE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54 VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Watchdog Timer RESET R FO E C R O NO NE MM T W E DE ND SI ED G NS Internal RESET 31 34 I/O pin (Note 1) 34 Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. TABLE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 12.1 and Section 12.2 Parameter No. Sym 30 TmcL 31 Twdt 32 TDRT 34 TioZ Characteristic Min Typ(1) Max Units MCLR Pulse Width (low) 100* -- -- ns VDD = 5.0V Watchdog Timer Time-out Period (No Prescaler) 7* 18* 30* ms VDD = 5.0V (Commercial) Device Reset Timer Period 7* 18* 30* ms VDD = 5.0V (Commercial) I/O Hi-impedance from MCLR Low -- -- 100* ns Conditions * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1995 Microchip Technology Inc. DS30015M-page 89 PIC16C5X PIC16CR54 FIGURE 12-5: TIMER0 CLOCK TIMINGS - PIC16CR54 T0CKI 40 41 42 TABLE 12-5: TIMER0 CLOCK REQUIREMENTS - PIC16CR54 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), -40C TA +85C (industrial), -40C TA +125C (automotive) Operating Voltage VDD range is described in Section 12.1 and Section 12.2 R FO E C R O NO NE MM T W E N DE D SI ED G NS AC Characteristics Parameter Sym Characteristic No. 40 Min Tt0H T0CKI High Pulse Width - No Prescaler - With Prescaler 41 Tt0L T0CKI Low Pulse Width - No Prescaler 42 Tt0P T0CKI Period - With Prescaler Typ(1) Max Units Conditions 0.5 TCY + 20* -- -- ns 10* -- -- ns 0.5 TCY + 20* -- -- ns 10* -- -- ns 20 or TCY + 40* N -- -- ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30015M-page 90 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 13.0 DC AND AC CHARACTERISTICS - PIC16CR54 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices are will properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively, where is standard deviation. FIGURE 13-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FOSC FOSC (25C) Frequency normalized to +25C 1.10 Rext 10 k Cext = 100 pF 1.08 1.06 1.02 1.00 0.98 R FO E C R O NO NE MM T W E DE ND SI ED G NS 1.04 VDD = 5.5V 0.96 0.94 VDD = 3.5V 0.92 0.90 0.88 0 10 20 25 30 40 50 60 70 T(C) TABLE 13-1: RC OSCILLATOR FREQUENCIES Cext Average Fosc @ 5V, 25C Rext Part to Part Variation 20 pF 100 pF 300 pF 3.3 k 5k 10 k 100 k 3.3 k 5k 10 k 100 k 3.3 k 5k 10 k 100 k 6.02 MHz 4.06 MHz 2.47 MHz 261 kHz 1.82 MHz 1.28 MHz 715 kHz 72.4 kHz 712.4 kHz 508 kHz 278 kHz 28 kHz 28% 25% 24% 39% 18% 21% 18% 28% 14% 13% 13% 23% Measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for full VDD range. 1995 Microchip Technology Inc. DS30015M-page 91 This document was created with FrameMaker 4 0 4 PIC16C5X PIC16CR54 FIGURE 13-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF FIGURE 13-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF 6.5 2.0 R = 3.3k R = 3.3k 6.0 1.8 5.5 1.6 5.0 1.4 R = 5k 4.5 Fosc (MHz) 1.2 R = 5k Fosc (MHz) 3.5 1.0 R FO E C R O NO NE MM T W E DE ND SI ED G NS 4.0 0.8 3.0 R = 10k 0.6 Measured on DIP Packages, T = 25C R = 10k 2.5 0.4 2.0 0.2 R = 100k 1.5 0.0 2.5 Measured on DIP Packages, T = 25C 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) 1.0 0.5 R = 100k 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30015M-page 92 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 FIGURE 13-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF FIGURE 13-5: TYPICAL IPD vs. VDD, WATCHDOG ENABLED 0.8 10 R = 3.3k 0.7 T = 25C 0.6 1.0 R = 5k IPD (A) 0.4 R FO E C R O NO NE MM T W E DE ND SI ED G NS FOSC (MHz) 0.5 0.1 R = 10k 0.3 0.2 Measured on DIP Packages, T = 25C 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.1 R = 100k 0.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 VDD (Volts) 6.0 FIGURE 13-6: MAXIMUM IPD vs. VDD, WATCHDOG ENABLED 35 30 -40C IPD (A) 25 20 15 10 +85C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) 1995 Microchip Technology Inc. DS30015M-page 93 PIC16C5X PIC16CR54 FIGURE 13-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD 2.00 VTH (Volts) 1.80 85C) to + -40C ( x a M 1.60 5C) 1.40 2 Typ (+ 0C in (-4 1.20 C) to +85 M 1.00 0.80 0.60 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 4.5 4.0 VIH, VIL (Volts) 3.5 R FO E C R O NO NE MM T W E N DE D SI ED G NS FIGURE 13-8: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD VIH 3.0 2.5 VIH 2.0 1.5 max 0.5 ) 85C 5C) 5C p +2 ty VIH min +8 C to (-40 C to +85C) VIL max (-40 VIL typ +25C 1.0 o+ C t (-40 5C) VIL min (-40C to +8 0.0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 5.5 6.0 Note: These input pins have Schmitt Trigger input buffers. FIGURE 13-9: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs. VDD 3.4 3.2 3.0 2.8 VTH (Volts) 2.6 C) 85 2.4 2.2 Max C) +25 ( p Ty ) 5C o +8 o+ C t (-40 2.0 Ct 40 1.8 (- Min 1.6 1.4 1.2 1.0 2.5 DS30015M-page 94 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 FIGURE 13-10: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25C) 10 0.1 R FO E C R O NO NE MM T W E DE ND SI ED G NS Idd (mA) 1.0 6.0 5.5 0.01 0.001 10k 5.0 4.5 4.0 3.5 3.0 2.5 100k 1M 10M External Clock Frequency (Hz) 1995 Microchip Technology Inc. DS30015M-page 95 PIC16C5X PIC16CR54 FIGURE 13-11: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK -40C TO +85C) 10000 100 R FO E C R O NO NE MM T W E N DE D SI ED G NS IDD (A) 1000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 10 10k 100k 1M 10M External Clock Frequency (Hz) DS30015M-page 96 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 FIGURE 13-13: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs. VDD 50 9000 45 8000 40 7000 35 6000 Max -40C 30 gm (A/V) Max +85C Typ +25C 25 5000 Typ +25C 4000 Max +70C 20 Min +85C R FO E C R O NO NE MM T W E DE ND SI ED G NS WDT period (ms) FIGURE 13-12: WDT TIMER TIME-OUT PERIOD vs. VDD 3000 15 2000 MIn 0C 10 100 MIn -40C 5 0 2 3 4 5 VDD (Volts) 1995 Microchip Technology Inc. 6 7 2 3 4 5 VDD (Volts) 6 7 DS30015M-page 97 PIC16C5X PIC16CR54 FIGURE 13-14: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs. VDD FIGURE 13-16: IOH vs. VOH, VDD = 3 V 45 0 Max -40C 40 -5 35 Min +85C 30 Typ +25C IOH (mA) 25 20 -15 15 R FO E C R O NO NE MM T W E DE ND SI ED G NS gm (A/V) -10 Typ +25C Max -40C Min +85C 10 5 -20 -25 0.0 0 2 3 4 5 VDD (Volts) 6 7 1.0 1.5 2.0 2.5 3.0 VOH (Volts) FIGURE 13-15: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD 2500 0.5 FIGURE 13-17: IOH vs. VOH, VDD = 5 V 0 -5 2000 Max -40C -10 Min +85C gm (A/V) IOH (mA) -15 1500 Typ +25C 1000 -20 Typ +25C -25 -30 Min +85C 500 -35 0 2 3 4 5 VDD (Volts) DS30015M-page 98 6 7 -40 1.5 Max -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOH (Volts) 1995 Microchip Technology Inc. PIC16C5X PIC16CR54 FIGURE 13-18: IOL vs. VOL, VDD = 3 V FIGURE 13-19: IOL vs. VOL, VDD = 5 V 45 90 80 Max -40C 35 70 30 60 25 Typ +25C 20 Max -40C Typ +25C 50 40 Min +85C 30 R FO E C R O NO NE MM T W E DE ND SI ED G NS 15 IOL (mA) IOL (mA) 40 Min +85C 10 5 0 0.0 20 10 0.5 1.0 1.5 2.0 2.5 3.0 0 0.0 0.5 VOL (Volts) 1.0 1.5 2.0 2.5 3.0 VOL (Volts) TABLE 13-2: INPUT CAPACITANCE FOR PIC16CR54 Typical Capacitance (pF) Pin 18L PDIP 18L SOIC RA, RB port 5.0 4.3 MCLR 2.0 2.0 OSC1, OSC2/CLKOUT 4.0 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account. 1995 Microchip Technology Inc. DS30015M-page 99 PIC16C5X PIC16CR54 R FO E C R O NO NE MM T W E DE ND SI ED G NS NOTES: DS30015M-page 100 1995 Microchip Technology Inc. PIC16C5X 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 18-Lead PDIP Example MMMMMMMMMMMMXXX MMMMMMMMXXXXXXX AABB CDE 28-Lead Skinny PDIP (.300") PIC16C56RCI/P456 9523 CBA Example MMMMMMMMMMMMMMMMM XXXXXXXXXXXXXXXXX PIC16C55RCI/P456 AABB CDE 28-Lead PDIP (.600") 9523 CBA Example MMMMMMMMMMMMXXX MMMMMMMMXXXXXXX XXXXXXXXXXXXXXX AABB CDE PIC16C55XTI/P126 9542 CDA Legend: MM...M XX...X AA BB C Microchip part number information Customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1995 Microchip Technology Inc. DS30015M-page 101 This document was created with FrameMaker 4 0 4 PIC16C5X 18-Lead SOIC MMMMMMMMM XXXXXXXXX AABB CDE 28-Lead SOIC MMMMMMMMMMMMMMMMMMXX XXXXXXXXXXXXXXXXXXXX AABB CDE 20-Lead SSOP MMMMMMMM XXXXXXXX AABB CDE 28-Lead SSOP MMMMMMMMMMMM XXXXXXXXXXXX AABB CDE Example PIC16C54XTI/S0218 9518 CDK Example PIC16C57-XT/SO 9515 CBK Example PIC16C54 XTI/218 9520 CBP Example PIC16C57XT/SS123 9525 CBK Legend: MM...M XX...X AA BB C Microchip part number information Customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30015M-page 102 1995 Microchip Technology Inc. PIC16C5X 18-Lead CERDIP Windowed Example MMMMMMMM MMMMMMMM AABB CDE 28-Lead CERDIP Skinny Windowed PIC16C54 /JW 9501 CBA Example MMMMMMMMMMMMMM XXXXXXXXXXXXXX AABBCDE 28-Lead CERDIP Windowed MMMMMMMMMM MMMMMM AABB CDE PIC16C57 /JW 9338 CCT Example PIC16C57 /JW 9538 CBA Legend: MM...M XX...X AA BB C Microchip part number information Customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week `01') Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1995 Microchip Technology Inc. DS30015M-page 103 PIC16C5X 14.2 18-Lead Plastic Dual In-Line (PDIP) - 300 mil N C E1 E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max 0 A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 - 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.620 6.096 2.489 7.620 7.874 3.048 18 0.889 0.127 DS30015M-page 104 Inches Notes Min Max 10 0 10 4.064 - 3.810 0.559 1.524 0.381 23.495 20.320 8.255 7.112 2.591 7.620 9.906 3.556 18 - - - 0.015 0.120 0.014 0.060 0.008 0.885 0.800 0.300 0.240 0.098 0.300 0.310 0.120 18 0.035 0.005 0.160 - 0.150 0.022 0.060 0.015 0.925 0.800 0.325 0.280 0.102 0.300 0.390 0.140 18 - - Reference Typical Reference Typical Reference Notes Reference Typical Reference Typical Reference 1995 Microchip Technology Inc. PIC16C5X 14.3 28-Lead Plastic Dual In-Line (PDIP) - 300 mil N E1 E C eA eB Pin No. 1 Indicator Area B2 D B1 S Base Plane Seating Plane L Detail A B3 A1 A2 A e1 B Detail A D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max 0 A A1 A2 B B1 B2 B3 C D D1 E E1 e1 eA eB L N S 3.632 0.381 3.175 0.406 1.016 0.762 0.203 0.203 34.163 33.020 7.874 7.112 2.540 7.874 8.128 3.175 28 0.584 1995 Microchip Technology Inc. Inches Notes Min Max 10 0 10 4.572 - 3.556 0.559 1.651 1.016 0.508 0.331 35.179 33.020 8.382 7.493 2.540 7.874 9.652 3.683 1.220 0.143 0.015 0.125 0.016 0.040 0.030 0.008 0.008 1.385 1.300 0.310 0.280 0.100 0.310 0.320 0.125 28 0.023 0.180 - 0.140 0.022 0.065 0.040 0.020 0.013 1.395 1.300 0.330 0.295 0.100 0.310 0.380 0.145 0.048 Typical 4 places 4 places Typical Reference Typical Reference Notes Typical 4 places 4 places Typical Reference Typical Reference DS30015M-page 105 PIC16C5X 14.4 28-Lead Plastic Dual In-Line (PDIP) - 600 mil N E1 E C eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min 0 10 0 10 A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 - 0.508 3.175 0.355 1.270 0.203 35.052 33.020 15.240 12.827 2.489 15.240 15.240 2.921 28 0.889 0.508 5.080 - 4.064 0.559 1.778 0.381 37.084 33.020 15.875 13.970 2.591 15.240 17.272 3.683 28 - - - 0.020 0.125 0.014 0.050 0.008 1.380 1.300 0.600 0.505 0.098 0.600 0.600 0.115 28 0.035 0.020 0.200 - 0.160 0.022 0.070 0.015 1.460 1.300 0.625 0.550 0.102 0.600 0.680 0.145 28 - - DS30015M-page 106 Max Inches Notes Typical Typical Reference Typical Reference Min Max Notes Typical Typical Reference Typical Reference 1995 Microchip Technology Inc. PIC16C5X 14.5 18-Lead Plastic Surface Mount (SOIC) - 300 mil e B h x 45 N Index Area E H C Chamfer h x 45 L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Symbol Min Max Inches Notes Min Max 0 8 0 8 A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.007 0.381 0.406 18 - 2.642 0.300 0.483 0.318 11.735 7.595 1.270 10.643 0.762 1.143 18 0.102 0.093 0.004 0.014 0.009 0.447 0.292 0.050 0.394 0.015 0.016 18 - 0.104 0.012 0.019 0.013 0.462 0.299 0.050 0.419 0.030 0.045 18 0.004 1995 Microchip Technology Inc. Reference Notes Reference DS30015M-page 107 PIC16C5X 14.6 28-Lead Plastic Surface Mount (SOIC) - 300 mil e B h x 45 N Index Area E H C Chamfer h x 45 L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Symbol Min Max Inches Notes Min Max 0 8 0 8 A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 17.703 7.416 1.270 10.007 0.381 0.406 28 - 2.642 0.300 0.483 0.318 18.085 7.595 1.270 10.643 0.762 1.143 28 0.102 0.093 0.004 0.014 0.009 0.697 0.292 0.050 0.394 0.015 0.016 28 - 0.104 0.012 0.019 0.013 0.712 0.299 0.050 0.419 0.030 0.045 28 0.004 DS30015M-page 108 Typical Notes Typical 1995 Microchip Technology Inc. PIC16C5X 14.7 20-Lead Plastic Surface Mount (SSOP) - 209 mil N Index area E H C L 1 2 3 B e A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Symbol Min Max 0 A A1 B C D E e H L N CP 1.730 0.050 0.250 0.130 7.070 5.200 0.650 7.650 0.550 20 - 1995 Microchip Technology Inc. Inches Notes Min Max 8 0 8 1.990 0.210 0.380 0.220 7.330 5.380 0.650 7.900 0.950 20 0.102 0.068 0.002 0.010 0.005 0.278 0.205 0.026 0.301 0.022 20 - 0.078 0.008 0.015 0.009 0.289 0.212 0.026 0.311 0.037 20 0.004 Reference Notes Reference DS30015M-page 109 PIC16C5X 14.8 28-Lead Plastic Surface Mount (SSOP) - 209 mil N Index area E H C L 1 2 3 B e A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Symbol Min Max Inches Notes Min Max 0 8 0 8 A A1 B C D E e H L N CP 1.730 0.050 0.250 0.130 10.070 5.200 0.650 7.650 0.550 28 - 1.990 0.210 0.380 0.220 10.330 5.380 0.650 7.900 0.950 28 0.102 0.068 0.002 0.010 0.005 0.396 0.205 0.026 0.301 0.022 28 - 0.078 0.008 0.015 0.009 0.407 0.212 0.026 0.311 0.037 28 0.004 DS30015M-page 110 Reference Notes Reference 1995 Microchip Technology Inc. PIC16C5X 14.9 18-Lead Ceramic Dual In-Line (CERDIP) with Window - 300 mil N C E1 E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A3 A e1 B A2 D1 Package Group: Ceramic Dual In-Line (CDP) Millimeters Symbol Min Max 0 A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 -- 0.381 3.810 3.810 0.355 1.270 0.203 22.352 20.320 7.620 5.588 2.540 7.366 7.620 3.175 18 0.508 0.381 1995 Microchip Technology Inc. Inches Notes Min Max 10 0 10 5.080 1.7780 4.699 4.445 0.585 1.651 0.381 23.622 20.320 8.382 7.874 2.540 8.128 10.160 3.810 18 1.397 1.270 -- 0.015 0.150 0.150 0.014 0.050 0.008 0.880 0.800 0.300 0.220 0.100 0.290 0.300 0.125 18 0.020 0.015 0.200 0.070 0.185 0.175 0.023 0.065 0.015 0.930 0.800 0.330 0.310 0.100 0.320 0.400 0.150 18 0.055 0.050 Typical Typical Reference Reference Typical Notes Typical Typical Reference Reference Typical DS30015M-page 111 PIC16C5X 14.10 28-Lead Ceramic Dual In-Line (CERDIP) with Window - 300 mil) N E1 E C Pin No. 1 Indicator Area eA eB D D1 Base Plane Seating Plane L B1 A1 A2 A e1 B D2 Package Group: Ceramic Dual In-Line (CDP) Millimeters Symbol Min Max 0 A A1 A2 B B1 C D D2 E E1 e eA eB L N D1 3.30 0.38 2.92 0.35 1.14 0.20 34.54 32.97 7.62 6.10 2.54 7.62 -- 2.92 28 0.13 DS30015M-page 112 Inches Notes Min Max 10 0 10 5.84 -- 4.95 0.58 1.78 0.38 37.72 33.07 8.25 7.87 2.54 7.62 11.43 5.08 28 -- .130 0.015 0.115 0.014 0.045 0.008 1.360 1.298 0.300 0.240 0.100 0.300 -- 0.115 28 0.005 0.230 -- 0.195 0.023 0.070 0.015 1.485 1.302 0.325 0.310 0.100 0.300 0.450 0.200 28 -- Typical Typical Reference Typical Reference Notes Typical Typical Reference Typical Reference 1995 Microchip Technology Inc. PIC16C5X 14.11 28-Lead Ceramic Dual In-Line (CERDIP) with Window - 600 mil N E1 E C Pin No. 1 Indicator Area eA eB D S S1 Base Plane Seating Plane L B1 A1 A3 A A2 e1 B D1 Package Group: Ceramic Dual In-Line (CDP) Millimeters Symbol Min Max 0 A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 -- 0.381 3.810 3.810 0.355 1.270 0.203 36.195 33.020 15.240 12.954 2.540 14.986 15.240 3.175 28 1.016 0.381 1995 Microchip Technology Inc. Inches Notes Min Max 10 0 10 5.461 1.524 4.699 4.445 0.585 1.651 0.381 37.465 33.020 15.875 15.240 2.540 15.748 18.034 3.810 28 2.286 1.778 -- 0.015 0.150 0.150 0.014 0.050 0.008 1.425 1.300 0.600 0.510 0.100 0.590 0.600 0.125 28 0.040 0.015 0.215 0.060 0.185 0.175 0.023 0.065 0.015 1.475 1.300 0.625 0.600 0.100 0.620 0.710 0.150 28 0.090 0.070 Typical Typical Reference Typical Reference Notes Typical Typical Reference Typical Reference DS30015M-page 113 PIC16C5X NOTES: DS30015M-page 114 1995 Microchip Technology Inc. PIC16C5X APPENDIX A: COMPATIBILITY APPENDIX B: WHAT'S NEW To convert code written for PIC16CXX to PIC16C5X, the user should take the following steps: B.1 1. The format of this data sheet has been changed to be consistent with other product families. This ensures that important topics are covered across all PIC16/17 families. Here is an overview list of new features: 2. 3. 4. 5. 6. 7. Check any CALL, GOTO or instructions that modify the PC to determine if any program memory page select operations (PA2, PA1, PA0 bits) need to be made. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any special function register page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to proper value for processor used. Remove any use of the ADDLW and SUBLW instructions. Rewrite any code segments that use interrupts. Format * Data Sheet Structure / Outline * Consistent Figures and Tables B.2 Additions Items that have been added to this data sheet are: * PIC16CR54 data * PIC16C5X-10 data * PIC16C5X/JW package information 1995 Microchip Technology Inc. DS30015M-page 115 This document was created with FrameMaker 4 0 4 PIC16C5X APPENDIX C: WHAT'S CHANGED Changes to this version of the PIC16C5X data sheet are: * Correction of the 28-lead SSOP package pin-out * Inclusion of errata sheet information DS30015M-page 116 1995 Microchip Technology Inc. um -- 20 1995 Microchip Technology Inc. This document was created with FrameMaker 4 0 4 -- -- -- -- 20 20 20 20 20 20 PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A PIC16CR58B(1) 2K 2K -- 2K 2K -- 1K -- -- 512 512 512 -- -- e 73 73 73 72 72 72 25 25 24 25 25 ( y M (M n 25 em or m io 25 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 es ) ) 12 12 12 20 20 20 12 12 20 12 12 12 12 12 od u Pr M Da ta (s le og Hz r ) a (w m M o r ds em ) or y RA 25 ns 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.25 ng 33 33 33 33 33 33 33 33 33 33 33 33 33 33 ) Features 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin DIP, SOIC, SSOP 28-pin DIP, SOIC, SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP r ns All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. Note 1: Please contact your local sales office for availability of these devices. 2: Not recommended for new designs. 2K 2K 20 PIC16CR56(1) PIC16CR57A -- 20 PIC16C56 (2) 1K 20 PIC16C55 PIC16CR54B 512 -- 20 PIC16CR54A (1) -- 20 PIC16CR54 (2) 512 512 M 20 im 20 ax PIC16C54A ge Ra N ts ol be ra t F r EP eq ue RO nc y RO M of O M p PIC16C54 e (V um tr ns of I by t er M Ti Pi I/O Peripherals ta Vo l io uc t Pa Memory s ge TABLE D-1: ck a Clock PIC16C7X APPENDIX D: PIC16/17 MICROCONTROLLERS PIC16C5X FAMILY OF DEVICES DS30390B-page 117 DS30390B-page 118 (M em Memory ge lta Peripherals Features PIC16C620 20 512 80 TMR0 2 Yes 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC; 20-pin SSOP PIC16C621 20 1K 80 TMR0 2 Yes 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC; 20-pin SSOP PIC16C622 20 2K 128 TMR0 2 Yes 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC; 20-pin SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7. am M g in m m p ) O ra gr ts Vo s) of ro ol og e te r y c P V s y c t ( n e n s) lP (b se rc re ia ue e( ge y s) e u l e r q r ( f n o r u e e R o a o S s Fr Re R od ut tS at em pt ins ge e M ui M al -o ar u a um M g c r n r n O p r k r r i P e im c ta R lta m te te ow m -C ax In Pa In I/O Da Vo Ti EP M Co In Br n tio a er y or TABLE D-2: ) Hz Clock PIC16C7X PIC16C62X FAMILY OF DEVICES 1995 Microchip Technology Inc. 1995 Microchip Technology Inc. 20 20 20 20 20 20 20 PIC16C62A(1) PIC16CR62(1) PIC16C63(1) PIC16C64 PIC16C64A(1) PIC16CR64(1) PIC16C65 4K 4K -- 2K 2K 4K -- 2K 2K 1K -- -- 2K -- -- -- 2K -- -- -- TMR0 192 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 36 -- 2 8 11 2 SPI/I2C, Yes USART 8 8 10 7 7 7 3 Yes 1 SPI/I2C Yes Yes 1 SPI/I2C 1 SPI/I2C -- -- -- -- -- 2 SPI/I2C, USART 1 SPI/I2C 1 SPI/I2C 1 SPI/I C -- 33 33 33 33 22 22 22 22 13 3.0-6.0 3.0-6.0 3.0-6.0 3.0-6.0 3.0-6.0 3.0-6.0 3.0-6.0 3.0-6.0 3.0-6.0 Yes Yes Yes Yes Yes Yes Yes Yes Yes 28-pin SDIP, SOIC, SSOP 18-pin DIP, SOIC 40-pin DIP; 44-pin PLCC, MQFP -- 40-pin DIP; 44-pin PLCC, MQFP Yes 40-pin DIP; 44-pin PLCC, MQFP Yes 40-pin DIP; 44-pin PLCC, MQFP, TQFP -- Yes 28-pin SDIP, SOIC Yes 28-pin SDIP, SOIC, SSOP Yes 28-pin SDIP, SOIC, SSOP -- -- 192 TMR0, 2 SPI/I2C, Yes 11 33 3.0-6.0 Yes Yes 40-pin DIP; TMR1, TMR2 USART 44-pin PLCC, MQFP, TQFP All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability. All PIC16CXX family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local sales office for availability of these devices. 20 20 PIC16C62 PIC16C65A(1) 20 TABLE D-3: PIC16C61 Memory Peripherals Features ) s y ( le or (M T) g n du em o in it o AR M a M m S r e U m m M p , ) ra ra O ) 2C W ts of og og ol /I /P t es r I r t r y e V y s r P ) ( et lP nc SP Po rce (b (s e pa ue es y ria )( le u m ve ng s e R u o ( or eq o a a t r l t C F R tS od or tS s es em ou lS e/ ui M M um up Pin lP ge nag rM ur lle rc O r i t a a k e r m a a w i M t i R p t l c r r o m -C te ax Se In In Br Da Pa Ca EP RO Ti Pa Vo I/O M ) Hz Clock PIC16C7X PIC16C6X FAMILY OF DEVICES DS30390B-page 119 DS30390B-page 120 (M M o em Memory ( le u od ) RT Peripherals s) s el n an Features 2K 20 PIC16C71A(1) PIC16C72(1) 36 68 36 TMR0 TMR0 TMR0 -- -- -- -- -- -- -- -- -- 4 4 4 4 4 4 13 13 13 3.0-6.0 3.0-6.0 3.0-6.0 Yes Yes Yes Yes 18-pin DIP, SOIC; 20-pin SSOP -- 18-pin DIP, SOIC Yes 18-pin DIP, SOIC; 20-pin SSOP Yes 28-pin SDIP, SOIC, SSOP 128 TMR0, 1 SPI/I2C -- 5 8 22 3.0-6.0 Yes TMR1, TMR2 5 11 22 3.0-6.0 Yes -- 28-pin SDIP, SOIC PIC16C73 20 4K 192 TMR0, 2 SPI/I2C, -- TMR1, TMR2 USART 20 4K 192 TMR0, 2 SPI/I2C, -- 5 11 22 3.0-6.0 Yes Yes 28-pin SDIP, SOIC PIC16C73A(1) TMR1, TMR2 USART PIC16C74 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 3.0-6.0 Yes -- 40-pin DIP; TMR1, TMR2 44-pin PLCC, MQFP USART 2 (1) 20 4K 192 TMR0, 2 SPI/I C, Yes 8 12 33 3.0-6.0 Yes Yes 40-pin DIP; PIC16C74A TMR1, TMR2 44-pin PLCC, MQFP, TQFP USART All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local sales office for availability of these devices. 1K 1K 20 20 PIC16C71 512 20 PIC16C70(1) A US g in M m m h m a , M C ) r a O 2C lts it) gr og tes) of /I PW rt -b ro Pr Vo s e/ SPI y o cy 8 ( ) P r e ( n b P et l c ( (s r pa s) ( ue ge es ur le ria te ry ve n r m o u ( e eq R o a t a r e o l S v F R od or tS s es ut /C it em lS on rup M -o re al P ag um M in ge cu rM lle n C O r u k r a i i m P t e a a i t c r r t R l p D te ow m -C ax Pa Se In A/ Pa I/O Da Vo Ti EP M In Br Ca pe ra n tio ry TABLE D-4: ) Hz Clock PIC16C7X PIC16C7X FAMILY OF DEVICES 1995 Microchip Technology Inc. 1995 Microchip Technology Inc. 10 PIC16C84A(1) 1K 1K -- 512 -- -- 512 -- 68 36 36 36 M RO M O R EP E F p O (M Memory Peripherals Features 64 64 64 64 TMR0 TMR0 TMR0 TMR0 4 4 4 4 13 13 13 13 Yes Yes Yes Yes 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC g in m m m ) ra s) ra ) ts te og og ol es r y r t V b P y s P ) ( ( l e s (b e ia M rc e( y O ng er ul ou or a R S d S s R P o it t em s M ge cu M EE up Pin ge a r r r i a k e r ta ta lt c -C m te Da Da In Ti Pa In Vo I/O o em M ry PIC16CR84(1) 10 -- 1K 68 64 TMR0 4 13 Yes 2.0-6.0 18-pin DIP, SOIC All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability. All PIC16CXX family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local sales office for availability of these devices. 10 10 PIC16C84 10 PIC16CR83(1) PIC16C83(1) M um im ax y nc ue q re of er n io at ) Clock TABLE D-5: Hz PIC16C7X PIC16C8X FAMILY OF DEVICES DS30390B-page 121 M 25 im um eq ue RO O of M nc y M 232 M pe Da ra Pr tio ta og n r (M em am Hz M ) RA or em or y (b y Ti m e( s) du l C a p PW tur e M s s y s) te o M er Fr EP 2K l Features ck a ge s m in g lts es s )( Se ax TMR0,TMR1, 2 2 Yes Yes 11 33 4.5-5.5 Yes Yes 55 40-pin DIP; TMR2,TMR3 44-pin PLCC, MQFP PIC17C43 25 4K 454 TMR0,TMR1, 2 2 Yes Yes 11 33 2.5-6.0 Yes Yes 58 40-pin DIP; TMR2,TMR3 44-pin PLCC, TQFP PIC17C44 25 8K 454 TMR0,TMR1, 2 2 Yes Yes 11 33 2.5-6.0 Yes Yes 58 40-pin DIP; TMR2,TMR3 44-pin PLCC, TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. PIC17C42 t(s Ex ) t t US A er RT er ru In na l t Po r ria Peripherals ng e n pt So u pt er ru In rc ns Pi I/O Ra ge (V o Si M n Memory ta Vo l ) r st In In gl e io t uc t tip ul ia Se r ui Ci rc ly ro be m r og lP r Nu am r st fI n ns io DS30390B-page 122 uc t TABLE D-6: Pa Clock PIC16C7X PIC17CXX FAMILY OF DEVICES 1995 Microchip Technology Inc. PIC16C7X D.1 Pin Compatibility Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55. Pin compatibility does not mean that the devices offer the same features. As an example, the PIC16C54 is pin compatible with the PIC16C71, but does not have an A/D converter, weak pull-ups on PORTB, or interrupts. TABLE D-7: PIN COMPATIBLE DEVICES Pin Compatible Devices Package PIC16C54, PIC16C54A, PIC16CR54, PIC16CR54A, PIC16CR54B, PIC16C56, PIC16CR56, PIC16C58A, PIC16CR58A, PIC16CR58B, PIC16C61, PIC16C620, PIC16C621, PIC16C622, PIC16C70, PIC16C71, PIC16C71A PIC16C83, PIC16CR83, PIC16C84, PIC16C84A, PIC16CR84 18 pin (20 pin) PIC16C55, PIC16CR55, PIC16C57, PIC16CR57A, PIC16CR57B 28 pin PIC16C62, PIC16CR62, PIC16C62A, PIC16C63, PIC16C72, PIC16C73, PIC16C73A 28 pin PIC16C64, PIC16CR64, PIC16C64A, PIC16C65, PIC16C65A, PIC16C74, PIC16C74A 40 pin PIC17C42, PIC17C43, PIC17C44 40 pin 1995 Microchip Technology Inc. DS30390B-page 123 PIC16C7X NOTES: DS30390B-page 124 1995 Microchip Technology Inc. PIC16C5X INDEX I A Absolute Maximum Ratings ............................................... 57 ALU ...................................................................................... 7 Applications .......................................................................... 3 Architectural Overview ......................................................... 7 Assembler .......................................................................... 54 B Block Diagram On-Chip Reset Circuit ................................................ 31 PIC16C5X Series ......................................................... 8 Timer0 ........................................................................ 23 TMR0/WDT Prescaler ................................................ 26 Watchdog Timer ......................................................... 35 Brown-Out Protection Circuit ............................................. 36 C C Compiler (MP-C) ...................................................... 51, 55 Carry .................................................................................... 7 Clocking Scheme ............................................................... 11 Code Protection ........................................................... 27, 37 Configuration Bits ............................................................... 27 Configuration Word PIC16C54/CR54/C55/C56/C57 ................................. 27 D DC Characteristics ..................................... 59, 60, 61, 62, 63 Development Support ........................................................ 51 Development Systems ....................................................... 55 Development Tools ............................................................ 51 Device Drawings 18-Lead Ceramic Dual In-Line (CERDIP) with Window - 300 mil .............................................. 111 18-Lead Plastic Dual In-Line (PDIP) - 300 mil ......... 104 18-Lead Plastic Surface Mount (SOIC) - 300 mil ..... 107 20-Lead Plastic Surface Mount (SSOP) - 209 mil .... 109 28-Lead Ceramic CERDIP Dual In-line with Window (300 mil)) ............................................. 112 28-Lead Ceramic Dual In-Line (CERDIP) with Window - 600 mil .............................................. 113 28-Lead Plastic Dual In-Line (PDIP) - 300 mil ......... 105 28-Lead Plastic Dual In-Line (PDIP) - 600 mil ......... 106 28-Lead Plastic Surface Mount (SOIC) - 300 mil ..... 108 28-Lead Plastic Surface Mount (SSOP) - 209 mil .... 110 Device Varieties ................................................................... 5 Digit Carry ............................................................................ 7 Dynamic Data Exchange (DDE) ........................................ 51 E Electrical Characteristics .................................................... 57 External Power-On Reset Circuit ....................................... 32 F Family of Devices ................................................................. 4 PIC16C5X ................................................................ 117 PIC17CXX ................................................................ 122 Features ............................................................................... 1 FSR .............................................................................. 20, 31 Fuzzy Logic Dev. System (fuzzyTECH-MP) ............. 51, 55 I/O Interfacing .................................................................... 21 I/O Ports ............................................................................ 21 I/O Programming Considerations ...................................... 22 ID Locations ....................................................................... 37 ID locations ........................................................................ 27 INDF ............................................................................ 20, 31 Indirect Data Addressing ................................................... 20 Instruction Cycle ................................................................ 11 Instruction Flow/Pipelining ................................................. 11 Instruction Set Summary ................................................... 40 Integrated .......................................................................... 54 L Loading of PC .................................................................... 18 Loading of PC Branch Instructions .................................... 18 M MCLR ................................................................................ 31 Memory Organization ........................................................ 13 Data Memory ............................................................. 13 Program Memory ....................................................... 13 MPASM Assembler ..................................................... 51, 54 MP-C C Compiler .............................................................. 55 MPSIM Software Simulator ......................................... 51, 55 O One-Time-Programmable (OTP) Devices ............................5 OPTION Register .............................................................. 17 OSC selection .................................................................... 27 Oscillator Configurations ................................................... 28 Oscillator Types HS .............................................................................. 28 LP .............................................................................. 28 RC ............................................................................. 28 XT .............................................................................. 28 P Packaging Information ..................................................... 101 PCL .................................................................................... 31 PIC16C5X DC and AC Characteristics .............................. 71 PICDEM-1 Low-Cost PIC16/17 Demo Board .............. 51, 53 PICDEM-2 Low-Cost PIC16CXX Demo Board ............ 51, 53 PICMASTER Probes ......................................................... 52 PICMASTER System Configuration .................................. 51 PICMASTER RT In-Circuit Emulator .............................. 51 PICSTART Low-Cost Development System ............. 51, 53 Pin Compatible Devices .................................................. 123 Pinout Description ......................................................... 9, 10 POR Oscillator Start-Up Timer (OST) .................... 27, 32, 34 PD ........................................................................ 30, 36 Power-On Reset (POR) ................................. 27, 31, 32 TO ........................................................................ 30, 36 PORTA ........................................................................ 21, 31 PORTB ........................................................................ 21, 31 PORTC ........................................................................ 21, 31 Power-Down Mode ............................................................ 37 Prescaler ........................................................................... 26 PRO MATE Universal Programmer .......................... 51, 53 Q Quick-Turnaround-Production (QTP) Devices ......................5 1995 Microchip Technology Inc. DS30015M-page 125 This document was created with FrameMaker 4 0 4 PIC16C5X R RC Oscillator ...................................................................... 30 Read Modify Write .............................................................. 22 Reset ............................................................................ 27, 30 Reset on Brown-Out ........................................................... 36 S Serialized Quick-Turnaround-Production (SQTP) Devices .. 5 SLEEP .......................................................................... 27, 37 Software Simulator (MPSIM) .............................................. 55 Special Features of the CPU .............................................. 27 STATUS ......................................................................... 7, 31 STATUS Word Register ..................................................... 16 Summary of Port Registers ................................................ 21 T Timer0 Switching Prescaler Assignment ................................ 26 Timer0 ........................................................................ 23 Timer0 (TMR0) Module .............................................. 23 TMR0 with External Clock .......................................... 25 Timing Diagrams and Specifications ............................ 65, 86 Timing Parameter Symbology and Load Conditions .... 64, 85 TRIS Registers ................................................................... 21 U UV Erasable Devices ........................................................... 5 LIST OF EXAMPLES Example 3-1: Instruction Pipeline Flow ............................ 11 Example 4-1: Indirect Addressing..................................... 20 Example 4-2: How To Clear RAM Using Indirect Addressing ................................................. 20 Example 5-1: Read-Modify-Write Instructions on an I/O Port ....................................................... 22 Example 6-1: Changing Prescaler (Timer0WDT).......... 26 Example 6-2: Changing Prescaler (WDTTimer0).......... 26 LIST OF FIGURES Figure 3-1: Figure 3-2: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: W W ........................................................................................ 31 Wake-up from SLEEP ........................................................ 37 Watchdog Timer (WDT) ............................................... 27, 34 Period ......................................................................... 34 Programming Considerations .................................... 34 Z Zero bit ................................................................................. 7 Figure 4-10: Figure 4-11: Figure 4-12: Figure 5-1: Figure 5-2: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: Figure 7-10: Figure 7-11: DS30015M-page 126 PIC16C5X Series Block Diagram .................... 8 Clock/Instruction Cycle .................................. 11 PIC16C54/CR54/C55 Program Memory Map and Stack....................................................... 13 PIC16C56 Program Memory Map and Stack....................................................... 13 PIC16C57 Program Memory Map and Stack....................................................... 13 PIC16C54/CR54/C56 Register File Map ....... 14 PIC16C55 Register File Map ......................... 14 PIC16C57 Register File Map ......................... 14 STATUS Register (Address:03h)................... 16 OPTION Register........................................... 17 Loading of PC Branch Instructions PIC16C54/CR54/C55 .................................... 18 Loading of PC Branch Instructions PIC16C56 ...................................................... 18 Loading of PC Branch Instructions PIC16C57 ...................................................... 18 Direct/Indirect Addressing.............................. 20 Equivalent Circuit for a Single I/O Pin............ 21 Successive I/O Operation .............................. 22 Timer0 Block Diagram ................................... 23 Electrical Structure of T0CKI Pin ................... 23 Timer0 Timing: Internal Clock/No Prescale ............................ 24 Timer0 Timing: Internal Clock/Prescale 1:2............................ 24 Timer0 Timing With External Clock ............... 25 Block Diagram of the Timer0/WDT Prescaler 26 Configuration Word for PIC16C54/CR54/C55/C56/C57 ..................... 27 Crystal Operation or Ceramic Resonator (HS, XT or LP OSC Configuration) ................ 28 External Clock Input Operation (HS, XT or LP OSC Configuration) ................ 28 External Parallel Resonant Crystal Oscillator Circuit............................................. 29 External Series Resonant Crystal Oscillator Circuit............................................. 29 RC Oscillator Mode........................................ 30 Simplified Block Diagram of On-Chip Reset Circuit.................................... 31 ElectriCal Structure of MCLR/VPP Pin ........... 32 External Power-On Reset Circuit (For Slow VDD Power-Up).............................. 32 Time-Out Sequence on Power-Up (MCLR Not Tied to VDD) ................................ 33 Time-Out Sequence on Power-Up (MCLR Tied to VDD): Fast VDD Rise Time..... 33 1995 Microchip Technology Inc. PIC16C5X Figure 7-12: Time-Out Sequence on Power-Up (MCLR Tied to VDD): Slow VDD Rise Time .... 33 Figure 7-13: Watchdog Timer Block Diagram .................... 35 Figure 7-14: Brown-Out Protection Circuit 1 ...................... 36 Figure 7-15: Brown-Out Protection Circuit 2 ...................... 36 Figure 8-1: General Format for Instructions ..................... 39 Figure 9-1: PICMASTER System Configuration............... 51 Figure 10-1: Load Conditions - PIC16C54/55/56/57 .......... 64 Figure 10-2: External Clock Timing - PIC16C54/55/56/57 . 65 Figure 10-3: CLKOUT and I/O Timing PIC16C54/55/56/57 ....................................... 67 Figure 10-4: Reset, Watchdog Timer, and Device Reset Timer Timing - PIC16C54/55/56/57 ............... 68 Figure 10-5: Timer0 Clock Timings - PIC16C54/55/56/57 . 69 Figure 11-1: Typical RC Oscillator Frequency vs. Temperature .................................................. 71 Figure 11-2: Typical RC Oscillator Frequency vs. VDD, CEXT = 20PF .......................................... 72 Figure 11-3: Typical RC Oscillator Frequency vs. VDD, CEXT = 100 PF ....................................... 72 Figure 11-4: Typical RC Oscillator Frequency vs. VDD, CEXT = 300 PF ....................................... 72 Figure 11-5: Typical IPD vs. VDD, Watchdog Disabled........................................ 73 Figure 11-6: Maximum IPD vs. VDD, Watchdog Disabled........................................ 73 Figure 11-7: Typical IPD vs. VDD, Watchdog Enabled......................................... 73 Figure 11-8: Maximum IPD vs. VDD, Watchdog Enabled......................................... 73 Figure 11-9: VTH (Input Threshold Voltage) of I/O Pins vs. VDD ................................................................ 74 Figure 11-10:VIH, VIL of MCLR, T0CKI and OSC1 (in RC Mode) vs. VDD .................................... 74 Figure 11-11:VTH (Input Threshold Voltage) of OSC1 Input (in XT, HS, and LP modes) vs. VDD ............... 74 Figure 11-12:Typical IDD vs. Frequency (External Clock, 25C) ................................... 75 Figure 11-13:Maximum IDD vs. Frequency (External Clock, -40C to +85C) .................. 75 Figure 11-14:Maximum IDD vs. Frequency (External Clock -55C to +125C) ................. 76 Figure 11-15:WDT Timer Time-out Period vs. VDD ............ 76 Figure 11-16:Transconductance (gm) OF HS Oscillator vs. VDD ................................................................ 76 Figure 11-17:Transconductance (gm) of LP Oscillator vs. VDD ................................................................ 77 Figure 11-18:IOH vs. VOH, VDD = 3 V .................................. 77 Figure 11-19:Transconductance (gm) of XT Oscillator vs. VDD ................................................................ 77 Figure 11-20:IOH vs. VOH, VDD = 5 V .................................. 77 Figure 11-21:IOL vs. VOL, VDD = 3 V ................................... 78 Figure 11-22:IOL vs. VOL, VDD = 5 V ................................... 78 Figure 12-1: Load Conditions ............................................. 85 Figure 12-2: External Clock Timing - PIC16CR54.............. 86 Figure 12-3: CLKOUT and I/O Timing - PIC16CR54 ......... 88 Figure 12-4: Reset, Watchdog Timer, and Device Reset Timer Timing - PIC16CR54............................ 89 Figure 12-5: Timer0 Clock Timings - PIC16CR54.............. 90 Figure 13-1: Typical RC Oscillator Frequency vs. Temperature .................................................. 91 Figure 13-2: Typical RC Oscillator Frequency vs. VDD, CEXT = 20 PF ......................................... 92 Figure 13-3: Typical RC Oscillator Frequency vs. VDD, CEXT = 100 PF ....................................... 92 1995 Microchip Technology Inc. Figure 13-4: Typical RC Oscillator Frequency vs. VDD, CEXT = 300 PF....................................... 93 Figure 13-5: Typical IPD vs. VDD, Watchdog Enabled ........................................ 93 Figure 13-6: Maximum IPD vs. VDD, Watchdog Enabled ........................................ 93 Figure 13-7: VTH (Input Threshold Voltage) of I/O Pins vs. VDD ................................................................ 94 Figure 13-8: VIH, VIL of MCLR, T0CKI and OSC1 (in RC Mode) vs. VDD .................................... 94 Figure 13-9: VTH (Input Threshold Voltage) of OSC1 Input (in XT, HS, and LP modes) vs. VDD .............. 94 Figure 13-10:Typical IDD vs. Frequency (External Clock 25C) .................................... 95 Figure 13-11:Maximum IDD vs. Frequency (External Clock -40C to +85C)................... 96 Figure 13-12:WDT Timer Time-out Period vs. VDD ............ 97 Figure 13-13:Transconductance (gm) OF HS Oscillator vs. VDD ................................................................ 97 Figure 13-14:Transconductance (gm) of LP Oscillator vs. VDD ................................................................ 98 Figure 13-15:Transconductance (gm) of XT Oscillator vs. VDD ................................................................ 98 Figure 13-16:IOH vs. VOH, VDD = 3 V.................................. 98 Figure 13-17:IOH vs. VOH, VDD = 5 V.................................. 98 Figure 13-18:IOL vs. VOL, VDD = 3 V................................... 99 Figure 13-19:IOL vs. VOL, VDD = 5 V................................... 99 LIST OF TABLES Table 1-1: Table 3-1: Table 3-2: Table 4-1: Table 5-1: Table 6-1: Table 7-1: Table 7-2: Table 7-3: Table 7-4: Table 7-5: Table 7-6: Table 7-7: Table 7-8: Table 7-9: Table 8-1: Table 8-2: Table 9-1: Table 9-2: Table 10-1: Table 10-2: Table 10-3: Table 10-4: PIC16C5X Family of Devices ...........................4 PIC16C54/CR54/C56 Pinout Description .........9 PIC16C55/C57 Pinout Description ................ 10 Special Function Register Summary ............. 15 Summary of Port Registers ........................... 21 Registers Associated With Timer0 ................ 24 Capacitor Selection For Ceramic Resonators PIC16C54/55/56/57 ....................................... 28 Capacitor Selection For Crystal Oscillator - PIC16C54/55/56/57 .. 28 Capacitor Selection For Ceramic Resonators - PIC16CR54 ......... 29 Capacitor Selection For Crystal Oscillator - PIC16CR54............... 29 Reset Conditions for Special Registers ......... 31 Reset Conditions for All Registers................. 31 Summary of Registers Associated with the Watchdog Timer ............................................ 35 TO/PD Status After Reset ............................. 36 Events Affecting TO/PD Status Bits .............. 36 OPCODE Field Descriptions ......................... 39 Instruction Set Summary ............................... 40 PICMASTER Probe Specification.................. 52 Development System Packages.................... 55 Cross Reference of Device Specs for Oscillator Configurations (RC, XT & 10) and Frequencies of Operation (Commercial Devices) .............. 58 Cross Reference of Device Specs for Oscillator Configurations (HS, LP & JW) and Frequencies of Operation (Commercial Devices) .............. 58 External Clock Timing Requirements PIC16C54/55/56/57 ....................................... 65 CLKOUT and I/O Timing Requirements PIC16C54/55/56/57 ....................................... 67 DS30015M-page 127 PIC16C5X Table 10-5: Reset, Watchdog Timer, and Device Reset Timer - PIC16C54/55/56/57 ........................... 68 Table 10-6: Timer0 Clock Requirements PIC16C54/55/56/57 ....................................... 69 Table 11-1: RC Oscillator Frequencies ............................. 71 Table 11-2: Input Capacitance for PIC16C54/56 .............. 78 Table 11-3: Input Capacitance for PIC16C55/57 .............. 78 Table 12-1: Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices).................................... 80 Table 12-2: External Clock Timing Requirements PIC16CR54 .................................................... 86 Table 12-3: CLKOUT and I/O Timing Requirements PIC16CR54 .................................................... 88 Table 12-4: Reset, Watchdog Timer, and Device Reset Timer - PIC16CR54 ....................................... 89 Table 12-5: Timer0 Clock Requirements - PIC16CR54 .... 90 Table 13-1: RC Oscillator Frequencies ............................. 91 Table 13-2: Input Capacitance for PIC16CR54................. 99 Table D-1: PIC16C5X Family of Devices....................... 117 Table D-2: PIC16C62X Family of Devices..................... 118 Table D-3: PIC16C6X Family of Devices....................... 119 Table D-4: PIC16C7X Family of Devices....................... 120 Table D-5: PIC16C8X Family of Devices....................... 121 Table D-6: PIC17CXX Family of Devices ...................... 122 Table D-7: Pin Compatible Devices ............................... 123 DS30015M-page 128 1995 Microchip Technology Inc. PIC16C5X CONNECTING TO MICROCHIP BBS Connect worldwide to the Microchip BBS using the CompuServe communications network. In most cases a local call is your only expense. The Microchip BBS connection does not use CompuServe membership services, therefore, you do not need CompuServe membership to join Microchip's BBS. There is no charge for connecting to the BBS, except toll charge to CompuServe access number, where applicable. You do not need to be a CompuServe member to take advantage of this connection (you never actually log in to CompuServe). The procedure to connect will vary slightly from country to country. Please check with your local CompuServe agent for details if you have a problem. CompuServe service allows multiple users at baud rates up to 14,400 bps. The following connect procedure applies in most locations: 1. 2. 3. 4. 5. Set your modem to 8 bit, No parity, and One stop (8N1). This is not the normal CompuServe setting which is 7E1. Dial your local CompuServe access number. Depress <ENTER> and a garbage string will appear because CompuServe is expecting a 7E1 setting. Type +, depress <ENTER> and Host Name: will appear. Type MCHIPBBS, depress < ENTER > and you will be connected to the Microchip BBS. Trademarks: PICMASTER and PICSTART are trademarks of Microchip Technology Inc. PIC is a registered trademark of Microchip Technology Incorporated in the U.S.A. PRO MATE, fuzzyLAB, the Microchip logo and name are trademarks of Microchip Technology Incorporated. fuzzyTECH is a registered trademark of Inform Software Corporation. I 2C is a trademark of Philips Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. MS-DOS and Microsoft Windows are registered trademarks of Microsoft Corporation. Windows is a trademark of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated. All other trademarks mentioned herein are the property of their respective companies. In the United States, to find CompuServe's phone number closest to you, set your modem to 7E1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. After the system responds with Host Name: Type, NETWORK, depress < ENTER > and follow CompuServe's directions. For voice information (or calling from overseas), you may call (614) 457-1550 for your local CompuServe number. ACCESS TO THE INTERNET Microchip's current WWW address is listed on the back page of this data sheet under Worldwide Sales & Service - Americas - Corporate Office. 1995 Microchip Technology Inc. DS30015M-page 129 This document was created with FrameMaker 4 0 4 PIC16C5X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C5X Y N Literature Number: DS30015M Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30015M-page 130 1995 Microchip Technology Inc. PIC16C5X PIC16C54/55/56/57 PRODUCT IDENTIFICATION SYSTEM To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office. PART NO. -XX Device Oscillator Type X Temperature Range /XX XXX Package Pattern a) PIC16C54, PIC16C54T(2) PIC16C55, PIC16C55T(2) PIC16C56, PIC16C56T(2) PIC16C57, PIC16C57T(2) Device Examples: b) c) Oscillator Type RC LP XT HS 10 b(1) = Resistor Capacitor = Low Power Crystal = Standard Crystal/Resonator = High Speed Crystal = 10 MHz Crystal = No type for JW(3) devices Temperature Range b(1) I E = 0C to +70C (Commercial) = -40C to +85C (Industrial) = -40C to +125C (Automotive) Package JW P S SO SP SS = Windowed CERDIP = PDIP = Die in Waffle Pack = SOIC (Gull Wing, 300 mil body) = Skinny PDIP (28 pin, 300 mil body) = SSOP (209 mil body) Pattern 3-digit Pattern Code for QTP (blank otherwise) d) PIC16C54 - XT/PXXX = "XT" oscillator, commercial temp., PDIP, QTP pattern. PIC16C55 - XTI/SO = "XT" oscillator, industrial temp., SOIC (OTP device) PIC16C55 /JW = Commercial temp. CERDIP with window. PIC16C57 - RC/S = "RC" oscillator, commercial temp., dice in waffle pack. Note 1: b = blank 2: T = in tape and reel - SOIC, SSOP packages only. 3: UV erasable devices are tested to all available voltage/frequency options. Erased devices are oscillator type RC. The user can select RC, LP, XT or HS oscillators by programming the appropriate configuration bits. PIC16CR54 PRODUCT IDENTIFICATION SYSTEM To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office. PART NO. -XX Device Oscillator Type X Temperature Range /XX XXX Package Pattern Device PIC16CR54, PIC16CR54T(2) Oscillator Type RC LP XT HS 10 = Resistor Capacitor = Low Power Crystal = Standard Crystal/Resonator = High Speed Crystal = 10 MHz Crystal b(1) I E = 0C to +70C (Commercial) = -40C to +85C (Industrial) = -40C to +125C (Automotive) Package P S SO SS = PDIP = Die in Waffle Pack = SOIC (Gull Wing, 300 mil body) = SSOP (209 mil body) Pattern 3-digit Pattern Code for ROM (blank otherwise) Temperature Range Examples: a) PIC16CR54 - XT/P169 = "XT" oscillator, commercial temp., PDIP with ROM pattern 169. b) PIC16CR54 - LP I/SO592 = "LP" oscillator, industrial temp., SOIC device with ROM code 592. Note 1: b = blank 2: T = in tape and reel - SOIC, SSOP packages only. Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. 1995 Microchip Technology Inc. DS30015M-page 131 This document was created with FrameMaker 4 0 4 WORLDWIDE SALES & SERVICE AMERICAS ASIA/PACIFIC EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.mchip.com/microchip Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 214 991-7177 Fax: 214 991-8588 Dayton Microchip Technology Inc. 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Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 0 1628 851077 Fax: 44 0 1628 850259 France Arizona Microchip Technology SARL 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Pegaso Ingresso No. 2 Via Paracelso 23, 20041 Agrate Brianza (MI) Italy Tel: 39 039 689 9939 Fax: 39 039 689 9883 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 12/04/95 All rights reserved. 1995, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. 1995 Microchip Technology Inc. DS30015M-page 132