The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the
device may change before final production or NEC corporation, at its own discretion, may withdraw the device prior to its production.
DESCRIPTION
The mPD78042AY, 78043AY, 78044AY, 78045AY, 78045Y are essentially the mPD78042A, 78043A, 78044A,
and 78045A models with an I2C bus control function added. They are ideal for applications in audio-visual
system.
These microcomputers incorporate many hardware peripherals such as an FIP® controller/driver, 8-bit
resolution A/D converter, timer, serial interface, and interrupt controller in addition to a high-speed/high
performance CPU.
In addition to these standard mask ROM models, one-time PROM models that can operate in the same voltage
range, EPROM models, and various development tools are being developed.
The functions of these microcomputers are described in detail in the following User’s Manual. Be sure to read
this manual when you design a system using any of these microcomputers.
mPD78044AY Series Preliminary User’s Manual: To be released
FEATURES
• High-capacity ROM and RAM
8-BIT SINGLE-CHIP MICROCOMPUTER
„ NEC Corp oration 1993
Document No. IP- 3323
(O. D. No. IP)
Date Published September 1993 P
Printed in Japan
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
mPD78042AY,78043AY,78044AY,78045AY
ITEM PROGRAM MEMORY DATA MEMORY
PRODUCT NAME
(ROM)
Internal high-speed RAM
Buffer RAM FIP display RAM
mPD78042AY 16K bytes
mPD78043AY 24K bytes
mPD78044AY 32K bytes
mPD78045AY 40K bytes
512 bytes
1024 bytes
64 bytes 48 bytes
• Wide range of instruction execution time - from high-speed (0.4 ms) to ultra low-speed (122 ms)
• I/O ports: 68
• FIP controller/driver: total display outputs: 34
• 8-bit resolution A/D converter: 8 channels
• Serial interface: 2 channels
• Timer: 6 channels
• Operation power supply voltage range: 2.7 to 6.0V
APPLICATIONS
VCRs, audio systems, etc.
mPD78042AY, 78043AY, 78044AY, 78045AY
2
ORDERING INFORMATION
PART NUMBER PACKAGE QUALITY GRADE
mPD78042AYGF-xxx-3B9 80-pin plastic QFP (14 x 20 mm) Standard
mPD78043AYGF-xxx-3B9 80-pin plastic QFP (14 x 20 mm) Standard
mPD78044AYGF-xxx-3B9 80-pin plastic QFP (14 x 20 mm) Standard
mPD78045AYGF-xxx-3B9 80-pin plastic QFP (14 x 20 mm) Standard
Remarks: "xxx" indicates ROM code number.
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and their recommended applications.
78K/0 SERIES
Pr oduc ts unde r ma ss prod ucti on
Products under development
Y serie s is fo r I
2
C bus.
m
PD78002Y series
m
PD78002 series
80-pin package
UART, D/A converter,
Real-time output port
Reinforced 16-bit timer/event
counter function
1 00-pin packag e
LCD controller/driver, UART
Re info rce d 16-b it
timer/event counter function
m
PD78044AY series
80-pin package
Reinfo rced FIP con troller/d river,
6-bit up/down counter
m
PD78054 series
m
PD78064 series
m
PD78064Y series
64-pin package
m
PD78044A series
m
PD78044 series
64-pin package
A/D converter,
16-bit timer/event counter,
FIP controller/driver,
Multiplication/division instructions
m
PD78024 series
m
PD78024Y series
m
PD78054Y series
m
PD78014Y series
m
PD78014Y series
64-pin package
A/D converter,
16-bit timer/event counter,
SIO with automatic transfer/reception function
Multiplication/division instruction
mPD78042AY, 78043AY, 78044AY, 78045AY
3
ROM
Internal high-speed RAM
Buffer RAM
FIP display RAM
mPD78042AY mPD78043AY mPD78044AY mPD78045AY
16K bytes 24K bytes 32K bytes 40K bytes
512 bytes 1024 bytes
64 bytes
48 bytes
FUNCTIONAL OUTLINE
ITEM
PRODUCT NAME
Instruction
cycle
Internal
memory
General-purpose registers 8 bits x 32 registers (8 bits x 8 registers x 4 banks)
Variable instruction execution time
w/main system 0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (at 5.0 MHz)
clock
w/subsystem 122 ms (at 32.768 kHz)
clock
Instruction set • Multiplecation/division (8 bits x 8 bits, 16 bits “ 8 bits)
• Bit (set, reset, test, Boolean algebra)
I/O ports (including those Total : 68 lines
multiplexed with FIP pins) • CMOS input : 2 lines
• CMOS I/O : 27 lines
• N-ch open-drain I/O : 5 lines
• P-ch open-drain I/O : 16 lines
• P-ch open-drain output : 18 lines
FIP controller/driver Total : 34 lines
• Segment : 9 to 24 lines
• Digit : 2 to 16 lines
A/D converter • 8-bit resolution x 8 channels
• Operating voltage range : VDD = 4.0 to 6.0 V
Serial interface • 3-line/SBI/2-line/I2C bus mode selectable : 1 channel
• 3-line mode (w/automatic transfer/receive function of up to 64 bytes): 1 channel
Timer • 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
• 6-bit up/down counter : 1 channel
Timer output 3 lines (one for 14-bit PWM output)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(at main system clock of 5.0 MHz)
32.768 kHz (at 32.768 kHz: subsystem clock)
Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz : (at 5.0 MHz: main system clock)
mPD78042AY, 78043AY, 78044AY, 78045AY
4
Maskable interrupt Internal 10 lines, external 4 lines
Non-maskable interrupt Internal 1 line
Software intrrupt Internal 1 line
Test input Internal 1 line
Operating voltage range VDD = 2.7 to 6.0 V
Package • 80-pin plastic QFP (14 x 20 mm)
ITEM mPD78042AY mPD78043AY mPD78044AY mPD78045AY
PRODUCT NAME
Vectored
interrupt
mPD78042AY, 78043AY, 78044AY, 78045AY
5
CONTENTS
1. PIN CONFIGURATION (Top View)....................................................................................................... 6
2. BLOCK DIAGRAM................................................................................................................................... 8
3. PINS FUNCTIONS .................................................................................................................................. 9
3.1 PORT PINS ...................................................................................................................................... 9
3.2 PINS OTHER THAN PORT PINS ...................................................................................................... 11
3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS .............................................................. 13
4. MEMORY SPACE .................................................................................................................................... 16
5. PERIPHERAL HARDWARE FUNCTIONS ............................................................................................. 17
5.1 PORTS ............................................................................................................................................. 17
5.2 CLOCK GENERATOR CIRCUIT ........................................................................................................ 18
5.3 TIMER/EVENT COUNTER ................................................................................................................ 18
5.4 CLOCK OUTPUT CONTROL CIRCUIT.............................................................................................. 22
5.5 BUZZER OUTPUT CONTROL CIRCUIT ........................................................................................... 22
5.6 A/D CONVERTER............................................................................................................................. 23
5.7 SERIAL INTERFACE ........................................................................................................................ 23
5.8 FIP CONTROLLER/DRIVER .............................................................................................................. 25
6. INTERRUPT FUNCTION ........................................................................................................................ 27
7. STANDBY FUNCTION ........................................................................................................................... 30
8. RESET FUNCTION .................................................................................................................................. 30
9. INSTRUCTION SET ................................................................................................................................ 31
10. PACKAGE DRAWINGS .......................................................................................................................... 34
APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 35
APPENDIX B. RELATED DOCUMENTS ..................................................................................................... 37
mPD78042AY, 78043AY, 78044AY, 78045AY
6
1. PIN CONFIGURATION (Top View)
80-Pin Plastic QFP (14 x 20 mm)
RemarksRemarks 1:1: Connect the IC (Internally Connected) pins directly to the VSS.
2:2: Connect the AVDD pin to the VDD pin.
3:3: Connect the AVSS pin to the VSS pin.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PD78042AYGF-xxx-3B9
µ
P94/FIP6 P114/FIP22
P95/FIP7P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
DD
AV
REFAV
P04/XT1
XT2
SSV
X1
X2
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P96/FIP8
P97/FIP9
P100/FIP10
P101/FIP11
P102/FIP12
P103/FIP13
P104/FIP14
P105/FIP15
VLOAD
P106/FIP16
P107/FIP17
P110/FIP18
P111/FIP19
P112/FIP20
P113/FIP21
P93/FIP5
P92/FIP4
P91/FIP3
P90/FIP2
P81/FIP1
P80/FIP0
VDD
P27/SCK0/SCL
P26/SO0/SB1/SDA1
P25/SI0/SB0/SDA0
P24/BUSY
P23/STB
P22/SCK1
P21/SO1
P20/SI1
RESET
P74
P73
AVSS
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P115/FIP23
P116/FIP24
P117/FIP25
P120/FIP26
P121/FIP27
P122/FIP28
P123/FIP29
P124/FIP30
P125/FIP31
P126/FIP32
P127/FIP33
VDD
P70
P71
P72
IC
P00/INTP0/TI0
P01/INTP1
P02/INTP2
P03/INTP3/CI0
P30/TO0
P31/TO1
P32/TO2
PD78043AYGF-xxx-3B9
µ
PD78044AYGF-xxx-3B9
µ
PD78045AYGF-xxx-3B9
µ
mPD78042AY, 78043AY, 78044AY, 78045AY
7
P00-P04 : Port0 SCK0,SCK1 : Serial Clock
P10-P17 : Port1 SCL : Serial Clock
P20-P27 : Port2 PCL : Programmable Clock
P30-P37 : Port3 BUZ : Buzzer Clock
P70-P74 : Port7 STB : Strobe
P80,P81 : Port8 BUSY : Busy
P90-P97 : Port9 FIP0-FIP33 : Fluorescent Indicator Panel
P100-P107 : Port10 VLOAD : Negative Power Supply
P110-P117 : Port11 X1,X2 : Crystal (Main System Clock)
P120-P127 : Port12 XT1,XT2 : Crystal (Subsystem Clock)
INTP0-INTP3 : Interrupt From Peripherals RESET : Reset
TI0-TI2 : Timer Input ANI0-ANI7 : Analog Input
TO0-TO2 : Timer Output AVDD : Analog Power Supply
CI0 : Counter Input AVSS : Analog Ground
SB0,SB1 : Serial Bus AVREF : Analog Reference Voltage
SDA0, SDA1 : Serial Data VDD : Power Supply
SI0,SI1 : Serial Input VSS : Ground
SO0,SO1 : Serial Output IC : Internally Connected
mPD78042AY, 78043AY, 78044AY, 78045AY
8
2. BLOCK DIAGRAM
TO0/P30
TI0/INTP0/P00
TO1/P31
TI1/P33
TO2/P32
TI2/P34
CI0/INTP3/P03
SDAO/SI0/SB0/P25
SDA1/SO0/SB1/P26
SCL/SCK0/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
ANI0/P10
-ANI7/P17
AV DD
AV SS
AV REF
INTP0/TI0/P00
-INTP3/CI0/P03
16 bit TIMER/
EVENT
COUNTER
8 bit TIMER/
EVENT
COUNTER 1
8 bit TIMER/
EVENT
COUNTER 2
WATCHDOG
TIMER
WATCH TIMER
6 bit UP/DOWN
COUNTER
SERIAL
INTERFACE 0
SERIAL
INTERFACE 1
A/D CONVERTER
INTERRUPT
CONTROL
PROGRAM
COUNTER
ROM
PROGRAM
MEMORY
ALU PSW SP
GENERAL REG.
RAM
DATA MEMORY
DECODE
AND
CONTROL
BUZZER
OUTPUT
CLOCK
OUTPUT
CONTROL CLOCK
DIVIDER
CLOCK GENERATOR
SUB MAIN STAND BY
CONTROL
BUZ/P36 PCL/P35 XT2 X1 X2P04/XT1
RESET VDD VSS IC
FIP
CONTROLLER/
DRIVER VLOAD
FIP0-FIP33
PORT0
PORT1
PORT2
PORT7
PORT8
PORT9
PORT11
PORT12
P00-P04
P10-P17
P20-P27
P70-P74
P80, P81
P90-P97
P110-P117
P120-P127
PORT3 P30-P37
P100-P107
PORT10
The capacities of the internal ROM and RAM differ depending on the product.Note:
mPD78042AY, 78043AY, 78044AY, 78045AY
9
SHARED BY:
INTP0/TI0
INTP1
INTP2
INTP3/CI0
XT1
ANI0-ANI7
SI1
SO1
SCK1
STB
BUSY
SI0/SB0/SDA0
SO0/SB1/SDA1
SCK0/SCL
TO0
TO1
TO2
TI1
TI2
PCL
BUZ
—
I/O
I/O
Port 2
8-bit I/O port
Can be specified for input or output in 1-bit units.
When used as an input port pin, a pull-up resistor can be
connected through software.
Port 0
5-bit I/O port
ON RESET
Input
Input
Input
Input
Input
Input
Input only
Can be specified for input or output in
1-bit units. When used as an input port
pin, a pull-up resistor can be connected
through software.
Input only
Port 1
8-bit I/O port
Can be specified for input or output in 1-bit units.
When used as an input port pin, a pull-up resistor can be
connected through software.*2
3. PINS FUNCTIONS
3.1 PORT PINS (1/2)
PIN NAME
P00
P01
P02
P03
P04*1
P10-P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
I/O
Input
I/O
Input
I/O
FUNCTION
*1: When the P04/XT1 pins is used as an input port pin, bit 6 (FRC) of the porcessor clock control register must
be set to 1. (At this time, do not use the feedback resistor of the subsystem clock oscillator circuit. )
*2: When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D
converter, be sure to place the port 1 in the input mode. In this case, the pull-up resistors are automaticaly
unused.
Port 3
8-bit I/O port
Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
When used as an input port pin, a pull-up resistor can be
connected through software.
A pull-down resistor can be connected in 1-bit units by mask
option.
mPD78042AY, 78043AY, 78044AY, 78045AY
10
ON RESET
Input —
Output FIP0, FIP1
Output FIP2-FIP9
Output FIP10-FIP17
Input FIP18-FIP25
Input FIP26-FIP33
PIN NAME I/O FUNCTION
Port 7
5-bit N-ch open-drain I/O port
P70-P74 I/O Can be specified for input or output in 1-bit units
Can directly drive LEDs
A pull-up resistor can be connected in 1-bits by mask options.
Port 8
2-bit P-ch open-drain high-voltage output port
P80, P81 Output Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by mask
option (whether VLOAD or VSS is connected can be specified in
2-bit units).
Port 9
8-bit P-ch open-drain high-voltage output port
P90-P97 Output Can directly drive LEDs.
A pull-down resistor can be conected in 1-bit units by mask
option (whether VLOAD or VSS is connected can be specified in 4-bit
units).
Port 10
8-bit P-ch open-drain high-voltage output port
P100-P107 Output P100 through P105 can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units
(whether VLOAD or VSS is connected can be specified in 4-bit units).
Port 11
8-bit P-ch open-drain high-voltage I/O port
P110-P117 I/O Can be specified for input or output in 1-bit units.
A pull-down resistor can be conneced in 1-bit units
(whether VLOAD or VSS is connected can be specified in 4-bit units).
Port12
8-bit P-ch open-drain high-voltage I/O port.
P120-P127 I/O Can be specified for input or output in 1-bit units.
A pul-down resistor can be connected in 1-bit units
(whether VLOAD or VSS is connected can be specified in 4-bit units).
SHARED BY:
3.1 PORT PINS (2/2)
mPD78042AY, 78043AY, 78044AY, 78045AY
11
PIN NAME I/O FUNCTION
INTP0 Valid edge (rising, falling, or both rising and fallng edges) can
INTP1 be specified.
INTP2 External interrupt input
INTP3 Falling edge-active external interrupt input
SI0
SI1
SO0
SO1
SB0
SB1
SDA0
SDA1
SCK0
SCK1
SCL
STB Output Automatic transfer/receive strobe output line of serial interface
BUSY Input Automatic transfer/receive busy input line of serial interface
TI0 External count clock input to 16-bit timer (TM0)
TI1 Input External count clock input to 8-bit timer (TM1)
TI2 External count clock input to 8-bit timer (TM2)
TO0 16-bit timer output (multiplexed with 14-bit PWM output)
TO1
TO2
CI0 Input Clock input to up/down counter
Clock output (for trimming main system clock and subsystem
clock)
BUZ Output Buzzer output
FIP0, FIP1
FIP2-FIP9
High-voltage, high-current digit/segment output of FIP
controller/driver
FIP16, FIP17
FIP18-FIP25
FIP26-FIP33
VLOAD — Connects pull-down resistor to FIP controller/driver
ON RESET SHARED BY:
P00/TI0
P01
P02
P03/CI0
P25/SB0/SDA0
P20
P26/SB1/SDA1
P21
P25/SI0/SDA0
P26/SO0/SDA1
P25/SI0/SB0
P26/SO0/SB1
P27/SCL
P22
P27/SCK0
P23
P24
P00/INTP0
Input P33
P34
P30
P31
P32
Input P03/INTP3
Input P36
P80, P81
P90-97
Output P106, P107
P110-P117
P120-P127
——
3.2 PINS OTHER THAN PORT PINS (1/2)
Input
Input
Input
Output
Output
Input
PCL
FIP10-FIP15
Output
Output
Output High-voltage segment output of FIP controller/driver Output
High-voltage, high-current digit output of FIP controller/driver Input
P100-P105
P35
Output
Input
Input
Input
Input Serial data input lines of serial interface Input
Output Serial data output lines of serial interface Input
I/O Serial data I/O lines of serial interface Input
I/O Serial clock I/O lines of serial interface Input
8-bit timer output
mPD78042AY, 78043AY, 78044AY, 78045AY
12
PIN NAME I/O FUNCTION ON RESET SHARED BY:
ANI0-ANI7 Input A/D converter analog input lines Input P10-P17
AVREF Input A/D converter reference voltage input line — —
AVDD — Analog power supply to A/D converter. Connected to VDD pin. — —
AVSS — A/D converter ground line. Connected to VSS pin. — —
RESET Input System reset input — —
X1 Input ——
X2 — ——
XT1 Input Input P04
XT2 — ——
V
DD — Positive power supply — —
VSS — Ground potential — —
IC — Internal connection. Connected directly to VSS pin. — —
3.2 PINS OTHER THAN PORT PINS (2/2)
Connect crystal for main system clock oscillation.
Connect crystal for subsystem clock oscillation.
mPD78042AY, 78043AY, 78044AY, 78045AY
13
3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS
Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins.
For the configuration of the I/O circuit of each type, refer to Fig. 3-1.
Table 3-1 I/O Circuit Type
P120/FIP26-P127/FIP33
RESET
XT2
AVREF
AVDD
AVSS
VLOAD
IC
15-A
2
16
—
Pin name
P00/INTP0/TI0
P01/INTP1
P02/INTP2
P03/INTP3/CI0
P04/XT1
P10/ANI0-P17/ANI7
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
P70-P74
P80/FIP0, P81/FIP1
P90/FIP2-P97/FIP9
P100/FIP10-P107/FIP17
P110/FIP18-P117/FIP25
Recommended connection method for unused pins
Connect to VSS.
For input : Connect to VSS.
For output : Open
Connect to VSS.
For input : Connect to VDD or VSS.
For output : Open
For input : Connect to VDD or VSS.
For output : Open
For input : Connect to VDD or VSS.
For output : Open
For input : Connect to VDD or VSS.
For output : Open
Open
I/O circuit type
2
8-A
16
11
8-A
5-A
8-A
5-A
8-A
10-A
5-C
8-B
5-C
13-A
14-A
I/O
Input
I/O
Input
I/O
I/O
I/O
I/O
Output
I/O
Input
—
For input : Connect to VDD or VSS.
For output : Open
—
Open
Connect to VSS.
Connect to VDD.
Connect to VSS.
Connect directly to VSS.
mPD78042AY, 78043AY, 78044AY, 78045AY
14
Type 5-C
Type 2 Type 8-A
Type 5-A Type 8-B
IN
Schmitt trigger input with hysteresis characteristics
VDD
VDD
pullup
enable
data
output
disable
P-ch
IN/OUT
N-ch
P-ch
VDD
VDD
pullup
enable
data
output
disable
P-ch
N-ch
IN/OUT
(Mask
Option)
P-ch
Type 10-A
P-ch
N-ch
VDD
pullup
enable
data
IN/OUT
open drain
output disable
VDD
P-ch
VDD
VDD
P-ch
P-ch
N-ch
IN/OUT
pullup
enable
data
output
disable
input
enable
VDD
P-ch
N-ch
P-ch
VDD
IN/OUT
(Mask
Option)
pullup
enable
data
output
disable
input
enable
Fig. 3-1 Pin I/O Circuits (1/2)
mPD78042AY, 78043AY, 78044AY, 78045AY
15
Fig. 3-1 Pin I/O Circuits (2/2)
Type 11
Type 14-A
Type 15-A
Type 13-A
V
DD
IN/OUT
(Threshold voltage)
V
REF
pullup
enable
data
output
disable
V
DD
P-ch
P-ch
N-ch
P-ch
N-ch
input enable
V
DD
+
–
IN/OUT
Comparator
N-ch
(Mask
Option)
data
output disable
Medium-voltage input buffer
V
DD
P-ch P-ch
N-ch
data OUT
(Mask
Option)
(Mask
Option)
V
DD
V
LOAD
V
DD
V
DD
data
N-ch
P-ch P-ch
OUT
V
LOAD
(Mask
Option)
(Mask
Option)
Type 16
P-ch
feedback
cut-off
XT1 XT2
mPD78042AY, 78043AY, 78044AY, 78045AY
16
4. MEMORY SPACE
Figure 4-1 shows the memory maps for mPD78042AY, 78043AY, 78044AY, and 78045AY.
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
mmmmH
mmmmH-1
FAC0H
FABFH
FA50H
FA4FH
0000H
nnnnH
1000H
0FFFH
0800H
07FFH
0080H
007FH
0040H
003FH
0000H
Special function
register (SFR)
256x8 bits
General-purpose
register
32x8 bits
Internal high-speed RAM*
Buffer RAM
64x8 bits
FIP display RAM
48x8 bits
Internal ROM*
CALLF entry area
Program area
CALLT entry area
Inhibited
Program area
Vector table area
Data
memory
space
Program
memory
space
Inhibited
FB00H
FAFFH
FA80H
FA7FH
nnnnH+1
nnnnH
Inhibited
Fig. 4-1 Memory Map
*: The internal ROM, internal high-speed RAM capacities vary depending on the product. (Refer to the
table below.)
FD00H
FB00H
PRODUCT INTERNAL ROM INTERNAL HIGH-SPEED RAM
NAME LAST ADDRESS FIRST ADDRESS
nnnnH mmmmH
mPD78042AY 3FFFH
mPD78043AY 5FFFH
mPD78044AY 7FFFH
mPD78045AY 9FFFH
mPD78042AY, 78043AY, 78044AY, 78045AY
17
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
I/O ports are classified into the following 5 kinds:
• CMOS input (P00, P04) : 2
• CMOS input/output (P01 - P03, ports 1-3) : 27
• N-ch open-drain input/output (port 7) : 5
• P-ch open-drain output (ports 8-10) : 18
• P-ch open-drain input/output (ports 11 and 12) : 16
Total : 68
Table 5-1 Port Function
PRODUCT PIN FUNCTION
Input port
I/O port. Can be specified for input or output in 1-bit units.
When used as input port, internal pull-up resistor can be connected through software.
I/O port. Can be specified for input or output in 1-bit units.
When used as input port, internal pull-up resistor can be connected through software.
I/O port. Can be specified for input or output in 1-bit units.
When used as input port, internal pull-up resistor can be connected through software.
I/O port. Can be specified for input or output in 1-bit units.
When used as input port, internal pull-up resistor can be connected through software.
Pull-down resistor can be connected in 1-bit units by mask option.
Can directly drive LED.
N-ch open-drain I/O port. Can be specified for input or output in 1-bit units.
Pull-up resistor can be connected in 1-bit units by mask option.
Can directly drive LED.
P-ch open-drain high-voltage output port.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 2-bit units).
P-ch open-drain high-voltage output port.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units).
P-ch open-drain high-voltage output port.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units).
P100-P105 can directly drive LED.
P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit
units.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units).
P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit
units.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units).
Port 0
Port 1
Port 2
Port 3
Port 7
Port 8
Port 9
Port 10
Port 11
Port 12
P00, P04
P01-P03
P10-P17
P20-P27
P30-P37
P70-P74
P80, P81
P90-P97
P100-P107
P110-P117
P120-P127
mPD78042AY, 78043AY, 78044AY, 78045AY
18
5.2 CLOCK GENERATOR CIRCUIT
The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock.
The instruction time can be changed.
•0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (with main system clock: 5.0 MHz)
•122 ms (with subsystem clock: 32.768 kHz)
Subsystem
clock generator
circuit
Main system
clock generator
circuit
Selector
Noise detector
circuit
Pre-scaler
Selector
Selector
Pre-scaler
To INTP0
sampling clock
Standby
control
circuit CPU clock (f
CPU
)
Clock to
hardware peripherals
Watch timer
Clock output circuit
f
XT
f
X
f
XT
XT1/P04
XT2
X1
X2
f
X
8
f
X
16
f
X
2f
X
2
2
f
X
2
3
f
X
2
4
STOP
Fig. 5-1 Clock Generator Circuit Block Diagram
5.3 TIMER/EVENT COUNTER
Six channels of timer/event counters are provided.
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
mPD78042AY, 78043AY, 78044AY, 78045AY
19
Table 5-2 Timer/Event Counter Groups and Configurations
16-BIT TIMER/ 8-BIT TIMER/ WATCH WATCHDOG 6-BIT UP/DOWN
EVENT COUNTER EVENT COUNTER TIMER TIMER COUNTER
Interval timer 1 channel 2 channels 1 channel 1 channel 1 channel
External event counter 1 channel 2 channels – – 1 channel
Timer output 1 output 2 outputs – – –
PWM output 1 output – – – –
Pulse width measurement 1 input – – – –
Square wave output 1 output 2 outputs – – –
Interrupt Request 1 2 2 1 1
FUNCTION GROUP
Internal bus
16-bit compare
register (CR00)
16-bit timer register(TM0)
16-bit capture register (CR01)
Internal bus
PWM
pulse
output
control
circuit
Selector
Output control
circuit
Edge
detector
circuit
Coincidence
Selector
Cleared
TI0/INTP0/P00
f
X
/2
3
f
X
/2
2
f
X
/2
INTP0
TO0/P30
INTTM0
f
X
Fig. 5-2 16-Bit Timer/Event Counter Block Diagram
mPD78042AY, 78043AY, 78044AY, 78045AY
20
Fig. 5-3 8-Bit Timer/Event Counter Block Diagram
Pre-scaler
5-bit counter
Selector Selector
Selector
Selector
f
X
/2
8
f
XT
f
W
f
W
2
9
f
W
2
8
f
W
2
7
f
W
2
6
f
W
2
5
f
W
2
4
f
W
2
13
f
W
2
14
INTWT
INTTM3
Fig. 5-4 Watch Timer Block Diagram
8-bit timer
register 2 (TM2)
Internal bus
Internal bus
8-bit compare
register (CR10) 8-bit compare
register (CR20)
8-bit timer
register 1 (TM1)
Output
control
circuit
Output
control
circuit
Coincidence Coincidence
SelectorSelector
Selector
Selector
Selector
Cleared
TO1/P31
INTTM2
TO2/P32
INTTM1
fX/212
fX/2-fX/210
fX/2-fX/210
fX/212
TI1/P33 Cleared
TI2/P34
mPD78042AY, 78043AY, 78044AY, 78045AY
21
CautionCaution:: When using the 6-bit up/down counter, set the CI0/P03/INTP3 pin in the input modeWhen using the 6-bit up/down counter, set the CI0/P03/INTP3 pin in the input mode
(set bit 3 (PM03) of the port mode register 0 to 1).(set bit 3 (PM03) of the port mode register 0 to 1).
Fig. 5-6 6-Bit Up/Down Counter Block Diagram
Pre-selector
Selector
RESET
Selector
Control circuit
8-bit
counter
INTWDT
maskable
interrupt
request
INTWDT
non-maskable
interrupt
request
f
X
2
4
f
X
2f
WDT
2
f
WDT
f
WDT
2
2
f
WDT
2
3
f
WDT
2
4
f
WDT
2
5
f
WDT
2
6
f
WDT
2
8
3
Fig. 5-5 Watchdog Timer Block Diagram
6-bit up/down counter
compare register (UDCC)
Selector
Load
Coincidence
Cleared
6-bit up/down counter (UDC)
Internal bus
Edge detector
circuit
INTP3/INTUD
CI0/P03/INTP3
Underflow
mPD78042AY, 78043AY, 78044AY, 78045AY
22
5.4 CLOCK OUTPUT CONTROL CIRCUIT
Clocks of the following frequencies can be output to the clock :
• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz)
• 32.768 kHz (with subsystem clock: 32.768 kHz)
Fig. 5-7 Clock Output Control Circuit Block Diagram
5.5 BUZZER OUTPUT CONTROL CIRCUIT
Clocks of the following frequencies can be output to the buzzer:
• 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz)
Fig. 5-8 Buzzer Output Control Circuit Block Diagram
fX/23
fX/24
fX/25
fX/26
fX/27
fX/28
fXT
Selector
PCL/P35
Sync circuit Output control circuit
fX/210
fX/211
fX/212
Selector
BUZ/P36
Output control circuit
mPD78042AY, 78043AY, 78044AY, 78045AY
23
5.6 A/D CONVERTER
An 8-bit resolution 8-channel A/D converter is provided.
This A/D converter can be started in the following two modes:
• Hardware start
• Software start
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
INTP3/P03 INTAD
INTP3
AVSS
AVREF
AVDD
Sample & hold circuit
Voltage comparator
Successive approximation
registor (SAR)
Series register string
Falling edge
detector
circuit
Control
circuit
A/D conversion result
register (ADCR)
Internal bus
Tap selector
Selector
Fig. 5-9 A/D Converter Block Diagram
5.7 SERIAL INTERFACE
Two channels of clocked serial interfaces are provided.
• Serial interface channel 0
• Serial interface channel 1
Table 5-3 Serial Interface Groups and Functions
FUNCTION SERIAL INTERFACE CHANNEL 0 SERIAL INTERFACE CHANNEL 1
3-line serial I/O mode • (MSB/LSB first selectable) • (MSB/LSB first selectable)
SBI (serial bus interface) mode • (MSB first) –
2-line serial I/O mode • (MSB first) –
3-line serial I/O
mode w/automatic – • (MSB/LSB first sectable)
transfer/reception function
I2C bus mode • –
mPD78042AY, 78043AY, 78044AY, 78045AY
24
Fig. 5-10 Serial Interface Channel 0 Block Diagram
Fig. 5-11 Serial Interface Channel 1 Block Diagram
Internal bus
Buffer RAM
Serial I/O shift register 1 (SIO1)
Automatic data
transfer/reception
interval specification
register (ADTI)
5-bit counter
SO1/P21
SI1/P20
Selector
Interrupt request
signal generator
circuit INTCSI1
f
X
/2
2
-f
X
/2
9
TO2
Serial
counter
Serial clock
control circuit
SCK1/P22
Automatic data transfer
reception address
pointer (ADTP)
STB/P23
BUSY/P24
Coincidence
Handshake
control
circuit
Internal bus
Serial I/O shift
Bus release/
command/acknowledge
detector circuit
Serial
counter
Serial clock
control circuit
Interrupt request
signal generator
circuit
Busy/acknowledge
output circuit
Selector Selector
Selector
Output
latch
INTCSI0
fX/22-fX/29
TO2
register 0 (SIO0)
SDA0/SI0/SB0/P25
SDA1/SO0/SB1/P26
SCL/SCK0/P27
mPD78042AY, 78043AY, 78044AY, 78045AY
25
5.8 FIP CONTROLLER/DRIVER
An FIP controller/driver having the following features is provided:
(a) Automatic output of segment signals (DMA operation) and digit signals by automatically reading display
data
(b) Display mode register (DSPM0, DSPM1) that can control an FIP of 9 to 24 segments and 2 to 16 digits
(c) Port pins not used for FIP display can be used as output port or I/O port pins.
(d) Display mode register (DSPM1) can adjust luminance in eight steps.
(e) Hardware suitable for key scan application using segment pins
(f) High-voltage output buffer (FIP driver) that can directly drive an FIP
(g) Display output pins can be connected to a pull-down resistor by mask option.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
00
Selecting number of digits
Selecting number of segments
Note:
If the total number of digits and segments exceeds 34, the specified number of digits takes precedence.
Fig. 5-12 Selecting Display Modes
mPD78042AY, 78043AY, 78044AY, 78045AY
26
Internal bus
Display data memory
Segment data latch
Digit signal
generator circuit
Port output latch
High-voltage buffer
FIP0/P80 FIP1/P81 FIP33/P127
Fig. 5-13 FIP Controller/Driver Block Diagram
mPD78042AY, 78043AY, 78044AY, 78045AY
27
6. INTERRUPT FUNCTION
The following four types of interrupt functions are available:
• Non-maskable interrupt : 1
• Maskable interrupt : 13
• Software interrupt : 1
• Test input : 1
mPD78042AY, 78043AY, 78044AY, 78045AY
28
(A) Internal non-maskable interrupt
Internal bus
Interrupt
request Priority
control circuit Vector table
address
generator circuit
Standby
release signal
(B) Internal maskable interrupt
Internal bus
Interrupt
request
Priority
control circuit Vector table
address
generator circuit
Standby
release signal
MK IE PR ISP
IF
(C) External maskable interrupt (INTP0)
Internal bus
MK IE PR ISP
IF
Interrupt
request
Standby
release signal
Priority
control circuit Vector table
address
generator circuit
Sampling clock
select register
(SCS)
External interrupt
mode register
(INTM0)
Sampling
clock Edge
detector
circuit
Fig. 6-1 Basic Configuration of Interrupt Function (1/2)
mPD78042AY, 78043AY, 78044AY, 78045AY
29
(D) External maskable interrupt (except INTP0)
Internal bus
MK IE PR ISP
IF
Interrupt
request
Standby
release signal
Priority
control circuit Vector table
address
generator circuit
External interrupt
mode register
(INTM0)
Edge
detector
circuit
(E) Software interrupt
Internal bus
Priority
control circuit Vector table
address
generator circuit
Interrupt
request
(F) Test input
Internal bus
MK
IF
Interrupt
request Standby
release signa
l
RemarksRemarks 1:1: IF :Interrupt request flag
2:2: IE :Interrupt enable flag
3:3: ISP :In-service priority flag
4:4: MK :Interrupt mask flag
5:5: PR :Priority specification flag
Fig. 6-1 Basic Configuration of Interrupt Function (2/2)
mPD78042AY, 78043AY, 78044AY, 78045AY
30
7. STANDBY FUNCTION
The standby function is to reduce the current dissipation of the system and can be effected in the following two
modes:
• HALT mode: In this mode, the operating clock of the CPU is stopped. By using this mode in combination
with the normal operation mode, the system can be operated intermittently, so that the
average current dissipation can be reduced.
• STOP mode: Oscillation of the main system clock is stopped. All the operations on the main system clock
are stopped, and therefore, the current dissipation of the system can be minimized with only
the subsystem clock oscillating.
*: By stopping the main system clock, the current dissipation can be reduced.
When the CPU operates on the subsystem clock, stop the main system clock by setting the MCC. The STOP
instruction cannot be used.
Fig. 7-1 Standby Function
8. RESET FUNCTION
The system can be reset in the following two modes:
• External reset by RESET pin
• Internal reset by watchdog timer that detects hang up
STOP mode
(Oscillation of main system
clock stopped)
Main system
clock operation Subsystem
clock operation*
HALT mode
(Clock supply to CPU stopped.
Oscillation continues)
HALT mode*
(Clock supply to CPU stopped.
Oscillation continues)
STOP
instruction
Interrupt
request Interrupt
request
CSS=0
CSS=1
HALT instruction
Interrupt
request
HALT instruction
mPD78042AY, 78043AY, 78044AY, 78045AY
31
9. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
SECOND
OPERAND
[HL + byte]
#byte A r* sfr saddr !addr16 PSW [DE] [HL] [HL + B]
$addr16
1None
FIRST [HL + C]
OPERAND
A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR
ADDC XCH XCH XCH XCH XCH XCH XCH ROL
SUB ADD ADD ADD ADD ADD RORC
SUBC ADDC ADDC ADDC ADDC ADDC ROLC
AND SUB SUB SUB SUB SUB
OR SUBC SUBC SUBC SUBC SUBC
XOR AND AND AND AND AND
CMP OR OROR OROR
XOR XOR XOR XOR XOR
CMP CMP CMP CMP CMP
rMOVMOV INC
ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
rl DBNZ
sfr MOV MOV
saddr MOV MOV DBNZ INC
ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV ROR4
ROL4
[HL + byte] MOV
[HL + B]
[HL + C]
XMULU
CDIVUW
*: Except for r=A
mPD78042AY, 78043AY, 78044AY, 78045AY
32
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
SECOND
OPERAND
#word AX rp* sfrp saddrp !addr16 SP None
FIRST
OPERAND
AX ADDW MOVW MOVW MOVW MOVW MOVW
SUBW XCHW
CMPW
rp MOVW MOVW* INCW
DECW
PUSH
POP
sfrp MOVW MOVW
saddrp MOVW MOVW
!addr16 MOVW
SP MOVW MOVW
*: Only when rp=BC, DE, HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
SECOND
OPERAND
A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
FIRST
OPERAND
A.bit MOV1 BT SET1
BF CLR1
BTCLR
sfr.bit MOV1 BT SET1
BF CLR1
BTCLR
saddr.bit MOV1 BT SET1
BF CLR1
BTCLR
PSW.bit MOV1 BT SET1
BF CLR1
BTCLR
[HL].bit MOV1 BT SET1
BF CLR1
BTCLR
CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1
AND1 AND1 AND1 AND1 AND1 CLR1
OR1 OR1 OR1 OR1 OR1 NOT1
XOR1 XOR1 XOR1 XOR1 XOR1
mPD78042AY, 78043AY, 78044AY, 78045AY
33
(4) Call/Branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
SECOND
OPERAND
AX !addr16 !addr11 [addr5] $addr16
FIRST
OPERAND
Basic operation BR CALL CALLF CALLT BR
BR BC
BNC
BZ
BNZ
Compound BT
operation BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
mPD78042AY, 78043AY, 78044AY, 78045AY
34
10. PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14 ¥ 20) (Unit: mm)
23.6±0.4
20.0±0.2
1.0
2.7
0.8
0.15
0.8
0.15
M
P80GF-80-3B9-2
0.35±0.10
14.0±0.2
17.6±0.4
3.0 MAX.
0.1±0.1
5°±5°
0.15
+0.10
1.8±0.2
0.8±0.2
Details of tip of pin
80
124
25
65
64 41
40
–0.05
mPD78042AY, 78043AY, 78044AY, 78045AY
35
APPENDIX A. DEVELOPMENT TOOLS
The following tools are available for development of systems using the mPD78042AY, 78043AY, 78044AY,
and 78045AY:
Language Processing Software
RA78K/0 *1, 2 Assembler package common to 78K/0 series
CC78K/0 *1, 2 C compiler package common to 78K/0 series
CC78K/0-L *1, 2 C compiler library source file common to 78K/0 series
PROM Writing Tools
PG-1500 PROM programmer
PA-78P048AGF *3
PA-78P048AKL-S *3
PG-1500 Controller *1 Control program for PG-1500
Debugging Tools
IE-78000-R In-circuit emulator common to 78K/0 series
IE-78000-R-BK Break board common to 78K/0 series
IE-78044-R-EM Emulation board common to mPD78044 series
EP-78130GF-R Emulation probe common to mPD78134 series
EV-9200G-80 Socket mounted to user system created for 80-pin plastic QFP
SD78K/0 *1 Screen debugger for IE-78000-R
DF78044 *1 Device file common to mPD78044 series
Real-Time OS *4
RX78K/0 *1, 2 Real-time OS common to 78K/0 series
Fuzzy Inference Development Support Systems
FE9000 *1 Fuzzy knowledge data creation tool
FT9080 *1 Translator
FI78K0 *1 Fuzzy inference module
FD78K0 *1, 3 Fuzzy inference debugger
*1: PC-9800 series (MS-DOSTM) base, IBM PC/ATTM (PC DOSTM) base
*2: HP9000 series 300TM (HP-UXTM) base, SPARCstationTM (Sun OSTM) base, EWS-4800 seriesTM (EWS-UX/VTM)
base
*3: Under development
*4: Not supported by mPD78042AY and 78043AY.
Programmer adapter connected to PG-1500
mPD78042AY, 78043AY, 78044AY, 78045AY
36
Development Tools From Other Companies
CONSULT EMULATOR ASSEMBLER C COMPILER SIMULATOR DEBUGGER OTHERS
Advanced Data Controls
OOO
––*
(C cross 78K0
–
(Phone: Tokyo 03-3576-5351)
compiler)
(CXDB/S) (CXDB/E)
Gaio Technology
OOO
–– –
(Phone: Tokyo 03-3662-3041) (XASS-V) (XDEB-V) (XDDI-V)
Data I/O Japan
–––––
(Phone: Tokyo 03-3436-4041)
LIFEBOARD
O
––* – – –
(Phone: Tokyo 03-3293-4714) (ICC78000)
Yokogawa Digital Computer
OO
––– –
(Phone: Tokyo 0422-56-9101) (AD200) (mVIEW)
*: The assembler is supplied with the C compiler package.
PROM
programmer
mPD78042AY, 78043AY, 78044AY, 78045AY
37
APPENDIX B. RELATED DOCUMENTS
mPD78042AY, 78043AY, 78044AY, 78045AY
38
mPD78042AY, 78043AY, 78044AY, 78045AY
39
GENERAL NOTES ON CMOS DEVICES
¿
STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled.
The insulation of the gates of the MOS device may be destroyed by a strong static charge.
Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or
conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use
grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate
and do not touch the pins of the device.
Handle boards on which MOS devices are mounted similarly.
¡
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices.
Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input
pin, intermediate level input may be generated due to noise, and an inrush current may flow through
the device, causing the device to malfunction. Therefore, fix the input level of the device by using a
pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose
timing is not specified), each pin should be connected to VDD or GND through a resistor.
Refer to "Processing of Unused Pins" in the documents of each devices.
¬
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application.
Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The
output status of pins, I/O setting, and register contents upon power application are not guaranteed.
However, the items defined for reset operation and mode setting are subject to guarantee after the
respective operations have been executed.
When using a device with a reset function, be sure to reset the device after power application.
mPD78042AY, 78043AY, 78044AY, 78045AY
40
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which
may appear in this document.
NEC Corporation does not assume any liability for infrin gement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability
arising from use of such device. No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables,
unclear reactor control systems and life support systems. If customers intend to use NEC devices for
above applications or they intend to use "Standard" quality grade NEC devices for applications not
intended by NEC, please contact our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equip-
ment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer
products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
FIP is a trademark of NEC Corporation.
EWS-4800 series and EWS-UX/V are trademarks of NEC Corporation.
MS-DOS is a trademark of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 300 and HP-UX are trademarks of Hewlett-Packard.
SPARCstation is a trademark of SPARC International, Inc.
Sun OS is a trademark of Sun Microsystems Inc.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
