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LM431
SNVS020H –MAY 2000–REVISED JANUARY 2016
LM431 Adjustable Precision Zener Shunt Regulator
1 Features 3 Description
The LM431 is a 3-terminal adjustable shunt regulator
1• Average Temperature Coefficient 50 ppm/°C with ensured temperature stability over the entire
• Temperature Compensated for Operation Over temperature range of operation. The output voltage
the Full Temperature Range may be set at any level greater than 2.5 V (VREF) up
• Programmable Output Voltage to 36 V merely by selecting two external resistors that
act as a voltage divided network. Due to the sharp
• Fast Turnon Response turnon characteristics this device is an excellent
• Low-Output Noise replacement for many Zener diode applications.
• Low-Dynamic Output Impedance The LM431 is available in space-saving SOIC-8,
• Available in Space-Saving SOIC-8, SOT-23, and SOT-23, and TO-92 packages.
TO-92 Packages Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
• Adjustable Voltage or Current Linear and SOIC (8) 4.90 mm × 3.91 mm
Switching Power Supplies LM431 SOT-23 (3) 2.92 mm × 1.30 mm
• Voltage Monitoring TO-92 (3) 4.30 mm × 4.30 mm
• Current Source and Sink Circuits (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Circuits Requiring Precision References
• Zener Diode Replacements
LM431 Symbol Functional Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM431
SNVS020H –MAY 2000–REVISED JANUARY 2016
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Table of Contents
8.3 Feature Description................................................. 10
1 Features.................................................................. 18.4 Device Functional Modes........................................ 11
2 Applications ........................................................... 19 Application and Implementation ........................ 12
3 Description............................................................. 19.1 Application Information............................................ 12
4 Revision History..................................................... 29.2 Typical Applications ................................................ 13
5 Pin Configuration and Functions......................... 310 Power Supply Recommendations ..................... 19
6 Specifications......................................................... 411 Layout................................................................... 19
6.1 Absolute Maximum Ratings ...................................... 411.1 Layout Guidelines ................................................. 19
6.2 ESD Ratings.............................................................. 411.2 Layout Example .................................................... 19
6.3 Recommended Operating Conditions....................... 412 Device and Documentation Support ................. 20
6.4 Thermal Information.................................................. 412.1 Community Resources.......................................... 20
6.5 Electrical Characteristics........................................... 512.2 Trademarks........................................................... 20
6.6 Typical Characteristics.............................................. 712.3 Electrostatic Discharge Caution............................ 20
7 Parameter Measurement Information .................. 712.4 Glossary................................................................ 20
8 Detailed Description............................................ 10 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 10 Information........................................................... 20
8.2 Functional Block Diagram ...................................... 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (March 2013) to Revision H Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
Changes from Revision F (April 2013) to Revision G Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 18
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5 Pin Configuration and Functions
D Package DBZ Package
8-Pin SOIC 3-Pin SOT-23
Top View Top View
Note: NC = Not internally connected.
LP Package
3-Pin TO-92
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME SOIC SOT-23 TO-92
Anode 2, 3, 6, 7 3 3 O Anode pin, normally grounded
Cathode 1 1 1 I/O Shunt current/output voltage
NC 4, 5 — — — No connect
Reference 8 2 2 I Reference pin for adjustable output voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Cathode voltage 37 V
Reference voltage –0.5 V
Continuous cathode current –10 150 mA
Reference input current 10 mA
TO-92 package 0.78 W
Internal power SOIC package 0.81 W
dissipation(3)(4) SOT-23 package 0.28 W
Industrial (LM431xI) –40 85 °C
Operating temperature Commercial (LM431xC) 0 70 °C
Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) TJ Max = 150°C.
(4) Ratings apply to ambient temperature at 25°C. Above this temperature, derate the TO-92 at 6.2 mW/°C, the SOIC at 6.5 mW/°C, the
SOT-23 at 2.2 mW/°C.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Cathode voltage VREF 37 V
Cathode current 1 100 mA
6.4 Thermal Information LM431
THERMAL METRIC(1) D (SOIC) DBZ (SOT-23) LP (TO-92) UNIT
8 PINS 3 PINS 3 PINS
RθJA Junction-to-ambient thermal resistance 126.9 267.7 162.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 72.2 138.3 85.8 °C/W
RθJB Junction-to-board thermal resistance 67.5 61 — °C/W
ψJT Junction-to-top characterization parameter 21.1 21.5 29.4 °C/W
ψJB Junction-to-board characterization parameter 67 60.1 141.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TA= 25°C unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VZ= VREF, II= 10 mA 2.44 2.495 2.55
LM431A (Figure 6 )
VZ= VREF, II= 10 mA
VREF Reference voltage 2.47 2.495 2.52 V
LM431B (Figure 6 )
VZ= VREF, II= 10 mA 2.485 2.5 2.51
LM431C (Figure 6 )
Deviation of reference input voltage VZ= VREF, II= 10 mA,
VDEV 8 17 mV
overtemperature(1) TA= full range (Figure 6 )
VZfrom VREF to 10 V −1.4 −2.7
ΔVREF/ Ratio of the change in reference voltage to the IZ= 10 mA mV/V
ΔVZchange in cathode voltage (Figure 7 )VZfrom 10 V to 36 V −1−2
R1= 10 kΩ, R2=∞, II= 10 mA
IREF Reference input current 2 4 μA
(Figure 7 )
Deviation of reference input current R1= 10 kΩ, R2=∞, II= 10 mA,
∝IREF 0.4 1.2 μA
overtemperature TA= full range (Figure 7 )
IZ(MIN) Minimum cathode current for regulation VZ= VREF(Figure 6 ) 0.4 1 mA
IZ(OFF) OFF-state current VZ= 36 V, VREF = 0 V (Figure 8) 0.3 1 μA
(1) Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature
range.
The average temperature coefficient of the reference input voltage, ∝VREF, is defined as:
Where:
T2– T1= full temperature change (0–70°C).
VREF can be positive or negative depending on whether the slope is positive or negative.
Example: VDEV = 8 mV, VREF = 2495 mV, T2– T1= 70°C, slope is positive.
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Electrical Characteristics (continued)
TA= 25°C unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VZ= VREF, LM431A, 0.75
Frequency = 0 Hz (Figure 6 )
rZDynamic output impedance(2) Ω
VZ= VREF, LM431B, LM431C 0.5
Frequency = 0 Hz (Figure 6 )
(2) The dynamic output impedance, rZ, is defined as:
When the device is programmed with two external resistors, R1 and R2, (see Figure 7), the dynamic output impedance of the overall
circuit, rZ, is defined as:
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6.6 Typical Characteristics
Note: The areas under the curves represent conditions that may
cause the device to oscillate. For curves B, C, and D, R2 and V+
were adjusted to establish the initial VZand IZconditions with CL= 0.
V+and CLwere then adjusted to determine the ranges of stability.
Figure 2. Stability Boundary Conditions
Figure 1. Dynamic Impedance vs Frequency
7 Parameter Measurement Information
Figure 3. Test Circuit for Dynamic Impedance vs Frequency Curve
Figure 4. Test Circuit for Curve A Above
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Parameter Measurement Information (continued)
Figure 5. Test Circuit for Curves B, C and D Above
Figure 6. Test Circuit for VZ= VREF
Note: VZ= VREF (1 + R1/R2) + IREF × R1
Figure 7. Test Circuit for VZ> VREF
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Parameter Measurement Information (continued)
Figure 8. Test Circuit for OFF-State Current
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8 Detailed Description
8.1 Overview
The LM431 is an adjustable precision shunt voltage regulator with ensured temperature stability over the entire
temperature range. The part has three different packages available to meet small footprint requirements, and is
available in three different tolerance grades.
8.2 Functional Block Diagram
Figure 9. LM431 Symbol
Figure 10. LM431 Block Diagram
8.3 Feature Description
The LM431 is a precision Zener diode. The part requires a small quiescent current for regulation, and regulates
the output voltage by shunting more or less current to ground, depending on input voltage and load. The only
external component requirement is a resistor between the cathode and the input voltage to set the input current.
An external capacitor can be used on the input or output, but is not required.
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Feature Description (continued)
Figure 11. Equivalent Circuit
8.4 Device Functional Modes
The LM431 is most commonly operated in closed-loop mode, where the reference node is tied to the output
voltage via a resistor divider. The output voltage remains in regulation as long as Izis between 1 mA and 100
mA. The part can also be used in open-loop mode to act as a comparator, driving the feedback node from
another voltage source.
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O
S
LOAD Z
V V
R
I I
+-
=
+
LM431
SNVS020H –MAY 2000–REVISED JANUARY 2016
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LM431 is an adjustable precision shunt voltage regulator with ensured temperature stability over the entire
temperature range. For space critical applications, the LM431 is available in space saving SOIC-8, SOT-23 and
TO-92 packages. The minimum operating current is 1 mA while the maximum operating current is 100 mA.
The typical thermal hysteresis specification is defined as the change in 25°C voltage measured after thermal
cycling. The device is thermal cycled to temperature 0°C and then measured at 25°C. Next the device is thermal
cycled to temperature 70°C and again measured at 25°C. The resulting VOUT delta shift between the 25°C
measurements is thermal hysteresis. Thermal hysteresis is common in precision references and is induced by
thermal-mechanical package stress. Changes in environmental storage temperature, operating temperature and
board mounting temperature are all factors that can contribute to thermal hysteresis.
In a conventional shunt regulator application (Figure 12), an external series resistor (RS) is connected between
the supply voltage and the LM431 cathode pin. RSdetermines the current that flows through the load (ILOAD) and
the LM431 (IZ). Since load current and supply voltage may vary, RSmust be small enough to supply at least the
minimum acceptable IZto the LM431 even when the supply voltage is at its minimum and the load current is at
its maximum value. When the supply voltage is at its maximum and ILOAD is at its minimum, RSmust be large
enough so that the current flowing through the LM431 is less than 100 mA.
RSmust be selected based on the supply voltage, (V+), the desired load and operating current, (ILOAD and IZ),
and the output voltage, see Equation 1.
(1)
The LM431 output voltage can be adjusted to any value in the range of 2.5 V through 37 V. It is a function of the
internal reference voltage (VREF) and the ratio of the external feedback resistors as shown in Figure 12. The
output voltage is found using Equation 2.
VO= VREF * (1 + R1/R2)
where
• VOis the output voltage (also, cathode voltage, VZ). The actual value of the internal VREF is a function of VZ. (2)
The corrected VREF is determined by Equation 3:
VREF =∆VZ* (∆VREF/∆VZ)+VY
where
• VY= 2.5 V and ∆VZ= (VZ– VY)
•ΔVREF/ΔVZis found in the Electrical Characteristics and is typically −1.4 mV/V for VZraging from VREF to 10 V
and –1 mV/V for VZraging from 10 V to 36 V. (3)
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_MIN O
S _MAX
LOAD _ MAX Z _ MIN
V V
RI I
+-
=
+
_MAX O
S _MIN
LOAD _ MIN Z _ MAX
V V
RI I
+-
=
+
LM431
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9.2 Typical Applications
9.2.1 Shunt Regulator
Figure 12. Shunt Regulator
9.2.1.1 Design Requirements
Design a shunt regulator with the following requirements:
• V+> VO
• VO=5V
Select RS(a resistor between V+and VO) such that: 1 mA < IZ< 100 mA
9.2.1.2 Detailed Design Procedure
The resistor RSmust be selected such that current IZremains in the operational region of the part for the entire
V+range and load current range. The two extremes to consider are V+at its minimum, and the load at its
maximum, where RSmust be small enough for IZto remain above 1 mA. The other extreme is V+at its
maximum, and the load at its minimum, where RSmust be large enough to maintain IZ< 100 mA. If unsure, try
using 1 mA ≤IR≤10 mA as a starting point; just remember the value of IZvaries with input voltage and load.
Use Equation 4 and Equation 5 to set RSbetween RS_MIN and RS_MAX.
(4)
(5)
Set feedback resistors R1and R2for a resistor divider based on Equation 2 and reproduced in Equation 6
VO= VREF * (1 + R1/R2) (6)
So, for a 5-V output voltage, VO, and VREF of 2.5 V, simple calculation yields R1/R2= 1. Based on this, select
R1=1kΩand R2 = 1 kΩ.
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Typical Applications (continued)
9.2.1.3 Application Curves
Figure 14. Thermal Information
Figure 13. Input Current vs VZ
Figure 15. Input Current vs VZ
9.2.2 Other Applications
Figure 16. Single Supply Comparator With Temperature Compensated Threshold
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Typical Applications (continued)
Figure 17. Series Regulator
Figure 18. Output Control of a Three Terminal Fixed Regulator
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Typical Applications (continued)
Figure 19. Higher Current Shunt Regulator
Figure 20. Crow Bar
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Typical Applications (continued)
Figure 21. Over Voltage and Under Voltage Protection Circuit
Figure 22. Voltage Monitor
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Typical Applications (continued)
Figure 23. Delay Timer
Figure 24. Current Limiter or Current Source
Figure 25. Constant Current Sink
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R physically close to device cathode
S
C physically close to device
IN C physically close to device
OUT
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10 Power Supply Recommendations
While a bypass capacitor is not required on the input voltage line, TI recommends reducing noise on the input
which could affect the output. TI recommends a 0.1-µF ceramic capacitor or larger.
11 Layout
11.1 Layout Guidelines
Place external components as close to the device as possible. Place RSclose to the cathode, as well as the
input bypass capacitor, if used. Keep feedback resistor close the device whenever possible.
11.2 Layout Example
Figure 26. LM431 Layout Recommendation
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM431ACM3/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431ACM3X SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431ACM3X/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431ACMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM431AIM3 SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431AIM3/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431AIM3X/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM431BCM3 SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431BCM3/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431BCM3X/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431BCMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM431BIM3 SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431BIM3/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431BIM3X SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431BIM3X/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM431CCM3/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM431CCM3X SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431CCM3X/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431CIM3 SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431CIM3/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431CIM3X SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
LM431CIM3X/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM431ACM3/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431ACM3X SOT-23 DBZ 3 3000 210.0 185.0 35.0
LM431ACM3X/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0
LM431ACMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM431AIM3 SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431AIM3/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431AIM3X/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0
LM431AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM431BCM3 SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431BCM3/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431BCM3X/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM431BCMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM431BIM3 SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431BIM3/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431BIM3X SOT-23 DBZ 3 3000 210.0 185.0 35.0
LM431BIM3X/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0
LM431BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM431CCM3/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431CCM3X SOT-23 DBZ 3 3000 210.0 185.0 35.0
LM431CCM3X/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0
LM431CIM3 SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431CIM3/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0
LM431CIM3X SOT-23 DBZ 3 3000 210.0 185.0 35.0
LM431CIM3X/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 3
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PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
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EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
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EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
www.ti.com
PACKAGE OUTLINE
3X 2.67
2.03
5.21
4.44
5.34
4.32
3X
12.7 MIN
2X 1.27 0.13
3X 0.55
0.38
4.19
3.17
3.43 MIN
3X 0.43
0.35
(2.54)
NOTE 3
2X
2.6 0.2
2X
4 MAX
SEATING
PLANE
6X
0.076 MAX
(0.51) TYP
(1.5) TYP
TO-92 - 5.34 mm max heightLP0003A
TO-92
4215214/B 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Lead dimensions are not controlled within this area.
4. Reference JEDEC TO-226, variation AA.
5. Shipping method:
a. Straight lead option available in bulk pack only.
b. Formed lead option available in tape and reel or ammo pack.
c. Specific products can be offered in limited combinations of shipping medium and lead options.
d. Consult product folder for more information on available options.
EJECTOR PIN
OPTIONAL
PLANE
SEATING
STRAIGHT LEAD OPTION
321
SCALE 1.200
FORMED LEAD OPTION
OTHER DIMENSIONS IDENTICAL
TO STRAIGHT LEAD OPTION
SCALE 1.200
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND
TYP
(1.07)
(1.5) 2X (1.5)
2X (1.07)
(1.27)
(2.54)
FULL R
TYP
( 1.4)0.05 MAX
ALL AROUND
TYP
(2.6)
(5.2)
(R0.05) TYP
3X ( 0.9) HOLE
2X ( 1.4)
METAL
3X ( 0.85) HOLE
(R0.05) TYP
4215214/B 04/2017
TO-92 - 5.34 mm max heightLP0003A
TO-92
LAND PATTERN EXAMPLE
FORMED LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X
SOLDER MASK
OPENING
METAL
2X
SOLDER MASK
OPENING
123
LAND PATTERN EXAMPLE
STRAIGHT LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X
METAL
TYP
SOLDER MASK
OPENING
2X
SOLDER MASK
OPENING
2X
METAL
12 3
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TAPE SPECIFICATIONS
19.0
17.5
13.7
11.7
11.0
8.5
0.5 MIN
TYP-4.33.7
9.75
8.50
TYP
2.9
2.4 6.75
5.95
13.0
12.4
(2.5) TYP
16.5
15.5
32
23
4215214/B 04/2017
TO-92 - 5.34 mm max heightLP0003A
TO-92
FOR FORMED LEAD OPTION PACKAGE
4203227/C
www.ti.com
PACKAGE OUTLINE
C
TYP
0.20
0.08
0.25
2.64
2.10 1.12 MAX
TYP
0.10
0.01
3X 0.5
0.3
TYP
0.6
0.2
1.9
0.95
TYP-80
A
3.04
2.80
B
1.4
1.2
(0.95)
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
0.2 C A B
1
3
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
3X (1.3)
3X (0.6)
(2.1)
2X (0.95)
(R0.05) TYP
4214838/C 04/2017
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
PKG
1
3
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
(2.1)
2X(0.95)
3X (1.3)
3X (0.6)
(R0.05) TYP
SOT-23 - 1.12 mm max heightDBZ0003A
SMALL OUTLINE TRANSISTOR
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
SYMM
PKG
1
3
2
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