AM29DL16XCT70ZC - Advanced Micro Devices

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to hel p you e val uate this product. A MD reserves the right to change or discontin ue work on this proposed

product without notice.

Publicati on# 21533 Rev: CAmendment/+5

Issue Date: Octob er 18, 1999

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29DL16xC

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flas h Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■Multiple bank architectures

— Three devices available with different bank sizes (refer

to Table 2)

■Secured Silicon (SecSi) Sector: Extra 64 KByte sector

—

F actory locked and identifiable:

16 bytes available f or

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

—

Customer lockable:

Can be read, programmed, or

erased just like other sectors. Once locked, data

cannot be changed

■Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

■Package options

— 48-ball FBGA

— 56-pin SSOP

— 48-pin TSOP

■Top or bottom boot block

■Manufactured on 0.32 µm process technology

■Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHARACTERISTICS

■High performance

— Access time as fast 70 ns

— Progr am time: 7 µs/word ty pical utilizi ng Accelerate funct ion

■Ultra low power consump tion (typic al values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

■Minimum 1 million write cycles guaranteed per sector

■20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■Data Manag eme nt So ftwa re (DM S)

— AMD-supplied software manages data programming

and erasing, enabling EEPROM emulation

— Eases sector erase limitations

■Supports Common Flash Memory Interface (CFI)

■Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■Any combination of sectors can be erased

■Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to reading array data

■WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program

timing

■Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

— Temporar y Sect or Unp rot ect allows cha ngi ng dat a in

protected sectors in-system

2 Am29DL16xC

PRELIMINARY

GENERAL DESCRIPTION

The Am29DL16xC family consists of 16 megabit, 3.0

volt-only flash memory devices, organized as 1,048,576

words of 16 bits each or 2,097,152 bytes of 8 bits each.

Word mode data appears on DQ0–DQ15; byte mode

data appears on DQ0–DQ7. The device is designed to

be programme d in-system with the standard 3.0 volt

VCC su pply, and can a lso be p rogrammed in stand ard

EPROM prog rammers.

The device is available with an access time of 70, 80,

90, or 120 ns. The devices are off ered in 56-pin SSOP,

48-pin TSOP, and 48-ball FBGA packages. Standard

cont rol pins— chip enable (CE #), wr ite enable (WE #),

and output enable (OE#)—control normal read and

write operations, and avoid bus contention issues.

The de vice requires only a single 3. 0 v o lt po wer sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

Sim ultaneous Read/Write Operations with

Zero Latency

The Simultan eous R ead/Wr ite a rchitect ure provide s

simultaneous operation by dividing the memory

space in to two banks. The device can improve overall

system perfor mance by allowing a host system to pro-

gram or erase in one bank, then immediately and

simultaneously read from the other bank, with zero la-

tency. This releases the system from waiting for the

completion of program or erase operations.

The Am29DL16xC device family uses multiple bank

architectures to provide flexibility for different applica-

tions. Three devices are available with the following

bank sizes:

Am29DL16xC Features

The Secured S ilicon (SecSi) Sec tor is an extra 64

Kbit sector capable of being permanently locked by

AMD or customers. The SecSi Sector Indica tor Bit

(DQ7) is permanently set to a 1 if the par t is factory

locked, and set to a 0 if customer loc kab le. Thi s wa y,

customer lockable par ts can never be used to replace

a factory locked par t.

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash ser vice), or

both. Customer Lockable par ts may utilize the SecSi

Secto r as bonus s pace, readi ng and wr iting like any

other flash sector, or may permanently lock their own

code there.

DMS (Data M anag ement Software) allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessar y to modify data in file str uctures,

as opposed to single-byte modifications. To write or

update a particula r piece of data ( a phon e number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memor y de-

vices), and more. Using DMS, user-wr itten software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memor y by calling one of only six functions. AMD pro-

vides this software to simplify system design and

software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or

erase operation is complete by using the dev ice sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically re tur ns

to reading array data.

The se ctor erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both progra m and erase

operations i n any combination of the sector s of mem-

ory. This can be achieved in-system or via

programming equipment.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

Device Bank 1 Bank 2

DL162 2 Mb 14 Mb

DL163 4 Mb 12 Mb

DL164 8 Mb 8 Mb

Am29DL16xC 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

BLOCK DIAGRAM

Part Number Am29DL16xC

Speed Op tion Standard Voltage Range: VCC = 2.7–3.6 V 70, 70R 80 90 120

Max Access Time (ns) 70 80 90 120

CE# Access (ns) 70 80 90 120

OE# Access (ns) 30 30 40 50

Upper Bank Address

A0–A19

RESET#

WE#

CE#

BYTE#

DQ0–DQ15

WP#/ACC

STATE

CONTROL

COMMAND

RY/BY#

Upper Bank

X-Decoder

Y-Decoder

Latches and Control Logic

OE# BYTE#

DQ0–DQ15

Lower Bank

Y-Decoder

X-Decoder

Latches and

Control Logic

Lower Bank Address

Status

Control

A0–A19

A0–A19A0–A19

DQ0–DQ15 DQ0–DQ15

21533C-1

4 Am29DL16xC

PRELIMINARY

CONNECTION DIAGRAMS

A15

A18

A14

A13

A12

A11

A10

A19

WE#

RESET#

WP#/ACC

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

48-Pin Standard TSOP

21533C-2

WP#/ACC

RY/BY#

A18

A17

CE#

VSS

OE#

DQ0

DQ8

RESET#

WE#

A19

A10

A11

A12

A13

A14

A15

A16

BTYE#

VSS

DQ15/A-1

DQ7

DQ14

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

56-Pin SSO P

Am29DL16xC 5

PRELIMINARY

CONNECTION DIAGRAMS

Special Handling Instructions for FBGA

Package

Specia l handling is required for Flash M emor y prod-

ucts in FBGA packages.

Flash memor y devices in FBGA packages may be

damaged if exposed to ul trasoni c cle aning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 V

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2NCA18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# V

CE#A0A1A2A4A3

21533C-4

48-Ball FBG A

Top View, Balls Facing Down

6 Am29DL16xC

PRELIMINARY

PIN DESCRIPTION

A0–A19 = 20 Addresses

DQ0–DQ14 = 15 Data Inputs/Outputs

DQ15/A-1 = DQ15 (Data Input/Output, word

mode), A-1 (LSB Address Input, byte

mode)

CE# = Chip Enable

OE# = Output Enable

WE# = Write Enable

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RESET# = Hardware Reset Pin, Active Low

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy Output

VCC = 3.0 volt-only single power supply

(see Product Selector Guide f or speed

options and v oltage supply toler ances)

VSS = Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

21533C-5

20 16 or 8

DQ0–DQ15

(A-1)

A0–A19

CE#

OE#

WE#

RESET#

BYTE#

RY/BY#

WP#/ACC

Am29DL16xC 7

PRELIMINARY

ORDERING INFORMATION

Standard Pr od ucts

AMD standard products are available in several packages and operating ranges. The order number (Valid

Combination) is formed by a combination of the following:

Valid Combinations

V alid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

Am29DL16xC T 70 E I OPTIONAL PROCESSING

Blank = Standard Processing

B=Burn-In

N = 16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125 °C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

Z = 56-Pin S h rink Small Outline Package (SSO056)

WC = 48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 9 mm package (FBC048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T= Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29DL16xC

16Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Comb inations for TSOP and SSOP Packages

AM29DL162CT70,

AM29DL162CB70 EI

AM29DL163CT70R,

AM29DL163CB70R ZC

AM29DL163CT70,

AM29DL163CB70 EI

AM29DL162CT90,

AM29DL162CB90 EI

AM29DL163CT90,

AM29DL163CB90 EI, ZI

AM29DL162CT120,

AM29DL162CB120 EI, EE

AM29DL163CT120,

AM29DL163CB120 EI, EE, ZI, ZE

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29DL162CT70,

AM29DL162CB70

WCI

D162CT70V,

D162CB70V

AM29DL163CT70,

AM29DL163CB70 D163CT70V,

D163CB70V

AM29DL164CT80,

AM29DL164CB80 D164CT80V,

D164CB80V

AM29DL162CT90,

AM29DL162CB90 D162CT90V,

D162CB90V

AM29DL163CT90,

AM29DL163CB90 D163CT90V,

D163CB90V

AM29DL164CT90,

AM29DL164CB90 D164CT90V,

D164CB90V

AM29DL162CT120,

AM29DL162CB120

WCI,

WCE

D162CT12V,

D162CB12V

I, E

AM29DL163CT120,

AM29DL163CB120 D163CT12V,

D163CB12V

AM29DL164CT120,

AM29DL164CB120 D164CT12V,

D164CB12V

8 Am29DL16xC
PRELIMINARY 
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are i nitiated through
the internal comm and register. The command register
itself d oes not occupy any addre ssable memor y lo ca-
tion. The register is a latch used to store the
comman ds, along with  the address  and data in for ma-
tion needed to execute the command. The contents of
the regi ster ser ve a s inputs to the in ternal  state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29DL16xC Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8 .5–12.5
 
V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, 
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector prot ect a nd sect or unpr otect  functi ons may also be implemented via  prog r amming e quipment.  See the  “Sec tor/Sec tor 
Block  Protect ion and  Unprote ction” secti on.
3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector 
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block 
Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Word/Byte Configuration
The BYTE# pin controls  whether the device data I/O
pins  operate in the  byte or word co nfiguration.  If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. Th e d ata I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set  for reading arr ay data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessar y in this mode to obtain array data.
Standard microprocessor read cycles that asser t valid
Operation CE# OE# WE# RESET# WP#/ACC Addresses
(Note 2) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE# 
= VIL
Read L L H H L/H AIN DOUT DOUT DQ8–DQ14 = High-Z, 
DQ15 = A-1
Write L H L H (Note 3) AIN DIN DIN
Standby VCC ± 
0.3 V XXVCC ± 
0.3 V H X High-Z High-Z High-Z
Output Disa ble L H H H L /H X High-Z High-Z High-Z
Reset X X X L L/H X High-Z High-Z High-Z
Sector Protect (Note 2) L H L VID L/H SA, A6 = L, 
A1 = H, A0 = L DIN XX
Sector Unprotect (Note 2) L H L VID (Note 3) SA, A6 = H, 
A1 = H, A0 = L DIN XX
Temporary Sector Unprotect X X X VID (Note 3) AIN DIN DIN High-Z

Am29DL16xC 9
PRELIMINARY 
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
See “Requirements for Reading Array Data” for more
infor mation. Refer to the AC Read-Only Operations
table for timing specific ations and to  Figure 1 3 for the
timing diagram. ICC1 in the DC Characteristics table
repre sents the  active curren t specifi cation for re ading
array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
infor mation. 
The device f eatures an Unlock Bypass mode to facili-
tate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Configuration” section has details on pro-
gramming data to the device using both standa rd and
Unlock By pass command sequences.
An erase oper at ion can er ase  one sect or, multiple sec-
tors, or the entire device. Tables 3–6 indicate the
addres s space that e ach sec tor occupie s. The devi ce
addres s space is d ivided in to two banks: B ank 1 con-
tains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors o f  unifor m size. A “bank ad-
dress” is the address bits required to uniquely select a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
ICC2 in the DC Characteristics table represents the ac-
tive current spe cification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one  of two functions
provided by the WP#/ACC pin. This  function is pr ima-
ril y intend ed to al low fas ter manufacturi ng thro ughput
at the factory. 
If the  system  asserts VHH on this pin, the d evice auto-
matically enters the aforementioned Unlock Bypass
mode, temporar ily unprotects any protected sec tors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would  use a two-cycle  program comm and sequen ce
as required by the Unlock Bypass mode. Removing
VHH from  the WP #/ACC pin retur ns the  device to nor-
mal operation. Note that the WP#/ A CC pin must not be
at VHH for operations other than accelerated program-
ming, or device damage may result. In addition, the
WP#/A CC pin must not be left floating or unconn ected;
inconsistent behavior of the device may result.
A utoselect Functions
If the system writes the autoselect command se-
quence, the device enter s the autoselect m ode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply  in
this mode. R efer to the  Autose lect Mode and Autose-
lect Command Sequence sections for more
information.
Sim ultaneous Read/Write Operations with 
Zero Lat e n cy
This d evice is capa ble of reading  data from  one ba nk
of memor y while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 20 shows how re ad and write cycles
may be  initiated for simultaneous operation with zero
latency. ICC6 and ICC7 in the DC Character istics table
represent the current specifications  for read-while-pro-
gram and read-while-er ase, respectively.
Standby Mode
When the  system is no t reading or wr iting to the de-
vice, it can place the  device in the st andby mod e. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and RESET#  pins are  both held at VCC ± 0.3 V.
(Note that this is a m ore restricte d voltage range tha n
VIH.) I f CE# and RESET# are  held at  VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be  greater. The  device  re-
quires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash dev ice en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC +

10 Am29DL16xC

PRELIMINARY

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched an d always available to the system.

ICC4 in the DC Characteristics table represents the

automatic sleep mode current specification .

RESET#: Hardware Reset Pin

The RESET# p in provides a hardware method of r e-

setting the device to reading array data. When the

RESET# pin is driven low for at least a per iod of tRP

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/w rite co mmand s for th e duration of the RE SET#

pulse. The device also resets the internal s tate ma-

chine to reading array data. The operation that was

interrupted should be reinitiated once th e device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

dra ws CMOS stan db y c urrent (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitr y. A system reset would thus also reset the Flas h

memory, enabling the system to read th e boot-up firm-

ware from the Flash memor y.

If RESET# is asserted during a program or erase op-

eration, the RY/B Y# pin remain s a “0” ( busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The sys-

tem c an thus monitor RY /BY# to deter mine w hether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tREADY (not during E mbedded Algo-

rithms). The system can read data tRH after the

RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2. Am29DL16xC Device Bank Divisions

Device

Part Number

Bank 1 Bank 2

Megabits Sector Sizes Megabits Sector Sizes

Am29DL162C 2 Mbit Eight 8 Kbyte/4 Kword,

three 64 Kbyte/32 Kword 14 Mbit Twen ty- eigh t

64 Kbyte/32 Kword

Am29DL163C 4 Mbit Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword 12 Mbit Twenty-four

64 Kbyte/32 Kword

Am29DL164C 8 Mbit Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword 8 Mbit Sixteen

64 Kbyte/32 Kword

Am29DL16xC 11

PRELIMINARY

Table 3. Sector Addresses for Top Boot Sector Devices

Note: The address range is A19:A-1 in byte mode (BYTE#=V

) or A19:A0 in word mode (BYTE#=V

). The bank address bits are A19–A17 for

Am29DL162CT, A19 and A18 f or Am29DL163CT, and A19 for Am29DL164CB.

Table 4. SecSi Sector Addresses for Top Boot Devices

Am29DL164CT

Am29DL163CT

Am29DL162CT

Sector Sector Address

A19–A12 Sector Size

(Kbytes/Kwords) (x8)

Address Range (x16)

Address Range

Bank 2

SA0 00000xxx 64/32 000000h-00FFFFh 00000h–07FFFh

SA1 00001xxx 64/32 010000h-01FFFFh 08000h–0FFFFh

SA2 00010xxx 64/32 020000h-02FFFFh 10000h–17FFFh

SA3 00011xxx 64/32 030000h-03FFFFh 18000h–1FFFFh

SA4 00100xxx 64/32 040000h-04FFFFh 20000h–27FFFh

SA5 00101xxx 64/32 050000h-05FFFFh 28000h–2FFFFh

SA6 00110xxx 64/32 060000h-06FFFFh 30000h–37FFFh

SA7 00111xxx 64/32 070000h-07FFFFh 38000h–3FFFFh

SA8 01000xxx 64/32 080000h-08FFFFh 40000h–47FFFh

SA9 01001xxx 64/32 090000h-09FFFFh 48000h–4FFFFh

SA10 01010xxx 64/32 0A0000h-0AFFFFh 50000h–57FFFh

SA11 01011xxx 64/32 0B0000h-0BFFFFh 58000h–5FFFFh

SA12 01100xxx 64/32 0C0000h-0CFFFFh 60000h–67FFFh

SA13 01101xxx 64/32 0D0000h-0DFFFFh 68000h–6FFFFh

SA14 01110xxx 64/32 0E0000h-0EFFFFh 70000h–77FFFh

SA15 01111xxx 64/32 0F0000h-0FFFFFh 78000h–7FFFFh

Bank 1

SA16 10000xxx 64/32 100000h-10FFFFh 80000h–87FFFh

SA17 10001xxx 64/32 110000h-11FFFFh 88000h–8FFFFh

SA18 10010xxx 64/32 120000h-12FFFFh 90000h–97FFFh

SA19 10011xxx 64/32 130000h-13FFFFh 98000h–9FFFFh

SA20 10100xxx 64/32 140000h-14FFFFh A0000h–A7FFFh

SA21 10101xxx 64/32 150000h-15FFFFh A8000h–AFFFFh

SA22 10110xxx 64/32 160000h-16FFFFh B0000h–B7FFFh

SA23 10111xxx 64/32 170000h-17FFFFh B8000h–BFFFFh

Bank 1

SA24 11000xxx 64/32 180000h-18FFFFh C0000h–C7FFFh

SA25 11001xxx 64/32 190000h-19FFFFh C8000h–CFFFFh

SA26 11010xxx 64/32 1A0000h-1AFFFFh D0000h–D7FFFh

SA27 11011xxx 64/32 1B0000h-1BFFFFh D8000h–DFFFFh

Bank 1

SA28 11100xxx 64/32 1C0000h-1CFFFFh E0000h–E7FFFh

SA29 11101xxx 64/32 1D0000h-1DFFFFh E8000h–EFFFFh

SA30 11110xxx 64/32 1E0000h-1EFFFFh F0000h–F7FFFh

SA31 11111000 8/4 1F0000h-1F1FFFh F8000h–F8FFFh

SA32 11111001 8/4 1F2000h-1F3FFFh F9000h–F9FFFh

SA33 11111010 8/4 1F4000h-1F5FFFh FA000h–FAFFFh

SA34 11111011 8/4 1F6000h-1F7FFFh FB000h–FBFFFh

SA35 11111100 8/4 1F8000h-1F9FFFh FC000h–FCFFFh

SA36 11111101 8/4 1FA000h-1FBFFFh FD000h–FDFFFh

SA37 11111110 8/4 1FC000h-1FDFFFh FE000h–FEFFFh

SA38 11111111 8/4 1FE000h-1FFFFFh FF000h–FFFFFh

Device Sector Address

A19–A12 Sector

Size (x8)

Address Range (x16)

Address Range

Am29DL162xCT 11111xxx 64/32 1F0000h-1FFFFFh F8000h–FFFFFh

12 Am29DL16xC

PRELIMINARY

Table 5. Sector Addresses fo r Bottom Boot Sector Devices

Note: The address range is A19:A-1 in byte mode (BYTE#=V

) or A19:A0 in word mode (BYTE#=V

). The bank address bits are A19–A17 for

Am29DL162CB, A19 and A18 for Am29DL163CB, and A19 for Am29DL164CB.

Table 6. SecSi Sector Addresses for Bottom Boot Devices

Am29DL164CB

Am29DL163CB

Am29DL162CB

Sector Sector Address

A19–A12 Sector Size

(Kbytes/Kwords) (x8)

Address Range (x16)

Address Range

Bank 1

SA0 00000000 8/4 000000h-001FFFh 00000h-00FFFh

SA1 00000001 8/4 002000h-003FFFh 01000h-01FFFh

SA2 00000010 8/4 004000h-005FFFh 02000h-02FFFh

SA3 00000011 8/4 006000h-007FFFh 03000h-03FFFh

SA4 00000100 8/4 008000h-009FFFh 04000h-04FFFh

SA5 00000101 8/4 00A000h-00BFFFh 05000h-05FFFh

SA6 00000110 8/4 00C000h-00DFFFh 06000h-06FFFh

SA7 00000111 8/4 00E000h-00FFFFh 07000h-07FFFh

SA8 00001XXX 64/32 010000h-01FFFFh 08000h-0FFFFh

SA9 00010XXX 64/32 020000h-02FFFFh 10000h-17FFFh

SA10 00011XXX 64/32 030000h-03FFFFh 18000h-1FFFFh

Bank 2

SA11 00100XXX 64/32 040000h-04FFFFh 20000h-27FFFh

SA12 00101XXX 64/32 050000h-05FFFFh 28000h-2FFFFh

SA13 00110XXX 64/32 060000h-06FFFFh 30000h-37FFFh

SA14 00111XXX 64/32 070000h-07FFFFh 38000h-3FFFFh

Bank 2

SA15 01000XXX 64/32 080000h-08FFFFh 40000h-47FFFh

SA16 01001XXX 64/32 090000h-09FFFFh 48000h-4FFFFh

SA17 01010XXX 64/32 0A0000h-0AFFFFh 50000h-57FFFh

SA18 01011XXX 64/32 0B0000h-0BFFFFh 58000h-5FFFFh

SA19 01100XXX 64/32 0C0000h-0CFFFFh 60000h-67FFFh

SA20 01101XXX 64/32 0D0000h-0DFFFFh 68000h-6FFFFh

SA21 01110XXX 64/32 0E0000h-0EFFFFh 70000h-77FFFh

SA22 01111XXX 64/32 0F0000h-0FFFFFh 78000h-7FFFFh

Bank 2

SA23 10000XXX 64/32 100000h-10FFFFh 80000h-87FFFh

SA24 10001XXX 64/32 110000h-11FFFFh 88000h-8FFFFh

SA25 10010XXX 64/32 120000h-12FFFFh 90000h-97FFFh

SA26 10011XXX 64/32 130000h-13FFFFh 98000h-9FFFFh

SA27 10100XXX 64/32 140000h-14FFFFh A0000h-A7FFFh

SA28 10101XXX 64/32 150000h-15FFFFh A8000h-AFFFFh

SA29 10110XXX 64/32 160000h-16FFFFh B0000h-B7FFFh

SA30 10111XXX 64/32 170000h-17FFFFh B8000h-BFFFFh

SA31 11000XXX 64/32 180000h-18FFFFh C0000h-C7FFFh

SA32 11001XXX 64/32 190000h-19FFFFh C8000h-CFFFFh

SA33 11010XXX 64/32 1A0000h-1AFFFFh D0000h-D7FFFh

SA34 11011XXX 64/32 1B0000h-1BFFFFh D8000h-DFFFFh

SA35 11100XXX 64/32 1C0000h-1CFFFFh E0000h-E7FFFh

SA36 11101XXX 64/32 1D0000h-1DFFFFh E8000h-EFFFFh

SA37 11110XXX 64/32 1E0000h-1EFFFFh F0000h-F7FFFh

SA38 11111XXX 64/32 1F0000h-1FFFFFh F8000h-FFFFFh

Device Sector Address

A19–A12 Sector

Size (x8)

Address Range (x16)

Address Range

Am29DL16xCB 00000XXX 64/32 000000h-00FFFFh 00000h-07FFFh

Am29DL16xC 13

PRELIMINARY

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice iden tification, a nd sector protec tion verificatio n,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be

programmed with i ts co rresponding programming al-

gorithm. However, the auto select codes can a lso b e

accessed in-system through the command register.

When using programming equipmen t, the autoselec t

mode requires VID (8.5 V to 12.5 V) on addres s pin A9.

Address pins A6, A1, and A0 must be as shown in

Table 7. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order a ddress bits (see Tables 3–6). Table 7

shows the r emaining address bits that are don’t car e.

When all necessary bits have been set as required,

the programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 14. This method

does not require VID. Refer to th e Autoselect Com-

mand Sequence section for more information.

Table 7. Am29DL16xC Autoselect Codes, (High Voltage Method)

Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA =

Sector Address, X = Don’t care.

Description CE# OE# WE#

A19

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ8 to DQ15 DQ7

DQ0

BYTE#

= VIH

BYTE#

= VIL

Manufacturer ID: AMD L L H BA X VID XLXLL X X 01h

Device ID: Am29DL162C L L H BA X VID X L X L H 22h X 2Dh (T), 2Eh (B)

Device ID: Am29DL163C L L H BA X VID X L X L H 22h X 28h (T), 2Bh (B)

Device ID: Am29DL164C L L H BA X VID X L X L H 22h X 33h (T), 35h (B)

Sector Protection

Verification LLHSAX

VID XLXHL X X 01h (protected),

00h (unprotected)

SecSi Sector Indicator Bit

(DQ7) LLHBAX

VID XLXHH X X 80h (factory locked),

00h (not factory

locked)

14 Am29DL16xC

PRELIMINARY

Sector/Sector Block Protection and

Unprotection

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjac ent sectors that are

protected or unprotected at the same time (see Tables

8 and 9).

T abl e 8. T op Boot Sector/Sector Block Addresses

for Protection/Unprotection

Table 9. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

The hardware sector protection feature disables both

progr am and er ase operat ions in any sect or. The hard-

ware sector unprotection feature re-enables both

program and eras e operations in p reviously protected

sectors. Sector protection and unprotect i on can be im-

plemented via two methods.

The primary method requires VID on the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 25 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect

wr ite cycle.

The alter nate method intended only for programming

equipment r equires VID on add ress pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices.

Publication number 22243 contains further details;

contact an AMD representative to request a copy.

The device is shipp ed with all sectors unprotected.

AMD o ffers the option of pr ogramming and protectin g

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode

section for details.

Sector / Sector

Blo ck A19–A12 Sector / Sector Block Size

SA0 00000XXX 64 Kbytes

SA1-SA3 00001XXX,

00010XXX,

00011XXX 192 (3x64) Kbytes

SA4- SA7 0 01XXXXX 256 (4x 64) Kbyt es

SA8-SA11 010XXXXX 256 (4x64) Kbytes

SA12- SA1 5 01 1XXXXX 256 (4x64 ) Kbytes

SA16- SA1 9 10 0XXXXX 256 (4x64 ) Kbytes

SA20- SA2 3 10 1XXXXX 256 (4x64 ) Kbytes

SA24- SA2 7 11 0XXXXX 256 (4x64 ) Kbytes

SA28-SA30 11100XXX,

11101XXX,

11110XXX 192 (3x64) Kbytes

SA31 11111000 8 Kbytes

SA32 11111001 8 Kbytes

SA33 11111010 8 Kbytes

SA34 11111011 8 Kbytes

SA35 11111100 8 Kbytes

SA36 11111101 8 Kbytes

SA37 11111110 8 Kbytes

SA38 11111111 8 Kbytes

Sector / Sector

Block A 19–A12 Sect or / S ector Block Size

SA38 11111XXX 64 Kbytes

SA37-SA35 11110XXX,

11101XXX,

11100XXX 192 (3x64) Kbytes

SA34- SA 31 110XXXX X 256 (4x6 4) Kbyt es

SA30- SA 27 101XXXX X 256 (4x6 4) Kbyt es

SA26- SA 23 100XXXX X 256 (4x6 4) Kbyt es

SA22- SA 19 011XXXX X 256 (4x6 4) Kbyt es

SA18- SA 15 010XXXX X 256 (4x6 4) Kbyt es

SA14- SA 11 001XXXX X 256 (4x6 4) Kbyt es

SA10-SA8 00001XXX,

00010XXX,

00011XXX 192 (3x64) Kbytes

SA7 00000111 8 Kbytes

SA6 00000110 8 Kbytes

SA5 00000101 8 Kbytes

SA4 00000100 8 Kbytes

SA3 00000011 8 Kbytes

SA2 00000010 8 Kbytes

SA1 00000001 8 Kbytes

SA0 00000000 8 Kbytes

Am29DL16xC 15

PRELIMINARY

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting certain boot sectors without

using VID. This function is one of two provided by the

WP#/ACC pin.

If the s yst e m asserts VIL on the W P#/ACC pin, the de-

vice disables program and erase functions in the two

“outermost” 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected

using the method described in “Sector/Sector Block

Protection and Unprotection”. The two ou ter most 8

Kbyte boot s ectors are the two sectors containin g the

lowest addres ses in a bo ttom-boo t-configured device,

or the two sectors containing the highest addresses in

a top-boot-configured device.

If th e system a sserts VIH on the WP#/ACC pin, the de-

vice reverts to whether the tw o outermost 8 Kb yt e boot

sectors were last set to be protected or unprotected.

That is, sector protection or unprotection for these two

sectors depends on whether they were last protected

or unprotected using the method described in “Sec-

tor/Sector Block Protection and Unprotection”.

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

Temporary Sector/Sector Block Unprotect

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjac ent sectors that are

protected or unprotected at the same time (see Tables

8 and 9).

This feature allows temporar y unprotection of previ-

ously protected sect ors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to VID (8.5 V – 12. 5 V). D uring this m ode,

formerly protected sectors can be programmed or

erased by selecting the sector addresses. Once VID is

removed from the RESET# pin, all the previously p ro-

tected sectors are prot ected again. Figure 1 shows the

algorithm, and Figure 24 shows the timing diagrams,

for this feature.

Figure 1. Temporary Sector Unprotect Operation

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

21533C-6

Notes:

1. All protected sectors unprotected (If WP#/ACC = VIL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once

again.

16 Am29DL16xC

PRELIMINARY

Note: The term “sector” in the figure applies to both sectors and sector blocks.

Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

21533C-7

Am29DL16xC 17

PRELIMINARY

SecSi (Secured Silicon) Sector Flash

Memory Region

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 64 Kbytes in length, and

uses a SecSi Sector Indicator Bit to indicate whether

or not the SecSi Sector is locked when shipped from

the factory. Th is bit is per manently set at the factor y

and cannot be changed , which prevents cloning of a

factory locked part. This ensures the security of the

ESN once the product is shipped to the field.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tor y-locked version is always protec ted when shippe d

from the factor y, and has the SecSi Sector Indicator

Bit permanently set to a “1.” The customer-lockable

version is ship ped with the unpr otected, allowing cus-

tomers to utilize the that sector in any manner they

choose. The customer-lockable version has the SecSi

Sector Indicator Bit permanently set to a “0.” Thus, the

SecSi Sector Indicator Bit prevents customer-lockable

devices from being used to replace devices that are

facto ry locked.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the

addresses normally occupied by the boot sect ors . This

mode of operation continues until the system issues

the Exit SecS i Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the boot sectors.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

In a factory lo cked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is available preprogrammed with one of the

following:

■A random, secure ESN only

■Customer code through the ExpressFlash service

■Both a random, secure ESN and customer code

through the ExpressFlash service.

In dev ices that ha v e an ESN, a Bottom Boot de vice will

have the 16-byt e ESN in the lowest addressab l e mem-

or y ar ea at ad dresses 00000 h–00 007h in word m ode

(or 000 000h–000 00Fh in byte mode). In the Top Boot

device the star ting address of the ESN will be at the

bottom of the lowest 8 Kbyte boot sector at addresses

F8000h–F8007h in word mode (or 1F0000h–1F000Fh

in byte mode).

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash ser vice. AMD

progr ams the customer’s code , with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the per manen tly locked. Contact an A MD

representative for details on using AMD’s Express-

Flash service.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional Fl as h m e mo ry s p ac e,

expanding the size of the available Flash array by 64

Kbytes. The Se cSi S ector can be rea d, programm ed,

and eras e d a s ofte n a s re qu ir ed . T he SecSi Se ctor area

can be protected using one of the following procedures:

■Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that

RESET# may be at either V IH or V ID

. This

allows in-system protection of the without raising

any device pin to a high voltage. Note that this

method is only applicable to the SecSi Sector.

■Write the three-cycle Enter SecSi Sector Region

command sequence, and then use the alternate

method of sector protection described in the “Sec-

tor/S ector Bloc k Prot ection and Unp rotectio n”.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region

command sequence to return to reading and writing

the remainder of the array.

The SecSi S ector protection must be used with cau-

tion since, once protected, there is no procedure

available for unprotecting the SecSi Sector area and

none of the bits in the SecSi Sector memory space

can be modified in any way.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadver tent writes (refer to Table 14 for com -

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which m ight otherwise be caused by

spurious system level signals during VCC power-up

and power-down transitions, or from system noise.

Low V CC Write Inhibit

When VCC is les s than VLKO, the device does not ac-

cept any write cycles. This protects data dur ing VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to reading array data. Subse-

18 Am29DL16xC

PRELIMINARY

quent writes are ignored until VCC is greater than VLKO.

The system must provide the proper signals to the

control pins to prevent unintentional writes when VCC

is greater than VLKO.

Write Pulse “Glitch” Protecti on

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE # must be a logica l zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH d uring power up,

the device does not accept commands on the rising

edge of WE #. The inter nal state mac hine is autom ati-

cally reset to reading array data on power-up.

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms t o be used for entire families of

devices. Software suppor t can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This device enters the CFI Query mode w hen the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The sys-

tem can read CFI information at the addresses given

in Tables 10–13. To terminate reading CFI data, the

system must write the reset command.

The system can also w rite the CFI query command

when the device is in the autoselect mode. The device

enters the CFI quer y mode, and the system can read

CFI data at the addresses given in Tables 10–13. The

system must write the reset command to return the

device to the autoselect mode.

For further infor mation, please refer to the CFI Specifi-

cation and CFI Pub licatio n 100, a vailab le via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD

representative f or copies of these documents.

Table 10. CFI Query Identification String

Addresses

(Word Mode) Addresses

(Byte Mode) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h Query Unique ASCII string “QRY”

13h

14h 26h

28h 0002h

0000h Primary OEM Command Set

15h

16h 2Ah

2Ch 0040h

0000h Address for Primary Extended Table

17h

18h 2Eh

30h 0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah 32h

34h 0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

Am29DL16xC 19

PRELIMINARY

Table 11. System Interface String

Table 12. Device Geometry Definition

Addresses

(Word Mode) Addresses

(Byte Mode) Data Description

1Bh 36h 0027h VCC Min. (write/erase )

D7–D4: volt, D3–D0: 100 millivolt

1Ch 38h 0036h VCC Max. (wr it e/eras e)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs

20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)

21h 42h 000Ah Typical timeout per individual block erase 2N ms

22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 46h 0005h Max. timeout for byte/word write 2N times typical

24h 48h 0000h Max. timeout for buffer write 2N times typical

25h 4Ah 0004h Max. timeout per individual block erase 2N times typical

26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

Addresses

(Word Mode) Addresses

(Byte Mode) Data Description

27h 4E h 0 01 5h Device Size = 2N byte

28h

29h 50h

52h 0002h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh 54h

56h 0000h

0000h Max. number of byte in multi-byte write = 2N

(00h = not supported)

2Ch 58h 0002h Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

001Eh

0000h

0001h

Erase Block Region 2 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Erase Block Region 3 Information

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

20 Am29DL16xC

PRELIMINARY

Table 13. Primary Vendo r-Specific Extended Query

Note:

The number of sectors in Bank 2 is device dependent.

Am29DL162 = 1Ch

Am29DL163 = 18h

Addresses

(Word Mode) Addresses

(Byte Mode) Data Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h Query-unique ASCII string “PRI”

43h 86h 0031h Major version number, ASCII

44h 88h 0031h Minor version number, ASCII

45h 8Ah 0000h Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Silicon Revision Number (Bits 7-2)

46h 8Ch 0002h Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 8Eh 0001h Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 90h 0001h Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 92h 0004h Sector Protect/Unprotect scheme

04 = 29LV800 mode

4Ah 94h 00XXh

(See Note) Simultaneous Operation

00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank)

4Bh 96h 0000h Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 98h 0000h Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 9Ch 0095h ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag

02h = Bottom Boot Device, 03h = Top Boot Device

Am29DL16xC 21
PRELIMINARY 
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the  command register initiates device
operations. Table 14 defines the valid register com-
mand sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data. 
All addresses are latched on the falling edge of WE#
or CE#, whiche ver happens lat er. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is autom atically set to reading array data
after device power-up. No c ommands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Er ase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any n on-erase-suspend ed sector wi thin the
same bank. After completing a prog r amming oper ation
in the Erase Suspend mode, the system may once
again read array data with the same exception. See
the Erase Suspend/Erase Resume Commands sec-
tion for more information.
The sys tem  
must
 issue the reset command to return a
bank to the  read  (or er ase-s uspend-read) mode  if  DQ5
goes high during an active program or erase opera-
tion, o r if the b ank is in th e autosele ct mode. See  the
next section, Reset Command, for mo re information.
See also  Requireme nts for R eading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table pro vides the read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command rese ts the banks to the
read o r erase-sus pend-read  mode. Addre ss bits are
don’t cares for this command.
The rese t com mand may be w ritten between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was wri ting to reading array data. On ce erasure
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programm ing begins. This resets the bank to
which the  system was w riting  to reading a rray data. If
the program command sequence is written to a bank
that is in the  Erase Suspend mode, wr iting the reset
command returns that bank to the erase-sus-
pend-read mode. Once progr amming begins, ho we ver,
the device ignores reset commands until the operation
is complete.
The reset comma nd may be wri tten between the s e-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return  to reading array data. If a
bank entered the autoselect mode while in the Erase
Suspend mode, wr iting the reset co mmand retur ns
that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
wr iting the re set comm and retur ns th e banks to  read-
ing array data (or erase-suspe nd-read mode  if that
bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer  and device c odes,
and determine whether or not a sector is protected.
Table 14 s hows the addres s and data  requiremen ts.
This method is an alternative to that shown in Table 7,
which is intended for PROM programmers and re-
quires VID on address pin A9. The autoselect
command sequence may be written to an address
within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively pro-
gra mming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by  a third
write cycle that contains the bank address and the au-
toselect command. The bank then enters the
autoselect mode. The system may read at any ad-
dress within the same bank any number of times
without initiating another autoselect command
sequence:
■A read cycle at address (BA)XX00h (where BA is
the bank address) returns the manufacturer code.
■A read cycle at address (BA)XX01h in word mode
(or (BA)XX02h in byte mode) returns the device
code. 
■A read cycle to an address containing a sector ad-
dress (SA) within the same bank, and the address
02h on A7–A0 in word mode (or the address  04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. (Refer to Ta-
bles 3–6 for valid sector addresses).
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the
bank was prev iously in Erase Suspend).

22 Am29DL16xC
PRELIMINARY 
Enter SecSi Sector/Exit SecSi Sector 
Command Sequence
The system can access the SecSi Sector region by is-
suing the three-cycle Enter SecSi Sector command
seq uence. The device con tinues to acc ess the SecS i
Sector region until the system issues the four-cycle
Exit SecSi Sector c ommand sequence.  The Exit SecSi
Sector com mand se quence retur ns th e device to  nor-
mal operation. Table 14 shows the address and data
requirements for both command sequences. See also
“SecSi (Secu red Silicon) Sector Flash Mem ory Re-
gion” for further information. Note that a hardware
reset (RESET#=VIL)  will reset the device to reading
array data.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up com-
mand. The progr am address  and data are written next,
which in turn initiate the Embedded Program algo-
rithm. The system is 
not
 required to provide fur ther
controls or timings. The device automatically provides
inter nally generated program pulses an d veri fies  the
programmed cell margin . Table 14 shows the  address
and data requirements for the byte program command
sequence.
When  the E mbedded  Program a lgor ithm is  comple te,
that ban k then return s to reading array data and a d-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to the Write Oper-
ation Status section for information on these status
bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note tha t a
hardware res et immediately ter minates the program
operation. The program command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set  DQ5 = 1, or caus e the DQ7 and
DQ6 status bits to indicate the operation was success-
ful. However, a  succeeding read will show that the
data is still “0.” Only erase operations can conv ert a “0”
to a “1.”
Unlock Bypass Command Sequen ce
The unlock bypass feature allows the system to pro-
gram bytes  or word s to a bank  fast er than u sing th e
standard  program com mand sequence. Th e unlock
bypass com mand sequ ence is ini tiated by first wr iting
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
That bank then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram comm and, A0h; the se cond cycle co ntains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 14 shows the req uire-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program a nd Unlock Bypass Reset comma nds
are valid. To exit th e unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the reading array data.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asser ts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC p in to accele rate the operati on. Note th at
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device dam-
age may  result.  In addit ion, t he WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may res ult.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 17 fo r timing diagrams.

Am29DL16xC 23

PRELIMINARY

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six b us cy cle oper ation. The chip er ase

command sequence is initiated by writing two unlock

cycles, followed by a set-up co mmand. Two additional

unlock write cycles ar e then followed by the c hip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not

require the system to

preprogram prior to erase. The Embedded Er ase algo-

rithm automatically preprogr ams a nd v e rifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to p rovide any co n-

trols or timings during these operations. Table 14

shows the address and data requirements for the chip

erase command sequence.

When the Embedded Erase algorithm is complete,

that bank returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6,

DQ2, or RY/BY#. Refer to the Write Operation Status

section f or information on these status bits.

Any commands written during the chip er ase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that

occurs, the chip erase command sequenc e should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations

tables in the AC Characteristics section for parame-

ters, and Figure 19 section for timing diagrams .

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then

f ollow ed by the address of the sector to be er ased, and

the sector erase command. Table 14 shows the ad-

dress and data requirements for the sector erase

command sequence.

The device does

not

require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire m emor y for

an all zero data patter n prior to electr ical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

ma y be done in any sequence , and the number of sec-

tors may be from one sector to a ll sectors. The time

between these additional cycles must be less than

50 µs, otherwise erasure may begin. Any sector erase

address and command following the exceeded

time-out may or may not be accepted. It is recom-

mended that processor interrupts be disabled during

this time to ensure all comm ands are accepted. Th e

interrupts can be re-enabled after the last Sector

Erase command is written. An y command other than

Sector Erase or Erase Suspend during the

time-out period resets that bank to reading array

data. The system must rewrite the command se-

quence and any additional addresses and commands.

The sy stem can mon itor DQ3 to dete rmine if the sec-

tor er ase ti mer has ti med out (See the s ection o n DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the

bank retur ns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

ter mine the status of the erase operatio n by reading

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21533C-8

Note: See Table 14 for program command sequence.

24 Am29DL16xC
PRELIMINARY 
DQ7, DQ6, DQ2, or R Y/BY# in the erasing bank. Ref er
to the Write Operation Status se ction for infor mation
on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the  erase operation. If
that occurs, the sector erase command sequence
shoul d be reinit iated once tha t bank h as retur ned to
reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations
tables in the AC Characteristics section for parame-
ters, and Figure 19 section for timing diagrams.
Erase Suspend/Erase Resume 
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase oper ation and then read
data from, or program data to, any sector not selected
f or er asure .  The bank address is  required when writing
this  command . This  comm and is valid  only dur ing th e
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur-
ing the chip erase  operation or Embedded  Program
algorithm. 
When the Erase Suspend  command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is writ-
ten during the sector erase time-out, the device
immedia tely terminates  the time-out period and sus -
pends the erase operation. 
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The sys-
tem can read data from  or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector i s actively eras ing or is erase-suspend ed.
Refer to the Wr ite Opera tion  Status section for infor-
mation on these status bits.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can deter mine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command s equence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume comman d. The bank
address of the erase-suspended bank is required
when  writi ng this c ommand. F ur ther w rites  of the R e-
sume c ommand  are ignored . Another E rase Suspen d
comman d can be written after the chip has  resumed
erasing. 
Figure 4. Erase Operation
START
Write Erase 
Command Sequence
(Notes 1, 2)
Data Poll to Erasing 
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded 
Erase
algorithm
in progress
21533C-9
Notes:
1. S ee Table 14 for erase command seq ue nce.
2. See the section on DQ3 for information on the sector 
erase timer.

Am29DL16xC 25
PRELIMINARY 
Table 14. Am29DL16xC Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = D ata read from locat ion RA d uring rea d oper at ion.
PA = Address of the memory location to be programmed. Addresses 
latch on the falling edge of the WE# or CE# pulse, whichever happens 
later.
PD = Data to be programmed at location PA. Data latches on the rising 
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or 
erased. Address bits A19–A12 uniquely select any sector.
BA = Address of the bank that is being s witched to autoselect mode, is 
in bypass mode, or is being erased.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in he x adecimal.
3. Except f or the read cycle and the fourth cycle of the autoselect 
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, 
except for RD and PD.
5. Unless otherwise noted, address bits A19–A11 are don’t cares.
6. No unlock or command cycles required when bank is reading 
array data.
7. The Reset command is required to return to reading array data 
(or to the erase-suspend-read mode if previously in Erase 
Suspend) when a bank is in the autoselect mode, or if DQ5 goes 
high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read 
cycle. The system must provide the bank address to obtain the 
manufacturer ID, device ID, or SecSi Sector factory protect 
information. Data bits DQ15–DQ8 are don’t care. See the 
Autose lect Command Sequence
 
section
 for more information.
9. The data is 80h for fac tory locked and 00h for not f actory locked.
10. The data is 00h for  an unprotected sector/sector bloc k and 01h for 
a protected sector/sector block. 
11. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to 
reading array data when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend mode. 
The Erase Suspend command is valid only during a sector erase 
operation, and requires the bank address.
14. The Erase Resume command is valid only during the Erase 
Suspend mode, and requires the bank address.
15. Command is valid when dev ice is ready to read array data or when 
device is in autoselect mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third  Fourth  Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufac turer ID Word 4555 AA 2AA 55 (BA)555 90 (BA)X00 01
Byte AAA 555 (BA)AAA
De vice ID  Word 4555 AA 2AA 55 (BA)555 90 (BA)X01 (see 
Table 7)
Byte AAA 555 (BA)AAA (BA)X02
SecSi Sector Factory 
Protect (Note 9) Word 4555 AA 2AA 55 (BA)555 90 (BA)X03 80/00
Byte AAA 555 (BA)AAA (BA)X06
Sector Protect Ver ify 
(Note 10) Word 4555 AA 2AA 55 (BA)555 90 (SA)X02 00/01
Byte AAA 555 (BA)AAA (SA)X04
Enter SecSi Sector Region Word 3555 AA 2AA 55 555 88
Byte AAA 555 AAA
Exit SecSi Sector Region Word 4555 AA 2AA 55 555 90 XXX 00
Byte AAA 555 AAA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2 BA 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 13) 1 BA B0
Erase Resume (Note 14) 1 BA 30
CFI Quer y (Note 15) Word 155 98
Byte AA

26 Am29DL16xC

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a program or erase operation: DQ2, DQ3, DQ5,

DQ6, and DQ7. Table 15 and the following subsec-

tions describe the f unction of t hese bits . DQ7 and DQ6

each offer a method for determining whether a pro-

gram or erase operation is complete or in progress.

The device also provides a har dware-based output

signal, RY/BY#, to determine whether an Embedde d

Program or Erase opera tion is in progress or has been

completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Program or Erase

algorithm is in progress or completed, or whether a

ban k is in Erase S usp end. Da ta# Polling is valid af ter

the rising edge of the final WE# pulse in the command

sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programm ing dur ing Erase Suspend. W hen the Em -

bedded Program algorithm is complete, the device

outputs the datum pro grammed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximatel y 1 µs, then that ba nk retur ns to reading

array data.

Dur ing th e Embe dded Erase algor ithm , Data# Polling

produc es a “0” on DQ 7. When the Embed ded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address w ithin any of the

secto rs selec ted for erasure to rea d valid status in for-

mation on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active f or appro ximately 100 µs, then the

bank returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the

system reads DQ7 at an address within a protected

sector, the status may not be valid.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. Tha t is, the device may chan ge from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid da ta. Even if the device has com -

pleted the program or erase operation and D Q7 has

valid data, the data outputs on DQ0–DQ6 m ay be stil l

invalid. Valid data on DQ0–DQ7 will appear on suc-

cessive read cycles.

Table 15 shows the outputs for Data# Po lling on DQ7.

Figure 5 shows the Data# Polling algor ithm. Figure 21

in the AC Characteristics section shows the Data#

Polling timing diagram.

Figure 5. Data# Polling Algorithm

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

21533C-10

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Am29DL16xC 27
PRELIMINARY 
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Em bedded Algorith m is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is  an open-drain output, sev-
eral RY/BY# pins can be tied together  in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is reading array data, the standby
mode, or one of the banks is in the erase-sus-
pend-read mode.
Table 15 shows the outputs f or RY/BY#. 
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has en tered th e Erase
Suspend mode.  Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cyc les to any address ca use
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After  an erase command sequence is written, if all
sectors s elected for erasing are pro tected, DQ6 tog-
gles for approximately 100 µs, then returns to readin g
arra y  data . If not  all selected secto rs are prot ected,  the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected. 
The syst em can use D Q6 and  DQ2 together  to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is ,  the Embedded Er as e alg orithm is in pr og ress),
DQ6 to ggles. When  the device enters  the Erase S us-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to deter mine which sectors are
erasing or erase-suspended. Alter natively, the system
can use DQ7 (see the subsection on DQ7: Data#
Polling).
If a program address falls within a protected sector,
DQ6 tog gles for approxima tely 1 µs after the program
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded  Pro-
gram algorithm is complete.
Table 15 shows the outputs  for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 22 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 23 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
 = Toggle? No
Program/Erase
Operation Not 
Complete, Write 
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
 = Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
21533C-11
Note: The system should recheck the toggle bit ev en if DQ5 
= “1” because the tog gle bit may stop toggling  as DQ5 
changes to “1.” See the subsections on DQ6 and DQ2 for 
more informat ion .
Figure 6. Toggle Bit Algorithm

28 Am29DL16xC
PRELIMINARY 
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is ,  the Embedded Er as e alg orithm is in pr og ress),
or whether that s ector is erase-s uspended. To ggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cy cles.) But DQ2 c annot distinguish
wheth er the sector i s actively erasing or i s erase-sus -
pended. D Q6, by comparis on, indicates whe ther the
device is actively erasing, or is in E rase Suspend, but
cannot d istingui sh which  sectors ar e select ed for era-
sure. Thus, both status bits are required for sector and
mode infor mation. Refer to Table 15 to compare out-
puts for DQ2 and DQ6. 
Figure 6 shows the toggle bit algorithm in flowchart
for m, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 2 2 shows the toggle bit timi ng diagram. Figure
23 shows the differences between  DQ2 and DQ6 in
graphical for m. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically,
the system  would note and  store the value of the tog-
gle bit after the first read. After the sec ond read, the
system would compare the new value of the toggle bit
with the first. If  the toggle bit is  not toggling,  the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
deter mines  that the toggle bit is  still toggling, the  sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then dete rmine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or er ase operatio n. If  it is still toggling, the  de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data. 
The remaining scenario is that the system initially de-
termines  that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it re-
turns to deter mine the status of the operation (top of
Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating
that the program or erase cycle was not  successfully
completed.
The de vi ce may output a “1” on DQ5 if the s yst em tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and  when the timing lim it
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must wr ite
the reset comm and to retur n to reading array data (or
to the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also  applies a fter each a dditional s ector erase  com-
mand. When the time-out period is complete, DQ3
switches from a “ 0” to a “1 .” If the time b etween addi-
tional sector er ase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (D ata# Po lling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence , an d then read DQ3.  If  DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will  accept a dditional  secto r erase co mmands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ 3 is high  on the second s tatus check, the
last command might not have been accepted.
Table 15 shows the status of DQ3 relative to the other
status bits.

Am29DL16xC 29

PRELIMINARY

Table 15. W rite Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must alwa ys provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

Status DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embe dd ed Pro gram Algorithm DQ7# Toggle 0 N/A No tog gle 0

Embedd ed Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspen d

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

30 Am29DL16xC

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V SS to –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V CC +0.5 V.

See Figure 7. During voltage transitions, input or I/O pins

may overshoot to VCC +2.0 V for periods up to 20 ns. See

Figure 8.

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V SS to

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC input voltage on pin A9 is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

3. No more tha n one outpu t may be shor ted to ground at a

time. Duration of the sh or t circuit shou ld not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stres s rating only; functional op eration of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C

Industrial (I) De vices

Ambient Temperature (TA). . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA). . . . . . . . .–55°C to +125°C

VCC Supply Voltages

VCC for standard v oltage range. . . . . . . 2.7 V to 3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

Figure 7. Maximum Negative

Overshoot Waveform Figure 8. Maximum Posi tive

Overshoot Waveform

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

21533C-12

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

21533C-13

Am29DL16xC 31
PRELIMINARY 
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specificat ions ar e test ed wit h VCC = VCCmax.
3. ICC activ e while Embedded Erase or Embedded Program is in progress .
4. Au tomatic sl eep mode enab les  the lo w po wer mode  when addresses  remain st abl e f or tACC + 30 ns. Typical sleep mode current is 
200 nA.
5. Not 100% tested.
Parameter 
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Lea ka ge Cur ren t VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Notes 1, 2)
CE# = VIL, OE# = VIH, 
Byte Mode 5 MHz 10 16 
mA
1 MHz 2 4
CE# = VIL, OE# = VIH, 
Word Mode 5 MHz 10 16 
1 MHz 2 4
ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL 15 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; 
VIL = VSS ± 0.3 V 0.2 5 µA
ICC6 VCC Active Read-While-Program 
Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA
Word 21 45
ICC7 VCC Active Read-While-Erase 
Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA
Word 21 45
ICC8
VCC Active 
Program-While-Erase-Suspended 
Current (Notes 2, 5) CE# = VIL, OE# = VIH 17 35 mA
IACC ACC Accelerated Program Current,
Word or Byte CE# = VIL, OE# = VIH ACC pin 5 10 mA
VCC pin 15 30 m A
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VHH
Voltage for WP#/ACC Sector 
Protect/Unprotect and Program 
Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V
VID V oltage for Autoselect and T emporary 
Sector Unp rot ect VCC = 3.0 V ± 10% 8.5 12.5 V
VOL Output Low Volta ge IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

32 Am29DL16xC

PRELIMINARY

DC CHARACTERISTICS

Zero-Power Flash

Note: Addresses are switching at 1 MHz

21533C-14

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

00 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

12345

Frequency in MHz

Supply Current in mA

Note: T = 25

21533C-15

Figure 10. Typical ICC1 vs. Frequency

2.7 V

3.6 V

Am29DL16xC 33

PRELIMINARY

TEST CONDITIONS

Table 16. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Test

Note: Diodes are IN3064 or equivalent

21533C-16

Figure 11. Test Setup

Test Condition 70, 80 90, 120 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap acit anc e) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput

21533C-17

Figure 12. Input W aveforms and Measurement Levels

34 Am29DL16xC

PRELIMINARY

AC CHARACTERISTICS

Read-Only Operations

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 16 for test speci ficat ions .

Parameter

Description Test Setup

Speed Options

JEDEC Std 70 80 90 120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 70 80 90 120 ns

tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 70 80 90 120 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 80 90 120 ns

tGLQV tOE Output Enable to Output Delay Max 30 30 40 50 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 25 30 30 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 25 30 30 ns

tAXQX tOH Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First Min 0 ns

tOEH Output Enable Hold

Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tOH

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tRH

tOE

tRH

0 V

RY/BY#

RESET#

tDF

21533C-18

Figure 13. Read Operation Timings

Am29DL16xC 35

PRELIMINARY

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Descri ptio n All Speed Optio ns UnitJEDEC St d

tReady RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

tReady RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH Reset High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

21533C-19

Figure 14. Reset Timings

36 Am29DL16xC

PRELIMINARY

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter Speed Options

JEDEC Std Description 70 80 90 120 Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 25 30 30 ns

tFHQV BYTE# Switching High to Output Active Min 70 80 90 120 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Outpu t

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

21533C-20

Figure 15. BYTE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

21533C-21

Figure 16. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

Am29DL16xC 37

PRELIMINARY

AC CHARACTERISTICS

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Spe ed Op tion s

JEDEC Std Description 70 80 90 120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 120 ns

tAVWL tAS Address Setup Time Min 0 ns

tASO Address Setup Time to OE# low during toggle bit

polling Min15151515ns

tWLAX tAH Address Hold Time Min 45 45 45 50 ns

tAHT Address Hold Time From CE# or OE# high

during toggle bit polling Min 0 ns

tDVWH tDS Data Setup Time Min 35 35 45 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOEPH Output Enable High during toggle bit polling Min 20 20 20 20 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 30 30 35 50 ns

tWHDL tWPH Write Pulse Width High Min 30 30 30 30 ns

tSR/W Latency Between Read and Write Operations Min 0 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs

Word Typ 11

tWHWH1 tWHWH1 Accelerated Programming Operation,

Word or Byte (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Write Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

38 Am29DL16xC

PRELIMINARY

AC CHARACTERISTICS

Figure 18. Accelerated Program Timing Diagram

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tGHWL

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

otes:

. PA = program address, PD = program data, DOUT is the true data at the program address.

. Illustration shows device in word mode.

21533C-22

Figure 17. Program Operation Timing s

WP#/ACC tVHH

VHH

VIL or VIH VIL or VIH

tVHH

Am29DL16xC 39

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Er ase), VA = Valid Address for reading s tatus data (see “Write Operation Status”).

. These wa vef orms are f o r the wor d mode .

21533C-23

Figure 19. Chip/Sector Erase Operation Timings

40 Am29DL16xC

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

Data

Valid

In Valid

Valid PA Valid RA

WPH

Valid

Out

ACC

OEH

GHWL

Valid

CE# Controlled Write CyclesWE# Controlled Write Cycle

Valid PA Valid PA

CPH

Read Cycle

SR/W

21533C-24

Figure 20. Back-to-back Read/Write Cycle Timings

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21533C-25

Figure 21. Data# Polling Timings (During Embedded Algorithms)

Am29DL16xC 41

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

tOEH

tDH

tAHT

tASO

tOEPH

tOE

Valid Data

(first read) (second read) (stops toggling)

tCEPH

tAHT

tAS

DQ6/DQ2 Valid Data

Valid

Status Valid

Status

RY/BY#

Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

21533C-26

Figure 22. Toggle Bit Timings (During Embedded Algorithms)

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

21533C-27

Figure 23. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Pro gra m

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

42 Am29DL16xC

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector/Sector Block Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tVHH VHH Rise and Fall Time (See Note) Min 250 ns

tRSP RESET# Setup Time for Temporary

Sector/Sector Block Unprotect Min 4 µs

tRRB RESET# Hold Time from RY/BY# High for

Temporary Sector/Sector Block Unprotect Min 4 µs

RESET#

tVIDR

VID

VSS, VIL,

or VIH

VID

VSS, VIL,

or VIH

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

tRRB

21533C-28

Figure 24. Temporary Sector/Sector Block Unprotect Timing Diagram

Am29DL16xC 43

PRELIMINARY

AC CHARACTERISTICS

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector/Sector Block Protect or Unprotect Verify

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

21533C-29

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram

44 Am29DL16xC

PRELIMINARY

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std Description 70 80 90 120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 120 ns

tAVWL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 45 45 50 ns

tDVEH tDS Data Setup Time Min 35 35 45 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 30 30 45 50 ns

tEHEL tCPH CE# Pulse Width High Min 30 30 30 30 ns

tWHWH1 tWHWH1 Programming Operation

(Note 2) Byte Typ 9 µs

Word Typ 11

tWHWH1 tWHWH1 Accelerated Programmin g Ope ration ,

Word or Byte (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

Am29DL16xC 45

PRELIMINARY

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = prog r am addr ess , SA = sect or addr ess , PD = prog r am d ata.

3. DQ7# is the complement of the data written to the device. DOUT i s the data written to t he device .

4. Waveforms are for the word mode.

21533C-30

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

46 Am29DL16xC

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case co nditi ons of 90

C, VCC = 2.7 V, 1,000,000 c ycles .

3. The typical chi p prog r ammi ng time is c onsider ably less t han the maxim um chi p prog r amming time list ed, si nce most b yt es

progra m faster tha n the max im um prog r am t imes l isted.

4. In the pre-pro gr ammi ng step of t he Embedded Er as e algorithm, all b yt es are prog r ammed to 00h before erasure.

5. System-lev el o verhead is the t ime r equired to ex ecute the t wo- or four-bus-cycle s equence for the prog r am c ommand. See Tab le

14 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s ec Ex clud es 00h programm ing

prior to erasure (Note 4)

Chip Erase Time 27 sec

Byte Program Time 9 300 µs

Excludes system level

overhead (Note 5)

Word Program Time 11 360 µs

Accelerat ed Byt e/Word Program Time 7 210 µs

Chip Program Time

(Note 3) Byte Mode 18 5 4 sec

Word Mode 12 36

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(includi ng A9, OE#, and RESE T#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Ret ent ion Tim e 150°C 10 Years

125°C 20 Years

Am29DL16xC 47

PRELIMINARY

PH YS ICAL DIMENSIONS

SSO056—56-Pin Shrink Small Outline Package (SSOP) (measured in millimeters)

SEE DETAIL "G"

SEE DETAIL "B"

0.20 M C

ASS

0.20 M CASS

0.10

56 29

128

Index Area

13.10

13.50 15.70

16.30

16-038-SSO56-2_AB

ES107

9.15.98 lv

23.40

24.00

SEATING PLANE

0.80 BSC

0.25

0.45 0.45

0.65

1.15

1.35

2.00

MAX

GAUGE PLANE

SEATING PLANE

DETAIL "G"

0.60

1.00

0.09 Min

0°

8°

A0.25

0.40 BSC

Even Lead Sides

X = D or F

DETAIL "B"

With Lead Finish

0.10

0.21 0.10

0.18

0.30

0.40

0.25

0.45

Base Metal SECTION A-A

48 Am29DL16xC

PRELIMINARY

PH YS ICAL DIMENSIONS

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm (measured in millimeters)

.25

.10

ZAB

0.20 (4X)

0.25

0.35

0.84

0.94

0.20

0.30

1.00

1.20

0.10 Z

0.25 Z

8.00 BSC

9.00 BSC

5.60 BSC

16-038-FBA-2_AA

ET153

11.6.98 lv

0.80

BSC

4.00 BSC

PIN 1 ID

0.40

BSC.

0.40 BSC.

Am29DL16xC 49

PRELIMINARY

PH YS ICAL DIMENSIONS

TS 048—48-Pin Standard TSOP (measured in millimeters)

18.30

18.50

19.80

20.20

11.90

12.10

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48-2

TS 048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

50 Am29DL16xC

PRELIMINARY

REVISION SUMMARY

Revision B (October 1998)

Global

Deleted the 90R and 120R speed options. Expanded

the full voltage range to 2.7–3.6 V.

Distinctive Characteristics

Added 125°C to 20-year data retention bullet.

Connection Diag rams

Changed the FBGA diagram from bottom view to top view.

Ordering Information

Changed the FBGA ordering nomenclature to “YC.”

The package designation is now FBC048. Revert ed to

WC in Revision C.

DC Characteristics

Changed maximum ILI current to ±3.0 µA.

Physi cal Dimensions

Updated the FBGA drawing, table, and notes. The

package designation is now FBC048. Deleted 40-pin

TSOP drawing.

Revision B+1

Comm and Defin itions table

Added the term “sector block ” to the notes

where appropriate.

DC Characteristics

Changed maximum ILI current to ±1.0 µA.

AC Characteristics

Temporar y Sector Unprotect:

Moved the accelerate d

program timing diagram to follow the program opera-

tions timings. Added the term “sector block” where

appropriate elsewhere on the page.

Revision C (January 1998)

Global

Changed data sheet tit le.

Product Selector Guide

Replaced “Full Voltage Range: VCC = 2.7–3.6 V” with

“Standard Voltage Range: VCC = 2.7–3.3 V.” Each par t

number now has a separat e set of speed opt ions.

Ordering Information

Added 70, 90R, and 120R speed options to the valid

combination table. Rever ted FBGA designator back to

WC.

Secured Silicon (SecSi) Sector Flash Memory

Region

Factory Locked: SecSi Sector Programmed and Pro-

tected at the Factory:

Corrected the address range of

the ESN and distinguished between word and byte

modes.

Operating Ranges

VCC Supply Voltages:

Replaced singl e voltage range

with voltage ranges for standard and regulated

devices.

Revision C+1 (March 19, 1999)

SecSi (Secured Silicon) Sector Flash Memory

Region

Customer Lockable subsection: In the bullets, text

shoul d refer to “Enter Sec Si Sector Regio n comman d

sequence.”

Revision C+2 (June 14, 1999)

Changed data sheet status to Preliminary.

Revision C+3 (August 9, 1999)

Global

Added Am29DL164 specification s to the document.

Ordering Informati on

Added the 70R speed option for the DL163, deleted

the SSOP for the DL162.

Test Specifications table

The 90 ns speed option is tested at 100 pF loading.

Revision C+4 (August 23, 1999)

Ordering Informati on

Tem perature Range:

Added “C = Commercial (0°C to

+70°C)”.

Operating Ranges

Added commercial device.

Revision C+5 (October 18, 1999)

Device Bus Operations

Autoselect M ode:

Added Am29DL164 device IDs to

the Autoselect Codes table.

Am29DL16xC 51

PRELIMINARY

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.