M66291GP - Renesas Electronics

To our custo mers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corpor ation took over all the business of both

companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid

Renesas Electronics document. W e appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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M66291GP/HP

ASSP (USB2.0 Device Controller)

Rev1.01 2004.11.01 page 1 of 122

REJ03F0125-0101Z

Rev1.01

2004.11.01

Overview

The M66291 is a general purpose USB (Universal Serial Bus) device controller compliant with the USB

Specification Revision 2.0 and supports full speed transfer. The USB transceiver circuit is included, and the M66291

meets all transfer types which are defined in the USB specification. The M66291 has FIFO of 3 Kbytes for data

transfer and can set 7 endpoints (maximum). Each endpoint can be set programmable of its transfer condition, so can

correspond to each device class transfer system of USB.

1.1 Features

z USB Specification Revision 2.0 compliant

z Supports Full Speed (12 Mbps) transfer

z Built-in USB transceiver circuit

z Built-in oscillation buffer (Supports 6M/12M/24 MHz of oscillator) and PLL at 48 MHz

z Supports Vbus direct connection (5 V withstand voltage input), D+ pin pullup output

z Supports all transfer type which is defined in the USB specification.(Control transfer / Bulk transfer / Interrupt

transfer / Isochronous transfer)

z Low power consumption operation (Average 15 mA at operation)

z Robust against signal distortion on USB transfer line due to SIE/DPLL(Digital Phase Lock Loop) of the original

design

z Easy making enumeration program and timing design because hardware manages the device state / control

transfer state (transition timing)

z Reduction of CPU load due to continuous transmit/receive mode (the mode for buffering several transaction data

into FIFO) This enables high performance and throughput improvement.

z Up to 7 endpoints (EP0 to EP6) selectable

z Data transfer condition selectable for each endpoint (EP1 to EP6)

Compatible to various applications (device class)

• Data transfer type (Bulk transfer / Isochronous transfer / Interrupt transfer)

• Transfer direction (IN, OUT)

• Packet size

z Built-in FIFO buffer (3 Kbytes) for endpoints

z Buffering conditions of FIFO memory settable per endpoint (EP1 to EP6)

• FIFO buffer size (up to 1Kbyte)

• Presence/Absence of double buffer configuration (setting of buffer size x 2)

z Four pieces of configurable FIFO ports

• Endpoint number allocation

• Access method switching (CPU, DMAC)

• Bit width (8-bit / 16-bit)

• Endian switching

z ”Interrupt queuing function” that eliminates the need of complicated factor analysis

z Connectable to various CPU/DMAC

• Bus width(8-bit / 16-bit)

• Interface voltage(2.7V to 5.5V)

• Interrupt signal and DMA control signal polarities settable

• Supports multi-word DMA (burst)

z FIFO access cycle of maximum 24 Mbytes/sec

Applications

Support all PC peripheral built-in USB

M66291GP/HP

Rev1.01 2004.11.01 page 2 of 122

Figure 1.1-1 M66291GP Pin Configuration

Core Power Supply

USB DATA(-)

USB DATA(+)

Vbus INPUT

TrON OUTPUT

TEST INPUT

DMA ACKNOW LEDG E 1

DM A REQ UEST 1

TC INPUT

INTERRUPT 1/ SOF OUTPUT

I/O POWER SUPPLY

GND

IOVcc

D11/P3

D10/P2

D9/P1

D8/P0

D12/P4

D13/P5

D14/P6

D15/A0

HWR/BYTE

INT0

LWR

RST

Dreq0

Dack0

HIGH-WRI TE ST ROBE/ BUS WI DTH SELECT

I N TERRUPT 0

READ ST RO BE

LOW-WR IT E ST R O BE

CHIP SE L E CT

RESET

DM A R EQU EST 0

DMA ACKN OWLEDG E 0

DATA

BUS

DATA BUS

I/O POWER

SUPPLY

CoreVcc

GND

Xin

Xout

DATA BU S

CO RE PO WER SUPPLY

O SCILL ATIO N IN PU T

OSCI LLATI ON OU TPUT

ADDRESS BU S

CoreVcc

GND

D-

D+

Vbus

TrON

TEST

Dack1

Dreq1

TC1

INT1/SOF

IOVcc

M66291GP

PIN CONFIGURATION

(TOP VIEW)

Outline

M6 6291G P: 48 P6Q -

A(LQFP)

M66291GP/HP

Rev1.01 2004.11.01 page 3 of 122

GND

IOVcc

D11/P3

D10/P2

D9/P1

D8/P0

D12/P4

D13/P5

D14/P6

D15/A0

HWR/BYTE

INT0

LWR

RST

Dreq0

Dack0

CoreVcc

GND

Xin

Xout

CoreVcc

GND

D-

D+

Vbus

TrON

TEST

Dack1

Dreq1

TC1

INT1/SOF

IOVcc

M66291HP

PIN CONFIGURATION

(TOP VIEW)

Outline

M66291HP:52PJV(VQFN)

13 27

Figure1.1-2 M66291HP Pin Configuration

M66291GP/HP

Rev1.01 2004.11.01 page 4 of 122

1.2 Block Diagram

The M66291 contains an USB-IP block, an I/O block, a bus interface unit (BIU), and a FIFO memory.

Figure 1.2 M66291 Block Diagram

USB-IPI/O Block Bus

Interface

Unit

(BIU)

Endpoint

Controller

FIFO Mem ory Controller

Vbus

Input Circuit

D+ Pin Pullup

Circuit

USB

Transceiver Serial Interface

Engine

(SIE)

(Oscillator)•Xin

•Xout

Bus In terface Pin s

•A1-6

•D0-7

•D8-15

•CS

•RD

•LWR

•HWR

Interrupt Pins

•INT0

•INT1/SOF

DMA Control Pin s

•Dreq0

•Dack0

•Dreq1

•Dack1

•TC1

Reset Pins

•RST

Test Pins

•TEST

Oscillation

Buffer

/48MHzPLL

FIFO Mem ory

CPU Inter f ac e Register

Transfer

Controller

(USB Power Supply)

•Vbus

(Pullup Resistance)

•TrON

(USB Data)

•D+

•D-

Interrupt Controller

M66291GP/HP

Rev1.01 2004.11.01 page 5 of 122

1.2.1 USB-IP

The USB-IP block contains a serial interface engine, a transfer controller, an endpoint controller, a FIFO

memory controller, an interrupt controller, and a CPU interface register.

(1) Serial Interface Engine (SIE)

The serial interface engine (SIE) executes low-order protocols processing of USB as follows:

•Extracts receive data/clock and generates transmit clock

•Serial - parallel conversion of transmit/receive data

•NRZI (Non Return Zero Invert) encoding and decoding

•Bit stuffing and destuffing

•SYNC (Synchronization pattern) and EOP (End Of Packet) detection

•USB address and endpoint detection

•CRC (Cyclic Redundancy Check) generation and checking

(2) T ransfer Controller

The transfer controller executes device state transition control and control transfer sequence control.

(3) Endpoint Controller

The endpoint controller executes status control per endpoint.

(4) FIFO Memory Controller

The FIFO memory controller controls the write/read of the transmit/receive data at SIE (USB bus) side and

internal bus (CPU bus) side under state control by the endpoint controller.

(5) Interrupt Controller

The interrupt controller outputs the status signals outputted by transfer controller and endpoint controller to

INT0, INT1/SOF interrupt pins according to the CPU interface register setting.

(6) CPU Interface Register

The CPU interface register block is composed of the registers for mode setting, command setting and status

reading.

1.2.2 Bus Interface Unit (BIU)

The bus interface unit (BIU) is a circuit to conform USB-IP to LSI external bus.

1.2.3 FIFO Memory

The FIFO memory is a FIFO for endpoint transmit/receive. It is possible to set 6 endpoints EP1 to EP6 in

addition to EP0, the endpoint for control transfer.

1.2.4 I/O Block

The I/O block is composed of USB transceiver, oscillation buffer, 48 MHz PLL, Vbus input circuit and D+ pin

pullup control circuit.

M66291GP/HP

Rev1.01 2004.11.01 page 6 of 122

(1) USB Transceiver

The USB transceiver, conforming to the USB Specification Revision 2.0, is composed of a pair of 2 pieces of

drivers D+/D- complying with full speed transfer mode, a pair of 2 pieces of single end receivers and a

differential input receiver. A serial resistance for impedance matching is needed external to the chip.

(2) Oscillation Buffer, 48 MHz PLL

The 48 MHz clock with accuracy ± 0.25% is needed at the USB-IP block. The M66291 has a built-in oscillation

buffer and a 48 MHz PLL. The PLL is capable of setting the multiplication number depending on the program

and can therefore be connected with an external oscillation of 6, 12 or 24 MHz. Further, it can also be operated

by the external 48 MHz clock without using the PLL function.

(3) Vbus Input Circuit, D+ Pin Pullup Control Circ uit

The M66291 is capable of learning the connection status with host/hub by means of Vbus pin, and can inform

the state of preparation at device side to host/hub by turning on/off the 1.5 KΩ D+ pin pullup.

The Vbus input buffer which is 5 V tolerant can be directly connected to the Vbus pin on the USB bus.

The current from TrON pin is supplied by Vbus input. Since the D+/D- pins of USB bus are operated at 0 V to

3.3 V, the TrON pin reduces the voltage to 3.3 V before output.

Since the USB is constantly pulled down by 15 KΩ at host/hub side when connected electrically, a current of 0.2

mA continuously flows into the D+ pin through the pullup resistance.

M66291GP/HP

Rev1.01 2004.11.01 page 7 of 122

1.3 Pin Functions

Item Pin name Input/

Output

Function Pin

Count

D7~D0 Input/

Output

Data Bus

This is a data bus to access the register from the system bus.

D14/P6~

D8/P0

Input/

Output

Data Bus / Port Signal

P6 to P0 are used as port signals when selected to 8-bit bus interface.

D14 to D8 are used as data signals when selected to 16-bit bus interface.

D15/A0 Input/

Output

D15 Signal / A0 Signal

A0 (LSB) is used as an address signal when selected to 8-bit bus interface.

D15 (MSB) is used as an data signal when selected to 16-bit bus interface.

A6~A1 Input Address Bus

This is an address bus to access the register from the system bus.

*CS Input Chip Select

"L" level enables communicatio n with the M66291.

*LWR Input Low-write Strobe

The lower data (D7 to D0) is written to the register at “L” level.

*HWR/*BYTE Input High-write Strobe / Bus Width Select

With the reset signal set to “H” level, the 8-bit bus interface is selected if this

pin is at “L” level. Further, if this pin is at “H” level, the 16-bit bus interface is

selected. When the 16-bit bus interface is selected, the upp er data (D15 to

D8) is written to the register at “L” level.

Fix to “L” level when set to 8-bit bus interface.

Bus

interface

*RD Input Read Strobe

Data are read from registers at "L" level

*INT0

(Note 1)

Output Interrupt 0

Interrupts are requested to the system at "L" level.

1Interrupt

interface

*INT1/*SOF

(Note 1)

Output Interrupt 1 / SOF Output

This pin is used as an interrupt 1 or as a SOF output pin to transmit USB SOF

signal according to register setting.

DMA

interface

*Dreq0

(Note 1)

Output DMA Request 0

This pin is used to request DMA tran sfer to endpoint FIFO fo r DMA channel 0 .

*Dack0

(Note 1)

Input DMA Ac k n o wl e d g e 0

This pin enables access of FIF O b y DMA transfer for DMA channel 0.

*Dreq1

(Note 1)

Output DMA Request 1

This pin is used to request DMA tran sfer to endpoint FIFO fo r DMA channel 1 .

M66291GP/HP

Rev1.01 2004.11.01 page 8 of 122

Item Pin Name Input/

Output

Function Pin

Count

*Dack1

(Note1)

Input DMA Ac k n o wl e d g e 1

This pin enables access of FIF O b y DMA transfer for DMA channel 1.

1DMA

interface

*TC1 Input Terminal Count 1

This pin indicates the final transfer c ycle at “L” lev el for DMA cha nnel 1.

This is valid only in write cycle. Set to “H” level when not used.

D+ Input/

Output

USB Data (+)

D+ of USB. Connect an external resistance in series.

D- Input/

Output

USB Data (-)

D- of USB. Connect an external resistance in series.

Vbus Input Vbus Input (with built-in pulldown resistance)

Connect to the Vbus of USB bus or to the 5V power supply.

Connection or shutdown of the Vbus can be detected.

USB

interface

TrON Output TrON Output

This pin is connected to the D+ pullup resistance of 1.5 KΩ.

This pin is used to control ON/OFF of the pullup resistance.

*RST Input Reset

This pin is used to initialize the val ues of the internal register or th e counter at

"L" level.

Xin Input Oscillator

Input

Xout Output Oscillator

Output

These pins are used to inp ut/output the signals of internal clock

oscillation circuits. Connect a crystal unit bet ween Xin and Xout

pins.

If an external clock signal is used, connect it to the Xin pin and

leave the Xout pin open.

TEST Input TEST Input (with built-in pulldown resistance)

This pin is input for the test. Set to "L" level or keep open.

CoreVcc

(Note 2)

⎯Core Power Supply

These pins are used as the power source for internal logic, FIFO memory, PLL

circuit, USB transceiver and oscillation buffer.

IOVcc

(Note 3)

⎯I/O Power Supply 2

Others

GND ⎯Ground 3

A pin preceded by an asterisk "*" is an active low pin.

(Example: *CS pin is an active low, CS)

Note 1: The polarities of *Dreq, *Dack, *INT, and *SOF pins can be changed by the internal registers.

Note 2: The Xin, Xout, Vbus, D+ and D- pins are all driven by CoreVcc.

Note 3: The pins for bus interface, interrupt, DMA control, reset and test are all driven by IOVcc. See Figure 1.2.

M66291GP/HP

Rev1.01 2004.11.01 page 9 of 122

Registers

How to Read Register Tables

cBit Numbers : Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the

registers located at odd addresses are b 15-b8, and those at even addresses are b7-b0.

dState of Register at Reset :

Represents the initial state of each register immediately after reset with hexadecimal numbers.

The "H/W reset" is the reset by an external reset signal; the "S/W reset" is the reset by the

USBE bit of the USB Operation Enable Register.

eAt Read: {... Read enabled

? ... Read disabled (Read value invalid)

0 ... Read always as 0

1 ... Read always as 1

fAt Write: { ... Write enabled

∆... Write enable conditionally (includes some conditions at write)

— ... Write disabled (Don’t care “0” and “1” at write)

X ··· Write disabled

Not implemented in the shaded portion.

b151413121110987654321b0

Abit Bbit Cbit

d H/W reset 0000

S/W reset 0000

USB bus reset 0000

b Bit name Function R W

15 Reserved. 0 -

14 A bit

(------------------------)

0: ------------------------

1: ------------------------ 00

13 B bit

(------------------------)

0: ------------------------

1: ------------------------ 00

12 C bit

(------------------------)

0: ------------------------

1: ------------------------ 00

M66291GP/HP

Rev1.01 2004.11.01 page 10 of 122

The M66291 register mapping is shown in Figure 2.1 and Figure 2.2, and each register is described below.

Address +1 address +0 address Reset state

b15 b8 b7 b0 H/W S/W USB bus

H’00 USB Operation Enable R egister H'0000 - -

H’02 Remote Wakeup Register H'0000 H'000 0 -

H’04 Sequence Bit Clear Register H'0000 H'000 0 -

H’06 (Reserved)

H’08 USB_Address Register H'0000 H'000 0 H'0000

H’0A Isochronous Status Register H'0000 H'0000 -

H’0C SOF Control Register H'0000 H'0000 -

H’0E Polarity Set Register H'0000 H'0000 -

H’10 Interrupt Enable Register 0 H'0000 H'0000 -

H’12 Interrupt Enable Register 1 H'0000 H'0000 -

H’14 Interrupt Enable Register 2 H'0000 H'0000 -

H’16 Interrupt Enable Register 3 H'0000 H'0000 -

H’18 Interrupt Status Register 0 H'0000 H'0000 Note

H’1A Interrupt Status Register 1 H'0000 H'0000 -

H’1C Interrupt Status Register 2 H'0000 H'0000 -

H’1E Interrupt Status Register 3 H'0000 H'0000 -

H’20 Requ est Register H'0000 H'000 0 -

H’22 Value Register H'0000 H'0000 -

H’24 Index Register H'0000 H'0000 -

H’26 Length Register H'0000 H'0000 -

H’28 Control Transfer Control Register H'0000 - -

H’2A EP0 Packet Size Register H'0008 - -

H’2C Automatic Response Control Register H'0000 - -

H’2E (Reserved)

H’30 EP0_FIFO Select Register H'0000 - -

H’32 EP0_FIFO Control Register H'0800 - -

H’34 EP0_FIFO Data Register ???? - -

H’36 EP0_FIFO Continuous Transmit Data Length Register H'0000 - -

Note : Refer to each register described below.

Figure 2.1 Register Mapping (1)

M66291GP/HP

Rev1.01 2004.11.01 page 11 of 122

Address +1 address +0 address Reset state

b15 b8 b7 b0 H/W S/W USB bus

H’38 (Reserved)

H’3A (Reserved)

H’3C (Reserved)

H’3E (Reserved)

H’40 CPU_FIFO Select Register H'0000 - -

H’42 CPU_FIFO Control Register H'0800 - -

H’44 CPU_FIFO Data Register ???? - -

H’46 SIE_FIFO Status Register H'0000 - -

H’48 D0_FIFO Select Register H'0000 - -

H’4A D0_FIFO Control Register H' 0800 - -

H’4C D0_FIFO Data Register ???? - -

H’4E DMA0_Transaction Count Register H'0000 - -

H’50 D1_FIFO Select Register H'0000 - -

H’52 D1_FIFO Control Register H'0800 - -

H’54 D1_FIFO Data Register ???? - -

H’56 DMA1_Transaction Count Register H'0000 - -

H’58 FIFO Status Register H'0000 H'0000 -

H’5A Port Control Register H'0000 - -

H’5C Port Data Register H'0000 - -

H’5E Drive Current Adjust Register H'0000 - -

H’60 EP1 Configuration Register 0 H'0000 - -

H’62 EP1 Configuration Register 1 H'0040 - -

H’64 EP2 Configuration Register 0 H'0000 - -

H’66 EP2 Configuration Register 1 H'0040 - -

H’68 EP3 Configuration Register 0 H'0000 - -

H’6A EP3 Configuration Register 1 H'0040 - -

H’6C EP4 Configuration Register 0 H'0000 - -

H’6E EP4 Configuration Register 1 H'0040 - -

H’70 EP5 Configuration Register 0 H'0000 - -

H’72 EP5 Configuration Register 1 H'0040 - -

H’74 EP6 Configuration Register 0 H'0000 - -

H’76 EP6 Configuration Register 1 H'0040 - -

Figure 2.2 Register Mapping (2)

M66291GP/HP

Rev1.01 2004.11.01 page 12 of 122

2.1 USB Operation Enable Register

Q USB Operation Enable Register (USB_ENAB LE) <Address : H’00>

b151413121110987654321b0

XCKE PLLC Xtal SCKE USBPC Tr_on USBE

0000000000000000

----------------

b Bit name Function R W

15 XCKE

Oscillation Buffer Enable 0 : Disable oscillation buffer (Disable clock supply to inside

PLL)

1 : Enable oscillation buffer (Enable clock supply to inside

PLL)

{{

14 PLLC

PLL Operation Enable 0 : Disable PLL (PLL through)

1 : Enable PLL

{{

13~12 Xtal

Clock Select 00 : External clock frequency : 48 MHz (PLL through)

10 : External clock frequency : 24 MHz

01 : External clock frequency : 12 MHz

11 : External clock frequency : 6 MHz

{{

11 SCKE

Internal Clock Enable 0 : Disable Internal clock

1 : Enable Internal clock

{{

10 USBPC

USB Transceiver Power Control 0 : Disable USB transceiver

1 : Enable USB transceiver

{{

9~8 Tr_on

Tr_on Output Control 00 : TrON output ="Hi-Z" (SIE operate stop)

01 : TrON output ="L"

10 : Reserved

11 : TrON output ="H"

{{

7~1 Reserved. Set it to “0”. 00

0 USBE

USB Module Operation Enable 0 : S/W reset state

1 : S/W reset state release

{{

(1) XCKE (Oscillation Buffer Enable) Bit (b15)

This bit sets enable/disable of the oscillation buffer.

The output clock from the oscillation buffer is supplied to the PLL.

Refer to Figure 2.3.

(2) PLLC (PLL Operation Enable) Bit (b14)

This bit sets enable/disable of PLL.

When this bit is set to “1”, the external clock into the PLL is multiplied according to the value set in the Xtal

bits before being output to the core block. Set the XCKE bit to “1” and wait until the oscillation circuit starts

and becomes stable before setting this bit to “1”.

When this bit is set to “0”, PLL stops operation and the external clock into the PLL is output to the core block

without being multiplied. Hence, be sure to supply the 48 MHz clock to the oscillation buffer when setting this

bit to “0”.

Refer to Figure 2.3.

M66291GP/HP

Rev1.01 2004.11.01 page 13 of 122

(3) Xtal (Clock Select) Bits (b13~b12)

These bits set the multiplication factor of the external clock into PLL.

Since it is necessary to supply 48 MHz to the core block, the setting values of these bits are determined by the

clock frequency to be input into the PLL.

Refer to Figure 2.3.

(4) SCKE (Internal Clock Enable) Bit (b11)

This bit sets the clock supply into the core block.

Set the PLLC bit to “1” and wait until the oscillation of the PLL stabilizes before setting this bit to “1”.

Refer to Figure 2.3.

Oscillation

buffer

XC K E bit

PLL

E xter nal clock

PLLC bit

Enable/Disable

SCKE bit

Xtal bits

Multiplying

factor

Core blockI/O b loc k

Enable/Disable

Figure 2.3 Clock Control

(5) USBPC (USB Transceiver Power Control) Bit (b10)

This bit sets the enable/disable of the USB transceiver block of I/O block.

Even if this bit is set to “0”, it is possible to receive the resume signal during the Suspended state (DVSQ bits

= “1xx”). It is necessary that the Tr_on bits be set to “x1” (during operation of SIE block).

(6) Tr_on (Tr_on Output Control) Bits (b9~b8)

These bits set the TrON signal output from I/O block and the enable/disable of SIE block in core block.

(7) USBE (USB Module Operation Enable) Bit (b0)

This bit sets S/W reset.

When this bit is set to “0”, the M66291 enters the S/W reset state and the registers are set to their S/W reset

state.

M66291GP/HP

Rev1.01 2004.11.01 page 14 of 122

2.2 Remote Wakeup Register

Q Remote Wakeup Register (REMOTE_WAKEUP) <Address : H’02>

b151413121110987654321b0

WKUP

0000000000000000

----------------

b Bit name Function R W

15~1 Reserved. Set it to “0”. 00

0WKUP

Remote Wakeup

Q Read

0 : Do not output the remote wakeup signal

1 : Output the remote wakeup signal

Q Write

0 : Invalid (Ignored when written)

1 : Output the remote wakeup signal

{{

(1) WKUP (Remote Wakeup) Bit (b0)

This bit controls the output of the remote wakeup signal (K state output).

This bit is valid only when the device state is “suspend” (DVSQ bits = “1xx”). The writing of “1” to this bit is

ignored when the device state is not suspend.

When “1” is written to this bit, the K state is output for 10 ms. The bit is automatically cleared to “0” after K

state output.

The bus idle state continues (this WKUP bit = “1”) for 2 ms after the Suspend state is detected when “1” is

written to this bit before outputting the K state for 10 ms.

The 2 ms and 10 ms time intervals are counted using a clock. Make sure that the counting stops if the clock is

not supplied (Note).

Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.

M66291GP/HP

Rev1.01 2004.11.01 page 15 of 122

2.3 Sequence Bit Clear Register

Q Sequence Bit Clear Register (SEQUENCE_BIT ) <Address : H’04>

b151413121110987654321b0

SQCLR

0000000000000000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 SQCLR

Sequence Bit Clear

Q Write

0 : Invalid (Ignored when written)

1 : Clear Sequence bit

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) SQCLR (Sequence Bit Clear) Bits (b6~b0)

These bits clear the sequence bit (the bit controlled by H/W) and turns the data PID into DATA 0 PID.

This bit immediately returns to “0” after writing “1”.

In the transfers after the sequence bit is cleared, the sequence bit is toggled through H/W control.

At S/W reset (USBE bit = “1”) and USB bus reset, the sequence bit of each endpoint is not cleared.

Note : Be sure to set the response PID of the endpoint whose sequence bit is desired to be cleared to NAK (EP0_PID

bits = “00”/EPi_PID bits = “00”) before writing “1” to this bit.

M66291GP/HP

Rev1.01 2004.11.01 page 16 of 122

2.4 USB_Address Register

Q USB_Address Register (USB_ADDRESS) <Address : H’08>

b151413121110987654321b0

USB_Addr

0000000000000000

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 USB_Addr

USB_Address

Q Read

USB address assigned by the host

{×

(1) USB_Addr (USB_Address) Bits (b6~b0)

These bits store the USB address assigned by the host.

On receiving SET_ADDRESS request from the host at default state (DVSQ bits = “001”), the requested device

address value is set to this register when the response is made through zero-length packet in status stage.

The device address value is set to these bits at the time of zero-length packet transmit even if the ASAD bit is

set to “0” (automatic response is invalid).

M66291GP/HP

Rev1.01 2004.11.01 page 17 of 122

2.5 Isochronous Status Register

Q Isochronous Status Register (ISOCHRONOUS_STATUS) <Address : H’0A>

b151413121110987654321b0

FMOD FRNM

0000000000000000

----------------

b Bit name Function R W

15~12 Reserved. Set it to “0”. ?0

11 FMOD

Frame Number Mode 0 : At SOF receive

1 : At Isochronous transfer complete

{{

10~0 FRNM

Frame Number Stores the frame number {×

This register is valid only for isochronous transfer. In other words, the register is valid status for the endpoint

that is set EPi_TYP bits to “11”.

(1) FMOD (Frame Number Mode) Bit (b11)

This bit sets the storage timing of the frame number to be stored to the FRNM bits.

When this bit is set to “0”, when the SOF packet is properly received, the frame number of the received SOF

packet gets stored.

When this bit is set to “1”, when the isochronous packet transfer completes, the frame number of the properly

received SOF packet gets stored.

(2) FRNM (Frame Number) Bits (b10~b0)

The frame number is stored in the FRNM with the timing set by the FMOD bit of this register. Here, the

SOFR bit is set to “1”.

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Rev1.01 2004.11.01 page 18 of 122

2.6 SOF Control Register

Q SOF Control Register (SOF_CNT) <Address : H’0C>

b151413121110987654321b0

SOFOE SOFA

0000000000000000

----------------

b Bit name Function R W

15 SOFOE

SOF Output Enable 0 : Disable SOF signal output

1 : Enable SOF signal output

{{

14 SOFA

SOF Polarity 0 : "L" active

1 : "H" active

{{

13~0 Reserved. Set it to “0”. 00

(1) SOFOE (SOF Output Enable) Bit (b15)

This bit sets the enable/disable of SOF signal output.

When this bit is set to “1”, if SOF packet is received, the INT1/SOF pin outputs SOF signal. The output polarity is

set by SOFA bit.

The SOF signal outputs the pulse (approx. 0.67 us) equivalent to 32 clocks of the 48 MHz clock after receiving

the PID field. Refer to Figure 2.4.

Since the INT1 pin is double-function pin, do not allocate the interrupt signal to this pin when using the SOF

signal (Set by the Polarity Set Register).

SYNC PID FLAME CRC5

Fixed length Approx. 0.67us

USB bus s ignal

SOF packet

("L" active)

SOF signal

Figure 2.4 SOF Signal Output Timing

(2) SOFA (SOF Polarity) Bit (b14)

This bit sets the output polarity of SOF signal.

M66291GP/HP

Rev1.01 2004.11.01 page 19 of 122

2.7 Polarity Set Register

Q Polarity Set Register (POLARITY_CNT) <Address : H’0E>

b151413121110987654321b0

VB01 RM01 SF01 DS01 CT01 BE01 NR01 RD01 RDYM INTL INTA

0000000000000000

----------------

b Bit name Function R W

15 VB01

Vbus Interrupt Assign 0 : Assigns to INT0 pin

1 : Assigns to INT1 pin (Note)

{{

14 RM01

Resume Interrupt Assign 0 : Assigns to INT0 pin

1 : Assigns to INT1 pin (Note)

{{

13 SF01

SOF Detect Interrupt Assign 0 : Assigns to INT0 pin

1 : Assigns to INT1 pin (Note)

{{

12 DS01

Device State Transition Interrupt Assign 0 : Assigns to INT0 pin

1 : Assigns to INT1 pin (Note)

{{

11 CT01

Control Transfer Transition Interrupt Assign 0 : Assigns to INT0 pin

1 : Assigns to INT1 pin (Note)

{{

10 BE01

Buffer Empty/Size Over Error Interrupt Assign 0 : Assigns to INT0 pin

1 : Assigns to INT1 pin (Note)

{{

9 NR01

Buffer Not Ready Interrupt Assign 0 : Assigns to INT0 pin

1 : Assigns to INT1 pin (Note)

{{

8 RD01

Buffer Ready Interrupt Assign 0 : Assigns to INT0 pin

1 : Assigns to INT1 pin (Note)

{{

7~3 Reserved. Set it to “0”. 00

2RDYM

Buffer Ready Mode 0 : Clears the EPB_RDY bits by reading/writing all data of

buffer

1 : Clears the EPB_RDY bits by writing "0" to EPB_RDY bit

{{

1INTL

Interrupt Output Sense 0 : Edge sensitive output

1 : Level sensitive output

{{

0INTA

Interrupt Polarity 0 : "L" active or change from “H” to “L”

1 : "H" active or change from "L" to "H"

{{

Note : In order to allocate the interrupt output signal to the INT1/SOF pin, set the SOF signal output to “disable” (SOFOE bit =

“0”).

(1) VB01 (Vbus Interrupt Assign) Bit (b15)

This bit selects the pin to output the Vbus interrupt signal.

(2) RM01 (Resume Interrupt Assign) Bit (b14)

This bit selects the pin to output the resume interrupt signal.

(3) SF01 (SOF Detect Interrupt Assign) Bit (b13)

This bit selects the pin to output the SOF detect interrupt signal.

(4) DS01 (Device State Transition Interrupt Assign) Bit (b12)

This bit selects the pin to output device state transition interrupt signal.

(5) CT01 (Control Transfer Tran sition Interrupt Assign) Bit (b11)

This bit selects the pin to output the control transfer transition interrupt signal.

M66291GP/HP

Rev1.01 2004.11.01 page 20 of 122

(6) BE01 (Buffer Empty/Size Over Error Interrupt Assign) Bit (b10)

This bit selects the pin to output the buffer empty/size over error interrupt signal.

(7) NR01 (Buffer Not Ready Interrupt Assign) Bit (b9)

This bit selects the pin to output the buffer not ready interrupt signal.

(8) RD01 (Buffer Ready Interrupt Assign) Bit (b8)

This bit selects the pin to output the buffer ready interrupt signal.

(9) RDYM (Buffer Ready Mode) Bit (b2)

This bit selects the method of clearing the buffer ready interrupt.

When this bit is set to “0”, the EPB_RDY bit is cleared to “0” after the CPU side buffer data are all read out or

after the writing of transmit data completes.

When this bit is set to “1”, the EPB_RDY bit is cleared to “0” by writing “0” to the EPB_RDY bit.

For details, refer to “EPB_RDY bit”.

Note : Refer to “3.2 FIFO Buffer” for CPU/SIE side.

(10) INTL (Interrupt Output Sense) Bit (b1)

This bit sets the sense mode for interrupt output from INT0 or INT1 pin.

When this bit is set to “0”, the INT0 or INT1 pin notifies the occurrence of interrupt at the edge set by the

INTA bit.

During edge sensitive output, when “0” is written to each interrupt factor bit to clear the interrupt, the output

signal outputs the negate value one time. If the other interrupt factor bits are set to “1”, the occurrence of

interrupt again is notified at the edge. The negate period is equivalent to 32 clocks (approx. 667 ns) of the 48

MHz clock.

In case the clock is not supplied (Note), the negate period does not occur. Make sure not to miss the interrupt

when Vbus interrupt or resume interrupt occurs.

When this bit is set to “1”, the INT0 or INT1 pin notifies the occurrence of interrupt at the level set by the

INTA bit.

During level sensitive output, the negate fails to work unless all interrupt factor bits are cleared even if “0” is

written to clear the interrupt to the interrupt factor bits.

Refer to Figure 2.5 and “3.1 Interrupt Function”.

Note : SCKE bit = “0” when XCKE bit = “1 ” , or XCKE bit = “0”.

M66291GP/HP

Rev1.01 2004.11.01 page 21 of 122

In terru p t factor 1

("H " a ctive)

Ne gate pe riod

(Approx.667ns)

Facto r 1 o ccu r

<Edge sense> Factor 1 clearFactor 2 occur Factor 2 clear

In terru p t factor 2

("H " a ctive)

Interrup t p in

("L" a ctive)

In terru p t factor 1

("H " a ctive)

Factor 1 occur

<Leve sense> F acto r 1 clearFactor 2 occur Factor 2 clear

In terru p t factor 2

("H " a ctive)

Interrup t p in

("L" a ctive)

Figure 2.5 Interrupt Signal Output Timing

(11) INTA (Interrupt Polarity) Bit (b0)

This bit sets the interrupt signal output polarity.

When this bit is set to “0”, the occurrence of interrupt is notified when;

In case of edge sense (INTL bit = “0”) : Change from “H” to “L”

In case of level sense (INTL bit = “1”) : “L” level

When this bit is set to “1”, the occurrence of interrupt is notified when;

In case of edge sense (INTL bit = “0”) : Change from “L” to “H”

In case of level sense (INTL bit = “1”) : “H” level

M66291GP/HP

Rev1.01 2004.11.01 page 22 of 122

2.8 Interrupt Enable Register 0

Q Interrupt Enable Register 0 (INT_ENABLE0) <Address : H’10>

b151413121110987654321b0

VBSE RSME SOFE DVSE CTRE BEMPE INTNE INTRE URST SADR SCFG SUSP WDST RDST CMPL SERR

0000000000000000

----------------

b Bit name Function R W

15 VBSE

Vbus Interrupt Enable 0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when VBUS bit is set to “1”)

{{

14 RSME

Resume Interrupt Enable 0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when RESM bit is set to "1")

{{

13 SOFE

SOF Detect Interrupt Enable 0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when SOFR bit is set to "1")

{{

12 DVSE

Device State Transition Interrupt Enable 0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when DVST bit is set to "1")

{{

11 CTRE

Control Transfer Transition Interrupt Enable 0 : Disable interrupt

1 : Enable interrupt

(Interrupt is occurs when CTRT bit is set to "1")

{{

10 BEMPE

Buffer Empty/Size Over Error Interrupt Enable 0 : Disable interrupt

1 : Enable interrupt

(Interrupt is occurs when BEMP bit is set to "1")

{{

9 INTNE

Buffer Not Ready Interrupt Enable 0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when INTN bit is set to "1")

{{

8 INTRE

Buffer Ready Interrupt Enable 0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when INTR bit is set to "1")

{{

7 URST

USB Reset Detect 0 : Disable DVST bit set

1 : Enable DVST bit set

{{

6 SADR

SET_ADDRESS Execute 0 : Disable DVST bit set

1 : Enable DVST bit set

{{

5SCFG

SET_CONFIGURATION Execute 0 : Disable DVST bit set

1 : Enable DVST bit set

{{

4SUSP

Suspend Detect 0 : Disable DVST bit set

1 : Enable DVST bit set

{{

3WDST

Control Write Transfer Status Stage 0 : Disable CTRT bit set

1 : Enable CTRT bit set

{{

2 RDST

Control Read Transfer Status Stage 0 : Disable CTRT bit set

1 : Enable CTRT bit set

{{

1CMPL

Control Transfer Complete 0 : Disable CTRT bit set

1 : Enable CTRT bit set

{{

0 SERR

Control Transfer Sequence Error 0 : Disable CTRT bit set

1 : Enable CTRT bit set

{{

This register sets enable of interrupt and enable/disable of setting DVST and CTRT bits to “1”.

Also refer to “3.1 Interrupt Function”.

M66291GP/HP

Rev1.01 2004.11.01 page 23 of 122

(1) VBSE (Vbus Interrupt Enable) Bit (b15)

This bit sets enable/disable of Vbus interrupt.

When this bit is set to “1”, the interrupt occurs if VBUS bit is set to “1”.

This bit is capable of writing/reading even if the clock is not supplied (Note).

Note : At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.

(2) RSME (Resume Interrupt Enable) Bit (b14)

This bit sets enable/disable of resume interrupt.

When this bit is set to “1”, the interrupt occurs if RESM bit is set to “1”.

This bit is capable of writing/reading even if the clock is not supplied (Note).

Note : At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.

(3) SOFE (SOF Detect Interrupt Enable) Bit (b13)

This bit sets enable/disable of SOF detect interrupt.

When this bit is set to “1”, the interrupt occurs if SOFR bit is set to “1”.

(4) DVSE (Device State Transition Interrupt Enable) Bit (b12)

This bit sets enable/disable of device state transition interrupt.

When this bit is set to “1”, the interrupt occurs if DVST bit is set to “1”.

The Conditions the DVST bit set are depend on the URST, SADR, SCFG or SUSP.

(5) CTRE (Control Transfer Transition Interrupt Enable) Bit (b11)

This bit sets enable/disable of control transfer transition interrupt.

When this bit is set to “1”, the interrupt occurs if CTRT bit is set to “1”.

The Conditions the DVST bit set are depend on the WDST, RDST, CMPL or SERR.

The complete of setup stage can not set enable/disable to set CTRT bit to “1”.

(6) BEMPE (Buffer Empty/Size Over Error Interrupt Enable) Bit (b10)

This bit sets enable/disable of buffer empty/size over error interrupt.

When this bit is set to “1”, the interrupt occurs if BEMP bit is set to “1”.

(7) INTNE (Buffer Not Ready Interrupt Enable) Bit (b9)

This bit sets enable/disable of buffer not ready interrupt.

When this bit is set to “1”, the interrupt occurs if INTN bit is set to “1”.

(8) INTRE (Buffer Ready Interrupt Enable) Bit (b8)

This bit sets enable/disable of buffer ready interrupt.

When this bit is set to “1”, the interrupt occurs if INTR bit is set to “1”.

(9) URST (USB Reset Detect) Bit (b7)

This bit selects whether to set the DVST bit to “1” or not at the USB bus reset detection.

The register is initialized by the USB reset detection, irrespective of the value of this bit.

(10) SADR (SET_ADDRESS Execute) Bit (b6)

This bit selects whether to set the DVST bit to “1” or not at the SET_ADDRESS execution.

For details, refer to “DVST bit”.

M66291GP/HP

Rev1.01 2004.11.01 page 24 of 122

(11) SCFG (SET_CONFIGURATION Execute) Bit (b5)

This bit selects whether to set the DVST bit to “1” or not at the SET_ CONFIGURATION execution.

For details, refer to “DVST bit”.

(12) SUSP (Suspend Detect) Bit (b4)

This bit selects whether to set the DVST bit to “1” or not at the suspend detection.

(13) WDST (Control Write Transfer Status Stage) Bit (b3)

This bit selects whether to set the CTRT bit to “1” or not when transited to status stage during control write

transfer.

(14) RDST (Control Read Transfer Status Stag e) Bit (b 2)

This bit selects whether to set the CTRT bit to “1” or not when transited to status stage during control read

transfer.

(15) CMPL (Control Transfer Complete) Bit (b1)

This bit selects whether to set the CTRT bit to “1” or not when the status stage completes during control

transfer.

(16) SERR (Control Transfer Sequence Error) Bit (b0)

This bit selects whether to set the CTRT bit to “1” or not when the sequence error is detected at control

transfer.

M66291GP/HP

Rev1.01 2004.11.01 page 25 of 122

2.9 Interrupt Enable Register 1

Q Interrupt Enable Register 1 (INT_ENABLE1) <Address : H’12>

b151413121110987654321b0

EPB_RE

0000000000000000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 EPB_RE

Buffer Ready Interrupt Enable 0 : Disable INTR bit set

1 : Enable INTR bit set

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

{{

(1) EPB_RE (Buffer Ready Interrupt Enable) Bits (b6~b0)

These bits select whether to set the INTR bit to “1” or not when the EPB_RDY bit is set to “1”.

Also refer to “3.1 Interrupt Function”.

M66291GP/HP

Rev1.01 2004.11.01 page 26 of 122

2.10 Interrupt Enable Register 2

Q Interrupt Enable Register 2 (INT_ENABLE2) <Address : H’14>

b151413121110987654321b0

EPB_NRE

0000000000000000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 EPB_NRE

Buffer Not Ready Interrupt Enable 0 : Disable INTN bit set

1 : Enable INTN bit set

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

{{

(1) EPB_NRE (Buffer Not Ready Interrupt Enable) Bits (b6~b0)

These bits select whether to set the INTN bit to “1” or not when the EPB_NRDY bit is set to “1”.

Also refer to “3.1 Interrupt Function”.

Note : Do not set the corresponding bit of this register to “1” when the endpoint is set to isochronous transfer (set by

EPi _TYP bits).

M66291GP/HP

Rev1.01 2004.11.01 page 27 of 122

2.11 Interrupt Enable Register 3

Q Interrupt Enable Register 3 (INT_ENABLE3) <Address : H’16>

b151413121110987654321b0

EPB_EMPE

0000000000000000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 EPB_EMPE

Buffer Empty/Size Over Error Interrupt Enable 0 : Disable BEMP bit set

1 : Enable BEMP bit set

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

{{

(1) EPB_EMPE (Buffer Empty/Size Over Error Interrupt Enable) Bits (b6~b0)

These bits select whether to set the BEMP bit to “1” or not when the EPB_EMP_OVR bit is set to “1”.

Also refer to “3.1 Interrupt Function”.

M66291GP/HP

Rev1.01 2004.11.01 page 28 of 122

2.12 Interrupt Status Register 0

Q Interrupt Status Register 0 (INT_STATUS0) <Address : H’18>

b151413121110987654321b0

VBUS RESM SOFR DVST CTRT BEMP INTN INTR Vbus DVSQ VALID CTSQ

0000000000000000

---1----0001----

b Bit name Function R W

15 VBUS

Vbus Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

{{

14 RESM

Resume Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

{{

13 SOFR

SOF Detect Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

{{

12 DVST

Device State Transition Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

{{

11 CTRT

Control Transfer Stage Transition Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

{{

10 BEMP

Buffer Empty/Size Over Error Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

Invalid (Ignored when written)

{×

9INTN

Buffer Not Ready Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

Invalid (Ignored when written)

{×

8INTR

Buffer Ready Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

Invalid (Ignored when written)

{×

M66291GP/HP

Rev1.01 2004.11.01 page 29 of 122

b Bit name Function R W

7 Vbus

Vbus Level

Q Read

0 : "L"

1 : "H"

Q Write

Invalid (Ignored when written)

{×

6~4 DVSQ

Device State

Q Read

000 : Powered state

001 : Default state

010 : Address state

011 : Configured state

1xx : Suspended state (Note)

Q Write

Invalid (Ignored when written)

{×

3 VALID

Setup Packet Detect

Q Read

0 : No detection

1 : Receiving the setup packet

Q Write

0 : This VALID bit clear

1 : Invalid (Ignored when written)

{{

2~0 CTSQ

Control Transfer Stage

Q Read

000 : Idle or setup stage

001 : Control read transfer data stage

010 : Control read transfer status stage

011 : Control write transfer data stage

100 : Control write transfer status stage

101 : Control write no data transfer status stage

110 : Control transfer sequence error

111 : Reserved

Q Write

Invalid (Ignored when written)

{×

Note : x is a optional value.

The b15 to b8 of this register are interrupt status bits. When the bit of the Interrupt Enable Register

corresponding to these bits are set to “1” (interrupt enable), the interrupt occurs by setting these bits to “1”.

(1) VBUS (Vbus Interrupt) Bit (b15)

This bit indicates the change of Vbus input.

This bit is set to “1” (Vbus interrupt occurs) when the Vbus input changes (“L”->“H” or “H”->“L”).

This bit is cleared to “0” by writing “0” (interrupt is cleared).

This bit is set to “1” and can be read out even if the clock is not supplied (Note). This bit can also be cleared by

writing “0”. In case the clock is not supplied, make sure to write “1” after writing “0” (no further interrupt will

be accepted).

Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.

M66291GP/HP

Rev1.01 2004.11.01 page 30 of 122

(2) RESM (Resume Interrupt) Bit (b14)

This bit indicates the change of USB bus state.

This bit is set to “1” when the USB bus state is changed from suspended (DVST bits = “1xx”) to “J”->“K” or

“J”->“SE0” (resume interrupt occurs).

This bit is cleared to “0” by writing “0” (interrupt is cleared).

This bit is set to “1” and can be read out even if the clock is not supplied (Note). This bit can also be cleared by

writing “0”. In case the clock is not supplied, make sure to write “1” after writing “0” (no further interrupt will

be accepted).

Note : At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.

(3) SOFR (SOF Detect Interrupt) Bit (b13)

This bit indicates that the SOF packet is received and the frame number is updated.

This bit is set to “1” when the SOF packet is received and the frame number is stored at the timing set by the

FMOD bit of the Isochronous Status Register (SOF detect interrupt occurs).

This bit is cleared to “0” by writing “0” (interrupt is cleared).

(4) DVST (Device State Transition Interrupt) Bit (b12)

This bit indicates the transition of the device state.

This bit is set to “1” when the transition of device states takes place as follows (device state transition

interrupt occurs):

(A) USB bus reset detect (Arbitrary state -> Default state):

When the SE0 state continues for 2.5 us or more in D+ and D- pins, the USB bus reset is detected,

causing this bit to be set to “1”.

(B) “SET_ADDRESS” execute (Default state -> Address state):

This bit is set to “1” when the SET_ADDRESS request is detected as (a) and the response is made

by zero-length packet in status stage.

(a) “SET_ADDRESS” request in case device address value in default state is not “0”:

In case the wValue in default state is “0”, this bit is not set to “1”. When this request is

received, the device address value is set to the USB_Address Register, irrespective of the

setting of this bit.

This bit is set to “1” when the requests below are detected and ACK is received after the response

is made through zero-length packet in status stage.

(a) “SET_CONFIGURATION” request in case configuration value in address state is not “0”

(b) “SET_CONFIGURATION” request in case configuration value in configured state is “0”

(D)Suspend detect (Powered/Default/Address/Configured state -> Suspended state):

The suspended state is detected and this bit is set to“1” when the idle state continues for 3 ms or

more in D+ and D- pins.

The Conditions that this bit indicates "1" depend on the URST, SADR, SCFG or SUSP bits.

This bit is cleared to “0” by writing “0” (interrupt is cleared).

The present device state can be confirmed by the DVSQ bits.

M66291GP/HP

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(5) CTRT (Control Tran sfer Stag e Transition Interrupt) Bit (b11)

This bit indicates the transition of stage in control transfers.

This bit is set to “1” when the stage transition of control transfer takes place as follows (control transfer stage

transition interrupt occurs):

Refer to Figure 2.7.

•Setup Stage Complete (When transmitting ACK)

•Control Write Transfer Status Stage Transition (When receiving IN token)

•Control Read Transfer Status Stage Transition (When receiving OUT token)

•Control Transfer Complete (When transmitting or receiving ACK)

•Control Transfer Sequence Error (When error occurs)

The Conditions that this bit indicates "1" depend on the WDST, RDST, CMPL or SERR bits.

This bit is cleared to “0” by writing “0” (interrupt is cleared).

The present stage can be confirmed by the CTSQ bits.

(6) BEMP (Buffer Empty/Size Over Error Interrupt) Bit (b10)

This bit indicates the occurrence of “buffer empty” or “buffer size over error”.

This bit is set to “1” when the EPB_EMP_OVR bit is set to “1” (buffer empty/buffer size over error interrupt

occurs).

This bit is cleared by setting all the bits of Interrupt Status Register 3 to “0”.

For details, refer to “Interrupt Status Register 3”.

(7) INTN (Buffer Not Ready Interrupt) Bit (b9)

This bit indicates the NAK has been sent to the host because of the “buffer not ready” state.

This bit is set to “1” when the EPB_NRDY bit is set to “1” (buffer not ready interrupt occurs).

This bit is cleared by setting all the bits of Interrupt Status Register 2 to “0”.

For details, refer to “Interrupt Status Register 2”.

(8) INTR (Buffer Ready Interrupt) Bit (b8)

This bit indicates the “buffer ready” state (that can be read/written).

This bit is set to “1” when the EPB_RDY bit is set to “1” (buffer ready interrupt occurs).

This bit is cleared by setting all the bits of Interrupt Status Register 1 to “0”.

For details, refer to “Interrupt Status Register 1”.

(9) Vbus (Vbus Level) Bit (b7)

This bit indicates the state of Vbus pin.

When this bit changes, the VBUS bit is set to “1”.

This bit is capable of reading the correct value even if the clock is not supplied (Note).

Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.

(10) DVSQ (Device State) Bits (b6~b4)

These bits indicate the present device states as follows:

000 : Powered State Power ON state

001 : Default State USB bus reset detected state

010 : Address State SET_ADDRESS request executed state

011 : Configured State SET_CONFIGURATION request executed state

1xx : Suspended State “suspended” detected state

Depending on the changes of these device states, the DVST bit and the RESM bit are set to “1” (set

enable/disable by the URST, SADR, SCFG or SUSP bits). For details, refer to “DVST bit” and Figure 2.6.

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Powered

state

(DV S Q bits ="000")

SET_ADDR ESS excecution

(When SADR b it= " 1 " , DVST b it is s et to " 1 " )

USB bus reset detection

(When URST bit= " 1 " , DVST b it is set to " 1 ")

R esume ( RES M b it is set to " 1 ")

Default

state

(DV S Q bits="001")

Configured

state

(DV S Q bits="011")

Suspended

state

(DV S Q bits="100")

Address

state

(DV S Q bits="010")

Suspended

state

(DV S Q bits="111")

Suspended

state

(DV S Q bits="101")

Suspended

state

(DV S Q bits="110")

Suspend detection

(Wh en SUSP b it=" 1 ", DV ST bit is set to "1 " )

R esume ( RES M b it is set to " 1 ")

SET _C ONF IGUR ATION excecution[ConfigurationValue=0]

(When SCF G bit= " 1 " , DVST b it is set to "1 " )

Suspend detection

(When SUSP b it=" 1 " , DVS T bit is set to "1 " )

R esume ( RES M b it is set to " 1 ")

Sus pend detection

(When SUSP b it=" 1 " , DVS T bit is set to "1 " )

Suspend detection

(When SUSP b it=" 1 " , DVST bit is set to "1 " )

R esume ( RES M b it is set to " 1 ")

USB bus reset detection

(Wh en URS T b it= " 1 " , DVST bit is set to "1 " )

N ote : Th e URST, SADR, SCFG and SUSP b its ( In terr u p t En able Reg is ter 0) in the paren th esis set enab le/disable to s et th e DVST b it to "1 " f or th e

c orr es p on d in g s tag e tr ansition. Th er e is n o b it to s et en able/d is ab le to s et the RESM b it to "1 " .

T he s tag e tran sition takes place even if th es e b its ar e inh ib ited to set to "1 " .

SE T _CON FIG UR A TIO N excecution[ConfigurationValue= 0]

(When SCFG b it= " 1 " , DVST b it is s et to " 1 " ) /

Figure 2.6 Device State Transition

(11) VALID (Setup Packet Detect) Bit (b3)

This bit indicates that the setup token has been received.

When the setup token is completely received, this bit is set to “1”.

When this bit is set to “1”, the writing to EP0_PID/CCPL bits of EP0_FIFO Control Register is ignored.

At the time of receiving the setup token, the interrupt has not occurred (the interrupt occurs only after the

termination of setup stage).

This bit is cleared to “0” by writing “0”.

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(12) CTSQ (Control Transfer Stage) Bits (b2~b0)

These bits indicate the present stage in the control transfer. Refer to Figure 2.7.

000 : Idle or Setup Stage

001 : Control Read Transfer Data Stage

010 : Control Read Transfer Status Stage

011 : Control Write Transfer Data Stage

100 : Control Write Transfer Status Stage

101 : Control Write No Data Transfer Status Stage

110 : Control Transfer Sequence Error (refer to below)

111 : Reserved

The control transfer sequence error is described below. When this error occurs, the EP0_PID bits are set to

“1x” (stall state).

•OUT token is received when data is never transferred against the IN token of the data stage.

•IN token is received at status stage.

•Data packet other than the zero-length packet is received at status stage.

•IN token is received when ACK response is never made against the OUT token of the data

stage.

•OUT token is received in status stage.

•OUT token is received in status stage.

•Data exceeding in size set by the EP0 Packet Size Register is received (the EPB_EMP_OVR

bit of the Interrupt Status Register 3 is set to “1”).

In case the amount of received data exceeds the wLength value in the request at the data stage of the

control write transfer, it is not recognized as the control transfer sequence error.

[CTSQ bits="1xx"]

Control transfer

sequence error

(Note)

ACK

receive

ACK transmit

Note : When the SERR bit is set to "1" and the control transfer sequence error causes the CTRT interrupt to

occur, the CTSQ bit values (1xx) are retained until "0" is written to the CTRT bit (interrupt is cleared).

Further, even after the completion of the next set up stage, the CTRT interrupt due to the completion

of the set up stage is not occurred until "0" is written to the CTRT bit.

When the SERR bit is set to "0", if setup token is received, the CTSQ bits changes to "000".

Error detection

: CTRT interrupt has occurred

(1) Setup stage completion

(2) Control read transfer

status stage transition

(3) Control write transfer

status stage transition

(4) Control transfer completion

(5) Control transfer

sequence error

[CTSQ bits="000"]

Setup stage

[CTSQ bits="011"]

Control write

transfer

data stage

[CTSQ bits="101"]

Control write

transfer no data

status stage

ACK

transmit

[CTSQ bits="010"]

Control read

transfer

status stage

[ CTSQ bits ="100"]

Control write

transfer

status stage

OUT token

receive

IN token receive

[CTSQ bits="000"]

Idle stage

ACK

receive

[CTSQ bits="001"]

Control read

transfer

data stage

Setup token receive

(1)

Setup token receive

(1)

(3)

(2)

(5)

(4)

Figure 2.7 Control Transfer Transition

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2.13 Interrupt Status Register 1

Q Interrupt Status Register 1 (INT_STATUS1) <Address : H’1A>

b151413121110987654321b0

EPB_RDY

0000000000000000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 EPB_RDY

Buffer Ready Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

Invalid (Ignored when written)

0 : Clear interrupt clear

1 : Invalid (Ignored when written)

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

{{

(1) EPB_RDY (Buffer Ready Interrupt) Bits (b6~b0)

The bit corresponding to each endpoint is set to “1” with the buffer at “ready” state.

The ready state refers to the state when CPU or DMAC can read or write the CPU side buffer. When the EPB_RE

bit is set to “1”, if this bit is set to “1”, the INTR bit is set to “1”, causing the buffer ready interrupt to occur.

Setting “1”/clearing to ”0” to this bit differs according to the endpoint and transfer direction as shown below:

Note : Refer to “3.2 FIFO Buffer” for CPU/SIE side.

zEndpoint 0

{ When set to control write transfer (ISEL bit = “0”)

The condition for this bit to be set to “1” is as follows:

•When the IVAL bit of the EP0_FIFO Control Register changes from “0” to “1”

The condition for this bit to be cleared to “0” differs according to the RDYM bit:

•RDYM bit = “0” : When the IVAL bit of the EP0_FIFO Control Register changes from

“1” to“0”

•RDYM bit = “1” : Writes “0” to this bit

{ When set to control read transfer (ISEL bit = “1”)

This bit is not set to “1” (Refer to “EPB_EMP_OVR bit”).

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zEndpoint 1~6

{ When set to OUT buffer (EPi_DIR bit = “0”)

The condition for this bit to be set to “1” is as follows:

•When the IVAL bit of the endpoint changes from “0” to “1”

•When the buffer data including the received short packet (including the zero-length

packet) are all read out

The condition for this bit to be cleared to “0” differs according to the RDYM bit (Note):

•RDYM bit = “0” : When the IVAL bit of the endpoint changes from “1” to “0”

•RDYM bit = “1” : Writes “0” to this bit

Note : When t he INTM bit at the endp oint specified by the DMA_EP bit is set to “0”, the IVAL bit is

retained to “1”. Thus, it is necessary to write “1” to the BCLR bit and to clear the IVAL bit to

“0” when RDYM bit is set to “0”. Even when the RDYM bit is set to “1”, this bit can be cleared

by writing “0”. It is necessary to write “1” to the BCLR bit and to clear the IVAL bit.

{ When set to IN buffer (EPi_DIR bit = “1”)

The condition for this bit to be set to “1” is as follows:

•When the IVAL bit of the endpoint changes from “1” to “0”

•Or when EPi_DER bit is changed from “0” to “1”

This bit is not be set to “1”.

The condition for this bit to be cleared to “0” differs according to the RDYM bits:

•RDYM bit = “0” : When the IVAL bit of the endpoint changes from “0” to “1”

•RDYM bit = “1” : Writes “0” to this bit

Note : The IVAL bit is located per endpoint. For details, refer to “3.2.4 IVAL Bit and EPB_RDY Bit”.

OUT token Data packet ACK packet

USB bus SYNC PID Addr Endp CRC EOP SYNC PID Data CRC EOP SYNC PID EOP

Interrupt output Occurrence of buffer ready interrupt

because the buffer could be read

Figure 2.8 Examples of Buffer Ready Interrupt Occurrence Timing (OUT transfer)

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2.14 Interrupt Status Register 2

Q Interrupt Status Register 2 (INT_STATUS2) <Address : H’1C>

b151413121110987654321b0

EPB_NRDY

0000000000000000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 EPB_NRDY

Buffer Not Ready Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear interrupt

1 : Invalid (Ignored when written)

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

{{

(1) EPB_NRDY (Buffer Not Ready Interrupt) Bits (b6~b0)

The bit corresponding to each endpoint is set to “1” when IN token/OUT token is received with the buffer at

“not ready” state.

The “not ready” state refers to the state when EP0_PID bits and EPi_PID bits are set to BUF/STALL response

and means that the buffer could not be received and transmitted.

When this bit is set to “1”, if the EP0_PID and EPi_PID bits are set to BUF, NAK response is executed, and if

they are set to STALL, STALL response is executed.

When the EPB_NRE bit is set to “1”, if this bit is set to “1”, the INTN bit is set to “1”, causing the buffer not

ready interrupt to occur.

This bit is cleared by writing “0”.

Note: In case the endpoint is set to isochronous transfer (set b y EPi_TYP bits), the corresponding bit of this register

may be set to “1”. Hence, do not set the corresponding bit of the Interrupt Enable Register 2 to “1”.

NAK/STALL

OUT token Data packet packet

USB bus SYNC PID Addr Endp CRC EOP SYNC PID Data CRC EOP SYNC PID EOP

Interrupt output Occurrence of buffer not ready interrupt

because the buffer could not be received

Figure 2.9 Examples of Buffer Not Ready Interrupt Occurrence Timing (OUT transfer)

NAK/STALL

IN token packet

USB bus SYNC PID Addr Endp CRC EOP SYNC PID EOP

Interrupt output Occurrence of buffer not ready interrupt

because the buffer could not be transmitted

Figure 2.10 Examples of Buffer Not Ready Interrupt Occurrence Timing (IN transfer)

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2.15 Interrupt Status Register 3

Q Interrupt Status Register 3 (INT_STATUS3) <Address : H’1E>

b151413121110987654321b0

EPB_EMP_OVR

0000000000000000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 EPB_EMP_OVR

Buffer Empty/Size Over Interrupt

Q Read

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear interrupt

1 : Invalid (Ignored when written)

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

{{

(1) EPB_EMP_OVR (Buffer Empty/Size Over Interrupt) Bits (b6~b0)

These bits indicate that the received data size exceeds the maximum packet size or that the buffers of the

endpoints 0 to 6 are empty.

z Endpoint 0

{When set to control write transfer (ISEL bit = “0”)

The condition for this bit to be set to “1” is as follows:

• Receives packet data with size exceeding the one set by the EP0 Packet Size Register

(Size-over detection).

In this case, the EP0_PID bits are set to STALL response.

Further the CTRT bit sets to “1” if the SERR bit is set to “1”.

This bit is set to “1” when size-over is detected, irrespective of the EP0_PID bit setting.

{When set to control read transfer (ISEL bit = “1”)

The condition for this bit to be set to “1” is as follows:

•When the IVAL bit of the EP0_FIFO Control Register changes from “1” to “0”.

•When transmit data exist in the buffer for EP0_FIFO and “1” is written to the BCLR bit.

z Endpoint 1~6

{When set to OUT buffer (EPi_DIR bit = “0”)

The condition for this bit to be set to “1” is as follows:

•Receives packet data with size exceeding the one set by the EPi_MXPS bits

(Size-over detection).

The EPi_PID bits are set to STALL response.

This bit isn’t set to “1” at isochronous transfer.

This bit is set to “1” when size-over is detected, irrespective of the EP0_PID bit setting.

{When set to IN buffer (EPi_DIR bit = “1”)

The condition for this bit to be set to “1” is as follows:

•When the data of SIE side buffer are all transmitted with the data not written to the CPU

side buffer (Buffer empty).

The conditions for this bit to be cleared to “0” in all bits are as follows:

•Writes “0” to this bit.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

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2.16 Request Register

Q Request Register (REQUEST_TYPE) <Address : H’20>

b151413121110987654321b0

bRequest bmRequestType

0000000000000000

----------------

b Bit name Function R W

15~8 bRequest

Request

Q Read

Request received in the setup stage

Q Write

Invalid (Ignored when written)

{×

7~0 bmRequestType

Request Type

Q Read

Request type received in the setup stage

Q Write

Invalid (Ignored when written)

{×

(1) bRequest (Request) Bits (b15~b8)

These bits store the bRequest of the device request received in the setup stage of the control transfer.

(2) bmRequestType (Request Type) Bits (b7~b0)

These bits store the bmRequestType of the device request received in the setup stage of the control transfer.

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2.17 Value Register

Q Value Register (REQUEST_VALUE) <Address : H’22>

b151413121110987654321b0

wValue

0000000000000000

----------------

b Bit name Function R W

15~0 wValue

Value

Q Read

Parameter of device request received in the setup stage

Q Write

Invalid (Ignored when written)

{×

(1) wValue (Value) Bits (b15~b0)

These bits store the wValue of the device request received at the setup stage of the control transfer.

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2.18 Index Register

Q Index Register (REQUEST_INDEX) <Address : H’24>

b151413121110987654321b0

wIndex

0000000000000000

----------------

b Bit name Function R W

15~0 wIndex

Index

Q Read

Parameter of device request received in the setup stage

Q Write

Invalid (Ignored when written)

{×

(1) wIndex (Index) Bits (b15~b0)

These bits store wIndex of the device request received in the setup stage of the control transfer.

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2.19 Length Register

Q Length Register (REQUEST_LENGTH) <Address : H’26>

b151413121110987654321b0

wlength

0000000000000000

----------------

b Bit name Function R W

15~0 wlength

Length

Q Read

Parameter of device request received in the setup stage

Q Write

Invalid (Ignored when written)

{×

(1) wlength (Length) Bits (b15~b0)

These bits store the wlength of the device request received at the setup stage of the control transfer.

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2.20 Control Transfer Control Register

Q Control Transfer Control Register (CONT ROL_TRANSFER) <Address : H’28>

b151413121110987654321b0

CTRR Ctr_Rd_Buf_Nmb CTRW Ctr_Wr_Buf_Nmb

0000000000000000

----------------

b Bit name Function R W

15 CTRR

Control Read Transfer Continuous Transmit

Mode

0 : Single transmit mode

1 : Continuous transmit mode

{{

14 Reserved. Set it to "0". 00

13~8 Ctr_Rd_Buf_Nmb

Control Read Buffer Start Number The top block number for the Control Read buffer {{

7CTRW

Control Write Transfer Continuous Receive

Mode

0 : Unit receive mode

1 : Continuous receive mode

{{

6 Reserved. Set it to “0”. 00

5~0 Ctr_Wr_Buf_Nmb

Control Write Buffer Start Number The top block number for the Control Write buffer {{

(1) CTRR (Control Read Transfer Continuous Transmit Mode) Bit (b15)

This bit sets the transmit mode at data stage of the control read transfer.

In case of single transmit mode, the transmit completes after transmitting one packet under the condition as

follows:

•Transmits the data equivalent to the size set by the EP0 Packet Size Register or transmits a short

packet by setting the IVAL bit to “1”.

In case of continuous transmit mode, the transmit completes after transmitting several packets under the

condition as follows:

•Transmits the data equivalent to the size set by the EP0_FIFO Continuous Transmit Data Length

In case of single transmit mode, the writing completes under the conditions as follows:

•Writes the data equivalent to the size set by the EP0 Packet Size Register to the buffer

(The IVAL bit of the EP0_FIFO Control Register changed to “1”).

•Writes “1” to the IVAL bit of the EP0_FIFO Control Register.

In case of continuous transmit mode, the writing completes under the conditions as follows:

•Writes the data equivalent to the size set by the EP0_FIFO Continuous Transmit Data Length

•Writes “1” to the IVAL bit of the EP0_FIFO Control Register.

The setting conditions of the IVAL bit of the EP0_FIFO Control Register change due to this bit.

(2) Ctr_Rd_Buf_Nmb (Control Read Buffer Start Number) Bits (b13~b8)

These bits set the beginning block number of the buffer to be used in control read transfer. The block number

is a number by dividing the FIFO buffer into 64 byte sections (Note 1).

When the mode is set to single transmit (CTRR bit = “0”), the blocks set by these bits only are used and, from

the following block, it is possible to set to the buffer of a different endpoint.

When the mode is set to continuous transmit (CTRR bit = “1”), the buffer equivalent to the size set by the

EP0_FIFO Continuous Transmit Data Length Register (max. 256 bytes) is used from the block numbers set by

these bits (Note 2).

Note 1: The M66291 is equipped with 3 Kbytes FIFO buffer and has blocks from H’0 to H’2F.

Note 2: Make sure that several endpoints do not get overlapped in the same buffer area.

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(3) CTRW (Control Write Transfer Continuous Receive Mode) Bit (b7)

This bit sets the receive mode at data stage of the control write transfer.

In case of unit receive mode, the receive completes after receiving one packet under the condition as follows:

•Receives the data equivalent to the size set by the EP0 Packet Size Register.

•Receives a short packet.

In case of continuous receive mode, the receipt completes after receiving several packets under the condition

as follows:

•Receives automatically the data equivalent to the size set by the EP0 Packet Size Register several

times and receives the data equivalent to 256 bytes.

•Receives the short packet.

The setting conditions of the IVAL bit of the EP0_FIFO Control Register change due to this bit.

(4) Ctr_Wr_Buf_Nmb (Control Write Buffer Start Number) Bits (b5~b0)

These bits set the beginning? block number of the buffer to be used in control write transfer. The block number

is a number for control by dividing the FIFO buffer into 64 byte sections (Note 1).

When the mode is set to unit receive (CTRW bit = “0”), the blocks set by these bits only are used and, from the

following block, it is possible to set to the buffer of a different endpoint.

When the mode is set to continuous receive (CTRW bit = “1”), the buffer equivalent to 256 bytes is used from

the block numbers set by these bits (Note 2).

Note 1: The M66291 is equipped with 3 Kbytes FIFO buffer and has blocks from H’0 to H’2F.

Note 2: Make sure that several endpoints do not get overlapped in the same buffer area.

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2.21 EP0 Packet Size Register

Q EP0 Packet Size Register (EP0_PACKET_SIZE) <Address : H’2A>

b151413121110987654321b0

EP0_MXPS

0000000000001000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 EP0_MXPS

Maximum Packet Size Upper limit of the transmit/receive data for one packet transfer

(Settable only 8,16,32 and 64)

{{

(1) EP0_MXPS (Maximum Packet Size) Bits (b6~b0)

These bits set the upper limit (byte count) of the transmit/receive data for one packet transfer at data stage.

Set the value of bMaxPacketSize0 transmitted to the host.

At the time of transmitting, the data equivalent to the size set by these bits is read from the buffer for

transmission. In case the buffer does not have the data equivalent to the size set by these bits, the data is

transmitted as the short packet.

At the time of receiving, the data equivalent to the size set by these bits is written to the buffer. If the received

packet data is larger than the size set by these bits, the following bits are set to "1":

•The EPB_EMP_OVR bit.

(buffer empty/Size over error interrupt occurs when the EPB_EMPE bit is set to “1”.)

•The CTRT bit when the SERR bit is set to “1”.

(control transfer stage transition interrupt occurs.)

Note: Set these bits after setting the response PID to NAK (EP0_PID bits = “00”).

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2.22 Automatic Response Control Register

Q Automatic Response Control Register (AUTO_RESPONSE_CONTROL) <Address : H’2C>

b151413121110987654321b0

ASCN ASAD

0000000000000000

----------------

b Bit name Function R W

15~2 Reserved. Set it to “0”. 00

1 ASCN

SET_CONFIGURATION Automatic Response

Mode

0 : Invalid of automatic response mode for

SET_CONFIGURATION

1 : Valid of automatic response mode for

SET_CONFIGURATION

{{

0 ASAD

SET_ADDRESS Automatic Response Mode 0 : Invalid of automatic response mode for SET_ADDRESS

1 : Valid of automatic response mode for SET_ADDRESS

{{

(1) ASCN (SET_CONFIGURATION Automatic Response Mode) Bit (b1)

This bit sets the valid/invalid of automatic response mode for SET_CONFIGURATION request.

With the automatic response mode set to valid, zero-length packet is automatically transmitted against the

requests below at the status stage before notifying the normal completion. Here, the CTRT bit is not set to “1”

(control transfer stage transition interrupt does not occur).

•SET_CONFIGURATION request of Configuration Value ≠ 0 in Address state

•SET_CONFIGURATION request of Configuration Value = 0 in Configured state

No automatic response is executed when the SET_CONFIGURATION request other than the ones given

above is received. In such case, the CTRT bit is set to “1” (control transfer stage transition interrupt occurs).

When the state gets changed after receiving the aforesaid requests, the DVST bit is set to “1” if the SCFG bit is

set to “1”, irrespective of the validity of this function (device state transition interrupt occurs).

(2) ASAD (SET_ADDRESS Automatic Response Mode) Bit (b0)

This bit sets the valid/invalid of automatic response mode for SET_ADDRESS request.

With the automatic response mode set to valid, zero-length packet is automatically transmitted against the

requests below at the status stage before notifying the normal completion. Here, the CTRT bit is not set to “1”

(control transfer stage transition interrupt does not occur).

•SET_ADDRESS request at Default state

No automatic response is executed when the SET_ADDRESS request other than the ones given above is

received. In such case, the CTRT bit is set to “1” (control transfer stage transition interrupt occurs).

When the state gets changed after receiving the aforesaid requests, the DVST bit is set to “1” if the SADR bit

is set to “1”, irrespective of the validity of this function (device state transition interrupt occurs).

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2.23 EP0_FIFO Select Register

Q EP0_FIFO Select Register (EP0_FIFO_SELECT) <Address : H’30>

b151413121110987654321b0

RCNT Octl BSWP ISEL

0000000000000000

----------------

b Bit name Function R W

15 RCNT

Read Count Mode 0: The ODLN bits are cleared by reading all receive data

1: The ODLN bits are counted down by reading receive data

{{

14~11 Reserved. Set it to “0”. 00

10 Octl

1 : EP0_FIFO Data Register is 8-bit mode

{{

9~8 Reserved. Set it to “0”. 00

7 BSWP

Byte Swap Mode 0 : Byte is treated as little ENDIAN

1 : Byte is treated as big ENDIAN

{{

6~1 Reserved. Set it to “0”. 00

0 ISEL

Buffer Select 0 : Control write transfer

1 : Control read transfer

{{

(1) RCNT (Read Count Mode) Bit (b15)

This bit sets the countdown methods of the ODLN bits at the time of reading the EP0_FIFO Data Register.

When this bit is set to “0”, the ODLN bit value does not change in spite of reading the data from the EP0_FIFO

Data Register, and is cleared to H’0 when all data is read out.

When this bit is set to “1”, the ODLN bit values are counted down every time the data is read from the

EP0_FIFO Data Register. Here, the down-count value differs as shown below depending on whether the

EP0_FIFO Data Register is set to 8-bit mode or 16-bit mode:

•8-bit mode : Down-count per “-1”

•16-bit mode : Down-count per “-2”

Note : Use the *HWR/*BYTE pin or the Octl bit of this register for setting the 8-bit/16-bit mode.

(2) Octl (Register 8-Bit Mode) Bit (b10)

This bit sets the access mode of the EP0_FIFO Data Register.

When this bit is set to “0”, the EP0_FIFO Data Register is set to 16-bit mode, and all bits of the EP0_FIFO

Data Register are valid.

When this bit is set to “1”, the EP0_FIFO Data Register is set to 8-bit mode, and the upper-order 8 bits of the

EP0_FIFO Data Register (b15 to b8) are invalid.

Set this bit before receiving the data.

When set to control write transfer (ISEL bit = “0”), change this bit before receiving the data. When set to

control read transfer (ISEL bit = “1”), if the E0req bit indicates “1”, do not change this bit.

This bit becomes invalid (fixed to 8-bit mode) when the mode is set to 8-bit by *HWR/*BYTE pin.

In such case, this bit is read “0”.

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(3) BSWP (Byte Swap Mode) Bit (b7)

This bit sets the endian of the EP0_FIFO Data Register.

When this bit is set to “0”, the EP0_FIFO Data Register gets such as little endian.

When this bit is set to “1”, the EP0_FIFO Data Register gets such as big endian.

b15~b8 b7~b0

Little Endian odd number address even number address

Big Endian even number address odd number address

Note: Don’t set this bit to “1” when the mode is set to 8-bit (set by the Octl bit or *HWR/*BYTE pin).

(4) ISEL (Buffer Select) Bit (b0)

This bit selects the buffer transfer direction of the endpoint 0 used in the control transfer.

When “0” is written to this bit, the buffer for control write transfer is valid.

When “1” is written to this bit, the buffer for control read transfer is valid.

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2.24 EP0_FIFO Control Register

Q EP0_FIFO Control Register (EP0_FIFO_CONTROL) <Address : H’32>

b151413121110987654321b0

EP0_PID IVAL BCLR E0req CCPL ODLN

0000100000000000

----------------

b Bit name Function R W

15~14 EP0_PID

Response PID 00 : NAK

01 : BUF

(Transmits response PID/data according to the state of

buffer etc,)

1x : STALL

{{

13 IVAL

IN Buffer Set/OUT Buffer Status <When set to control write transfer>

Q Read

0: Disables the reading of data from the buffer

1: Enables the reading of data from the buffer

Q Write

Invalid (Ignored when written)

Q Read

0 : Incomplete to write the data to buffer

1 : Complete to write the data to buffer

Q Write

0 : Invalid (Ignored when written)

1 : Complete to write the data to buffer

(Forced completion : Transmits the short packet)

{{

12 BCLR

Buffer Clear <When set to control write transfer >

Q Write

0 : Invalid (Ignored when written)

1 : Buffer clear (When the IVAL bit is set to "1")

Q Write

0 : Invalid (Ignored when written)

1 : Buffer clear (Note : When the IVAL bit is set to “1”,

make sure to set the EP0_PID bits to “00” before

executing the aforesaid operatio ns.)

11 E0req

EP0_FIFO Ready 0 : Enables to access EP0_FIFO Data Register etc,

1 : Disables to access EP0_FIFO Data Register etc,

{×

10 CCPL

Control Transfer Control 0 : NAK response at status stage

1 : Normal completion response at status stage

(ACK response/zero-length packet transmit)

{{

9 Reserved. Set it to “0”. 00

8~0 ODLN

Control Write Receive Data Length Stores the receive data length in control write transfer {×

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(1) EP0_PID (Response PID) Bits (b15~b14)

These bits set the PID for response to the host at data/status stage of the control transfer.

At setup stage, the ACK response is executed irrespective of these bits.

Writing these bits are ignored when the VALID bit is equal to“1”.

When these bits are set to “00”

• Data stage : NAK response

• Status stage : NAK response

When these bits are set to “01”

• Data stage : ACK response after receiving the data if the SIE side buffer can be ready to

receive

: NAK response if the SIE side buffer is not ready to receive

In case the SIE side buffer is not ready to receive, the EPB_NRD bit is

set to “1” when OUT token is received.

•Status stage : Depends on CCPL bit

• Data stage : Transmits the data if the SIE side buffer is not ready to transmit

: NAK response if the SIE side buffer is not ready to transmit

In case the SIE side buffer is not ready to transmit, the EPB_NRD bit is

set to “1” when IN token is received.

•Status stage : Depends on CCPL bit

When these bits are set to “1x”

• Data stage : STALL response

In case the SIE side buffer is not ready to receive/transmit, the

EPB_NRD bit is set to “1” when OUT token is received.

• Status stage : STALL response

The NAK response is not executed even if these bits are set to “00” when the data is being received at data

stage. The settings of these bits are reflected from the next transaction.

Similarly, the transmission is not interrupted even if these bits are set to “00” when the data is being

transmitted at data stage.

Further, these bits are automatically set to the values below when the following states occur:

z When setup token is received

• "00" (NAK)

z When the request set to automatic response (SET_ADDRESS or SET_CONFIGURATION) is received

• "01" (BUF)

The CCPL bit also is automatically set to “1” and transmits the zero-length packet at the succeeding

status stage (IN transaction).

z When sequence error occurs (CTSQ bits are set to “110”)

• "1x" (STALL)

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(2) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)

This bit indicates valid value when the E0req bit of this register is set to “0”.

zWhen set to control write transfer (ISEL bit = “0”)

When this bit is set to “1”, the buffer is at CPU side and can be read.

This bit is set to “1” at completion of receiving data.

The conditions of receive completion depend on the CTRW bit.

When this bit is set to “1”, the EPB_RDY bit is set to “1” (buffer ready interrupt occurs).

This bit is cleared to “0” due to one of the reasons as follows:

•Reads out all the data received in the CPU side buffer.

•Writes “1” to the BCLR bit.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

zWhen set to control read transfer (ISEL bit = “1”)

When this bit is set to “0”, the buffer is at CPU side and can be written.

This bit is cleared to “0” due to one of the reasons as follows:

•Transmits completely SIE side buffer.

•Writes “1” to the BCLR bit.

The transmit completion is changed by the CTRR bit.

When this bit is set to “0” if the EPB_EMPE bit is set to “1”, the EPB_EMP_OVR bit is set to “1” (buffer

empty/size over error interrupt occurs).

This bit is set to “1” due to one of the reasons as follows:

•Completely writes the transmit data to CPU side buffer.

•Writes “1” to this bit.

When “1” is written to this bit, the write is forcibly completed. When some written data exists

in the buffer, that data is transmitted as the short packet. Here, if the buffer is empty or

cleared, the zero-length packet is transmitted. The buffer can be cleared using the BCLR bit.

Further, the zero-length packet can be transmitted by writing “1” simultaneously to this bit

and to the BCLR bit. In this case the buffer is cleared by setting “1” to BCLR bit, and this bit

is cleared to “0” after the zero-length packet is transmitted.

The write completion also is changed by the CTRR bit.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

(3) BCLR (Buffer Clear) Bit (b12)

This bit clears the data written to the CPU side buffer.

zWhen set to control write transfer (ISEL bit = “0”)

When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:

•Clears CPU side buffer.

•Clears the IVAL bit of this register.

•Clears the ODLN bits of this register.

zWhen set to control read transfer (ISEL bit = “1”)

When the IVAL bit is set to “0”, the following operations are executed by writing “1” to this bit:

•Clears CPU side buffer.

Further, the zero-length packet can be transmitted by writing “1” simultaneously to this bit and to the

IVAL bit. For details, refer to “IVAL bit”.

When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:

•Clears SIE side buffer (Unlike the other endpoints, the SIE side buffer can also be cleared by

this bit).

•Clears the IVAL bit of this register.

Note: When the IVAL bit is set to “1”, make sure to set the EP0_PID bits to “00” before executing the aforesaid

operations.

This bit automatically returns to “0” after the buffer is cleared.

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Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

Note: In case the transmit data exists in the buffer for EP0_FIFO, the buffer empty interrupt occurs in the concerned

endpoint when “1” is written to the BCLR bit.

(4) E0req (EP0_FIFO Ready) Bit (b11)

When this bit is equal to “1”, this bit indicates the states as follows:

•EP0_FIFO Data Register can not be accessed.

•The IVAL bit value of this register is invalid.

•The ODLN bit values of this register are invalid.

Make sure that this bit is equal to “0” before accessing the aforesaid registers/bits.

(5) CCPL (Control Transfer Control) Bit (b10)

This bit controls the status stage of the control transfer.

When this bit is set to “1”, the operations below are executed at status stage of the control transfer and notifies

the normal completion of the control transfer:

zWhen set to control write transfer (ISEL bit = “0”)

•Transmits the zero-length packet after receiving IN token if the EP0_PID bits are set to “01”.

zWhen set to control read transfer (ISEL bit = “1”)

•ACK response to the host after receiving the zero-length packet following OUT token if the

EP0_PID bits are set to “01”.

When this bit is set to “0”, NAK response is executed to the host after receiving the IN token/OUT token at

status stage of the control transfer.

This bit is automatically cleared to “0” by receiving the setup token.

(6) ODLN (Control Write Receive Data Length) Bits (b8~b0)

These bits are valid for control write transfer and indicate the data number (byte count) received from the

CPU side buffer.

Further, these bits are set to execute countdown when the EP0_FIFO Data Register is read out. This

operation changes according to the RCNT bit. For details, refer to “RCNT bit”.

These bits indicate the valid value when the E0req bit of this register is equal to “0”.

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2.25 EP0_FIFO Data Register

Q EP0_FIFO Data Register (EP0_FIFO_DATA) <Address : H’34>

b151413121110987654321b0

EP0_FIFO

????????????????

----------------

b Bit name Function R W

15~0 EP0_FIFO

EP0_FIFO Data <When set to control write transfer>

Q Read

Reads receive data

Q Write

Writes transmit data

{{

Note:The upper 8 bits (b15 to b8) become invalid in the 8-bit-mode (using the Octl bit of the EP0_FIFO Select Register or

*HWR/*BYTE pin).

(1) EP0_FIFO (EP0_FIFO Data) Bits (b15~b0)

The receive data from the CPU side buffer is read or the transmit data to the CPU side buffer is written

through this register.

When set to control write transfer (ISEL bit = “0”), the receive data from the buffer is read through this

When set to control read transfer (ISEL bit = “1”), the transmit data to the buffer is written through this

Make sure that the E0req bit is set to “0” before reading/writing these bits.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

M66291GP/HP

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2.26 EP0 Continuous Transmit Data Length Register

Q EP0 Continuous Transmit Data Length Register (EP0_SEND_LEN) <Address : H’36>

b151413121110987654321b0

SDLN

0000000000000000

----------------

b Bit name Function R W

15~9 Reserved. Set it to “0”. 00

8~0 SDLN

Control Read Continuous Transmit Data Lengt

Control read continuous transmit data length {{

(1) SDLN (Control Read Continuous Transmit Data Length) Bits (b8~b0)

These bits are valid when the EP0 is set to continuous transmit mode (CTRR bit = “1”) at the time of control

read transfer (ISEL bit = “1”).

These bits set the total byte count of the data transmitted (over multiple transactions) during data stage of

control read transfer.

These bits can be set to maximum 256 bytes. When total byte count exceeds 256, set the 256 bytes and the

excess byte in several cycles.

When the integral multiples of the value set by the EP0 Packet Size Register is set to these bits, the zero-

length packet is automatically added after all data are transmitted. The zero-length packet is not

automatically added if the SDLN are set to 256 to transmit 256 bytes data or more.

Write to the buffer after setting this bit. Set these bits before writing to the buffer.

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2.27 CPU_FIFO Select Register

Q CPU_FIFO Select Register (CPU_FIFO_SELECT) <Address : H’40>

b151413121110987654321b0

RCNT RWND BSWP Octl CPU_EP

0000000000000000

----------------

b Bit name Function R W

15 RCNT

Read Count Mode 0: The CPU_DTLN bits are cleared by reading all receive

data

1: The CPU_DTLN bits are counted down by reading receive

data

{{

14~13 Reserved. Set it to “0”. 00

12 RWND

Buffer Rewind <When set to OUT buffer>

Q Write

0 : Invalid (Ignored when written)

1 : Clears the buffer reading pointer

Q Write

0 : Invalid (Ignored when written)

1 : Clears the buffer writing pointer

11~8 Reserved. Set it to “0”. 00

7 BSWP

Byte Swap Mode 0 : Byte is treated as little ENDIAN

1 : Byte is treated as big ENDIAN

{{

6Octl

1 : CPU_FIFO Data Register is 8-bit mode

{{

5~4 Reserved. Set it to “0”. 00

3~0 CPU_EP

CPU Access Endpoint Designate 0001 :EP1 (Endpoint 1)

0010 :EP2 (Endpoint 2)

0011 :EP3 (Endpoint 3)

0100 :EP4 (Endpoint 4)

0101 :EP5 (Endpoint 5)

0110 :EP6 (Endpoint 6)

Other than those above : Invalid

{{

(1) RCNT (Read Count Mode) Bit (b15)

This bit sets the countdown methods of the CPU_DTLN bits at the time of reading the CPU_FIFO Data

When this bit is set to “0”, the CPU_DTLN bit value does not change in spite of reading the data from the

CPU_FIFO Data Register, and is cleared to H’0 when all data is read out.

When this bit is set to “1”, the CPU_DTLN bit values are counted down every time the data is read from the

CPU_FIFO Data Register. Here, the down-count value differs as shown below depending on whether the

CPU_FIFO Data Register is set to 8-bit mode or 16-bit mode:

•8-bit mode : Down-count per “-1”

•16-bit mode : Down-count per “-2”

Note : Use the *HWR/*BYTE pin or the Octl bit of this register for setting the 8-bit/16-bit mode.

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(2) RWND (Buffer Rewind) Bit (b12)

This bit rewinds (initializes) the buffer pointer.

zWhen set to OUT buffer (EPi_DIR bit = “0”)

When the IVAL bit of the CPU_FIFO Control Register is set to “1”, the buffer reading pointer can be

initialized by writing “1” to this bit. This enables reading of the receive data from the beginning.

zWhen set to IN buffer (EPi_DIR bit = “1”)

When the IVAL bit of the CPU_FIFO Control Register is set to “0”, the buffer writing pointer can be

initialized by writing “1” to this bit. This enables resetting of the transmit data from the beginning.

The operation is equivalent to the case when “1” is set to the BCLR bit if set to IN buffer.

(3) BSWP (Byte Swap Mode) Bit (b7)

This bit sets the endian of the CPU_FIFO Data Register.

When this bit is set to “0”, the CPU_FIFO Data Register gets such as little endian.

When this bit is set to “1”, the CPU_FIFO Data Register gets such as big endian.

b15~b8 b7~b0

Little Endian odd number address even number address

Big Endian even number address odd number address

Note: Do not set this bit to “1” when the mode is set to 8-bit (set by the Octl bit or *HWR/*BYTE pin).

(4) Octl (Register 8-Bit Mode) Bit (b6)

This bit sets the access mode of the CPU_FIFO Data Register.

When this bit is set to “0”, the CPU_FIFO Data Register is set to 16-bit mode, and all bits of the CPU_FIFO

Data Register are valid.

When this bit is set to “1”, the CPU_FIFO Data Register is set to 8-bit mode, and the upper-order 8 bits of the

CPU_FIFO Data Register (b15 to b8) are invalid.

When set to OUT buffer (EPi_DIR bit = “0”), change this bit before receiving the data. When set to IN buffer

(EPi_DIR bit = “1”), if the Creq bit is equal to “1”, do not change this bit.

This bit becomes invalid (fixed to 8-bit mode) when the mode is set to 8-bit by *HWR/*BYTE pin.

In such case, this bit is read “0”.

Note: The access width of the CPU_FIFO Data Register is controlled by the logical sum of this bit and the EPi_Octl

bits of the EPi Configuration Register 1 specified by the CPU_EP b i ts. Hence, the mode is set to 8-bit if “1” is

set to either this bit or to the EPi_Octl bits of the EPi Configuration Register 1. Make sure that both bits must be

set to “0” to change to 16-bit mode.

(5) CPU_EP (CPU Access Endpoint Designate) Bits (b3~b0)

These bits select the endpoint accessed by CPU.

Make sure that the endpoint selection does not get overlapped with the selection by the DMA_EP bits.

When making a change in these bits to select the other the endpoint, make sure that the source endpoint and

the destination endpoint to be changed are not under the access by the CPU or during receiving/transmitting

of SIE (under access to FIFO buffer).

M66291GP/HP

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2.28 CPU_FIFO Control Register

Q CPU_FIFO Control Register (CPU_FIFO_CONTROL) <Address : H’42>

b151413121110987654321b0

IDLY IVAL BCLR Creq CPU_DTLN

0000100000000000

----------------

b Bit name Function R W

15 Reserved. Set it to “0”. 00

14 IDLY

Isochronous Transmit Delay Set 0 : Disable of IDLY function

1 : Enable of IDLY function

{{

13 IVAL

IN Buffer Set/OUT Buffer Status <When set to OUT buffer>

Q Read

0: Disables reading data from the buffer

1: Enables reading data from the buffer

Q Write

Invalid (Ignored when written)

Q Read

0 : Incomplete to write the data to buffer

1 : Complete to write the data to buffer

Q Write

0 : Invalid (Ignored when written)

1 : Complete to write the data to buffer

(Forced completion : Transmits short packet)

{{

12 BCLR

Buffer Clear <When set to OUT buffer>

Q Write

0 : Invalid (Ignored when written)

1 : Buffer clear (When the IVAL bit is set to "1")

Q Write

0 : Invalid (Ignored when written)

1 : Buffer clear (When the IVAL bit is set to "0")

11 Creq

CPU_FIFO Ready 0 : Enables accessing CPU_FIFO Data Register etc,

1 : Disables accessing CPU_FIFO Data Register etc,

{×

10~0 CPU_DTLN

CPU_FIFO Receive Data Length Register Stores the receive data length (byte count) {×

M66291GP/HP

Rev1.01 2004.11.01 page 57 of 122

(1) IDLY (Isochronous Transmit Delay Set) Bit (b14)

In isochronous transfer, transmission can be started by writing “1” to this bit or to the IVAL bit after writing

the transmit data to the buffer (Note).

When “1” is written to this bit, the data is transmitted by receiving the IN token after confirming the received

SOF packet. After the data transmit starts, this is cleared to “0” (Refer to Figure 2.11).

When “1” is written to the IVAL bit of this register, the data is transmitted by receiving the next IN token

(Refer to Figure 2.12).

Note: Set the transmit data size + 1 byte or more to the EPi_MXPS bits. When set to transmit data size, the IVAL bit is

set to “1” when the writing to the buffer completes. Hence, this function is not applicable when set to 1023

bytes, the maximum value of the EPi_MXPS bits.

F lame # m

SOF

Flame #(m+1)

ID L Y = " 1" set

SOF IN

Transmit start

z z zz z z

z z zz z zz z z

Figure 2.11 Transmit start timing at IDLY bit = “1”

F lame # m

SOF IN

IVAL="1" set Transmit start

z z zz z zz z z

Figure 2.12 Transmit start timing at IVAL bit = “1”

(2) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)

This bit indicates valid value when the Creq bit of this register is equal to “0”.

This bit sets/clears the EPB_RDY bit to “1” (Refer to “EPB_RDY bit”).

zWhen set to OUT buffer (EPi_DIR bit = “0”)

When this bit is set to “1”, the receive data in the CPU side buffer is ready to be read.

This bit is set to “1” due to one of the reasons as follows:

{When set to single buffer mode (EPi_DBLB bit = “0”)

•Completes receiving (SIE side buffer).

•Writes “1” to the TGL bit.

{When set to double buffer mode (EPi_DBLB bit = “1”)

•Completes receiving of SIE side buffer and reading of CPU side buffer.

•Writes “1” to the TGL bit.

The receive completion is changed by the EPi_RWMD bit.

This bit is cleared to “0” due to one of the reasons as follows:

•Reads out all the receive data in the CPU side buffer.

•Writes “1” to the BCLR bit.

•Writes “1” to the ACLR bit.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

M66291GP/HP

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zWhen set to IN buffer (EPi_DIR bit = “1”)

When this bit is set to “0”, the CPU side buffer is ready to write the transmit data.

This bit is cleared to “0” due to one of the reasons as follows:

{When set to single buffer mode (EPi_DBLB bit = “0”)

•Completes transmitting of SIE side buffer.

•Writes “1” to the SCLR bit.

•Writes “1” to the ACLR bit.

{When set to double buffer mode (EPi_DBLB bit = “1”)

•Completes transmitting of SIE side buffer and writing of CPU side buffer.

•Writes “1” to the SCLR bit.

•Writes “1” to the ACLR bit.

•Writes “1” to the BCLR bit.

The transmit completion is changed by the EPi_RWMD bit.

This bit is set to “1” due to one of the reasons as follows:

•Completes writing the transmit data to CPU side buffer.

•Writes “1” to this bit.

When “1” is written to this bit, the write operation is forcibly completed. When some written

data exists in the buffer, that data is solely transmitted as the short packet. Here, if the

buffer is empty or cleared, the zero-length packet is transmitted. The buffer can be cleared

using the BCLR bit. Further, the zero-length packet can be transmitted by writing “1”

simultaneously to this bit and to the BCLR bit. In this case the buffer is cleared by setting “1”

to BCLR bit, and this bit is cleared to “0” after the zero-length packet is transmitted.

The write completion also is changed by the EPi_RWMD bit.

(3) BCLR (Buffer Clear) Bit (b12)

This bit clears the data written to the CPU side buffer.

zWhen set to OUT buffer (EPi_DIR bit = “0”)

When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:

•Clears CPU side buffer.

•Clears the IVAL bit of this register.

•Clears the CPU_DTLN bits of this register.

zWhen set to IN buffer (EPi_DIR bit = “1”)

When the IVAL bit is set to “0”, the following operations are executed by writing “1” to this bit:

•Clears CPU side buffer.

Further, the zero-length packet can be transmitted by writing “1” simultaneously to this bit and to the

IVAL bit. For details, refer to “IVAL bit”.

This bit automatically returns to “0” after the buffer is cleared.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

(4) Creq (CPU_FIFO Ready) Bit (b11)

When this bit is equal to “1”, this bit indicates the states as follows:

•CPU_FIFO Data Register can not be accessed.

•The IVAL bit value of this register is invalid.

•The CPU_DTLN bit values of this register are invalid.

Make sure that this bit is equal to “0” before accessing the aforesaid registers/bits.

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(5) CPU_DTLN (CPU_FIFO Receive Data Length Register) Bits (b10~b0)

These bits are valid against the endpoint set to the OUT buffer (EPi_DIR bit = “0”) and indicates the receive

data number (byte count) in the CPU side buffer.

Further, these bits are set to execute countdown when the CPU_FIFO Data Register is read out. This

operation changes according to the RCNT bit of the CPU_FIFO Select Register. For details, refer to “RCNT

bit”.

These bits indicate the valid value when the Creq bit of this register is equal to “0”.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

M66291GP/HP

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2.29 CPU_FIFO Data Register

Q CPU_FIFO Data Register (CPU_FIFO_DATA) <Address : H’44>

b151413121110987654321b0

CPU_FIFO

????????????????

----------------

b Bit name Function R W

15~0 CPU_FIFO

CPU_FIFO Data <When set to OUT buffer>

Q Read

Reads receive data

Q Write

Writes transmit data

{{

Note:The upper 8 bits (b15 to b8) become invalid in the 8-bit mode (using the Octl bits or *HWR/*BYTE pin).

(1) CPU_FIFO(CPU_FIFO Data) Bits (b15~b0)

The receive data from the CPU side buffer is read or the transmit data to the CPU side buffer is written

through this register.

When set to OUT buffer (EPi_DIR bit = “0”), the receive data from the CPU side buffer is read through this

When set to IN buffer (EPi_DIR bit = “1”), the transmit data to the CPU side buffer is written through this

Make sure that the Creq bit is equal to “0” before reading/writing these bits.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

Note: When set to 16-bit mode, the M66291 is capable of recognizing the byte data written. Henc e, it is possible to

transmit the odd b yte data by setting “1” to the IVAL bit after writing the byte data.

M66291GP/HP

Rev1.01 2004.11.01 page 61 of 122

2.30 SIE_FIFO Status Register

Q SIE_FIFO Status Register (SIE_FIFO_STATUS) <Address : H’46>

b151413121110987654321b0

TGL SCLR Sreq SIE_DTLN

0000000000000000

----------------

b Bit name Function R W

15~14 Reserved. Set it to “0”. 00

13 TGL

Buffer Toggle <When set to OUT buffer>

Q Write

0 : Invalid (Ignored when written)

1 : Forces the buffer to toggle in receive ready state to read

ready state

Q Write

0 : Invalid (Ignored when written)

1 : Inhibited

12 SCLR

Buffer Clear <When set to OUT buffer>

Q Write

0 : Invalid

1 : Inhibited

0 : Invalid (Ignored when written)

1 : Clears the buffer in transmit ready state

11 Sreq

SIE_FIFO Ready 0 : Enables to be write to TGL bit/SCLR bit

1 : Disables to be write to TGL bit/SCLR bit

{×

10~0 SIE_DTLN

SIE_FIFO Receive Data Length Receive data length of SIE internal FIFO {×

This register is valid against the endpoint set by the CPU_EP bits.

(1) TGL (Buffer Toggle) Bit (b13)

This bit is valid against the endpoint set to the OUT buffer (EPi_DIR bit = “0”) and is used for continuous

transmit/receive mode (EPi_RWMD = “1”). Do not write “1” when set to the IN buffer (EPi_DIR bit = “1”)

When “1” is written to this bit, the SIE side buffer is forced to complete receiving. The buffer is toggled,

irrespective of the presence/absence of the CPU side buffer data (causing the SIE side buffer to complete

receiving and to get toggled, and the IVAL bit to set to “1”). Make sure that the buffer data in the CPU side are

not cleared.

Here, the EPB_RDY bit also is set to “1” (buffer ready interrupt occurs).

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

Note: Make sure that the response PID is set to NAK (EPi_PID bits = “00”) and the Sreq bit to “0” before writing “1” to

this bit.

M66291GP/HP

Rev1.01 2004.11.01 page 62 of 122

(2) SCLR (Buffer Clear) Bit (b12)

This bit is valid against the endpoint set to the IN buffer (EPi_DIR bit = “1”). Do not write “1” when set to the

OUT buffer (EPi_DIR bit = “0”)

The SIE side buffer is cleared by writing “1” to this bit.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

Note: Make sure that the response PID is set to NAK (EPi_PID bits = “00”) and the Sreq bit to “0” before writing “1” to

this bit.

(3) Sreq (SIE_FIFO Ready) Bit (b11)

This bit indicates to enable/disable of writing to the TGL bit and SCLR bit.

When this bit is set to “1”, do not write to the TGL bit and SCLR bit.

(4) SIE_DTLN (SIE_FIFO Receive Data Length) Bits (b10~b0)

These bits are valid against the endpoint set to the OUT buffer (EPi_DIR bit = “0”) and indicates the receive

data number (byte count) in the SIE side buffer (renewed after every ACK transmit).

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

M66291GP/HP

Rev1.01 2004.11.01 page 63 of 122

2.31 Dn_FIFO Select Registers (n=0~1)

Q D0_FIFO Select Register (D0_FIFO_SELECT) <Address : H’48>

Q D1_FIFO Select Register (D1_FIFO_SELECT) <Address : H’50>

b151413121110987654321b0

BUST DFORM RWND ACKA REQA INTM DMAEN BSWP Octl DMA_EP

0000000000000000

----------------

b Bit name Function R W

15 BUST

Burst Mode 0 : Cycle Steal Transfer

1 : Burst Transfe r

{{

13~14 DFORM

Transfer Method 00 : Controls by DACK signal and read/write sig nal

01 : Controls by DACK signal only

10 : Controls by chip select/address signal and read/w rite signal

11 : Reserved

{{

12 RWND

Buffer Rewind <When set to OUT buffer>

Q Write

0 : Invalid (Ignored when written)

1 : Clears the buffer reading pointer

Q Write

0 : Invalid (Ignored when written)

1 : Clears the buffer writing pointer

11 ACKA

DACK Polarity 0 : "L" active

1 : "H" active

{{

10 REQA

DREQ Polarity 0 : "L" active

1 : "H" active

{{

9INTM

DMA Interrupt Mode 0 : Sets “1” to EPB_RDY bit by completion of DMA transfer

1 : Sets “1” to EPB_RDY bit by completion of receiving

{{

8 DMAEN

DMA Enable 0 : Disable DMA transfer

1 : Enable DMA transfer (assertion of DREQ signal)

{{

7 BSWP

Byte Swap Mode 0 : Byte is treated as little ENDIAN

1 : Byte is treated as big ENDIAN

{{

6Octl

1 : Dn_FIFO Data Register is 8-bit mode

{{

5~4 Reserved. Set it to “0”. 00

3~0 DMA_EP

DMA Transfer Endpoint Designate 0001 :EP1 (Endpoint 1)

0010 :EP2 (Endpoint 2)

0011 :EP3 (Endpoint 3)

0100 :EP4 (Endpoint 4)

0101 :EP5 (Endpoint 5)

0110 :EP6 (Endpoint 6)

Other than those above : Invalid

{{

M66291GP/HP

Rev1.01 2004.11.01 page 64 of 122

(1) BUST (Burst Mode) Bit (b15)

When set to cycle steal transfer, the assertion and negation of the DREQ signal are repeated every time the

signal is subjected to DMA transfer (8-bit or 16-bit) when the CPU side buffer can be accessed. The negation is

executed when the Dn_FIFO Data Register is accessed.

When set to burst transfer, it keeps on asserting the DREQ signal until the reading/writing of the CPU side

buffer completes when the CPU side buffer can be accessed.

It is possible to forcibly complete the writing and then enabling transmit of short packet by asserting the TC

signal at the time of writing.

(2) DFORM (Transfer Method) Bit (b14~b13)

These bits select the DMA transfer method.

zWhen set to “00”

At the time of reading, the data of the Dn_FIFO Data Register is available while the DACK signal is at

“L” and the read signal at “L”.

At the time of writing, the data is written to the Dn_FIFO Data Register when the DACK signal is at

“L” and by the rising edge of write signal.

zWhen set to “01”

Only the DACK signal is used and the Read/Write signal is not used (the Read/Write signal is ignored).

At the time of reading, the data of the Dn_FIFO Data Register is available while the DACK signal is at

“L”.

At the time of writing, the data is written to the Dn_FIFO Data Register by the rising edge of DACK

signal.

zWhen set to “10”

In place of the DACK signal (the DACK signal is ignored here), the address signal can be used to

read/write the data of the Dn_FIFO Data Register.

At the time of reading, the data of the Dn_FIFO Data Register is available when the read signal is at

“L”.

At the time of writing, the data is written to the Dn_FIFO Data Register by the rising edge of write.

When the endpoint set to the OUT buffer (EPi_DIR bit = “0”) is assigned to the DMA_EP, writing operation to

the Dn_FIFO Data Register is ignored.

Similarly, when the endpoint set to the IN buffer (EPi_DIR bit = “1”) is assigned to the DMA_EP, reading

operation to the Dn_FIFO Data Register is ignored (undefined value is read).

(3) RWND (Buffer Rewind) Bit (b12)

This bit rewinds (clears) the buffer pointer.

zWhen set to OUT buffer (EPi_DIR bit = “0”)

When the IVAL bit of the Dn_FIFO Control Register is set to “1”, the buffer reading pointer can be

cleared by writing “1” to this bit. This enables reading of the receive data from the beginning.

zWhen set to IN buffer (EPi_DIR bit = “1”)

When the IVAL bit of the Dn_FIFO Control Register is set to “0”, the buffer writing pointer can be

cleared by writing “1” to this bit. This enables resetting of the transmit data from the beginning.

(4) ACKA (DACK Polarity) Bit (b11)

This bit sets the DACK signal polarity.

(5) REQA (DREQ Polarity) Bit (b10)

This bit sets the DREQ signal polarity.

M66291GP/HP

Rev1.01 2004.11.01 page 65 of 122

(6) INTM (DMA Interrupt Mode) Bit (b9)

This bit sets the timing of setting “1” to the EPB_RDY bit.

When this bit is set to “0”, the EPB_RDY bit is set to “1” after reading all buffer data including the

received short packet (including the zero-length packet) <buffer ready interrupt occurs>.

In case of reading the buffer, the buffer state as well as the bits below are retained. This enables the

reading of the received data length using the buffer ready interrupt.

•IVAL bit of the Dn_FIFO Control Register (“1” retained)

•DMA_DTLN bits of the Dn_FIFO Control Register

It is necessary to write “1” to the BCLR bit and to clean the buffer in order to receive the next data.

Thus clears the IVAL bit to “0”, and the EPB_RDY bits also are cleared if the RDYM bit is set to “0”. If

the RDYM bit is set to “1”, the EPB_RDY bits are cleared to “0” by writing “0” to the EPB_RDY bit.

When this bit is set to “1”, the EPB_RDY bit is set to “1” under the same conditions as the endpoint not

specified by the DMA_EP bits (buffer ready interrupt occurs).

When this bit is set to “0”, the EPB_RDY bit cannot be set to “1”.

When this bit is set to “1”, the EPB_RDY bit is set to “1” under the same conditions as the endpoint not

specified by the DMA_EP bits (buffer ready interrupt occurs).

Note: Do not use with DMAEN = “0” when this bit is set to “0”.

(7) DMAEN (DMA Enable) Bit (b8)

This bit sets the enable/disable of the output of the DREQ signal for DMA transfer.

When this bit is set to “1”, the DMA transfer is set to enable mode, making the DREQ signal ready for

assertion.

When this bit is written to “0”, the DMA transfer is disabled, allowing no output of DREQ signal.

Note: Do not use with INTM = “0” when this bit is set to “0”.

(8) BSWP (Byte Swap Mode) Bit (b7)

This bit sets the endian of the Dn_FIFO Data Register.

When this bit is set to “0”, the Dn_FIFO Data Register gets such as little endian.

When this bit is set to “1”, the Dn_FIFO Data Register gets such as big endian.

b15~b8 b7~b0

Little Endian odd number address even number address

Big Endian even number address odd number address

Note: Don’t set this bit to “1” when the mode is set to 8-bit (set by the Octl bit or *HWR/*BYTE pin).

M66291GP/HP

Rev1.01 2004.11.01 page 66 of 122

(9) Octl (Register 8-Bit Mode) Bit (b6)

This bit sets the access mode of the Dn_FIFO Data Register.

When this bit is set to “0”, the Dn_FIFO Data Register is set to 16-bit mode, and all bits of the Dn_FIFO Data

When this bit is set to “1”, the Dn_FIFO Data Register is set to 8-bit mode, and the upper-order 8 bits of the

Dn_FIFO Data Register (b15 to b8) are invalid.

When set to OUT buffer (EPi_DIR bit = “0”), change this bit before receiving the data. When set to IN buffer

(EPi_DIR bit = “1”), if the Dreq bit is equal to “1”, do not change this bit.

This bit becomes invalid (fixed to 8-bit mode) when the mode is set to 8-bit by *HWR/*BYTE pin.

In such case, this bit is read “0”.

Note: The access width of the Dn_FIFO Data Register is controlled by the logical sum of this bit and the EPi_Octl bits

of the EPi Configuration Register 1 specified by the DMA_EP bits. Hence, the mode is set to 8-bit if “1” is set to

either this bit or to the EPi_Octl bits of the EPi Configuration Register 1. Make sure that both bits must be set to

“0” to change to 16-bit mode.

Note: Do not change this bit while accessing the Dn_FIFO Data Register.

(10) DMA_EP (DMA Transfer Endpoint Designate) Bits (b3~b0)

These bits select the endpoint of DMA transfer.

Make sure that the endpoint selection does not get overlapped with the selection by the CPU_EP bits.

When making a change in these bits to select the other endpoint, make sure that the source endpoint and the

destination endpoint to be changed are not under the access by the CPU/DMA or during

receiving/transmitting of SIE (under access to FIFO buffer).

M66291GP/HP

Rev1.01 2004.11.01 page 67 of 122

2.32 Dn_FIFO Control Registers (n=0~1)

Q D0_FIFO Control Register (D0_FIFO_CONTROL) <Address : H’4A>

Q D1_FIFO Control Register (D1_FIFO_CONTROL) <Address : H’52>

b151413121110987654321b0

TRCLR TREN IVAL BCLR Dreq DMA_DTLN

0000100000000000

----------------

b Bit name Function R W

15 TRCLR

Transaction Count Clear

Q Write

0 : Invalid (Ignored when written)

1 : Clears the DMAn_Transaction Count Register

14 TREN

Transaction Count Enable 0 : Disable of transaction count function

1 : Enable of transaction count function

{{

13 IVAL

IN Buffer Set/OUT Buffer Status <When set to OUT buffer>

Q Read

0: Disables the reading of data from the buffer

1: Enables the reading of data from the buffer

Q Write

Invalid (Ignored when written)

Q Read

0 : Incomplete to write the data to buffer

1 : Complete to write the data to buffer

Q Write

0 : Invalid (Ignored when written)

1 : Complete to write the data to buffer

(Forced completion : Transmits short packet)

{{

12 BCLR

Buffer Clear <When set to OUT buffer>

Q Write

0 : Invalid (Ignored when written)

1 : Buffer clear (When the IVAL bit is set to "1")

Q Write

0 : Invalid (Ignored when written)

1 : Buffer clear

11 Dreq

D_FIFO Ready 0 : Enables to access Dn_FIFO Data Register

1 : Disables to access Dn_FIFO Data Register

{×

10~0 DMA_DTLN

D_FIFO Receive Data Length Register Stores the receive data length (byte count) {×

(1) TRCLR (Transaction Count Clear) Bit (b15)

When written to “1”, this bit clears the value of the DMAn_Transaction Count Register.

The writing of “1” to this bit is not retained and is automatically cleared to “0”.

(2) TREN (Transaction Count Enable) Bit (b14)

This bit sets the enable/disable of transaction count function.

Refer to “2.34 DMAn_Transaction Count Registers (n=0~1)”.

M66291GP/HP

Rev1.01 2004.11.01 page 68 of 122

(3) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)

This bit indicates valid value when the Dreq bit of this register is equal to “0”.

The operation of this bit is the same as that of the IVAL bit of the CPU_FIFO Control Register.

Take care the setting of the EPB_RDY bit to “1” using this bit (buffer ready interrupt occurs) changes

according to the INTM bit (Refer to “EPB_RDY/INTM bit”).

(4) BCLR (Buffer Clear) Bit (b12)

This bit indicates valid value when the Dreq bit of this register is set to “0”.

The operation of this bit is the same as that of the BCLR bit of the CPU_FIFO Control Register.

(5) Dreq (D_FIFO Ready) Bit (b11)

When this bit is equal to “1”, this bit indicates the states as follows:

•Dn_FIFO Data Register can not be accessed.

•The IVAL bit value of this register is invalid.

•The DMA_DTLN bit values of this register are invalid.

Make sure that this bit is equal to “0” before making access to the aforesaid registers/bits.

(6) DMA_DTLN (D_FIFO Receive Data Length Reg ister) Bits (b10~b0)

These bits are valid against the endpoint set to the OUT buffer (EPi_DIR bit = “0”) and indicates the receive

data number (byte count) in the CPU side buffer.

These bits indicate the valid value when the Dreq bit of this register is equal to “0”.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

M66291GP/HP

Rev1.01 2004.11.01 page 69 of 122

2.33 Dn_FIFO Data Registers (n=0~1)

Q D0_FIFO Data Register (D0_FIFO_DATA) <Address : H’4C>

Q D1_FIFO Data Register (D1_FIFO_DATA) <Address : H’54>

b151413121110987654321b0

D_FIFO

????????????????

----------------

b Bit name Function R W

15~0 D_FIFO

D_FIFO Data <When set to OUT buffer>

Q Read

Reads receive data

Q Write

Writes transmit data

{{

Note:The upper 8 bits (b15 to b8) become invalid in the 8-bit mode (using the Octl bits or *HWR/*BYTE pin).

(1) D_FIFO(D_FIFO Data) Bits (b15~b0)

The receive data from the CPU side buffer is read or the transmit data to the CPU side buffer is written

through this register.

When set to OUT buffer (EPi_DIR bit = “0”), the receive data from the CPU side buffer is read through this

When set to IN buffer (EPi_DIR bit = “1”), the transmit data to the CPU side buffer is written through this

Make sure that the Dreq bit is equal to “0” before reading/writing these bits when the DMAEN bit is set to "0".

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

Note: When set to 16-bit mode, the M66291 is capable of recognizing the byte data written. Hence, it is possible to

transmit the odd byte data by setting “1” to the IVAL bit or asserting the TC pin after writing the byte data.

M66291GP/HP

Rev1.01 2004.11.01 page 70 of 122

2.34 DMAn_Transaction Count Registers (n=0~1)

Q DMA0_Transaction Count Register (DMA0_TRN_COUNT) <Address : H’4E>

Q DMA1_Transaction Count Register (DMA1_TRN_COUNT) <Address : H’56>

b151413121110987654321b0

TRNCNT

0000000000000000

----------------

b Bit name Function R W

15~0 TRNCNT

Transaction Count <TREN bit = "0">

Packet count that completes the receiving

(behaving as the compare register)

Q Read

The number of the received packets (behaving as the current

Q Write

Packet count that completes the receiving

(behaving as the compare register)

{{

(1) TRNCNT (Transaction Count) Bits (b15~b0)

This register is used under the following conditions:

•When set to OUT buffer (EPi_DIR bit = ”0”).

•When set to continuous receive mode (EPi_RWMD bit = ”1”).

•When set to bulk transfer mode (EPi_TYP bits = ” 01”)

•When accessing using Dn_FIFO Data Register.

With the transaction count function set to be enabled (TREN bit = “1”), the following conditions are added to

the buffer receive completion condition. In case of the receive completion, refer to the “EPi_RWMD bit of the

EPi Configuration Register 0”.

•When the value set by this register conforms to the packet receive count.

(Conformity between current register and compare register; See below.)

This register is composed of two registers as follows:

•Current register :Counting of the received packet number (counts up at the TREN bit = “1”)

•Compare register :The value that completes the receiving

It is necessary to clear the TNCNT bits as the current register to “0” by writing “1” to the TRCLR bit before the

next transfer.

M66291GP/HP

Rev1.01 2004.11.01 page 71 of 122

2.35 FIFO Status Register

Q FIFO Status Register (FIFO_STATUS) <Address : H’58>

b151413121110987654321b0

EPB_STS

0000000000000000

----------------

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 EPB_STS

Endpoint 0~6 Buffer Status

Q Read

0: Disables the reading and writing of data to and from the

buffer

1: Enables the reading and writing of data to and from the

buffer

{×

(1) EPB_STS (Endpoint 0~6 Buffer Status) Bits (b6~b0)

The condition for setting this bit to “1” is the same as that of the Interrupt Status Register 1.

Make sure that the condition for clearing this bit to “0” differs as follows.

The condition for clearing this bit to “0” is always the same as in the case of the RDYM bit set to “0”. Hence,

the presence/absence of data in the buffer can be confirmed by reading these bits even after the interrupt is

cleared by writing “0” to the Interrupt Status Register 1.

M66291GP/HP

Rev1.01 2004.11.01 page 72 of 122

2.36 Port Control Register

Q Port Control Register (PORT_CNTL) <Address : H'5A>

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

PIEN PDIR

000000000 0 0 0 0 0 0 0

--------- - - - - - --

b Bit name Function R W

15 Reserved. Set it to “0”. 00

14~8 PIEN

Port Input Enable 0 : Disable Port Input

1 : Enable Port Input

The port number corresponds to the bit number.

b8 :P0 pin

b9 :P1 pin

b10 :P2 pin

b11 :P3 pin

b12 :P4 pin

b13 :P5 pin

b14 :P6 pin

{{

7 Reserved. Set it to “0”. 00

6~0 PDIR

Port Direction 0 : Input Port

1 : Output Port

The port number corresponds to the bit number.

b0 :P0 pin

b1 :P1 pin

b2 :P2 pin

b3 :P3 pin

b4 :P4 pin

b5 :P5 pin

b6 :P6 pin

{{

The port pins, P0 ~ P6, automatically turn to input/output ports by setting to 8-bit bus interface mode

(controlled by HWR/BYTE pin). When set to 16-bit bus interface mode, all functions of this register become

invalid. Further, the writing into this register at 16-bit bus interface mode becomes invalid while the reading

becomes H’0000.

M66291GP/HP

Rev1.01 2004.11.01 page 73 of 122

(1) PIEN (Port Input Enable) Bits (b14~b8)

These bits set the enable/disable of port input.

When “0” is written to this bit, the related port pin does not work as the input pin even if the PDIR bit of this

is read out as “0”.

When the PDIR bit of this register is set to “0”, the related port pin works as the input pin by writing “1” to

this bit.

When the PDIR bit of this register is set to “1”, these bits become invalid (and works as an output port).

(2) PDIR (Port Input/Output Select) Bits (b6~b0)

These bits select input/output direction of the port pin.

M66291GP/HP

Rev1.01 2004.11.01 page 74 of 122

2.37 Port Data Register

Q Port Data Register (PORT_DATA) <Address : H'5C>

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

PDAT

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

- - - - - - - - - - - - - - --

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~7 Reserved. Set it to “0”. 00

6~0 PDAT

Port Data 0 : ”L” level

1 : ”H” level

The port number corresponds to the bit number.

b0 : P0 pin

b1 : P1 pin

b2 : P2 pin

b3 : P3 pin

b4 : P4 pin

b5 : P5 pin

b6 : P6 pin

{{

The port pins, P0 ~ P6, automatically turn to input/output ports by setting to 8-bit bus interface mode

(controlled by HWR/BYTE pin). When set to 16-bit bus interface mode, all functions of this register become

invalid. Further, the writing into this register at 16-bit bus interface mode becomes invalid while the reading

becomes H’0000.

(1) PDAT (Port Data) Bits (b6~b0)

These bits indicate the port pin state.

When the PIEN bit of the Port Control Register is set to “0”, this bit reads out “0”.

M66291GP/HP

Rev1.01 2004.11.01 page 75 of 122

2.38 Drive Current Adjust Register

Q Drive Current Adjust Register (I_ADJ) <Address : H'5E>

b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b0

LDRV

0 0 0 0 0 0 0 0 0 0 0 0 0 0 00

- - - - - - - - - - - - - - --

- - - - - - - - - - - - - - - -

b Bit name Function R W

15~1 Reserved. Set it to “0”. 00

0 LDRV

Drive Current Adjust 0 : When IOVcc=2.7~3.6V

1 : When IOVcc=4.5~5.5V

{{

(1) LDRV (Drive Current Adjust) Bit (b0)

This bit is used to adjust the drive current of the output pins.

The output pins here refer to D15/A0, D14/P6~D8/P0, D7~D0, *INT0, *INT1/*SOF, *Dreq0, and *Dreq1 pins.

M66291GP/HP

Rev1.01 2004.11.01 page 76 of 122

2.39 EPi Configuration Registers 0 (i=1~6)

Q EP1 Configuration Register 0 (EP1_0CONFIG) <Address : H’60>

Q EP2 Configuration Register 0 (EP2_0CONFIG) <Address : H’64>

Q EP3 Configuration Register 0 (EP3_0CONFIG) <Address : H’68>

Q EP4 Configuration Register 0 (EP4_0CONFIG) <Address : H’6C>

Q EP5 Configuration Register 0 (EP5_0CONFIG) <Address : H’70>

Q EP6 Configuration Register 0 (EP6_0CONFIG) <Address : H’74>

b151413121110987654321b0

EPi_TYP EPi

EPi_

ITMD EPi_Buf_siz EPi_

DBLB EPi_

RWMD EPi_Buf_Nmb

0000000000000000

----------------

b Bit name Function R W

15~14 EPi_TYP

Transfer Type 00 : Invalid

01 : Bulk transfer

10 : Interrupt transfer

11 : Isochronous transfer

{{

13 EPi_DIR

Transfer Direction 0 : OUT buffer (Receives data from the host)

1 : IN buffer (Transmits data to the host)

{{

12 EPi_ITMD

Interrupt Toggle Mode 0 : E nable data resend function (normal toggle mode)

1 : Disable data resend function (forced toggle mode)

{{

11~8 EPi_Buf_siz

Buffer Size Endpoint buffer size {{

7 EPi_DBLB

Double Buffer Mode 0 : Single buffer mode

1 : Double buffer mode

{{

6 EPi_RWMD

Continuous Transmit/Receive Mode 0 : Single transmit /receive mode

1 : Continuous transmit/receive mode

{{

5~0 EPi_Buf_Nmb

Buffer Start Number The top block number of buffer {{

(1) EPi_TYP (Transfer Type) Bits (b15~b14)

These bits are used to set the transfer type of the endpoint.

(2) EPi_DIR (Transfer Direction) Bit (b13)

This bit is used to set the transfer direction of the endpoint.

After switching the transfer direction, clear the buffer by the BCLR bit.

(3) EPi_ITMD (Interrupt Toggle Mode) Bit (b12)

This bit sets the enable/disable of data resend function at interrupt transfer.

This bit can be set to “1” only when the transfer type is set to interrupt transfer (EPi_TYP bits = “10”). Set this

bit to “0” for other transfer modes.

When the data resend function is set to disable, the new data is transmitted at the next transmission by

toggling the DATA PID and the buffer, even if the ACK is not received after transmitting the data at interrupt

transfer. Here, the IVAL bit is cleared to “0” and the EPB_RDY bit is set to “1” (buffer ready interrupt has

occurred).

When the data resend function is set to enable, the normal toggle sequence is executed. When the

transmission completes normally, the DATA PID and the buffer got toggled to transmit the next data. In case

ACK cannot be received after the data is transmitted, the DATA PID and the buffer do not get toggle, and the

same data in the buffer is resent.

M66291GP/HP

Rev1.01 2004.11.01 page 77 of 122

(4) EPi_Buf_siz (Buffer Size) Bits (b11~b8)

These bits set the buffer size in 64-byte unit (Note).

When set to double buffer mode (EPi_DBLB bit = “1”), the buffer double in size set by these bits is used.

Set the values to these bits as follows:

•Continuous transmit/receive mode : Value set by this register > Value set by the EPi_MXPS bits

•Single transmit/receive mode : Value set by this register ≥ Value set by the EPi_MXPS bits

Set in the manner as follows (single transmit/receive mode only) to write “1” to the IDLY bit at isochronous

transfer mode (set by EPi_TYP bits):

•Single transmit/receive mode : Value set by this register > Value set by the EPi_MXPS bits

When set to IN buffer (EPi_DIR bit = “1”), if the integral multiples of the value set by the EPi_MXPS bits is set

to these bits, the zero-length packet can be added after all data are transmitted. For details, refer to the

setting of “1” to the EPi_NULMD bit.

Note: The M66291 is equipped with 3 Kbytes FIFO buffer. The Maximum buffer size is 1024Bytes for an endpoint, and

the minimum one is 64Bytes.

(5) EPi_DBLB (Double Buffer Mode) Bit (b7)

This bit sets the single buffer mode/double buffer mode.

This bit is applicable to bulk/isochronous/interrupt transfers (set by the EPi_TYP bits).

When set to double buffer mode, 2 buffers of size set by the EPi_Buf_siz bits are secured and are allocated to

SIE side buffer and CPU side buffer.

zDouble buffer mode when set to OUT buffer (EPi_DIR bit = “0”)

{SIE side buffer:

•The data received by SIE can be written.

•Can not be accessed by CPU/DMA.

{CPU side buffer:

•Can not be accessed by SIE.

•The received data can be read by CPU/DMA.

{Buffer toggle condition (switching of SIE side buffer and CPU side buffer)

•SIE side buffer receive completion and CPU side buffer read completion (empty)

The receive completion changes according to the single/continuous transmit/receive mode.

For details, refer to the “EPi_RWMD bit” and the “TGL bit”.

zDouble buffer mode when set to IN buffer (EPi_DIR bit = “1”)

{SIE side buffer:

•SIE can transmit the written data.

•Can not be accessed by CPU/DMA.

{CPU side buffer:

•Can not be accessed by SIE.

•CPU/DMA can write the data for transmission.

{Buffer toggle condition (switching of SIE side buffer and CPU side buffer)

•CPU side buffer write completion and SIE side buffer transmit completion (empty)

The write and transmit completion changes according to the single/continuous

transmit/receive mode.

For details, refer to the “EPi_RWMD bit”.

Note: Refer to “3.2 FIFO Buffer” for CPU/SIE side.

M66291GP/HP

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(6) EPi_RWMD (Continuous Transmit/Receive Mode) Bit (b6)

This bit sets the transmit/receive mode at bulk transfer.

This bit can be set to “1” only when the transfer type is set to bulk transfer (EPi_TYP bits = “01”).

Set to “0” for other transfer modes.

zWhen set to OUT buffer (EPi_DIR bit = “0”)

In case of single transmit/receive mode, the receive completes after receiving one packet under the

conditions as follows:

•Receives the data equivalent to the size set by the EPi_MXPS bits.

• Receives the short packet (including the zero-length packet).

In case of continuous transmit/receive mode, the receive completes after receiving several packets

under the conditions as follows:

•Receives automatically the data equivalent to the size set by the EPi_MXPS bits several

times and receives the data equivalent to the byte set by the EPi_Buf_siz bit.

•Receives the short packet (including the zero-length packet).

•When the value set by the DMAn_Transaction Count Register conforms to the packet

receiving count.

zWhen set to IN buffer (EPi_DIR bit = “1”)

In case of single transmit/receive mode, the transmit completes after transmitting one packet under

the conditions as follows:

•Transmits the data equivalent to the size set by the EPi_MXPS bits or the zero-length

packet.

In case of continuous transmit/receive mode, the transmit completes after transmitting several packets

under the conditions as follows:

•Transmits automatically the data equivalent to the size set by the EPi_MXPS bits several

times and transmits the data equivalent to the byte set by the EPi_Buf_siz bit.

In case of single transmit/receive mode, the write completes under the conditions as follows:

•Writes the data equivalent to the size set by the EPi_MXPS bits to the buffer (IVAL bit

changed to “1”).

•Writes “1” to the IVAL bit of the CPU_FIFO Control/Dn_FIFO Control Register.

In case of continuous transmit/receive mode, the write completes under the conditions as follows:

•Writes the data equivalent to the size set by the EPi_Buf_siz bit to the buffer (IVAL bit

changed to “1”).

•Writes “1” to the IVAL bit.

The set/clear conditions of the IVAL bit change according to this bit.

(7) EPi_Buf_Nmb (Buffer Start Number) Bits (b5~b0)

These bits set the beginning block number of the buffer.

The block number is a number by dividing the FIFO buffer into 64 byte sections (Note 1).

The domain set by the EPi_Buf_siz bit from the block set by these bits is secured as the buffer (Note 2).

Note 1: The M66291 is equipped with 3 Kbytes FIFO buffer and has the blocks from H’0 to H’2F.

Note 2: Make sure that several endpoints may not get overlapped in the same buffer area.

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Rev1.01 2004.11.01 page 79 of 122

2.40 Epi Configuration Registers 1 (i=1~6)

Q EP1 Configuration Register 1 (EP1_1CONFIG) <Address : H’62>

Q EP2 Configuration Register 1 (EP2_1CONFIG) <Address : H’66>

Q EP3 Configuration Register 1 (EP3_1CONFIG) <Address : H’6A>

Q EP4 Configuration Register 1 (EP4_1CONFIG) <Address : H’6E>

Q EP5 Configuration Register 1 (EP5_1CONFIG) <Address : H’72>

Q EP6 Configuration Register 1 (EP6_1CONFIG) <Address : H’76>

b151413121110987654321b0

EPi_PID EPi_

NULMD EPi_

ACL

EPi_

Octl EPi_MXPS

0000000001000000

----------------

b Bit name Function R W

15~14 EPi_PID

Response PID 00 : NAK

01 : BUF

(Transmits response PID/data according to the state of

buffer etc,)

1x : STALL

{{

13 Reserved. Set it to “0”. 00

12 EPi_NULMD

Zero-Length Packet Addtion Transmit Mode 0 : Disable to transmit zero-length packet automatically

1 : Enable to transmit zero-length packet automatically

{{

11 EPi_ACLR

OUT Buffer Automatic Clear Mode 0 : Exit buffer clear mode

1 : Buffer clear mode

Make sure to set “0” after setting “1”.

{{

10 EPi_Octl

1 : CPU/Dn_FIFO Data Register is 8-bit mode

{{

9~0 EPi_MXPS

Maximum Packet Size Upper size limit of the data transmitted/re ceived in one packet

Interrupt transfer :0~64

Bulk transfer :only 8,16,32 and 64

Isochronous transfer :0~1023

{{

(1) EPi_PID (Response PID) Bits (b15~b14)

These bits set the PID to be responded to the host.

These bits are valid only when the transfer type is set to bulk transfer mode or interrupt transfer mode

(EPi_TYP bits = “01” or “10”). Set these bits to “01” at isochronous transfer mode (EPi_TYP bits = “11”).

When these bits are set to “00”, the NAK response is executed, regardless of the buffer state.

When these bits are set to “01”;

•ACK response after receiving the data with the SIE side buffer in the receive ready state.

•NAK response with the SIE side buffer in the receive not ready state.

When the SIE side buffer is not in receive ready state, if the OUT token is received, the

EPB_NRD bit is set to “1”.

•Transmits the data with the SIE side buffer in transmit ready state.

•NAK response with the SIE side buffer not in the transmit ready state.

When the SIE side buffer is in the transmit not ready state, if the IN token is received, the

EPB_NRD bit is set to “1”.

When these bits are set to “1x”, the STALL response is executed, regardless of the buffer state.

When set to OUT buffer, if a data exceeding the maximum packet size is received, regardless of these bit

values, these bits are set automatically to “1x” (STALL).

(2) EPi_NULMD (Zero-Length Packet Addtio n Transmit Mode) Bit (b12)

M66291GP/HP

Rev1.01 2004.11.01 page 80 of 122

This bit is valid at continuous transmit/receive mode (EPi_RWMD bit = “1”) when set to IN buffer (EPi_DIR

bit = “1”). Set to “0” for the other modes.

In case of the completion of SIE side buffer transmit, if the IVAL bit is set to “0”, the zero-length packet

automatically transmitted in the last under the condition as follows:

•When the buffer size set by the EPi_Buf_siz bit is the integral multiple of the size set by the

EPi_MXPS bits.

In case of the continuous transmit/receive mode, the data equivalent to the size set by the EPi_MXPS bits is

automatically transmitted several times before transmitting the data equivalent to the size set by the

EPi_Buf_siz bit.

(3) EPi_ACLR (OUT Buffer Auto-Clear Mode) Bit (b11)

When set to OUT buffer (EPi_DIR bit = “0”), all buffers both of CPU and SIE sides are cleared by setting “1” to

this bit.

This bit does not get automatically cleared to “0” even after the buffers are cleared.

When this bit is set to “1”, if BUF is set to the EPi_PID bits, the NAK response is not executed against the

received OUT token. Instead, the ACK response is sent to the host after receiving the data. The received data

is not written to the buffer. Further, with the EPi_PID bits set to NAK/STALL, the NAK/STALL response is

executed.

When set to IN buffer (EPi_DIR bit = “1”), only the SIE side buffer and the buffer with the writing completed

(the buffer when IVAL bit = “1”) are cleared by setting “1” to this bit.

When this bit is set to “1”, if BUF is set to the EPi_PID bits, the NAK response is given against the received IN

token. Further, with the EPi_PID bits set to NAK/STALL, the NAK/STALL response is executed.

Note: When set to IN buffer, make sure to set the response PID to NAK (EPi_PID bits = “00”) bef ore setting this bit to

“1”.

(5) EPi_Octl (Register 8-Bit Mode) Bit (b10)

This bit has the same function as the Octl bit of the CPU_FIFO Select Register or the Octl bit of the Dn_FIFO

Select Register. Please refer to the items of these registers.

(6) EPi_MXPS (Maximum Packet Size) Bits (b9~b0)

These bits set the upper limit (byte count) of the data transmitted and received in one packet transfer.

Set the wMaxPacketSize value transmitted to the host.

In case of transmitting, the data equivalent to the size set by these bits is read out from the buffer for transmit.

If the buffer does not have the data equivalent to the set by these bits, the data is transmitted as the short

packet.

In case of receiving, the received data equivalent to the size set by these bits is written to the buffer. In case

the received data exceeds the size set by these bits, the following bit is set to "1":

•The EPB_EMP_OVR bit

(buffer empty/size-over error interrupt occurs when the EPB_EMPE bit is set to “1”).

Note: Set this bit after setting the response PID to NAK (EPi_PID bits = “00”).

M66291GP/HP

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M66291 OPERATIONS

3.1 Interrupt Function

There are 8 factors of interrupts in the M66291.

For details, refer to the “Interrupt Status Registers 0 to 3”.

The enable/disable of interrupt can be set by the Interrupt Enable Registers 0 to 3.

Each bit of the Interrupt Status Register is set to “1” according to the factor even if the Interrupt Enable

Registers 0 to 3 are set to interrupt inhibit mode.

The list of interrupts in M66291 is given in Table 3.1 and the diagrams related to the interrupt in Figure 3.1.

Table 3.1 List of Interrupts

Status Bit

(Interrupt Name) Interrupt Factor Related Item

VBUS

(Vbus Interrupt) Change of Vbus input level

(change of "L"->"H", "H"->"L") Confirmation of Vbus pin input state by the

Vbus bit of the Interrupt Status Register 0

RESM

(Resume Interrupt) Change of USB bus state in suspend state

("J"->"K" or "SE0") Confirmation of current device state by the

DVSQ bits of the Interrupt Status Register 0

SOFR

(SOF Detect Interrupt) Receive of SOF packet ⎯

DVST

(Device State Transition

Interrupt)

• Detection of USB bus reset

• Detection of suspend state

• Execution of "SET_ADDRESS"

• Execution of "SET_CONFIGURATION"

Confirmation of current device state by the

DVSQ bits of the Interrupt Status Register 0

CTRT

(Control Transfer Stage

Transition Interrupt)

• Transition of control write transfer status stage

• Transition of control read transfer status stage

• Completion of control transfer

• Occurrence of control transfer sequence error

• Completion of setup stage

Confirmation of current control transfer stage

state by the CTSQ bits of the Interrupt Status

BEMP

(Buffer Empty / Size Over

Interrupt)

• Transmit of all the data stored in the buffers at each

endpoint

• Receive of packet exceeding the maximum packet size

during receiving data packet

Confirmation of endpoint number occurred the

interrupt by the EPB_EMP_OVR bits of the

Interrupt Status Register 3

INTN

(Buffer Not Ready Interrupt) When NAK response is automatically executed because

of the buffer not ready state in the IN/OUT token of each

endpoint

Confirmation of endpoint number occurred

the interrupt by the EPB_NRDY bits of the

Interrupt Status Register 2.

INTR

(Buffer Ready Interrupt) When each endpoint is buffer ready state

(read /write enable state) Confirmation of endpoint number of the

occurred interrupt by the EPB_RDY bits of

the Interrupt Status Register 1.

M66291GP/HP

Rev1.01 2004.11.01 page 82 of 122

VBSE

USB reset occur

SET_ADDRES S detect

SET_CONF IGURATION detect

Suspend det ect

VBUS

RSME RESM

SOFE SOFR

DVSE DVST

URST

SADR

SCFG

SUSP

CTRE CTRT

Control write transfer

Status stage transition

Con trol transfer com p l ete

Control transfer sequence error

RDST

SERR

WDST

CMPL

Setup stage complete

Control read transfer

Status stage transition

BEMPE BEMP

<<<Interrupt Enabl e Regi ste r 3>>>

EPB_EMPE

b0b1~b6 <<Interrupt Status Register 3>>>

EPB_EMP_OVR

INTNE INTN

<<<Interrupt Enable Register 2>> >

EPB_NRE <<<Interrup t Status Register 2>>>

EPB_NRDY

INTRE INTR

<<<Interrupt Enable Register 1>> >

EPB_RE <<<Inte rrupt Status Registe r 1>>>

EPB_RDY

b0b1~b6

Edge/level

generator

circuit

INT0/INT1

assign

circuit

INT0

INT1

Bit name <<<Int errupt Enable Re g iste r 0>>>

Bit nam e <<<Interrupt Status Registe r 0>>>

ReadOnly

Figure 3.1 Interrupt Related Diagram

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Rev1.01 2004.11.01 page 83 of 122

3.2 FIFO Buffer

The M66291 has 6 endpoints available for bulk/interrupt/isochronous transfers in addition to endpoint 0 for

control transfer.

The M66291 is equipped with a total of 3 Kbytes FIFO that can be used as the buffer of the endpoint and can be

assigned arbitrary byte count in 64-byte unit against each endpoint.

3.2.1 FIFO Buffer Configuration

The endpoint buffer can be set for double buffer configuration and continuous transmit/receive mode. Each

buffer configuration is set by the registers as follows:

Endpoint 0:

• Control Transfer Control Register

• EP0 Packet Size Register

• EP0_FIFO Continuous Transmit Data Length Register

Endpoint 1~6:

• EPi Configuration Register 0

• EPi Configuration Register 1

3.2.2 Buffer Access

The buffers of endpoints 0 to 6 can be accessed by the four data registers as follows:

<EP0_FIFO Data Register>

• Quantity : 1 piece

• Exclusively used for endpoint 0

<CPU_FIFO Data Register >

• Quantity : 1 piece

• Shared with endpoints 1 to 6 (specified by the CPU_EP bits)

<Dn_FIFO Data Register >

• Quantity : 2 pieces

• Shared with endpoints 1 to 6 (specified by the DMA_EP bits)

• Can be accessed by DMAC

These four data registers can be set independently to 8-bit/16-bit mode by the Octl bit.

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3.2.3 Buffer State and IVAL Bit

(1) Buffer state and IVAL bit of the OUT buffer

The relation between buffer state and IVAL bit is shown in Figure 3.2 when the buffer is set to OUT (set by

the EPi_DIR bit/ISEL bit).

The single/double buffer mode is set by the EPi_DBLB bit. The double buffer mode cannot be set at endpoint 0.

CPU bus

Empty

z Wh en set to O UT bu ff er

SIE bus

IV AL b it = " 0 "

Receive

data

Receive data

IV AL b it = " 1 "

Receive

data

IV AL b it = " 0 "

Empty

Empty

SIE bus

IV AL b it = " 0 "

Receive

data

Receive data

IV AL b it = " 1 "

Empty

Em pty IVAL bit ="0"

Receive data

Empty

Receive

data

Receiv e co mp letion (N o te 2)

Receive

data

Receive data Empty

Receive data

Empty IV AL b it = " 1 "

(EPB_ RDY bit is s et to "1" )

IV AL b it = " 0 "

IV AL b it = " 1 "

(E P B_ R DY bit is s et to "1" )

Receive

data

Empty

Empty Empty

IVAL bit ="1 "

IVAL bit ="0 "

IV AL b it = " 1 "

(EPB_RDYb it is set to"1" )

N ote 1. Respon se to the host wh en EP0_ PID/EPn _ PID b its are s et to "0 1 (BUF)" .

Note 2 . Abou t the r eceives completion, refer t o th e follow s:

z Endpoint 0

CTR W bit of C ontrol Transfer Control Register

z O thers endpoint 0

EPnR WMD bit of EPn C onfiguration R egister

CPU bus

Accessable

Not accessable

R e a d c ompletion

Receiv e co mp letion (N o te 2)

Read co mp letion

R e a d c omple t ion

SIE s ide buffer CP U side buffer

SIE s ide buffer CP U s ide buffer

Receive data

IV AL b it = " 0 "

Empty IV AL b it = " 0 "

Resp on se ( Note 1)

ACK

NAK

ACK

NAK

R esp on se (Not e 1)

ACK

NAK

ACK

NAK

ACK

Receiv e co mp letion (N o te 2)

Figure 3.2 Relation between Buffer State and IVAL Bit (when set to OUT buffer)

M66291GP/HP

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(2) Buffer state and IVAL bit of the IN buffer

The relation between buffer state and IVAL bit is shown in Figure 3.3 when the buffer is set to IN (set by the

EPi_DIR bit/ISEL bit).

The single/double buffer mode is set by the EPi_DBLB bit. The double buffer mode cannot be set at endpoint 0.

CPU bus

z Wh en s et to IN b u f f er

SIE bus

IVAL bit =" 0 "

Transmit

data

T ran s m it data

IVAL bit =" 1 "

Transmit

data

IVAL bit =" 1 "

Empty

Empty

SIE bus

IVAL bit =" 0 "

Empty

Empty IVAL bit ="1"

Transmit data

Empty

Transmit data Empty IVA L b it ="0 "

(EPB_ RDY bit is set to " 1 " )

IVAL bit =" 1 "

Empty

Empty Empty

IVAL bit =" 0 "

(EPB_ RDY bit is set to " 1 " )

Note 1 . Res p on se to t h e h ost wh en EP0_ PID/E Pn _PID b its are set to "0 1(BUF) ".

Note 2 . Abou t the tr an smit/w r ite comp letion s, ref er to the f ollow s:

z Endp oint 0

CTRR b it of Con trol Tr an sfer Contr ol Re g ister

z Oth ers end p oin t 0

EPnRWMD bit of E P n C onfiguration Register

CPU bus

Accessable

Not accessable

Transmit

data

T ran s m it data

Empty

Transmit

data Transmit

data

T ran s m it data

Transmit

data

Write com p letion (No te 2)

Transmit com p letion (No te 2)

SIE side buffer C P U side buffer

Empty

Transmit data IVA L bit =" 1 "

IVAL bit =" 0 "

(EPB_ RDY bit is set to " 1 " )

Empty

Respon se (Not e1 )

NAK

Transmits data

NAK

SIE side buffer CP U s ide buff er

NAK

Transmits data

NAK

Transmits data

NAK

Respon se (Not e 1 )

Write com p letion (No te 2)

Transmit com p letion (N o te 2) Write com p letion (N o te 2)

Transmit com p letion (No te 2)

Figure 3.3 Relation between Buffer State and IVAL Bit (when set to IN buffer)

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3.2.4 IVAL Bit and EPB_RDY Bit

The IVAL bit is available per endpoint.

These IVAL bits can be specified by the CPU_EP bits and the DMA_EP bits, and the read/write is possible by

the IVAL bit of the CPU_FIFO Control Register and the IVAL bit of the Dn_FIFO Control Register.

The EPB_RDY bit can be set/cleared by the IVAL bit at each endpoint, irrespective of the aforesaid setting.

Similarly, the EPB_NRDY bit and EPB_EMP_OVR bit can be set/cleared regardless of the CPU_EP

bit/DMA_EP bit.

Make sure that the “1” setting to the EPB_RDY bit of the endpoint specified by the DMA_EP bit changes

according to the setting of the INTM bit.

EP0_FIFO D ata Regis ter

(EP0_FIFO C ontrol Register)

Endpoint 0

IVAL IVAL bit

CPU_FIFO Data Register

(C P U_ F IF O Control R egister)

Endpoint 1

IVAL IVAL bit

Endpoint 2

IVAL

Endpoint 3

IVAL

Designates by CP U_EP bit

Endpoint i

IVAL

D0_FIFO Data Register

(D0_FIFO C ontrol Register)

IVAL bit

D1_FIFO Data Register

(D1_FIFO C ontrol Register)

IVAL bit

Dn_FIFO Data Register

(Dn_FIFO C ontrol R egister)

IVAL bit

Designates by DMA_E P bit

Designates by DMA_EP bit

Interrupt Status R egis ter1 (EPB _R D Y)

Interrupt Status Register2 (EPB_NRDY)

Interrupt Status Register 3 (EPB_EMP_O VR )

FIFO S tatus R egister (EP B _S TS )

Fix

Figure 3.4 IVAL Bit and EPB_RDY Bit

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Rev1.01 2004.11.01 page 87 of 122

3.3 USB Data Transfer Function Overview

The M66291 is capable of executing the USB transfer by processing the operations as follows:

(1) Response against the control transfer request

(2) Enable of transmitting after storing the transmit data to the buffer

Enable of receiving and reading the receive data from the buffer

(3) Stall processing

(4) Suspend/resume processing

3.3.1 Data Receive Function

The data receiving operation of the setup transaction and the OUT transaction differs as follows.

zSetup transaction (control transfer setup stage)

The device request data received from the host (8 bytes) are stored to 4 different registers.

Here, ACK response is executed to the host and the control transfer stage transition interrupt has

occurred.

zOUT transaction

In the data packet after receiving OUT token from the host, when the buffer receives the packet of

maximum size or the short packet, the ACK response is executed to the host and the buffer ready

interrupt has occurred (ready for reading the receive data).

When the buffer is not in the receive ready state, the buffer not ready interrupt has occurred.

3.3.2 Data Transmit Function

The data transmit is executed on receiving the request for data transmit by the IN token packet.

zIN transaction

After the IN token is received from the host, the buffer data is transmitted. On completion of the buffer

data transmit, the buffer ready interrupt has occurred (ready for writing the transmit data).

When the buffer is not in transmit ready state, the buffer not ready interrupt has occurred.

3.3.3 Data Transfer Sequence

The data written to the FIFO Data Register are transmitted to the USB bus in the order of LSB first. The

same is true when the data received from the USB bus is stored to the FIFO Data Register.

116

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15

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3.3.4 DMA Transfer Overvie w

The M66291 is capable of DMA transfer in 16-bit/8-bit width (specified by the Octl bit) against the endpoint 1

to 6.

The DREQ pin is asserted when the endpoint buffer set to the Dn_FIFO Select Register is in read/write ready

state. The output of DREQ pin is enabled by the DMAEN bit.

In order to write the data to transmit the short packet by the DMA_FIFO, assert the TC pin or set the IVAL

bit to “1” after writing last data.

Further, when read by using DMA, the timing of the buffer ready interrupt occurrence can be changed by the

INTM bit.

3.3.5 DMA Transfer Method

The DMA transfer method is set by the DFORM bit of the Dn_FIFO Control Register.

(1) Cycle Steal Mode (BUST bit = "0")

At cycle steal mode, the DREQ pin is asserted at every transfer (8-bit/16-bit).

(A-1) DMA transfer control by the DACK pin and read/write pins (DFORM bits = “00”):

At this mode, the DACK pin and read/write pins are used to access to the Dn_FIFO Data Register

of the M66291.

(A-2) DMA transfer control solely by the DACK pin (DFORM bits = “01”):

At this mode, only the DACK pin is used to access to the Dn_FIFO Data Register of the M66291.

The read/write pins are not used in this mode (are ignored).

(A-3) DMA transfer control by the chip select pin and the address pins (DFORM bits = “10”):

In this mode, the address pins and read/write pins are used to access the Dn_FIFO Data Register

of the M66291. The DACK pin is not used in this mode (is ignored).

(2) Burst Mode (BUST bit = "1")

At burst mode, the DREQ pin is asserted until all data in the buffer has been transferred , and is negated

when the transfer completes.

(B-1) DMA transfer control by the DACK pin and read/write pins (DEFORM bits = “00”):

This mode operates with the same timing as (A-1).

(B-2) DMA transfer control by the chip select pin and address pins (DEFORM bits = “10”):

This mode operates with the same timing as (A-3).

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(A-1 ) D F ORM = 0 0 Write

DMA_REQ

(A-2 ) D F ORM = 0 1 Write

(A-1 ) D F ORM=0 0 Read

(A-3 ) D F ORM = 1 0 Write (A-3 ) D F ORM=1 0 Read

DMA_ACK

Write

Data

Read

DMA_REQ

DMA_ACK

Input Output

(A-2 ) D F ORM=0 1 Read

DMA_REQ

DMA_ACK

Data

Input

DMA_REQ

DMA_ACK

Data

• T he r ead /w r ite pin is ig n or ed .

• T he r ead p in is ig n or ed .

Data

• T h e w r it e p i n is ig nor ed.

Output

• The read/write pin is ignored.

DMA_REQ

Address

Write

Data

Input

• The DMA_ACKn/read pin is ignored.

Valid address

Read

DMA_REQ

Output

Data

• The DM A_ A C K n/write pin is ignored.

V alid ad dressAddress

N ote: T h is f igu re ind ic ates th e D MA_ RE Q and DMA_ACK p ins at "L " ac tive.

Figure 3.5 Access Timing at Cycle Steal Transfer

(B-1 ) D F ORM = 0 0 Write

DMA_REQ

(B-1 ) DFOR M = 00 R ead

DMA_ACK

Write

Data

Input Output

• T he read pin is ignored.

Data

• T he write p in is ignored.

Address

∗ : Valid address

• The DMA_ACK/write pin is ignored.

Input Input

DMA_REQ

DMA_ACK

Read

Output Output

(B-2 ) D F ORM = 1 0 Write

DMA_REQ

(B-2 ) DFOR M = 10 R ead

Write

Data

∗

Output

N ote: T h is f igu re ind ic ates th e D MA_ RE Q and DMA_ A CK p ins at "L " ac tive.

Data

Input Input

DMA_REQ

Read

Output Output

∗ ∗

Input

Address ∗ ∗ ∗

∗ : Valid address

• The DMA_ACK/read pin is ignored.

Figure 3.6 Access Timing at Burst Transfer

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3.4 Control Transfer Overview

The control transfer is composed of three stages as follows:

(1) Setup stage

(2) Data stage (some control transfers don't include)

(3) Status stage

The M66291 automatically controls the stages of the control transfers by the hardware and is capable of

generating interrupt against the aforesaid stage transition.

The control transfers are executed by the endpoint 0.

The examples of control write transfer, control read transfer, control write no data transfer, control transfer

error and continuous setup operations are shown in Figure 3.7 to Figure 3.12.

(1) Setup stage

The transition to the setup stage occurs when the setup token is received.

The request data received at the setup stage (8 bytes) is automatically stored to four registers (Request, Value,

Index and Length) before the ACK response is executed.

For SET_ADDRESS request and SET_CONFIGURATION request, the M66291 can respond automatically to

the host. As for the other requests, execute data analysis (decoding) and processing by the software after the

setup stage complete interrupt has occurred.

When the setup token is received, the VALID bit is set to “1”, the EP0_PID and CCPL bits are changed as

shown below, then these bits are protected until the VALID bit is cleared:

• EP0_PID bits “00” : NAK response (response at data stage)

• CCPL bit “0” : NAK response (response at status stage)

(2) Data stage

The transition to the data stage occurs when the IN token/OUT token is received after the setup stage. In case

of the request with no data stage, the transition to the status stage executes by receiving the OUT token after

the setup stage.

• Control write transfer (OUT transaction)

With the buffer set to receive ready state (buffer empty), the EP0_PID bits are set to “01” to make ACK

response to the host after receiving the data.

When the buffer is ready for data reading, the buffer ready interrupt occurs to enable reading of the

receive data by the EP0_FIFO Data Register.

• Control read transfer (IN transaction)

With the buffer set to transmit ready state (buffer contains transmit data), the data is transmitted to

the host by setting the EP0_PID bits to “01”.

When the buffer is ready to accept new transmit data, the buffer ready interrupt occurs.

(3) Status stage

The transition to the status stage occurs when IN token and OUT token are received after the data stage,

causing the control write/read transfer status transition interrupt to occur. In this case, setting the EP0_PID

bits to “01” and the CCPL bit to “1” enables to notify the normal completion to the host.

In the case of the request with no data stage, this interrupt works as the setup stage complete interrupt.

M66291GP/HP

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SETUP

DATA0

DDR EP CRC5

8 bytes data (CW) CRC16

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ ="011"

Interrupt

VALID confirm

CTRT interrupt confirm

CTRT interrupt clear

VALID clear

Request data analysis

Execute the following

processing on the basis of the

request data analysis result.

Set the EP0 response PID to

BUF (“01”).

Abandon request data

analysis result

W ait for the next CTRT

interrupt

VALID='1'

VALID='0'

OUT

DDR EP CRC5

NAK

CTRT='0'

VALID='0'

OUT

DDR EP CRC5

NAK

OUT

DDR EP CRC5 EP0_PID = "01"

DATA1 MAX packet size data CRC16

OUT

DDR EP CRC5

DATA0 Short packet data CRC16

DDR EP CRC5

NAK

DDR EP CRC5

DATA1 CRC16 (0 byte length data)

CTRT='1'

CTSQ ="100"

Interrupt

Transmit

no-problem confirm

CTRT interrupt confirm

CTRT interrupt clear

Set the CCPL Set EP0 response

PID to STALL (“1x”)

problem

No-problem

CTRT='0'

CCPL = '1'

H/W state S/W procedure USB bus

DATA1 MAX packet size data CRC16

DDR EP CRC5

NAK

DDR EP CRC5

NAK

Interrupt

INTR= '1'

EPB_RDY[0]='1' EPB_RDY[0] interrupt confirm

Read receive data from EP0_FIFO

SETUP : SETUP PID

OUT : OUT PID

IN : IN PID

DDR : USB address (H'00~H'7F)

EP : Endpoint (H'0~H'3)

CRC5 : 5 bits CRC

: Data to device from host

: Data to host from device

CK : ACK PID

NAK : NAK PID

STALL : STALL PID

EPB_RDY[0]='0'

CTRT='1'

CTSQ ="000"

Interrupt

CTRT interrupt confirm

CTRT interrupt clear

CTRT='0'

DATA0 : DATA0 PID

DATA1 : DATA1 PID

CR : Control read transfer

CW : Control write transfe

ND : Control no data transfer

CRC16 : 16 bits CRC

• Set the continuous transmit mode.

Figure 3.7 Examples of Control Write Transition Operations

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Rev1.01 2004.11.01 page 92 of 122

SETUP

DATA0

ADDR EP CRC5

8 bytes data (CR) CRC16

ACK

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ = "001"

Interrupt

VALID c onfirm

CTR T interrupt confirm

CTRT interrupt clear

VALID clear

R eq u es t d ata an alys is

E xecute t h e followin g

pr oces sin g on th e b asis of the

req uest d ata analys is resu lt.

1. Set the tr an s mit d ata to the

EP0 FIFO

2. Set the EP0 response PID

to BUF (" 0 1")

Abandon request data

analys is result

Wait for the n ext CTRT

interrupt

VALID='1'

VALID='0'

IN ADDR EP CRC5

NAK CTRT='0'

VALID='0'

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

Write d ata to

EP0_FIFO

(IVAL='1')

EP0_P ID = "01"

DATA1 MAX pa ck et size data CRC16

ACK

IN ADDR EP CRC5

DATA0 Short packet data CRC16

ACK

OUT ADDR EP CRC5

DATA1 CRC16 (0 byte length data)

NAK

OUT ADDR EP CRC5

DATA1 CRC16 (0 byte length data)

ACK

CTRT='1'

CTSQ = "010"

Interrupt

Transmit

no-problem confirm

CTR T interrupt confirm

CTRT interrupt clear

S et the CCPL Set EP0 response

PID to STALL("1x")

problem

No-problem

CTRT='0'

CCPL = '1'

H/W state S/W procedureUSB bus

SETU P : SET U P PID

OUT : OUT PID

IN : IN P ID

AD D R : U SB addres s (H '00~H'7F)

E P : End p oin t ( H'0 ~H'3)

C RC5 : 5 bits CRC

DATA0 : DATA0 PID

DATA1 : DATA1 PID

: Data to device f r om h ost

: Data to h ost f r om d evice

C R : Control r ead tr an sfer

C W : Con tr ol write transf er

N D : Control n o data tran sfer

CRC16 : 16 bits CRC

ACK : ACK PID

NAK : NAK PID

STALL : STALL PID

CTRT='1'

CTSQ = "000"

Interrupt

CTR T interrupt confirm

CTRT interrupt clear

CTRT='0'

Set the c on tinu ous tra nsmit mo de.

Figure 3.8 Examples of Control Read Transition Operations

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SETUP

DATA0

ADDR EP CRC5

8 bytes data (ND) CRC16

ACK

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ ="101"

Interrupt

VA LID confirm

CT R T interru pt c on firm

CTRT interrupt clear

VA L ID c lear

Reque st data analysis

Execute the following

processing on the basis of the

request data analysis result.

1. Set the EP 0 response P ID

to B U F ("01 ")

2. S et th e C C PL

Aban don request data

an a lys is re s u lt

Wait for the n ext C T R T

interrupt

VALID='1'

VALID='0'

CTRT='0'

VALID='0'

EP0_PID = "01"

CCPL='1'

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

DATA1 CRC16 (0 byte length data)

ACK

H/W state S/W procedureUSB bus

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

NAK

SETUP : SETUP PID

OUT : OUT PID

IN : IN PID

ADD R : USB address (H'00~H '7F)

EP : Endpoint (H'0~H'3)

CR C 5 : 5 bits C R C

DATA0 : DATA0 PID

DATA1 : DATA1 PID

: Da ta to d evic e fro m h os t

: Da ta to h os t from dev ice

CR : Control read transfer

CW : C o ntro l write tran sfe r

ND : C o ntrol n o d ata tran sfe r

CR C 1 6 : 1 6 bits C R C

ACK : ACK PID

NAK : NAK PID

STALL : STALL PID

Reques t data

analysis result

confirm e d to have

no-problem

Set EP0 response

PID to STALL("1x")

problem

No-problem

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

NAK

CTRT='1'

CTSQ ="000"

Interrupt

CT R T interru pt c on firm

CTRT interrupt clear

CTRT='0'

Figure 3.9 Examples of No Data Control Transition Operations

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Rev1.01 2004.11.01 page 94 of 122

SETUP

DATA0

ADDR EP CRC5

8 bytes data (CR ) CRC16

ACK

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ ="001"

Interrupt

VALID confirm

CTRT interrupt confirm

CT R T inte rrupt c lea r

VA LID clear

Reque st data analysis

Execute the following

processing on the basis of the

request data analysis result.

1. S et th e tra ns mit d ata to th e

EP 0 F IF O

2. Set the EP 0 response P ID

to B U F ("01 ")

Abandon request data

analysis result

Wait for th e n ext C T R T

interrupt

VALID='1'

VALID='0'

IN ADDR EP CRC5

NAK CTRT='0'

VALID='0'

IN ADDR EP CRC5

NAK

Write data to

EP0_FIFO

(IVAL='1')

EP0_PID =

"01"

OUT ADDR EP CRC5

DATA1 CRC 16 (0 byte length data)

STALL

CTRT='1'

CTSQ ="110"

EP0_PID="10"

Interrupt

CTR T interrupt confirm

CT R T inte rrupt c lea r

CTRT='0'

H/W state S/W procedureUSB bus

SETUP : SETUP PID

OUT : OUT PID

IN : IN PID

AD DR : USB add ress (H'00~H'7F)

EP : Endpoint (H'0~H'3)

CR C 5 : 5 bits C RC

DATA0 : DATA0 P ID

DATA1 : DATA1 P ID

: Da ta to de vice from hos t

: Da ta to ho s t from d e vice

CR : Control read transfer

CW : Control write transfer

ND : C on trol n o d ata tra n sfe r

CR C 1 6 : 1 6 b its C R C

ACK : ACK PID

NAK : NAK PID

STALL : STALL PID

SETUP

DATA0

ADDR EP CRC5

8 bytes data(CR ) CRC16

ACK

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ ="001"

Interrupt

IN ADDR EP CRC5

NAK

CTRT interrupt confirm

CT R T inte rrupt c lea r

VA LID clear

Reque st data analysis

Figure 3.10 Examples of Control Transfer Error Operations

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Rev1.01 2004.11.01 page 95 of 122

SETUP

DATA0

ADDR EP CRC5

8 bytes data (CR) CRC16

ACK

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ ="001"

Interrupt

VALID confirm

CTRT interrupt confirm

CTRT interrupt clear

VA LID clear

Reque st data analysis

Execute the follo wing

processing on the basis of

the re qu es t d ata a na lysis

result.

1. S et th e trans mit data to

the E P0 FIF O

2. S et th e E P 0 re s po ns e

PID to B U F ("01 ")

Abandon request data

analysis result

Wait for the n ext C T R T

interrupt

VALID='1'

VALID='0'

IN ADDR EP CRC5

NAK CTRT='0'

VALID='0'

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

Write d a ta to

EP0_FIFO

(IVAL='1')

EP0_PID = "01"

DATA1 MAX packet size data CRC16

ACK

H/W state S/W procedureUSB bus

SETUP : SETUP PID

O U T : O UT PID

IN : IN PID

AD DR : US B ad dress (H'00~H'7F)

EP : Endpoint (H'0~H'3)

CR C 5 : 5 bits CRC

DATA 0 : DATA0 P ID

DATA 1 : DATA1 P ID

: Da ta to de vice from hos t

: Da ta to ho s t from d evic e

CR : C on trol rea d tra ns fe r

CW : C o n tro l w rite tra n s fe r

ND : C on trol n o d ata tran sfe r

CR C 1 6 : 1 6 b its C R C

ACK : ACK PID

NAK : NAK PID

STALL : STALL PID

SETUP

DATA0

ADDR EP CRC5

8 bytes data (CR) CRC16

ACK

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ ="001"

Interrupt

VALID confirm

CTRT interrupt confirm

CTRT interrupt clear

VA LID clear

Reque st data analysis

Execute the following

processing on the basis of the

request data analysis result.

1. S et th e tra ns mit d ata to th e

EP 0 F IF O

2. Set the EP 0 response P ID

to B U F ("01 ")

Abandon request data

analysis result

Wait for the n ext C T R T

interrupt

VALID='1'

VALID='0'

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

NAK

Figure 3.11 Examples of Setup Continuous Operations (1)

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Rev1.01 2004.11.01 page 96 of 122

SETUP

DATA0

ADDR EP CRC5

8 bytes data (CR ) CRC16

ACK

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ ="001"

Interrupt

VALID confirm

CT R T inte rrup t co nfirm

CT R T inte rrup t clea r

VALID clear

Reques t data analysis

Execute the following

processing on the basis of the

request data analysis result.

1. S et th e trans mit data to th e

EP 0 F IF O

2. S et th e E P 0 res p on s e P ID

to B U F ("01 ")

Aba ndon request data

analysis result

Wait for the n ext C T R T

interrupt

VALID='1'

VALID='0'

IN ADDR EP CRC5

NAK CTRT='0'

VALID='0'

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

Write d a ta to

EP0_FIFO

(IVAL='1')

EP0_PID = "01"

DATA1 MAX packet size data CRC16

ACK

H/W state S/W procedureUSB bus

SETUP : SETUP PID

OUT : OUT PID

IN : IN PID

AD DR : USB add ress (H'00~H'7F)

EP : Endpoint (H'0~H'3)

CRC5 : 5 bits CRC

DATA0 : DATA0 P ID

DATA1 : DATA1 P ID

: Da ta to de vice from hos t

: Da ta to ho s t from d e vice

CR : C on trol rea d tra ns fe r

CW : C on trol w rite tran s fer

ND : C on trol n o d ata tran sfe r

CR C 1 6 : 1 6 b its C R C

ACK : ACK PID

NAK : NAK PID

STALL : STALL PID

SETUP

DATA0

ADDR EP CRC5

8 bytes data (CR ) CRC16

ACK

VALID='1'

EP0_PID="00"

CCPL='0'

CTRT='1'

CTSQ ="001"

Interrupt

IN ADDR EP CRC5

NAK

Write d a ta to

EP0_FIFO

(IVAL='1')

EP0_PID = "01"

VALID confirm

CT R T inte rrup t co nfirm

CT R T inte rrup t clea r

VALID clear

Reques t data analysis

Execute the following

processing on the basis of the

request data analysis result.

1. Clear the E P0 _FIFO

2. S et th e trans mit data to th e

EP 0 F IF O

3. S et th e E P 0 res p on s e P ID

to B U F ("01 ")

Aba ndon request data

analysis result

Wait for the n ext C T R T

interrupt

VALID='1'

VALID='0'

IN ADDR EP CRC5

NAK

IN ADDR EP CRC5

DATA1 MAX packet size data CRC16

ACK

Figure 3.12 Examples of Setup Continuous Operations (2)

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Rev1.01 2004.11.01 page 97 of 122

3.5 Enumeration

Figure 3.13 shows the overview of enumeration operations.

Ho st side

procedure H/W procedure S/W side

procedure

USBbus connect

(P C p ower ON etc .)

FullSpeed

device recognition

Vbus interrupt

F u llSpee d

device notification

(Set the Tr_ ON bits)

In itialize p r ocedu r e

Powered state

(DVSQ="000")

USB bus reset Device state

tran sition in ter rup t

(U S B bu s reset) USB reset p r ocedu r e

GET_DESCRIPTOR

reques t (A DDR= 0 ) Con tr ol t ransfer

s tage tr ansition

interrupt Descriptor

data set

D es c riptor rec eive

SET_ADDRESS

request

Control transfer

stage transition interrupt

(at d i s a b le d a uto ma tic

response)

GET_DESCRIPTOR

request (ADDR ≠0) Cont r ol tr an sfer

s tage tr ansition

interrupt Descriptor

data set

Descriptor receive

SET_CONFIGURATION

request

C onfiguration receive

Default state

(DVSQ="001")

Address state

(DVSQ="010")

Device state

tran sition in ter rup t

(SetAddress)

SetAddress procedure

Control transfer

stage transition interrupt

(at d i s a b le d a uto ma tic

response)

Device state

tran sition in ter rup t

(SetConfiguration)

Configured

state

(DVSQ="011")

Figure 3.13 Overview of Bus ⋅ Enumeration Operations

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Rev1.01 2004.11.01 page 98 of 122

3.5.1 FIFO Buffer Management

The M66291 is equipped with the registers below in order to execute high-level management of the FIFO

buffer set to continuous transmit/receive mode.

(1) SIE_FIFO Status Register

This register can forcibly toggle the FIFO buffer at SIE side of double buffer, enabling the CPU to access to

the SIE side FIFO. Further, the CPU can refer to the received data number in the SIE side FIFO.

(2) Transaction Count Register

When the continuous transfer mode buffer set in the OUT bulk transfer, the data receive count by MAX

packet size is specified, enabling the transaction only for the set count. It is convenient for the DMA

transfer.

(3) FIFO Status Register

This register is used for referring to the FIFO buffer status.

3.5.2 Cautions at FIFO Data Access

Make sure of the items as follows when accessing the FIFO Data Register.

When 8-bit width is selected in CPU interface:

The FIFO data can not be set to 16-bit mode by the register bit (Octl), while *LWR pin becomes valid as the

write strobe at 8-bit mode.

When 16-bit width is selected in CPU interface:

The FIFO data can be set both to 16-bit and 8-bit modes by the register bit (Octl).

B-1) 16-bit mode (Octl bit =“0”)

When accessing data for write, assert *HWR and *LWR pins simultaneously for word access, and *LWR

pin for byte access. At byte access, D7 to 0 become valid.

B-2) 8-bit mode (Octl bit =“1”)

When accessing data for write, *LWR pin is valid as the write strobe. Here, D7 to 0 become valid.

When accessing data for read, D15 to 8 and D7 to 0 are the same.

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3.5.3 CPU Interface Bus Width Selection

The bus width is selected by the *HWR/*BYTE pin level at the rising of the *RST pin.

The 8-bit width is selected when *HWR/*BYTE pin is “L” level and 16-bit when it is “H” level.

With the 8-bit width selected, fix the *HWR/*BYTE pin to “L”.

3.5.4 Combination of CPU Interface Input Pins

CPU

Interface

*CS *HWR *LWR *RD Valid

address

D15-8 D7-0 Remarks

L L L H A6-0 Note 1 Data input Wr ites the lower byte

L L H L A6-0 Note 1 Data output Reads the lower byte

8-bit

width

H X X X A6-0 Note 1 Hi-Z

L L H H A6-1 Data input Hi-Z Writes the upper byte

L H L H A6-1 Hi-Z Data input Writes the lower byte

L L L H A6-1 Data input Data input Writes the upper and lower bytes

L H H L A6-1 Data output Data output Reads the upper and lower bytes

16-bit

width

H X X X A6-1 Hi-Z Hi-Z

X : Don’t care

Hi-Z : High impedance

Note 1: The D15/A0 become input pins, while the others depend on the ports setting.

Note 2: The above figure is not applicable when accessing to the FIFO Data Register.

HWR/BYTE

RST

HWR/BYTE

RST

"L"

When select to 8-bit bus width When select to 16-bit bus width

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3.5.5 Register Data Access

(1) Writing when CPU interface 16-bit width is selected

When 16-bit width is selected, A6 to 1 becomes valid.

Further, *HWR pin becomes valid as the write strobe for D15 to 8 while *LWR pin for D7 to 0 at the time of data

writing.

(2) Writing when CPU interface 8-bit width is selected

When 8-bit width is selected, A6 to 0 becomes valid.

Further, *LWR pin becomes valid as the write strobe at the time of data writing. Here, fix the *HWR/*BYTE pin to

“L” level.

Note: The above figures are not applicab le when accessing the FIFO Data Register.

A6~1

D15~8

LWR

HWR

D7~0

Valid a dress

A6~0

D7~0

LWR

HWR/

BYTE

Valid adress

"L"

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3.5.6 Clock

48 MHz clock is needed for the internal operation of the M66291.

A built-in PLL enables an external clock of 6, 12, 24, or 48 MHz to be input. Selection is realized by XTAL bit

of the USB Operation Enable Register. When an external 48 MHz clock is used, the PLL is not needed, so the

PLL operation should be disabled.

A built-in oscillation buffer enables the device to be clocked from a crystal unit.

The device is set to standby state by the USB Operation Enable Register. Oscillation is halted (clock input

halted) by XCKE bit, PLL is halted by PLLC bit, and clock supply to the USB block is halted by SCKE bit.

To prevent unstable behavior, clock supply to USB block must be applied as follow:

a. Enables clock input by the XCKE,

b. Wait until oscillation stabilizes,

c. Start PLL by the PLLC bit,

d. Wait until PLL oscillation stabilizes (less than 1ms),

e. then start clock supply to USB block by the SCKE bit.

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ELECTRICAL CHARACTERISTICS

4.1 Absolute Maximum Ratings

Symbol Parameter Ratings Unit

CoreVcc USB Core supply voltage -0.3 ~ +4.2 V

IOVcc System interface supply voltage -0.3 ~ +6.5 V

Vbus Vbus input voltage -0.3 ~ +5.5 V

VI(IO) System interface input voltage -0.3 ~ IOVcc+0.3 V

VO(IO) System interface output voltage -0.3 ~ IOVcc+0.3 V

Pd Power dissipation 400 mW

Ts t g Storage temperature -55 ~ +150 °C

4.2 Recommended Operating Conditions

Ratings UnitSymbol Parameter

Min. Typ. Max.

To p r = 0 ~ +70 °C 3.0 3.3 3.6 VCoreVcc USB Core supply voltage

To p r = -20 ~ +85 °C 3.15 3.3 3.45 V

5V 4.5 5.0 5.5 VIOVcc System interface supply

voltage 3V 2.7 3.3 3.6 V

GND Supply voltage 0 V

VI(IO) System interface input voltage 0 IOVcc V

VI(Vbus) Input voltage (only Vbus input) 0 5.25 V

VO(IO) System interface output voltage 0 IOVcc V

USB transfer state 0 +25 +70 °CTo p r Operating temperature

Not USB transfer state -20 +25 +85 °C

Normal input 500 nstr, tf Input rise, fall time

Schmidt trigger input 5 ms

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4.3 Electrical Characteristics (IOVcc=2.7~3.6V,CoreVcc=3.0~3.6V)

Limits UnitSymbol Parameter Condition

Min. Typ. Max.

VIH "H" input voltage CoreVcc = 3.6V 2.52 3.6 V

VIL "L" input voltage

Xin

CoreVcc = 3.0V 0 0.9 V

VIH "H" input voltage IOVcc = 3.6V 0.7IOVcc 3.6 V

VIL "L" input voltage

Note1

IOVcc = 2.7V 0 0.3IOVcc V

VT+ Threshold voltage in positive

direction 1.4 2.4 V

VT- Threshold voltage in negative

direction 0.5 1.65 V

VTH Hysteresis voltage

Note 2 IOVcc = 3.3V

0.8 V

VO H "H" output voltage IOH = -50uA 2.6 V

VO L "L" output voltage

Xout CoreVcc = 3.0V

IOL = 50uA 0.4 V

VO H "H" output voltage IOH = -2mA IOVcc-0.4 V

VO L "L" output voltage

Note 3 IOVcc = 2.7V

IOL = 2mA 0.4 V

VO H "H" output voltage IOH = -4mA IOVcc-0.4 V

VO L "L" output voltage

Note 4 IOVcc = 2.7V

IOL = 4mA 0.4 V

VT+ Threshold voltage in positive

direction 1.4 2.4 V

VT- Threshold voltage in negative

direction

Note 5 CoreVcc=3.3V

0.5 1.65 V

II H "H" input current VI = IOVcc 10 uA

II L "L" input current

IOVcc = 3.6V

VI = GND -10 uA

IOZH "H" output current in off status VO = IOVcc 10 uA

IOZL "L" output current in off status

15-0

IOVcc = 3.6V

VO = GND -10 uA

Rd v Pull down resistance Note 5 500 kΩ

Rd t Pull down resistance Note 6 50 kΩ

Icc(A) Average supply current in

operation mode Note 7 f(Xin)=48MHz,IOVcc=3.6V,

CoreVcc=3.6V,USB transmit state 15 30 mA

Icc(S) Supply current in static mode Note 7 Oscillator disable, PLL disable,

USB transceiver enable,

TrON=H/L output

*CS,*HWR/*BYTE,*LWR,

*Dack0,*Dack1=IOVcc,

D15-0=0 ~ IOVcc,

Other input VI=IOVcc or GND

IOVcc = 3.6V,CoreVcc=3.6V

Vbus=5.0V, suspend state

30 200 uA

Icc(S) Supply current in static mode Note 7 Oscillator disable, PLL disable,

USB transceiver enable,

TrON=Hi-Z

*CS,*HWR/*BYTE,*LWR,

*Dack0,*Dack1=IOVcc,

D15-0=0 ~ IOVcc,

Other input VI=IOVcc or GND

IOVcc = 3.6V,CoreVcc=3.6V

Vbus=GND, H/W reset state

10 100 uA

M66291GP/HP

Rev1.01 2004.11.01 page 104 of 122

Note 1: A6-1, TEST input pins and D15-0 input/output pins

Note 2: *CS, *RD, *LWR, *HWR/*BYTE, *Dack0, *Dack1, *TC1, *RST input pins

Note 3: *INT0, *Dreq0, *Dreq1 output pins

Note 4: D15-0 input/output pins, *INT1/SOF output pins

Note 5: Vbus input pin

Note 6: TEST input pin

Note 7: The supply current is the total of IOVcc, CoreVcc.

M66291GP/HP

Rev1.01 2004.11.01 page 105 of 122

4.4 Electrical Characteristics (IOVcc=4.5~5.5V,CoreVcc=3.0~3.6V)

Limits UnitSymbol Parameter Condition

Min. Typ. Max.

VIH "H" input voltage CoreVcc = 3.6V 2.52 3.6 V

VIL "L" input voltage

Xin

CoreVcc = 3.0V 0 0.9 V

VIH "H" input voltage IOVcc = 5.5V 0.7IOVcc 5.5 V

VIL "L" input voltage

Note 1

IOVcc = 4.5V 0 0.3IOVcc V

VT+ Threshold voltage in positive

direction 2.3 3.7 V

VT- Threshold voltage in negative

direction 1.25 2.3 V

VTH Hysteresis voltage

Note 2 IOVcc = 5.0V

0.8 V

VO H "H" output voltage IOH = -50uA 2.6 V

VO L "L" output voltage

Xout CoreVcc = 3.0V

IOL = 50uA 0.4 V

VO H "H" output voltage IOH = -2mA 4.1 V

VO L "L" output voltage

Note 3 IOVcc = 4.5V

IOL = 2mA 0.4 V

VO H "H" output voltage IOH = -4mA 4.1 V

VO L "L" output voltage

Note 4 IOVcc = 4.5V

IOL = 4mA 0.4 V

VT+ Threshold voltage in positive

direction 1.4 2.4 V

VT- Threshold voltage in negative

direction

Note 5 CoreVcc=3.3V

0.5 1.65 V

II H "H" input current Vi= IOVcc 10 uA

II L "L" input current

IOVcc = 5.5V

Vi = GND -10 uA

IOZH "H" output current in off status Vo = IOVcc 10 uA

IOZL "L" output current in off status

15-0

IOVcc = 5.5V

Vo = GND -10 uA

Rd v Pull down resistance Note 5 500 kΩ

Rd t Pull down resistance Note 6 50 kΩ

Icc(A) Average supply current in

operation mode Note 7 f(Xin)=48MHz,IOVcc=5.5V,

CoreVcc=3.6V,USB transmit state 15 30 mA

Icc(S) Supply current in static mode Note 7 Oscillator disable, PLL disable,

USB transceiver enable,

TrON=H/L output

*CS,*HWR/*BYTE,*LWR,

*Dack0,*Dack1=IOVcc,

D15-0=0 ~ IOVcc,

Other input VI=IOVcc or GND

IOVcc = 5.5V,CoreVcc=3.6V

Vbus=5.0V, suspend state

30 200 uA

Icc(S) Supply current in static mode Note 7 Oscillator disable, PLL disable,

USB transceiver enable,

TrON=Hi-Z

*CS,*HWR/*BYTE, *LWR,

*Dack0,*Dack1=IOVcc,

D15-0=0 ~ IOVcc,

Other input VI=IOVcc or GND

IOVcc = 5.5V,CoreVcc=3.6V

Vbus=GND,H/W reset state

10 100 uA

M66291GP/HP

Rev1.01 2004.11.01 page 106 of 122

Note 1: A6-1, TEST input pins and D15-0 input/output pins

Note 2: *CS, *RD, *LWR, *HWR/*BYTE, *Dack0, *Dack1, *TC1, *RST input pins

Note 3: *INT0, *Dreq0, *Dreq1 output pins

Note 4: D15-0 input/output pins, *INT1/SOF output pins

Note 5: Vbus input pin

Note 6: TEST input pin

Note 7: The supply current is the total of IOVcc, CoreVcc.

M66291GP/HP

Rev1.01 2004.11.01 page 107 of 122

4.5 Electrical Characteristics (D+/D-)

4.5.1 DC Characteristics

Limits UnitSymbol Parameter Test condition

Min. Typ. Max.

VDI Differential input sensitivity |(D+)-(D-)| 0.2 V

VCM Differential common mode range 0.8 2.5 V

VSE Single ended receiver threshold 0.8 2.0 V

VOL "L" output voltage RL of 1.5KΩ to 3.6V 0.3 V

VOH "H" output voltage

CoreVcc =

3.0V RL of 1.5KΩ to GND 2.8 3.6 V

IOZL "L" output current in off status VO =0V -10 10 uA

IOZH "H" output current in off status

CoreVcc =

3.6V VO =3.6V -10 10 uA

Ro(Pch) Output impedance VO =0V 4 7 15 Ω

Ro(Nch) Output impedance

CoreVcc =

3.3V VO =3.3V 4 7 15 Ω

4.5.2 AC Characteristics

Limits UnitSymbol Parameter Test condition

Min. Typ. Max.

tr Rise transiti on time 10% to 90% of the data signal :

amplitude CL=50pF 4 20 ns

tf Fall transition time 90% to 10% of the data signal :

amplitude CL=50pF 4 20 ns

TRFM Rise/fall time matching tr/tf 90 110 %

VCRS Output signal crossov er voltage CL=50pF 1.3 2.0 V

M66291GP/HP

Rev1.01 2004.11.01 page 108 of 122

4.6 Switching Characteristics (IOVcc=2.7~3.6V or 4.5~5.5V)

LimitsSymbol Parameter Test conditions

Min. Typ. Max.

Unit Refer

No.

ta(A) Address access time 40 ns 1

tv(A) Data vali d time after address 0 ns 2

ta(CTRL) Control access time 30 ns 3

tv(CTRL) Data valid time after control 0 ns 4

ten(CTRL) Control output enable time 0 20 ns 5

tdis(CTRL) Output disable time after control 0 20 ns 6

tdis(CTRL-

Dreq )

Dreq disable time after control 50 ns 7

tdis(Dack -

Dreq )

Dreq disable time after Dack 50 ns 8

ta(Dack) Dack access time 30 ns 9

ten(Dack) Output enable time after Dack CL=50pF 0 20 ns 10

tv(Dack) Data valid time after Dack 0 ns 11

tdis(Dack) Output disable time after Dack 0 20 ns 12

tdis(CTRLH

-Dreq )

Dreq disable time after control 50 ns 13

td(CTRL-

INT)

INT negate delay time 250 ns 14

twh(INT) INT "H" pulse width 650 ns 15

twh(Dreq ) Dreq "H" pulse width 50 ns 16

ten(Dack -

Dreq )

Dreq enable time after Dack 30 ns 17

ten(CTRL-

Dreq )

Dreq enable time after control 50 ns 18

M66291GP/HP

Rev1.01 2004.11.01 page 109 of 122

4.7 Timing Requirements (IOVcc=2.7~3.6V or 4.5~5.5V)

LimitsSymbol Parameter Test conditions

Min. Typ. Max.

Unit Refer

No.

tsuw(A) Address write setup time 30 ns 30

tsur(A) Address read setup time 0 ns 31

thw(A) Address write hold time 0 ns 32

thr(A) Address read hold time 30 ns 33

tw(CTRL) Control pulse width (Write) 30 ns 34

trec(CTRL) Control recovery time (FIFO) 30 ns 35

trecr(CTRL) Control recovery time (REG) 15 ns 36

tw(Dack) Dack pulse width 30 ns 37

tsu(D) Data setup time 20 ns 38

th(D) Data hold time 0 ns 39

tw(cycle) F IFO access cycle time 100 ns 40

tsud(A) DMA address setup time 15 ns 41

thd(A) DMA address hold time 0 ns 42

tw(RST) Reset pulse width 100 ns 43

tst(RST) Control start time after RESET 500 ns 44

tsu(BYTE) Byte mode setup time 250 ns 45

th(BYTE) Byte mode hold time 250 ns 46

twr(CTRL) Control pulse width (Read) 50 ns 47

td1(Dack-TC) TC delay time 1 0 ns 48

td2(Dack-TC) TC delay time 2 30 ns 49

M66291GP/HP

Rev1.01 2004.11.01 page 110 of 122

4.8 Measurement circuit

4.8.1 Pins except for USB buffer block

4.8.2 USB buffer block

CLRL=1kΩ

SW2

SW1

Elements to

be m easured

P.G.

RL=1kΩ

Vcc

Input

tdis(CTRL(LZ))

tdis(CTRL(HZ))

ta(CTRL(ZL))

ta(CTRL(ZH))

Item SW1 SW2

open

(1) Input pulse level : 0 ~ 3.3V, 0 ~ 5.0V

Input pulse rise/fall time : tr,tf=3ns

Input tim ing standard voltage : IO V c c/2

O utput tim ing judge voltage : IOV cc /2

(Th e td is ( L Z ) is jud g ed b y 10 % of th e

outpu t amp litu d e and the td is (HZ ) b y

90 % of th e outp u t amp litud e.)

(2 ) Th e electr ostatic capacit y CL in clud es

the s tr ay c apacitance of th e wire

connection and the input c apac itance

of th e pr ob e.

50Ω

GND

D15-0

D 15-0 other output

D+

RL=15kΩ

RL=27Ω

Vcc

RL=1.5KΩ

D-

RL=15kΩ

RL=27Ω

Vcc

GND

Elements to

be m easured

(1 ) Th e tr a n d tf are ju d g ed b y th e tran sition time o f

the 10% amplitude point and 90% amplitude point

resp ectively.

(2 ) Th e electrostatic cap acity CL inclu d es the s tr ay

capac itanc e of the w ire connection and the

in p u t c ap acitan c e of th e p rob e .

M66291GP/HP

Rev1.01 2004.11.01 page 111 of 122

4.9 Timing Diagram

4.9.1 CPU interface timing

(1-1) Write timing (*RD=”H”)

(1-2) Read timing (*LWR=”H”, *HWR=”H”)

Address is established

tsuw(A) thw(A)

tw(cycle)

tw(CTRL) trec(CTRL), trecr(CTRL)

35 36

No te 1

Note 1

D ata is established

tsu(D) th(D)

38 39

A6-1

(A6-0)

LWR

(HWR)

D15-0

(D7-0)

No te 2

No te 7

A ddress is established

31 tsur(A) thr(A) 33

tw(cycle)

twr(CTRL) trec(CTRL), trecr(CTRL)

N ote 1

N ote 3

Da ta is established

tv(CTRL)

tdis(CTRL)

A6-1

(A6-0)

D15-0

(D7-0)

5ten(CTRL)

tv(A)

35 36

ta(CTRL)

ta(A) 1

N ote 7

M66291GP/HP

Rev1.01 2004.11.01 page 112 of 122

Note 1: tw(cycle), trec(CTRL) are necessary for making access to FIFO .

Further trecr(CTRL) is valid at the time of register access.

Note 2: Writing through t he c ombination of *CS, *HWR a nd *LWR is carried out during the ov erlap of ac tiv e (“L”).

The specification from the rising edge is valid from the earliest inactive signal.

The specification of pulse width becomes valid during the overlap of active (“L”).

Note 3: Reading through the combination of *CS, *RD is carried out during the overlap of active (“L”).

The specification from the falling edge is valid from the latest active signal.

The specification from the rising edge is valid from the earliest inactive signal.

The specification of pulse width becomes valid during the overlap of active (“L”).

Note 7: In 8-bit Mode, D7~0 and A6~0 become valid.

M66291GP/HP

Rev1.01 2004.11.01 page 113 of 122

4.9.2 DMA Transfer Timing 1

When set to Cycle Steal Transfer (DMA Transfer Mode Register: BUST = 0)

(2-1) Write timing 1 (DMAEN=1, DFORM=00)

(2-2) Read timing 1 (DMAEN=1, DFORM=00)

tw(CTRL)

Note 4

D ata is established

tsu(D) th(D)

38 39

Dack

LWR

(HWR)

D15-0

(D7-0)

Dreq

ten(Dack-Dreq)

ten(CTRL-Dreq)

tdis(CTRL-Dreq)

twh(Dreq) 16

Note 5

Note 7

twr(CTRL) 47

D ata is e stab lishe d

tv(CTRL)

tdis(CTRL)

D15-0

(D7-0)

5ten(CTRL) 4

ta(CTRL)

N ote 4

Dack

Dreq

ten(CTRL-Dreq)

tdis(CTRL-Dreq)

twh(Dreq) 16

ten(Dack-Dreq)

Note 6

Note 7

M66291GP/HP

Rev1.01 2004.11.01 page 114 of 122

Note 4: *Dack="L" level is the condition for inactive *Dreq, and the latter signal of twh(Dreq) or ten(CTRL-Dreq)

becomes valid as the specification o f active *Dreq at the time of next DMA transfer.

Note 5: Writing through the combination of *Dack, *HWR and *LWR is carried out du ring the overlap of active (“L”).

The specification of the rising edge is valid from the earliest inactive signal.

The specification of pulse width is valid during the overlap of active (“L”).

Note 6: Reading through the combination of *Dack and *RD is carried out during the overlap of active (“L”).

The specification from the falling edge is valid from the latest active signal.

The specification from the rising edge is valid from the earliest inactive signal.

The specification of pulse width is valid during the overlap of active (“L”).

Note 7: In 8-Bit Mode, D7~0 becomes valid.

M66291GP/HP

Rev1.01 2004.11.01 page 115 of 122

(2-3) Write timing 2 (DMAEN=1, DFORM=01)

(2-4) Read timing 2 (DMAEN=1, DFORM=01)

Note 4: *Dack="L" level is the condition for inactive *Dreq, and the latter signal of tw h(Dreq) or ten(Dack-Dreq)

becomes valid as the specification of active *Dreq at the time of next DMA transfer.

Note 7: In 8-Bit Mode, D7~0 becomes valid.

No te 4

Data is established

tsu(D) th(D)

38 39

Dack

D15-0

(D7-0)

Dreq

ten(Dack-Dreq)

tdis(Dack-Dreq)

twh(Dreq) 16

No te 7

tw(Dack) 37

D ata is establishe d

tv(Dack)

tdis(Dack)

D15-0

(D7-0)

10 ten(Dack) 11

No te 4

Dack

Dreq

ten(CTRL-Dreq) 18

tdis(Dack-Dreq) 8

twh(Dreq) 16

tw(Dack) 37

ta(Dack)

Note 7

M66291GP/HP

Rev1.01 2004.11.01 page 116 of 122

(2-5) Write timing 3 (DMAEN=1, DFORM=10) (*RD=”H”)

Note 2: Writing through the combination of *CS, *HWR and *LWR is carried out during the overlap of active (“L”).

The specification of the rising edge is valid from the earliest inactive signal.

The specification of pulse width is valid during the overlap of active (“L”).

Note 7: In 8-Bit Mode, D7~0 and A6~0 become valid.

A ddress is estab lished

tsud(A) thd(A) 42

tw(CTRL)

D ata is establishe d

tsu(D) th(D)

38 39

A6-1

(A6-0)

LWR

(HWR)

D15-0

(D7-0)

tdis(CTRLH-Dreq) twh(Dreq)

13 16

ten(CTRL-Dreq) 18

Dreq

Note 7

Note 2

No te 2

M66291GP/HP

Rev1.01 2004.11.01 page 117 of 122

(2-6) Read timing 3 (DMAEN=1, DFORM=10) (*LWR=”H”, *HWR=”H”)

Note 3: Reading through the combination of *CS and *RD is carried out during the overlap of active (“L”).

The specification of the falling edge is valid from the latest active signal.

The specification of the rising edge is valid from the earliest inactive signal.

The specification of pulse width becomes valid during the overlap of active (“L”).

Note 7: In 8-Bit Mode, D7~0 and A6~0 become valid.

A ddress is established

31 tsur(A) thr(A) 33

twr(CTRL) 47

D ata is estab lished

tv(CTRL)

tdis(CTRL)

A6-1

(A6-0)

D15-0

(D7-0)

5ten(CTRL)

tv(A)

ta(CTRL)

ta(A) 1

ten(CTRL-Dreq) 18

Dreq

tdis(CTRL-Dreq) 7thw(Dreq) 16

Note 7

No te 3

M66291GP/HP

Rev1.01 2004.11.01 page 118 of 122

4.9.3 DMA Transfer Timing 2

When set to Burst Transfer (DMA Transfer Mode Register : BUST=1)

(3-1) Write timing (DMAEN=1, DFORM=00)

(3-2) Read timing (DMAEN=1, DFORM=00)

Note 5: Writing through the combination of *Dack, *HWR a nd *LWR is carried out during the o verlap of active (“L”):

The specification of the rising edge is valid from the earliest inactive signal.

The specification of pulse width becomes valid during the overlap of active (“L”).

Note 6: Reading through the combination of *Dack and *RD is carried out during the overlap of active (“L”).

The specification from the falling edge is valid from the latest active signal.

The specification from the rising edge is valid from the earliest inactive signal.

The specification of pulse width becomes valid during the overlap of active (“L”).

Note 7: In 8-Bit Mode, D7~0 becomes valid.

tsu(D) th(D)

38 39

LWR

(HWR)

D15-0

(D7-0)

tdis(CTRL-Dreq)

Dreq

tw(cycle)

tw(CTRL) trec(CTRL)

34 35

Dack

No te 5

No te 7

tv(CTRL)

LWR

(HWR)

D15-0

(D7-0)

tdis(CTRL-Dreq)

Dreq

twr(CTRL) trec(CTRL)

47 35

Dack

ta(CTRL)

tw(cycle)

No te 7

No te 6

tv(CTRL)

LWR

(HWR)

D15-0

(D7-0)

tdis(CTRL-Dreq)

Dreq

twr(CTRL) trec(CTRL)

47 35

Dack

ta(CTRL)

tw(cycle)

No te 7

No te 6

M66291GP/HP

Rev1.01 2004.11.01 page 119 of 122

(3-3) Write timing (DMAEN=1, DFORM=10)

(3-4) Read timing (DMAEN=1, DFORM=10)

tv(CTRL)

LWR

(HWR)

D15-0

(D7-0)

tdis(CTRL-Dreq)

Dreq

twr(CTRL) trec(CTRL)

47 35

ta(CTRL)

tw(cycle)

Address is

established Address is

established A ddress is

established

tsur(A) thr(A)

31 33

A6-1

(A6-0)

ta(A)

tv(A) 2

Note 7

No te 6

tsu(D) th(D)

38 39

LWR

(HWR)

D15-0

(D7-0)

tdis(CTRL-Dreq)

Dreq

tw(cycle)

tw(CTRL) trec(CTRL)

34 35

Address is

established Address is

established

tsuw(A) thw(A)

30 32

A6-1

(A6-0)

No te 5

No te 7

M66291GP/HP

Rev1.01 2004.11.01 page 120 of 122

Note 5: Writing through the combination of *Dack, *HWR and *LWR is carried out du ring the overlap of active (“L).

The specification from the rising edge is valid from the earliest inactive signal.

The specification of pulse width becomes valid during the overlap of active (“L”).

Note 6: Reading through the combination of *Dack and *RD is carried out during the overlap of active (“L”).

The specification from the falling edge is valid from the latest active signal.

The specification from the rising edge is valid from the earliest inactive signal.

The specification of pulse width becomes valid during the overlap of active (“L”).

Note 7: In 8-Bit Mode, D7~0 becomes valid.

M66291GP/HP

Rev1.01 2004.11.01 page 121 of 122

(3-5) TC timing

4.10 Interrupt Timing

4.11 Reset Timing

Note 2: Writing through the combination of *CS, *HWR and *LWR is carried out during the overlap of active (“L”).

The specification from the rising edge is valid from the earliest inactive signal.

td1(Dack-TC)

Dack

td2(Dack-TC)

Dack

td(CTRL-INT)

Note 2

twh(INT)

INT

CS, LWR

(HWR)

tst(RST)

tw(RST)

N ote 2

RST

CS, LWR

(HWR)

M66291GP/HP

Rev1.01 2004.11.01 page 122 of 122

4.12 Bus Interface Select Timing

"L"or"H" fixed

RST

HWR/BYTE

tsu(BYTE) th(BYTE)

REVISION HISTORY M66291 Data Sheet

Description

Rev. Date Page Summary

1.00 Apr 9, 2001 - F irst edition issued

1,6 Modified:

USB Specificati on Revision 2.0

3Added:

M66291HP Pin Configration

9Moved:

How to Read Register Tables

10,42,43,60,

69,77,78 Modified:

M66291

102 Modified:

4.2 Recommended Operating Conditions (CoreVcc,Topr)

1.01 Nov 1, 2004

125 Added:

52PJV-A PKG Code.

LQFP48-P-77-0.50 –

Weight(g)

–

JEDEC Code

EIAJ Package Code Lead Material

Cu Alloy

48P6Q-A Plastic 48pin 7✕7mm body LQFP

–

0.1

–

––

0.2

–

––

–

–––

–

Symbol Min Nom Max

Dimension in Millimeters

0.225 ––

I21.0 ––

MD7.4 ––

ME7.4

8°0°0.1

1.0 0.650.50.35 9.29.08.8 9.29.08.8 0.5 7.17.06.9 7.17.06.9 0.1750.1250.105 0.270.220.17 1.4

01.7

48 37

I2Recommended Mount Pad

A1A2

Detail F Lp

Lp 0.45

–

0.6

0.25

–

0.75

–

0.08

bxM

MMP

52PJV-A Plastic 52pin 7 X 7mm body VQFN

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Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999

Renesas Technology (Shanghai) Co., Ltd.

26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China

Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952

Renesas Technology Singapore Pte. Ltd.

1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

RENESAS SALES OFFICES

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