I] CATALYST Preliminary SEMICONDUCTOR CAT28LV256 256K-Bit CMOS E?PROM FEATURES @ 3.0V to 3.6V Supply m CMOS and TTL Compatible /O m Read Access Times: 250/300/350 ns m@ Automatic Page Write Operation: m Low Power CMOS Dissipation: - 1 to 64 Bytes in 10ms ~ Active: 8 mA Max. Page Load Timer Standby: 100 WA Max. m@ End of Write Detection: i . Toggle Bit @ Simple Write Operation: = 099 : On-Chip Address and Data Latches ~ DATA Polling Self-Timed Write Cycle with Auto-Clear @ Hardware and Software Write Protection @ Fast Write Cycle Time: @ 100,000 ProgranvVErase Cycles ~ 10ms Max. m 100 Year Data Retention @ Commercial and Industrial! Temperature Ranges DESCRIPTION The CAT28LV256 is a fast, low power, low voltage CMOS E?PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and Vcc power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28LV256 features hardware and software write protection and an internal Error Correction Code (ECC) for extremely high reliability. The CAT28LV256 is manufactured using Catalysts advanced CMOS floating gate technology. Itis designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP, 32-pin PLCC or 32- pin PLCC, and TSOP, packages. BLOCK DIAGRAM ADDR. BUFFER ROW 32,768 x 12 AeA - E2PROM 4 DECODER & LATCHES =2P RON INADVERTENT HIGH VOLTAGE > t Voc WRITE GENERATOR 64 BYTE PAGE PROTECTION CE 14 ECC LOGIC OE ______-_ ] CONTROL WE Loaic f V/O BUFFERS DATA POLLING TIMER AND TOGGLE BIT VOo.vO7 AovAs , A ALATCHES " COLUMN DECODER 6096 FHD FO2 1996 by Catalyst Semiconductor, Inc. 8-71 Characteristics subject to change without noticeCAT28LV256 Preliminary PIN CONFIGURATION PIN FUNCTIONS DIP Package (P) PLCC Package (N) Pin Name Function TV SI oO asa fe 28 FE) Voc ESEV OSE Ao-A14 Address Inputs AiO 2 27 FI WE VWOo-VO7 Data Inputs/Outputs A773 26 FI Aig 43 2 1 323130 - 446004 25 Dl Ag Ag C5 2917] Ag CE Chip Enable As 5 24 Flag 45S 281 Ag OE Output Enable Agl] 6 23 FP Ay Ag 7 27070 Any AgQh7 22 PoE 4gC] 8 2671 NC WE Write Enable AaoC] 8 21 DB Aigo Ao 9 2517) OE Vv a1 cc 3.0V - 3.6V Suppl A,C}9 20 [CE A; Cy 10 2417 Ato pp AoC] 10 19 1) vO? Ag] 11 23171 CE Vss Ground WOoC] 11 18 vOg = NCC 12 2217) 07 NC No Connect vo, 12 17 Dvog WoO 13 2117 Og vos 13 16 Fi woy 14 15 16 17 18 19 20 VssC 14 15 (1 Og Eg Be Sse 5096 FHD FOt TSOP Top View (8mm X 14mm) (T14) A2 F110 32 FR Ag Ay S42 313 Ay Ap O13 30 FE Ag VOg 4 29 FO Ag vO, 5 28 FI A7 VOg CTY6 27 FO Aya NC C7 26 FT Ay4 Vss O48 25 FX NC NC C9 247 Veco VO3 410 23 FNC VO, O11 22 Ho WE VOs OH 12 21 Ag VOg 4 13 20 FO Ag vO7 (14 19 Fo Ag CE C1 15 18 FS Ay Ayo = 16 17 = GE TSOP Top View (8mm X 13.4mm) (T13) GE cai 0 28 H3 Ajo Ay, oe 27 R=CE Ag 3 26 A 07 Ag 4 25 3 1/05 Aig o45 24 F305 WE c416 23 F 1/04 Voc 47 22 FO 1/03 Aig Crys 21 F7 GND Ai2 COI9 20 HO I/02 A7 4110 19 5 Oy Ag od 18 FE VOo As 4112 17 > Ag Ag 4413 16 Ay A3 01414 15 A= Ao 8-72Preliminary CAT28LV256 CAPACITANCE Ta = 28C, f = 1.0 MHz Symbol Test Max. Units Conditions Cyo Input/Output Capacitance 10 pF Vivo = OV Cin) Input Capacitance 6 pF Vin = OV ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias.................- -55C to +125C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Storage Temperature -65C to +150C . - . . These are stress ratings only, and functional operation Voltage on Any Pin with of the device at these or any other conditions outside of Respect to Ground) ........... -2.0V to+Vcc+2.0V_ those listed in the operational sections of this specifica- Vcc with Respect to Ground ...........+: -2.0V to +7.0V _ tion is not implied. Exposure to any absolute maximum Package Power Dissipation rating for extended periods may affect device perfor- Capability (Ta = 25C) oo... cccccsecccesseeesteeceees 1.0W mance and reliability. Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current ooo ee 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Test Method Neno) | Endurance 104 or 105 Cycles/Byte | MIL-STD-883, Test Method 1033 Tor") Data Retention 100 Years MIL-STD-883, Test Method 1008 Vzap) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 litH!@4 | Latch-Up 100 mA JEDEC Standard 17 MODE SELECTION Mode CE WE OE vo Power Read L H L Dout ACTIVE Byte Write (WE Controlled) VS H Din ACTIVE Byte Write (CE Controlled) VS L H Din ACTIVE Standby, and Write Inhibit H Xx X High-Z STANDBY Read and Write Inhibit x H H High-Z ACTIVE Note: (1) This parameter is tasted initially and after a design or process change that affects the parameter. (2) The minimum OC input voltage is -0.5V. During transitions, inputs may undershoot to 2.0V for periods of tess than 20 ns. Maximum DC voltage on output pins is Voc +0.5V, which may overshoot to Voc +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to Voc +1V. 8-73CAT28LV256 Preliminary D.C. OPERATING CHARACTERISTICS Vcc = 3.0V to 3.6V, unless otherwise specified Limits Symbol! | Parameter Min. | Typ.| Max. |Units Test Conditions lec Vcc Current (Operating, TTL) 15 mA CE = OE = Vi, f = 1Atrc min, All I/O's Open Issc | Vec Current (Standby, CMOS) 150 | pA CE = Vine, All I/Os Open let Input Leakage Current ~1 1 pA Vin = GND to Voc ILo Output Leakage Current -5 5 HA Vout = GND to Vcc, CE = Vin Vin) High Level Input Voltage 2 Vcc +0.3] V Vit Low Level Input Voltage -0.3 0.6 Vv Vou High Level Output Voltage 2 Vv lon = -100nA VoL Low Level Output Voltage 0.3 Vv lo. = 1.0mA Vwi Write Inhibit Voltage 2 Vv Note: (1) Vine = Voc -0.3V to Voc +0.3V. A.C. CHARACTERISTICS, Read Cycle Vcc = 3.0V to 3.6V, unless otherwise specified 28LV256-25 | 28LV256-30 | 28LV256-35 Symbol Parameter Min. Max.| Min. Max. Min. Max.| Units trc Read Cycle Time 250 300 350 ns tce CE Access Time 250 300 350 | ns taa Address Access Time 250 300 350 | ns toe OE Access Time 100 110 110] ns ti") CE Low to Active Output 0 0 0 ns torz\?) GE Low to Active Output 0 0 0 ns tyz(2) CE High to High-Z Output 55 60 60 | ns touz2) | OE High to High-Z Output 55 60 60 | ns ton!) Output Hold from Address Change 0 0 0 ns Note: (1} This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. 8-74Preliminary CAT28LV256 Figure 1. A.C. Testing Input/Output Waveform(1) Voc - 0.3 ZoV INPUT PULSE LEVELS x REFERENCE POINTS 0.6 V 0.0V 28LV256 FO6 Note: (1) Input rise and fall timas (10% and 90%) < 10 ns. Figure 2. A.C. Testing Load Circuit (example) 1.8K DEVICE UNDER TEST OUTPUT + C INCLUDES JIG CAPACITANCE Cy = 100 pF 28LV256 FO6 A.C. CHARACTERISTICS, Write Cycle Vcc = 3.0V to 3.6V, unless otherwise specified 28LV256-25 | 28LV256-30 | 28LV256-35 Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max.| Units twe Write Cycle Time 10 10 10 | ms tas Address Setup Time 0 0 0 ns taH Address Hold Time 100 100 100 ns tcs CE Setup Time 0 0 0 ns tcH CE Hold Time 0 0 0 ns tow?) CE Pulse Time 150 150 150 ns toes OE Setup Time 0 0 0 ns toEH OE Hold Time 0 0 0 ns twp) WE Pulse Width 150 150 150 ns tos Data Setup Time 50 50 50 ns tox Data Hold Time 0 0 0 ns tinit!? Write Inhibit Period After Power-up 5 10 5 10 5 10 | ms tarc(3) Byte Load Cycle Time 0.15 | 100 | 0.15 | 100 | 0.15 | 100] us Note: (1) (2) (3) This parameter is tested initially and after a design or process change that affects the parameter. A write pulse of less than 20ns duration will not initiate a write cycle. however a transition from HIGH to LOW within tg_c max. stops the timer. A timer of duration tgic max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; 8-75CAT28LV256 Preliminary DEVICE OPERATION Byte Write ee Read . Awrite cycle is executed when both CE and WE are low, Data stored in the CAT28LV256 is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. Figure 3. Read Cycle + tac _____ > ADDRESS x x ICE - ae \ / k tog + Ed OE \ } Vi WE a t+tOH2> Loz Hp OH > betHZ > DATA OUT Hien { XX DATA VALID DATAVALID = TAA 28LV256 FOB Figure 4. Byte Write Cycle [WE Controlled] ADDRESS tAly tcs XXKXX < two XAXKXAXAXAXAA rion 4 twp AMM DATA OUT DATA IN OXKXKM) KN HIGH-Z DATA VALID 1OEH ++ 'BLC > OKA 5096 FHO FO6 8-76Preliminary CAT28LV256 Page Write The page write mode of the CAT28LV256 (essentially an extended BYTE WRITE mode) allows from 1 to 64 bytes of data to be programmed within a single E7PROM write cycle. This effectively reduces the byte-write time by a factor of 64. Following an initial WRITE operation (WE pulsed low, for twp, and then high) the page write mode can begin by issuing sequential WE pulses, which load the address and data bytes into a 64 byte temporary buffer. The page address where data is to be written, specified by bits Ag to Ara, is latched on the last falling edge of WE. Each byte within the page is defined by address bits Ao to As (which can be loaded in any order) during the first and subsequent write cycles. Each successive byte load cycle must begin within tsic max of the rising edge of the preceding WE pulse. There is no page write window limitation as long as WE is pulsed low within taic max. Upon completion of the page write sequence, WE must stay high a minimum of tatc max for the internal auto- matic program cycle to commence. This programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. A page write will only write data to the locations that were addressed and will not rewrite the entire page. Figure 5. Byte Write Cycle [CE Controlled] tAH ADDRESS OOM RON OX -e tBLC >] ey = ZY TIA mz TN aa DATA OUT DATA IN DATA VALIO 5096 FHD FO? cE \ [TD [TD [Ts, STs [Ts LTT twP tBLC ADDRESS XX Xx SS -X LAST BYTE BYTEO BYTE1 BYTE 2 Xo n BYTE n+1 BYTE n+2 5006 FHD F10 8-77Figure 8. Toggle Bit CAT28LV256 Pretiminary DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/Ool/O6 are indeterminate) until the programming cycle is com- plete. Upon completion of the self-timed write cycle, all /Os will output true data during a read cycle. Toggle Bit In addition to the DATA Polling feature, the device can determine the completion of a write cycle, while a write cycle is in progress, by reading data from the device. This results in l/Og toggling between one and zero. Once the write is complete, however, I/Og stops toggling and valid data can be read from the device. Figure 7. DATA Polling X ce VW NLS NY =a 1 dF WE \ / letoEH>y Le- tor _ E 7 two > 5096 FHD F114 WE 7 IVSAS\, tOE (1) Note: (1) Beginning and ending state of I/Og is indeterminate. tOES (1) twe 1 2aLV256 F14 8-78Preliminary HARDWARE DATA PROTECTION The following hardware data protection features are incorporated into the CAT28LV256. (1) Vec sense provides write protection when Vcc falls below 2.0V min. (2) Apower on delay mechanism, tint (see AC charac- teristics), provides a 5 to 10 ms delay before a write sequence, after Vcc has reached 2.4V min. (3) Write inhibit is activated by holding any one of OE low, CE high, or WE high. CAT28LV256 (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. SOFTWARE DATA PROTECTION The CAT28LV256 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28LV256 is in the standard operating mode). Figure 9. Write Sequence for Activating Software Data Protection WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AA5A WRITE DATA: Ad ADDRESS: 5555 SOFTWARE DATA PROTECTION ACTIVATED ! WRITE DATA: XX TO ANY ADDRESS (1) WRITE LAST BYTE TO LAST ADDRESS 096 FHD F08 Note: (1) Max., after SDP activation. Write protection is activated at this point whether or not any more writes are completed. Figure 10. Write Sequence for Deactivating Software Data Protection WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AAA WRITE DATA: 80 ADDRESS: 5555 WRITE DATA: AA ADDRESS: 5555 WRITE DATA: 55 ADDRESS: 2AAA y WRITE DATA: 20 ADDRESS: 555 5096 FHD FOR Writing to addresses must occur within taic 8-79CAT28LV256 Preliminary To activate the software data protection, the device must To allow the user the ability to program the device with be sent three write commands to specific addresses with an E2PROM programmer (or for testing purposes) there specific data (Figure 9). This sequence of commands is a software command sequence for deactivating the (along with subsequent writes) must adhere to the page data protection. The six step algorithm (Figure 10) will write timing specifications (Figure 11). Once this is done, reset the internal protection circuitry, and the device will all subsequent byte or page writes to the device must be return to standard operating mode (Figure 12 provides preceded by this same set of write commands. The data reset timing). After the sixth byte of this reset sequence protection mechanism is activated until a deactivate has been issued, standard byte or page writing can sequence is issued, regardless of power on/off transi- commence. tions. This gives the user added inadvertent write pro- tection on power-up in addition to the hardware protec- tion provided. Figure 11. Software Data Protection Timing DATA AA 55 two > ADDRESS 5555 2AAA CE WRITES ENABLED _. - WE 5096 FHD F139 Figure 12. Resetting Software Data Protection Timing DATA AA 55 80 AA 55 20 two | sDP ADDRESS 5555 2AAA 5555 5555 2AAA 5555 RESET DEVICE UNPROTECTED 5096 FHD F14 ORDERING INFORMATION | Prefix Device # | Suffix | CAT 28LV256 N +25 TE7 Optional Endurance Temperature Range Tape & Reel Company Blank = 10,000 Cycle Blank = Commercial (0C to +70C) || | TE7: 500/Reel ID H = 100,000 Cycle | = Industrial (-40C to +85C) TE13: 2000/Reel Product Package Speed Number P: PDIP 25: 250ns N: PLCC 30: 300ns 28LV256 F16 713: TSOP (8mmx13.4mm) 35: 350ns T14: TSOP (8mmx14mm) Notes: (1) The device used in the above example is a CAT28LV256HNI-25TE7 (100,000 Cycle Endurance, PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel}. 8-80