LM48557TLX/NOPB - NATIONAL SEMICONDUCTOR

LM48557

LM48557 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume

Controland Reset

Literature Number: SNAS486C

LM48557 March 9, 2010

Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C

Volume Control and Reset

General Description

The LM48557 is a single supply, mono, ceramic speaker driv-

er with an integrated charge-pump, designed for portable

devices, such as cell phones and portable media players,

where board space is at a premium. The LM48557 charge

pump allows the device to deliver 5.8VRMS from a single 4.2V

supply.

The LM48557 features high power supply rejection ratio

(PSRR), 80dB at 217Hz, allowing the device to operate in

noisy environments without additional power supply condi-

tioning. Flexible power supply requirements allow operation

from 2.7V to 4.5V. The LM48557 features an active low reset

input that reverts the device to its default state. Additionally,

the LM48557 features a 36-step I2C volume control and mute

function. The low power Shutdown mode reduces supply cur-

rent consumption to 0.01µA.

The LM48557’s superior click and pop suppression elimi-

nates audible transients on power-up/down and during shut-

down. The LM48557 is available in an ultra-small 16-bump

micro SMD package (1.965mmx1.965mm).

Key Specifications

■ Output Voltage at VDD = 4.2V

RL = 1µF +22Ω, THD+N ≤ 1% 5.8VRMS (typ)

Features

■Integrated Charge Pump

■Bridge-tied Load Output

■Differential Input

■High PSRR

■I2C Volume and Mode Control

■Reset Input

■Advanced Click-and-Pop Suppression

■Low Supply Current

■Minimum external components

■Micro-power shutdown

■Available in space-saving 16-bump micro SMD package

Applications

■Mobile phones

■PDAs

■Notebook Electronic Devices

■MP3 Players

Boomer® is a registered trademark of National Semiconductor Corporation.

LM48557 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset

Typical Application

30098103

FIGURE 1. Typical Audio Amplifier Application Circuit

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LM48557

Connection Diagrams

TL Package

1.965mm x 1.965mm x 0.6mm

30098112

Top View

Order Number LM48557TL

See NS Package Number TLA1611A

16–Bump micro SMD Marking

30098110

Top View

XY – Date Code

TT – Lot Traceability

G – Boomer Family

M2 – LM48557TL

Ordering Information

Order Number Package Package DWG # Transport Media MSL Level Green Status

LM48557TL 16–Bump micro SMD TLA1611A 250 units on tape and reel 1 RoHS & no Sb/Br

LM48557TLX 16–Bump micro SMD TLA1611A 3000 units on tape and reel 1 RoHS & no Sb/Br

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LM48557

UR Package

1.965mm x 1.965mm x 0.35mm

30098112

Top View

Order Number LM48557UR

See NS Package Number URA1611A

16–Bump micro SMD Marking

30098101

Top View

XY – Date Code

TT – Lot Traceability

G – Boomer Family

N5 – LM48557UR

Ordering Information

Order Number Package Package DWG # Transport Media MSL Level Green Status

LM48557UR 16–Bump micro SMD URA1611A 250 units on tape and reel 1 RoHS & no Sb/Br

LM48557URX 16–Bump micro SMD URA1611A 3000 units on tape and reel 1 RoHS & no Sb/Br

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LM48557

Bump Descriptions

Bump Name Description

A1 SVDD Signal Power Supply

A2 SGND Signal Ground

A3 VCM Common Mode Sense Input

A4 IN- Amplifier Inverting input

B1 OUT- Amplifier Inverting output

B2 OUT+ Amplifier Non-Inverting Output

B3 RESET Active Low Reset Input. Connect to VDD for normal operation.

Toggle between VDD and GND to reset the device.

B4 IN+ Amplifier Non-Inverting Input

C1 CPVSS Charge Pump Output

C2 SCL I2C Serial Clock Input

C3 SDA I2C Serial Data Input

C4 I2CVDD I2C Supply Voltage

D1 C1N Charge Pump Flying Capacitor Negative Terminal

D2 PGND Power Ground

D3 C1P Charge Pump Flying Capacitor Positive Terminal

D4 PVDD Power Supply

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LM48557

Absolute Maximum Ratings (Note 1, Note

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (Note 1) 5.25V

Storage Temperature −65°C to +150°C

Input Voltage −0.3V to VDD +0.3V

Power Dissipation (Note 3) Internally Limited

ESD Rating-Human Body Model

(Note 4) 2kV

ESD Rating-Machine Model

(Note 5) 150V

Junction Temperature 150°C

Thermal Resistance

θJA (typ) - (TLA1611A) 63°C/W

Soldering Information

See AN-1112 "Micro SMD Wafer Level Chip Scale

Package."

Operating Ratings

Temperature Range

TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C

Supply Voltage

PVDD and SVDD 2.7V ≤ VDD ≤ 4.5V

I2CVDD 1.7V ≤ I2CVDD ≤ 4.5V

Electrical Characteristics VDD = 4.2V (Note 1, Note 2)

The following specifications apply for AV = 6dB, RL = 1µF + 22Ω, C1 = 2.2µF, C2 = 2.2µF, f = 1kHz, unless otherwise specified.

Limits apply for TA = 25°C.

Symbol Parameter Conditions

LM48557

Units

Min Typ Max

(Note 7) (Note 6) (Note 7)

VDD Supply Voltage Range 2.7 4.5 V

I2CVDD I2C Supply Voltage Range 1.7 4.5 V

IDD

Quiescent Power Supply

Current VIN = 0V, RL = ∞ 5 8 mA

ISD Shutdown Current Shutdown Enabled 0.01 1 µA

|VOS|Differential Output Offset

Voltage

VIN = 0V, AV = 0dB 3 12 mV

VIN = 0V, AV = 48dB 40 160 mV

VIH Logic High Input Threshold RESET, VDD = 2.7V to 4.5V 1.4 V

VIL Logic Low Input Threshold RESET, VDD = 2.7V to 4.5V 0.4 V

AVGain

Minimum Gain Setting

Volume Control = 000001 -25.5 -25 -24.5 dB

Maximum Gain Setting

Volume Control = 111111 47 48 49 dB

AV(MUTE) Mute Attenuation Volume Control = 000000 –90 dB

RIN Input Resistance 1 3 MΩ

VIN

Common Mode Input Voltage

Range -1 1 VP-P

VOOutput Voltage

RL = 1µF + 22Ω, THD+N = 1%

f = 1kHz 5.5 5.8 VRMS

15.6 16.4 VP-P

f = 5kHz 4.0 VRMS

RL = 2.2µF + 10Ω, THD+N = 1%

f = 1kHz 5.6 VRMS

f = 5kHz 2.9 VRMS

THD+N Total Harmonic Distortion +

Noise VO = 4VRMS, f = 1kHz, AV = 48dB 0.05 %

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LM48557

Symbol Parameter Conditions

LM48557

Units

Min Typ Max

(Note 7) (Note 6) (Note 7)

PSRR Power Supply Rejection Ratio

(Figure 2)

VDD = 4.2V + 200mVP-P (sine),

Inputs AC GND, CIN = 0.1µF, AV = 0dB

fRIPPLE = 217Hz 80 dB

fRIPPLE = 1kHz 80 dB

VDD = 4.2V + 200mVP-P (sine),

Inputs AC GND, CIN = 0.1µF, AV = 48dB

f = 1kHz 15 40 dB

f = 5kHZ 40 dB

CMRR Common Mode Rejection Ratio

(Figure 3)

VCM = 200mVP-P (sine),

CIN = 0.1µF, AV = 48dB

fRIPPLE = 500Hz 16 36 dB

fRIPPLE = 1kHz 37 dB

fSW

Charge Pump Switching

Frequency 230 300 370 kHz

SNR Signal To Noise Ratio VOUT = 5VRMS, f = 1kHz

AV = 48dB 74 dB

∈OS Output Noise AV = 0dB, A-Weighted Filter 20 30 µV

AV = 48dB, A-weighted Filter 1 mV

TWU Wake Up Time From shutdown 5 ms

I2C Interface Characteristics 1.7V ≤ I2CVDD ≤ 4.5V (Notes 1, 2) The following specifications

apply for RPU = 1kΩ to I2CVDD, unless otherwise specified. Limits apply for TA = 25°C.

Symbol Parameter Conditions

LM48557

Units

Min Typ Max

(Note 7) (Note 6) (Note 7)

VIH Logic Input High Threshold SDA, SCL 0.7 x I2CVDD V

VIL Logic Input Low Threshold SDA, SCL 0.3 x I2CVDD V

VOL Logic Output Low Threshold SDA, ISDA = 3.6mA 0.35 V

IOH Logic Output High Current SDA, SCL, I2CVDD = 4.5V 2 µA

SCL Frequency 400 kHz

6 SDA Setup Time 100 ns

5 SDA Stable Time 0 250 900 ns

1 Start Condition Time 100 ns

7 Stop Condition Time 100 ns

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LM48557

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Operating Ratings is not implied. The Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond

such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Operating Ratings except as otherwise modified or specified by the

Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum

allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.

Note 4: Human body model, applicable std. JESD22-A114C.

Note 5: Machine model, applicable std. JESD22-A115-A.

Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Operation Rating at the time of product characterization and are not

guaranteed.

Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.

30098106

FIGURE 2. PSRR Test Circuit

30098104

FIGURE 3. CMRR Test Circuit

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LM48557

Typical Performance Characteristics

THD+N vs Frequency

VDD = 3.6V, ZL = 1µF + 22Ω

AV = 48dB, VO = 2.5V

30098132

THD+N vs Frequency

VDD = 4.2V, ZL = 1µF + 22Ω

AV = 48dB

30098133

THD+N vs Output Voltage

ZL = 1µF + 22Ω, AV = 0dB

30098126

Output Voltage vs Frequency

VDD = 4.2V, ZL = 1µF + 22Ω

THD+N = 1%

30098127

Power Consumption vs Output Voltage

VDD = 3.6V, ZL = 1µF + 22Ω

30098128

Power Consumption vs Output Voltage

VDD = 4.2V, ZL = 1µF + 22Ω

30098129

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LM48557

CMRR vs Frequency

VDD = 4.2V, VRIPPLE = 200mVP-P, AV = 48dB

30098170

PSRR vs Frequency

VDD = 4.2V, VRIPPLE = 200mVP-P

30098135

Output Voltage vs Supply Voltage

ZL = 1µF + 22Ω, THD+N = 1%

30098130

Supply Current vs Supply Voltage

No Load

30098131

Charge Pump Output Voltage vs Load Current

VDD = 4.2V

30098171

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LM48557

Application Information

I2C COMPATIBLE INTERFACE

The LM48557 is controlled through an I2C compatible serial

interface that consists of a serial data line (SDA) and a serial

clock (SCL). The clock line is uni-directional. The data line is

bi-directional (open drain). The LM48557 and the master can

communicate at clock rates up to 400kHz. Figure 4 shows the

I2C interface timing diagram. Data on the SDA line must be

stable during the HIGH period of SCL. The LM48557 is a

transmit/receive slave-only device, reliant upon the master to

generate the SCL signal. Each transmission sequence is

framed by a START condition and a STOP condition (Figure

5). Each data word, device address and data, transmitted

over the bus is 8 bits long and is always followed by an ac-

knowledge pulse (Figure 6). The LM48557 device address is

11011110.

I2C BUS FORMAT

The I2C bus format is shown in Figure 6. The START signal,

the transition of SDA from HIGH to LOW while SCL is HIGH,

is generated, alerting all devices on the bus that a device ad-

dress is being written to the bus.

The 7-bit device address is written to the bus, most significant

bit (MSB) first, followed by the R/W bit. Set R/W = 0; the

LM48557 is a WRITE-ONLY device and will not respond to

R/W = 1. In other words, the LM48557 will not issue an ACK

when R/W = 1. Each address bit is latched in on the rising

edge of the clock. Each address bit must be stable while SCL

is HIGH. After the last address bit is transmitted, the master

device releases SDA, during which time, an acknowledge

clock pulse is generated by the LM48557. If the LM48557 re-

ceives the correct address, the device pulls the SDA line low,

generating an acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit reg-

ister data word is sent. Each data bit should be stable while

SCL is HIGH. The LM48557 has two registers, Mode Control

and Volume Control. The register address and register data

are combined into a single byte, the most significant bit (MSB)

indicates which register is being addressed. To address the

Mode Control register, set the MSB of the data byte to 0, fol-

lowed by seven bits of register data. To address the Volume

Control register, set the MSB of the data byte to 1, followed

by seven bits of register data. After the 8-bit register data word

is sent, the LM48557 sends another ACK bit. The LM48557

supports single and multi-byte write operations, any number

of data bytes can be transmitted to the device between

START and STOP conditions. Following the acknowledge-

ment of the last register data word, the master issues a STOP

bit, allowing SDA to go high while SCL is high.

30098111

FIGURE 4. I2C Timing Diagram

300981g8

FIGURE 5. Start and Stop Diagram

300981e2

FIGURE 6. Example Write Sequence

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LM48557

TABLE 1. Device Address

B7 B6 B5 B4 B3 B2 B1 B0 R/W

Device

Address 1 1 0 1 1 1 1 0

TABLE 2. Control Registers

Name

B7 B6 B5 B4 B3 B2 B1 B0

Mode

Control 0 0 0 0 0 0 MUTE SHDN

Volume

Control 1 0 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

TABLE 3. Mode Control Registers

BIT NAME VALUE DESCRIPTION DEFAULT

SETTING

B0 SHDN 0 Shutdown mode 0

1 Normal operation

B1 MUTE 0 Normal operation 0

1Device mute, AV = -90dB.

B2 RESERVED* X Unused, Set to 0 0

B3 RESERVED* X Unused, Set to 0 0

B4 TESTMODE 0 Set B4 to 0. B4 = 1 enables TESTMODE. See

TESTMODE section. 0

B5 RESERVED* X Unused, Set to 0 0

B6 RESERVED* X Unused, Set to 0 0

B7 REGISTER

ADDRESS 0 Set to 0 to access Mode Control register 0

*RESERVED bits are Don't Cares and are ignored by the device. The state of the RESERVED bits does not affect device operation.

TABLE 4. Volume Control Registers

BIT NAME VALUE DESCRIPTION DEFAULT

SETTING

B0:B5 VOL0:VOL5 See Volume

Control Table Controls amplifier gain/attenuation 0

B6 RESERVED* X Unused, Set to 0 0

B7 REGISTER

ADDRESS 1 Set to 1 to access Volume Control register 1

*RESERVED bits are Don't Cares and are ignored by the device. The state of the RESERVED bits does not affect device operation.

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LM48557

SINGLE AND MULTI-BYTE WRITE OPERATION

The LM48557 supports both single-byte and multi-byte write

operations. A single-byte write operation begins with the mas-

ter device transmitting a START condition followed by the

device address (Figure 7). After receiving the correct device

address, the LM48557 generates an ACK bit. The master de-

vice transmits the register data byte, after which the LM48557

generates and ACK bit. Following the ACK, the master issues

a STOP condition, completing the singly-byte data transfer.

A multi-byte write operation is similar to a single-byte opera-

tion, the master device issues a START condition and device

address, and the LM48557 responds with an ACK (Figure 8).

The master device then transmits the first data byte. Following

the LM48557’s ACK, the master device does not issue a

STOP condition, transmitting a second data byte instead. The

LM48557 responds with an ACK bit. The master device can

continue to issue data bytes, and the LM48557 will respond

with an ACK, until a STOP condition is issued. Once a STOP

condition is issued, the LM48557 ignores the I2C bus until the

master issues the LM48557’s device address.

30098109

FIGURE 7. Single-Byte Write Example

30098105

FIGURE 8. Multi-Byte Write Example

GENERAL AMPLIFIER FUNCTION

The LM48557 is a fully differential ceramic speaker driver that

utilizes National’s inverting charge pump technology to deliv-

er over 5.8VRMS to a 1µF ceramic speaker while operating

from a single 4.2V supply. The low noise, inverting charge

pump generates a negative supply voltage (CPVSS) from the

positive supply voltage (PVDD). The LM48557 takes advan-

tage of the increased head room created by the charge pump

and the bridge-tied load (BTL) architecture, delivering signif-

icantly more voltage than a single-ended, single-supply am-

plifier to the speaker.

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LM48557

TABLE 5. Volume Control Table

VOLUME

STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB)

(MUTE) 0 0 0 0 0 0 -90

2 0 0 0 0 0 1 -25

3 0 0 0 0 1 0 -22

4 0 0 0 0 1 1 -19

5 0 0 0 1 0 0 -16

6 0 0 0 1 0 1 -13

7 0 0 0 1 1 0 -10

8 0 0 0 1 1 1 -8

9 0 0 1 0 0 0 -6

10 0 0 1 0 0 1 -4

11 0 0 1 0 1 0 -2

12 0 0 1 0 1 1 0

13 0 0 1 1 0 0 2

14 0 0 1 1 0 1 4

15 0 0 1 1 1 0 6

16 0 0 1 1 1 1 8

17 0 1 0 0 0 0 10

18 0 1 0 0 0 1 12

19 0 1 0 0 1 0 14

20 0 1 0 0 1 1 16

21 0 1 0 1 0 0 18

22 0 1 0 1 0 1 20

23 0 1 0 1 1 0 22

24 0 1 0 1 1 1 24

25 0 1 1 0 0 0 26

26 0 1 1 0 0 1 28

27 0 1 1 0 1 0 30

28 0 1 1 0 1 1 32

29 0 1 1 1 0 0 34

30 0 1 1 1 0 1 36

31 0 1 1 1 1 0 38

32 0 1 1 1 1 1 40

Do Not Use Volume Steps 33-60 See Table 6

61 1 1 1 1 0 0 42

62 1 1 1 1 0 1 44

63 1 1 1 1 1 0 46

64 1 1 1 1 1 1 48

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LM48557

TABLE 6. Unused Volume Steps

VOLUME

STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 GAIN

(dB)

33 1 0 0 0 0 0 -90

34 1 0 0 0 0 1 -25

35 1 0 0 0 1 0 -22

36 1 0 0 0 1 1 -19

37 1 0 0 1 0 0 -16

38 1 0 0 1 0 1 -13

39 1 0 0 1 1 0 -10

40 1 0 0 1 1 1 -8

41 1 0 1 0 0 0 -6

42 1 0 1 0 0 1 -4

43 1 0 1 0 1 0 0

44 1 0 1 0 1 1 4

45 1 0 1 1 0 0 8

46 1 0 1 1 0 1 12

47 1 0 1 1 1 0 14

48 1 0 1 1 1 1 16

49 1 1 0 0 0 0 18

50 1 1 0 0 0 1 20

51 1 1 0 0 1 0 22

52 1 1 0 0 1 1 24

53 1 1 0 1 0 0 26

54 1 1 0 1 0 1 28

55 1 1 0 1 1 0 30

56 1 1 0 1 1 1 32

57 1 1 1 0 0 0 34

58 1 1 1 0 0 1 36

59 1 1 1 0 1 0 38

60 1 1 1 0 1 1 40

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LM48557

VOLUME CONTROL

The LM48557 has a 64 step volume control, but only 36 steps

are recommended for use. Use steps 1 through 32 and steps

61 through 64 to set the gain of the device. Accessing steps

33 through 60 results in the repeated gain conditions shown

in Table 6. Steps 33 through 60 are not tested and should not

be used.

SHUTDOWN FUNCTION

The LM48557 features a low-power shutdown mode that dis-

ables the device lowers the quiescent current to 0.01µA. Set

bit B0 (SHDN) of the Mode Control register to 0 to disable the

amplifier and charge pump. Set SHDN to 1 for normal oper-

ation. Shutdown mode does not clear the I2C register. When

re-enabled, the device returns to its previous volume setting.

To clear the I2C register, either remove power from the device,

or toggle RESET (see RESET section).

RESET

The LM48557 features an active low reset input. Driving RE-

SET low clears the I2C register. Volume control is set to

000000 (-90dB) and SHDN is set to 0, disabling the device.

While RESET is low, the LM48557 ignores any I2C data. After

the device is reset, and RESET is driven high, the LM48557

remains in shutdown mode with the volume set to -90dB. Re-

enable the device by writing to the I2C register.

MUTE

The LM48557 features a mute mode. Set bit B1 (MUTE) of

the Mode Control register to 1 to mute the device. In mute

mode, the gain is set to -90dB, equivalent to the volume step

1. Set MUTE = 0 to unmute the device. Once unmuted, the

device returns to its previous volume step.

TEST MODE

If enabled, TESTMODE does not affect device performance

under normal operating conditions. Operating above the rec-

ommended supply voltage range with TESTMODE enabled

can result in damage to the device.

PROPER SELECTION OF EXTERNAL COMPONENTS

Power Supply Bypassing/Filtering

Proper power supply bypassing is critical for low noise per-

formance and high PSRR. Place the supply bypass capaci-

tors as close to the device as possible. Place a 1µF ceramic

capacitor from VDD to GND. Additional bulk capacitance may

be added as required.

Charge Pump Capacitor Selection

Use low ESR ceramic capacitors (less than 100mΩ) for opti-

mum performance.

Charge Pump Flying Capacitor (C1)

The flying capacitor (C1) affects the load regulation and out-

put impedance of the charge pump. A C1 value that is too low

results in a loss of current drive, leading to a loss of amplifier

headroom. A higher valued C1 improves load regulation and

lowers charge pump output impedance to an extent. Above

2.2µF, the RDS(ON) of the charge pump switches and the ESR

of C1 and C2 dominate the output impedance. A lower value

capacitor can be used in systems where low maximum output

power requirements.

Charge Pump Hold Capacitor (C2)

The value and ESR of the hold capacitor (C2) directly affects

the ripple on CPVSS. Increasing the value of C2 reduces out-

put ripple. Decreasing the ESR of C2 reduces both output

ripple and charge pump output impedance. A lower value ca-

pacitor can be used in systems where low maximum output

power requirements.

Input Capacitor Selection

Input capacitors block the DC component of the audio signal,

eliminating any conflict between the DC component of the

audio source and the bias voltage of the LM48557. The input

capacitors create a high-pass filter with the input resistors

RIN. The -3dB point of the high pass filter is found using Equa-

tion (1) below.

f = 1 / 2πRINCIN (Hz) (1)

Where the value of RIN is given in the Electrical Characteris-

tics Table.

High pass filtering the audio signal helps protect the speakers.

When the LM48557 is using a single-ended source, power

supply noise on the ground is seen as an input signal. Setting

the high-pass filter point above the power supply noise fre-

quencies, 217Hz in a GSM phone, for example, filters out the

noise such that it is not amplified and heard on the output.

Capacitors with a tolerance of 10% or better are recommend-

ed for impedance matching and improved CMRR and PSRR.

COMMON MODE SENSE

The LM48557 features a common mode sense pin (VCM, pin

A3) that includes additional common mode cancelling circuit-

ry that improves the CMRR. When the volume control is set

at a high gain step such as 48dB, any mismatch in the input

capacitors would degrade CMRR performance significantly.

With the VCM pin connected to the ground of the input source,

it takes the input capacitor mismatches out of the equation

and therefore improves the CMRR. Another advantage with

this feature is that only one input capacitor is needed in the

single-ended configuration as opposed to two well matched

capacitors. See next section for details of different configura-

tions of the LM48857.

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LM48557

SINGLE-ENDED INPUT CONFIGURATION

Ground-Referenced Audio Source

The LM48557 input stage is compatible with ground-refer-

enced input sources, such as CODECs with an integrated

headphone amplifier. Connect either input, IN+ or IN- to the

CODEC output, and connect the unused input and VCM to

the CODEC output ground (Figure 9). An input coupling ca-

pacitor in series with the source and device input is recom-

mended to block the CODEC output offset voltage, minimiz-

ing click and pop and zipper noise during volume transitions.

30098107

FIGURE 9. Single-Ended Input Configuration with a Ground-Referenced Source

NON-GROUND REFERENCED AUDIO SOURCE

Stereo-to-Mono Conversion

The LM48557 can convert a single-ended stereo signal to a

mono BTL signal (Figure 10). Connect the left and right

CODEC outputs in parallel through two equal value resistors

to either IN+ or IN-, and connect the unused input and VCM

to the CODEC ground. Select the value of the resistors based

on the desired frequency response created by the combina-

tion of the input resistor and the input coupling capacitor.

30098108

FIGURE 10. Single-Ended Stereo-to-Mono BTL Conversion

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LM48557

PCB Layout Guidelines

Minimize trace impedance of the power, ground and all output

traces for optimum performance. Voltage loss due to trace

resistance between the LM48557 and the load results in de-

creased output power and efficiency. Trace resistance be-

tween the power supply and ground has the same effect as a

poorly regulated supply, increased ripple and reduced peak

output power. Use wide traces for power supply inputs and

amplifier outputs to minimize losses due to trace resistance,

as well as route heat away from the device. Proper grounding

improves audio performance, minimizes crosstalk between

channels and prevents switching noise from interfering with

the audio signal. Use of power and ground planes is recom-

mended.

Place all digital components and route digital signal traces as

far as possible from analog components and traces. Do not

run digital and analog traces in parallel on the same PCB lay-

er. If digital and analog signal lines must cross either over or

under each other, ensure that they cross in a perpendicular

fashion.

LM48557TL Demoboard Bill of Materials

Designator Quantity Description

U1 1 LM48557TL Differential, Mono, Ceramic Speaker Driver with I2C Volume Control, and Reset

C1, C2, C5, C6, C7 5 CAP CERAMIC 2.2µF 10V X5R 10% 0603

C3, C4 2 CAP .1µF 16V CERAMIC X7R 10% 1206

C8 1 CAP TANT LOESR 10µF 16V 10% SMD

J2 1 CONN SOCKET PCB VERT 16POS .1"

JU1, JU2, JU3, JU4,

VCM, VDD, GND,

I2CVDD, IN+, IN-,

OUT+, OUT-

12 CONN HEADER VERT .100 2POS 30Au

JU5 1 CONN HEADER VERT .100 3POS 30Au

R1, R2 2 RES 5.1K OHM 1/10W 5% 0603 SMD

R3 1 RES 20K OHM 1/10W 5% 0603 SMD

JU1_SH, JU2_SH,

JU3_SH, JU5_SH 4 Jumper Shunt w/handle, 30uin gold plated, 0.100" pitch

www.national.com 18

LM48557

PC Board Layout

30098125

Silk Screen

30098124

Top Layer

30098122

Layer 2 30098123

Layer 3

19 www.national.com

LM48557

30098120

Bottom Layer

30098121

Bottom Silkscreen

www.national.com 20

LM48557

Demo Board Schematic

30098119

FIGURE 11. LM48557 Demo Board Schematic

21 www.national.com

LM48557

Revision History

Rev Date Description

1.0 07/08/09 Initial released.

1.01 07/15/09 Deleted the “Tru-GND...” trademark on the cover page.

1.02 08/05/09 Text edits.

1.03 08/06/09 Fixed a typo error.

1.04 01/11/10 Added the LM48557UR package drawing, top markings, and the marketing outline.

www.national.com 22

LM48557

Physical Dimensions inches (millimeters) unless otherwise noted

16-Bump micro SMD

Order Number LM48557TL

NS Package Number TLA1611A

X1 = 1.965± 0.03 X2 = 1.965 ± 0.03 X3 = 0.6 ± 0.075

23 www.national.com

LM48557

Package Preview

16–Bump micro SMD

NS Package Number URA16XXX

X1 = 1.965 ± 0.03 X2 = 1.965 ± 0.03 X3 = 0.350 ± 0.045

www.national.com 24

LM48557

Notes

25 www.national.com

LM48557

Notes

LM48557 Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset

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