MX9691LG - Macronix International

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

SINGLE CHIP SOLID STATE DISK CONTROLLER

1. FEATURE

Host Interface

• PCMCIA 2.1 and PC Card ATA standard compatible.

- Memory mapped or I/O operation.

• Compatible with all PC Card Services and Socket

Service.

• Fast ATA host-to-buffer burst transfer rates up to

20MB/sec. which support PIO mode 4(16.6MB/sec)

and DMA mode 2(16.6MB/sec).

• Automatic sensing of PCMCIA or True IDE host inter

face.

• Integrated PCMCIA attribute memory of 256 bytes

(CIS)

- CIS and Buffer RAM use same SRAM area to

simplify internal bus design

• PCMCIA card configuration register support.

• Polarity control for Host reset signal.

• PCMCIA twin card support.

• PCMCIA based ATA address decode support.

• Emulate the IBM task file for PC/AT.

• Separate status for Host reset signal and Host program

reset.

• Separate Host and Disk interrupt pins.

Flash Memory Interface

• Support all the control signals to execute read/ write/

erase operation for flash memory.

• Flexible Disk Capacity Configuration for series type or

linear type flash memory

- Upto 32MB(unformatted) capacity for 16 pcs. 16Mbit

linear type flash memory.

- Upto 1GB(unformatted) capacity for 32 pcs. 256Mbit

series type flash memory.

• Flash Memory Power Down or write protect control

support.

• Flash Memory Ready/Busy status detect.

• Inverted data bus control to reduce flash memory

program/erase operation in DOS FAT and ECC code

field.

• Optional store firmware in flash memory array w/o

external ROM while MXIC's MX29F1610(linear type)

used.

- Allow code fetch in Shadow ROM during flash

memory program or erase.

Buffer RAM Mana ger

• Dual port circular Buffer RAM control

• 1KB data Buffer RAM.

• Automatically correct error data in Buffer RAM.

- Single word error correct and double word detect.

• Provide logic to speed up Buffer RAM access.

• Support 8 bit as well as 16 bit transfer on host bus.

DSP core

• High performance MX93011 DSP (21Mips) core.

• 4KB Internal RAM(direct access).

• 2KB Internal expansion RAM(indirect access) for store

data or shadow ROM space.

• ICE debugging mode supported to ease system

verification.

• Lower power and automatic power saving operation.

- Automatic Standby Mode. (Operating Current < 10mA,

VCC=5.5V), wake-up by interrupt signal.

- Very Low Operating Current Sleep Mode.

(<1mA,VCC=5.5V), wake-up by Host reset signal or

Host program reset or ATA command asserted by host.

Technology

• 128 pin LQFP(14X14X1.4 mm3)

• 128 pin TQFP(14X14X1.0 mm3)

• 0.6um Low-power, High-speed CMOS technology.

• 5Volt ± 10% or 3.3Volt ± 5%.

Utility Support

• Provide integrated test environment with 82365SL-

compatible adaptor.

• Firmware upload from host and allows easy upgrade for

custom feature.

• Physical devices test cover basic PCB test after

assembly and more detial analysis.

• Logical sector test cover SSD functionality and data

transfer test.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

2. GENERAL DESCRIPTION

The Macronix's Solid State Disk controller MX9691L is

a wide-range supply voltage(3.3V olt~5V olt) and fully in-

tegrated flash memory controller that provides all the

control logic for PCMCIA/True IDE host and flash

memory. The MX9691L combines 1KB dual-port buffer

and buffer manager, integrated MX93011 DSP core, and

a complete host interface for both the PC Card ATA and

True IDE standard.

The MX9691L provides flexible disk capacity configu-

ration and supports all the control signals to execute

read/write/erase operation for linear type or series type

flash memory chip. It is typically configured with up to

32MB(unfor matted) capacity for 16 pcs. 16Mbit linear

flash memory or 1GB(unformatted) capacity for 32 pcs.

256Mbit series type flash memory while capacity

extention mode is enabled for series type flash memory

used. The MX9691L also provides fle xible architecture

to implement defect management and wear-leveling by

firmware f or series type or linear type flash memory.

In linear mode, the linear type 16 Mbit flash memory is

supported, such as MXIC's MX29F1610 etc. In flash

memory interface there are two banks of flash memory to

be provided. Each bank support 8 pcs. flash memory when

linear type flash memory is used. In series mode, the se-

ries type 16MBit/32Mbit/64Mbit/256Mbit flash memory is

supported, such as Toshiba's TC5816FT/TR or

TC58V32FT, Samsung's KM29N16000T/R or

KM29N32000TS/RS etc. Each bank support or 16 pcs.

flash memory when series type flash memory is used.

The MX9691L is fully compliant with the PC Card ATA

specification. It includes 256 bytes of integrated attr ibute

memory(for the required Card Inf ormation Structure) and

four Card Configuration registers. The PCMCIA device

driver can access the MX9691L's ATA command block

through four different modes by writing the different modes

by writing the configur ation index of the attrib ute memory

configuration option register .

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

3. PIN CONFIGURATION

HA2

REG#

HA1

SPKR

HA0

GNDP

STSCHG

HD0

HD8

HD1

HD9

HD2

HD10

IOIS16#

PWR_RST

TEST

VCCP

GNDP

ROMWR#

ROMCS#

SCTRL#

HLDA#

VCCX32

SWAIT#

GNDX32

DCE#

PCE#

WR#

RD#

FA16

FA15

A14

A13

A12

LED#

GNDP

A11

A10

FA19

FRY/FBY#

INT1#

NMI#

HOLD#

VCCP

WRFLASH0#

WRFLASH1#

FA18

FA17

A15

GNDP

WP#

GNDP

RDFLASH0#

FCE7#

FCE2#

VCCP

FCE1#

FCE0#

GND

FCE6#

FCE5#

FCE4#

FCE3#

VCC

RDFLASH1#

D10

D11

GNDP

D12

D13

D14

D15

SE#

HD3

HD11

HD4

HD12

HD5

HD13

HD6

HD14

GNDP

IREQ#

INPACK#

HD7

HD15

HCE1#

HCE2#

HA10

VCCP

HOE#

IOR#

HA9

GND

IOW#

HA8

VCC

HWE#

HA7

HA6

HA5

HRESET

HA4

WAIT

HA3

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

4. PIN DESCRIPTION

Host Interface

Symbol No. Type Description

HA[10:0] 92,94, I Host address line 10-0.

96-97,99 (CMOS) These pins include internal pull-up resistors.

101-103,

106,109,

113

HD[15:0] 84-89, I/O Host data line 15-0.

116-117, (TTL) These pins include internal bus holder circuit that k eep

121-128 previous state when tri-state.

HOE#,HWE# 104,111 I Host memory read/write/mode select :

(CMOS) Both pins include internal pull-up resistors that is default in

PCMCIA mode.

IOR#,IOW# 107,110 I Host I/O access.

(CMOS) Both pins include internal pull-up resistor .

HRESET/HRESET# 100 I The host reset signal, when active , initializ es the control/

(CMOS) status registers and stops any command in process.

In PCMCIA mode, the signal is activ e high.

In True IDE mode, this signal is activ e low.

This signal include internal pull-down resistor .

W AIT/ IOCHRDY 98 O ,OD W AIT or INPUT CHANNEL READY : In both PCMCIA and

(CMOS) True IDE modes, this signal holds host transf ers until the

controller is ready to respond.

RDY/BSY#/ 119 O , Z READY/BUSY or HOST INTERR UPT : In PCMCIA mode,

IREQ#/ (CMOS) this signal has two functions. In PCMCIA common memory

HOSTINT mode, this signal is ready/busy. It is asserted busy b y the

reset logic, and can be deasserted by the DSP or

represents the ready/busy bit of ATA status register .

In PCMCIA I/O mode, this signal is IREQ#.

In T rue IDE mode, this active high signal is HOSTINT, which,

when enable , send an interrupt to the host.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

Symbol No. Type Description

WP/IOCS16# 83 O ,OD WRITE PROTECT or 16-bit I/O TRANSFER :

(CMOS) In PCMCIA mode, this bit has two functions . In PCMCIA

common-memory mode,this signal indicates write protect.

In PCMCIA I/O mode, when IOIS16# is asserted low, it

indicates that a 16-bit data transfer is active on PCMCIA

bus.

In True IDE mode, the IOCS16# signal indicates that a

16-bit buffer transfer is activ e on the host bus.

This open drain signal is only driven on assertion(low).

REG#/DA CK# 95 I Attribute memory and I/O select :

(CMOS) In PCMCIA mode, this signal is used to select attribute

memory and I/O space. In True IDE mode, this signal is

used during DMA with the DREQ, IOR# and IOW# signals

to transfer data between the host and the MX9691L. This pin

includes an internal pull-up resistor.

HCE1#/ 115 I Card enable 1 or Chip select 0:In PCMCIA mode,this signal

CS1FX# (CMOS) is card enable 1. This signal can enab le either e v en or odd

numbered-address bytes onto HD7:0. In True IDE mode, this

signal accesses the MX9691 command block registers. This

input is ignored during DMA data transfer, i.e. when the

D A CK# signal is lo w. This pin includes an internal pull-up

resistor.

HCE2#/ 114 I Card enable 2 or Chip select 1:

CS3FX# (CMOS) In PCMCIA mode,this signal is card enable 2. This signal

can enable odd numbered-address b ytes onto HD15:8. In

True IDE mode, this signal accesses the MX9691L control

bloc k registers. This pin includes an internal pull-up

resistor.

INPACK#/ DREQ 118 O Input Acknowledge or DMA request :In PCMCIA mode , this

(CMOS) signal is asserted when the MX9691 is configured to respond

to I/O card read cycles at all addresses. In True IDE mode,

this signal is DREQ and is issued during DMA transfers to

indicate that the MX9691L is ready for DMA tr ansf er.

SPKR/D ASP# 93 I/O Speak er or sla ve present : In PCMCIA mode , the

(CMOS) output-enable f or this signal is controlled b y the card

configuration registers. In True IDE mode, this signal is used

as the slav e-present detector.

STSCHG/ 90 I/O Status change or pass diagnostics :In PCMCIA mode, this

PDIAG# (CMOS) signal is used to indicate changes in the RDY/BSY#,WP

signals in card configuration registers. In True IDE mode,

this active low signal is used between two embedded ATA

drive to indicate that the drive in sla v e mode has passed

diagnostics.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

External Memory Bus Interface

Symbol No. Type Description

D[15:0] 33-37,39-41, I/O DSP IO/RAM/ROM/FLASH memory array external data bus.

55-58,60-63 (CMOS) These pins include internal pull- up resistors.

A[15:0] 3-5,8-11, I/O In Free-run mode, these signals are output that used as DSP

22-24,26-31 (CMOS) IO/RAM/ROM e xternal address. A14-A0 are used f or flash

memory array address also. In upgrade mode , these

address are used for ROM address that controlled by

CYH,CYL registers. In ICE-deb ugging mode,these address

are input, asserted by DSP ICE(e xternal MX93011 DSP).

And the internal DSP is disabled at this time .

These pins include internal pull-up resistors.

PCE# 67 I/O In F ree-run mode, this signal is output that is used as

(TTL) e xternal program chip enable. In upgrade mode, this signal

is drived to high. In ICE-debugging mode , this signal is

input, asserted by DSP ICE(e xternal MX93011 DSP). And

the internal DSP is disabled at this time. This pin includes a

bus holder circuit.

DCE# 68 I/O In F ree-run mode, this signal is output that is used as

(TTL) e xternal data chip enable. In upgr ade mode, this signal is

drived to high. In ICE-debugging mode, this signal is input,

asserted by DSP ICE(e xternal MX93011 DSP). And the

internal DSP is disabled at this time . This pin includes a bus

holder circuit.

RD# 65 I/O In F ree-run mode, this signal is output that is used as DSP

(TTL) IO/RAM/ROM e xternal read. In upgrade mode, this signal is

output and asserted when the data register is read in host

interface . In ICE-deb ugging mode, this signal is input, as

serted by DSP ICE(e xternal MX93011 DSP). And the

internal DSP is disabled at this time .

This pin includes a bus holder circuit.

WR# 66 I/O In F ree-run mode, this signal is output that is used as DSP

(TTL) IO/RAM/ROM e xternal write. In upgrade mode, this signal is

drived to high. In ICE-debugging mode, this signal is input,

asserted by DSP ICE(e xternal MX93011 DSP). And the

internal DSP is disabled at this time . This pin includes a bus

holder circuit.

NMI# 15 I Non maskable interrupt pin.

(CMOS) This pin includes an pull-up resistor .

INT1# 14 I/O In F ree-run mode, this signal is input that is used as

(CMOS) interrupt pin. Interrupt will be internally asserted also when

data transfer done , or command end. In ICE-deb ugging

mode, this signal is output and asserted when data transfer

done, or command end. This pin includes an pull-up resistor.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

Symbol No. Type Description

HOLD# 16 I/O In F ree-run mode, this signal is input that is used as holding

(CMOS) DSP clock down and release b us. Bus hold will be internally

asserted also when upgrade mode enable . In ICE-debug

ging mode, this signal is output and asserted when upgrade

mode enable . This pin includes an pull-up resistor.

HLD A# 73 I/O In Free-run mode, this signal is output that is used as ack to

(CMOS) HOLD# signal. This signal will be internally sent to PCMCIA/

ATA interf ace also when upg rade mode enable . In ICE-de

bugging mode , this signal is input and ac k to HOLD# when

upgrade mode enab le.

XF#/SCTRL# 7 4 O Sleep control, this pin can be directly asserted to low while

(CMOS) power down bit is set by DSP. This pin is connected to

e xternal RC circuit. Def ault inactiv e (Logic High).

In ICE-debugging mode , this signal is used to reset DSP.

Flash Memory Interface

Symbol No. Type Description

F A19/CLE 12 O In linear mode, this signal is used as flash memory chip high

(CMOS) address line 19. In series mode, this signal is used as flash

memory chip command latch enable.

F A18/ALE/ 20 I/O In linear mode, this signal is used as flash memory chip high

ICEMODE (CMOS) address line 18. In series mode, this signal is used as flash

memory chip address latch enable. This signal is also used

to select whether the MX9691 initializes in F ree-run mode

or in ICE-debugging mode at po w er-on reset. If this pin go

high, then the MX9691L will switch to Free-run mode at

power-on reset,and if this pin remains low , then the MX9691L

will initializes in ICE-deb ugging mode. This pin includes an

internal pull-up resistor .

ICE-debugging mode select :

ICEMODE=1 —> Free-run mode.

ICEMODE=0 —> ICE-debugging mode.

FA17/EROM 21 I/O(CMOS) This signal is used as flash memory chip high address line

17. This signal is also used to select whether the firmw are

store in linear type flash memory arra y or in separ ate

external ROM at power-on reset. If this pin go high, then the

firmware will be e xecuted in linear type flash memory arra y,

and if this pin remains low , then the firmware will be executed

in separate e xternal ROM.

Store firmware in external ROM or linear type Flash memory

arra y select:

EROM = 0 —> Store in External R OM.

EROM = 1 —> Store in flash memory array.

This pin includes an internal pull-up resistor.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

Symbol No. Type Description

FA[16:15]/ 1-2 I/O This signal is used as flash memory chip high address line

ATADET[1:0] (CMOS) 16-15. These signals are also used to select configuration in

True IDE mode at power-on reset. ATADET1 is connected to

DSP's IPT1. ATADET0 is connected to DSP's IPT0. VDD is

connected to IPT2.

Master/Slav e selection in True IDE mode :

ATADET1 ATADET0 mode selected

1 1 one drive

0 0 master of two drives

1 0 slav e of tw o drives

This power-on configuration can be accessed from PCMCIA/

ATA port 601Ch bit3-2. These pins include internal pull-up

resistors.

RDFLASH1# 5 4 O Flash memory ouptut enable 1 for bank1:

(CMOS) This signal will be asserted by flash memory read operation

when flash memory read address latch, port 601Dh

bit 8= 1(i.e. F A23=1).

Note: Flash memory access window is mapped to 32KW

data and code space 8000h~ffffh.

RDFLASH0# 4 2 O Flash memory ouptut enable 0 for bank0:

(CMOS) This signal will be asserted by flash memory read operation

when flash memory read address latch, port 601Dh

bit 8 = 0(i.e. F A23=0).

WRFLASH1# 19 O Flash memory write enable 1 f or bank1:

(CMOS) This signal will be asserted by flash memory write operation

when flash memory write address latch, port 601Fh

bit 8 = 1(i.e. F A23=1).

WRFLASH0# 18 O Flash memory write enable 0 f or bank0:

(CMOS) This signal will be asserted by flash memory write operation

when flash memory write address latch, port 601Fh

bit 8 = 0(i.e. F A23=0).

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

Symbol No. Type Description

FCE[7:0]# 43-44, O Flash memory chip enable 7-0 :

46-47 (CMOS) In linear mode, These signals are decoded from port 601Dh

49-52 bit 7-5 when flash memory read or port 601Fh bit 7-5 when

flash memory write.

Decoding combination :

bit7 bit6 bit5 FCE[7:0]#

0 0 0 11111110

0 0 1 11111011

0 1 0 11101111

0 1 1 10111111

1 0 0 11111101

1 0 1 11110111

1 1 0 11011111

1 1 1 01111111

In series mode, These are decoded from port 601Dh bit 7-5

only when port 601Eh bit 2 is set.

PWD0#/WP# 32 O In linear mode, this signal is used as deep power-do wn

(CMOS) control of flash memory chips of bank0. PWD0# is activ e

low and also locks out erase or program operation providing

data protection during power transitions . Po wer down pin

PWD0# will be active if FA23=1.

In series mode, this signal is used to protect the device from

inadvertent programming or erasing. WP# is activ e lo w.

PWD1#/SE# 64 O In linear mode, this signal is used as deep po wer-do wn

(CMOS) control of flash memory chips of bank1. PWD1# is activ e

low and also locks out erase or program operation providing

data protection during power transitions . Po wer down pin

PWD0# will be active if FA23=0. In series mode,this signal

is used to spare area control. SE# is active low.

FR Y/FBY# 13 I Flash memory Ready/busy input:

(CMOS) This signal indicate the state of erase or program oper ation

in flash memory chips.This pin includes an internal pull-up

resistor.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

Control R OM interface

Symbol No. Type Description

R OMCS#/ 75 O ROM chip select/Flash memory data buffer enable :

FWIN# (CMOS) In F ree-run mode , this signal is used as ROM chip enable if

firmware that stored in e xternal R OM. In ICE-deb ugging

mode, this signal is used as flash memory data buffer (74640)

enable if firmware that stored in flash memory arra y.

R OMWR#/FDIR 76 O ROM write enable/Flash memory data buff er direction

(CMOS) control:

In Free-run mode, this signal is used as ROM write enable if

firmware that stored in e xternal R OM. In ICE-deb ugging

mode, this signal is used as flash memory data buffer (74640)

direction control if firmware that stored in flash memory

array.

Miscellaneous

Symbol No. Type Description

X1 79 I Crystal input.

X2 78 O Crystal ouput.

SWAIT# 71 I(CMOS Sleep wait, this pin is connected to e xternal RC circuit.

Schmitt)

N.C . 70 O No connect.

TEST 81 I This signal is used to select the main system clock, either

(CMOS) from external clock source if this signal is high or from

internal PLL circuit if this signal is low. This pin includes an

internal pull-up resistor .

PWR_RST# 82 I(CMOS Pow er on reset, CMOS Schmite-triggered:

Schmitt) The MX9691L include debouncing circuit to stabilize

internal DSP reset signal.

LED# 6 O LED output:

(CMOS) This signal is connected to external LED in debugging

system to indicate system status. The LED will be turn-on

during reset. The contorl firmw are will turn off the LED after

H/W initialization and pass diagnostics. If system f ail, the

control firmware will flash the LED to indicate some error

occur. This signal will be high if port 601Ch bit0 set to 1 or

OPTR bit2 set to 1.

VCC 17,45,53, 5 or 3.3 volt Pow er pin

72,80,105,

112

GND 7,25,38, Ground pin

48,59,69,

77,91,108,

120

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

5. Functional and Operation Description

5-1. Bloc k Dia gram

MX93011

DSP CORE

Clock & Reset

1KB Buffer

RAM

4KB Internal

RAM

2KB Internal

RAM

Flash Memory

Control

ECC Control

Logic

256 Byte

CIS RAM

MX9691L Signal Chip Solid State Disk Controller

Buffer RAM

Control

External Memory Bus

Clock

Host Interface

PCMCIA/ATA Flash

Interface

PCMCIA/ATA

interface

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

5-2. System Memory Map

Data Space :

Address Function & Usage

0000h~007fh Internal RAM (128W) to store control v ariables

0080h~07ffh Internal RAM(1920W) for flash memory algorithm usage

0800h~5fffh User define (22kW)

6000h~63ffh I/O range(1kW): ATA CTL. use I/O r ange (6000h~601fh)

6400h~6fffh User define (3kW)

7000h~73ffh User define (1kW)

7400h~77ffh Internal RAM (1kW) for expansion RAM or shadow R OM space

7800h~7fffh ROM Data space(2kW)

8000h~ffffh Flash memory access windows(32kW)

Program Space :

Address Function & Usage

0000h~77ffh ROM prog ram space (32kW)

7800h~7fffh Unused

8000h~ffffh Flash memory access windows(32kW)

5-3. P o wer -on detection

* Store firmware in external ROM or Flash memory array

FA17/EROM = 0 —> Store in External ROM

FA17/EROM = 1 —> Store in flash memory array

* Master/Slave selection in True IDE mode :

FA16/ATADET1 FA15/ATADET0 mode selected

1 1 one drive

0 0 master of two drives

1 0 slave of two drives

Note : For some customers design the master/slave

selection is selected by only one jumper that may be

FA16 or FA15. It need to change firmware only.

* ICE debugging mode select :

FA18/ICEMDOE = 0 ---> ICE-debugging mode

FA18/ICEMODE = 1---> Free-run mode, DSP fetch

code from external memory bus and execute it.

* Flash memory data buffer control

ROMCS# is replaced by FWIN# if ICE-debugging

mode & firmware in linear type flash memory array.

ROMWR# is replaced by FDIR if ICE-debugging mode

& firmware in linear type flash memory array.

* PCMCIA mode or True IDE mode select

HOE# Mode

0 True IDE mode

1 PCMCIA mode

To enable True IDE mode this input should be grounded

by the host.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

5-4. Decoding Configuration of all registers in Host interface

* Common Momory Mode Decode

CE1# CE2# REG# HA10 HA9:4 HA3:0 HOE# =0 HWE# = 0

0 0 1 0 xh 000xb Read Data Register HD[15:0] Write Data Register HD[15:0]

0 1 1 0 xh 0000b Read Data HD[7:0] Write Data HD[7:0]

Even & Odd byte Even & Odd b yte

1 0 1 0 xh 0000b Error Status HD[15:8] F eatures HD[15:8]

0 1 1 0 xh 0001b Error Status HD[7:0] Features HD[7:0]

1 0 1 0 xh 0001b Error Status HD[15:8] F eatures HD[15:8]

0 0 1 0 xh 001xb Sector Count HD[7:0] Sector Count HD[7:0]

Sector Number HD[15:8] Sector Number HD[15:8]

0 1 1 0 xh 0010b Sector Count HD[7:0] Sector Count HD[7:0]

0 1 1 0 xh 0011b Sector Number HD[7:0] Sector Number HD[7:0]

1 0 1 0 xh 0011b Sector Number HD[15:8] Sector Number HD[15:8]

0 0 1 0 xh 010xb Cyl. Lo w HD[7:0] Cyl. Lo w HD[7:0]

Cly. High HD[15:8] Cly. High HD[15:8]

0 1 1 0 xh 0100b Cyl. Low HD[7:0] Cyl. Lo w HD[7:0]

0 1 1 0 xh 0101b Cly. High HD[7:0] Cly. High HD[7:0]

1 0 1 0 xh 0101b Cly. High HD[15:8] Cly. High HD[15:8]

0 0 1 0 xh 011xb Drive/Head HD[7:0] Drive/Head HD[7:0]

Ctl. Status HD[15:8] Command HD[15:8]

0 1 1 0 xh 0110b Drive/Head HD[7:0] Drive/Head HD[7:0]

0 1 1 0 xh 0111b Ctl. Status HD[7:0] Command HD[7:0]

1 0 1 0 xh 0111b Ctl. Status HD[15:8] Command HD[15:8]

0 0 1 0 xh 100xb Read Data Register HD[15:0] Write Data Register HD[15:0]

(Duplicate) (Duplicate)

0 1 1 0 xh 1000b Read Data HD[7:0] Write Data HD[7:0]

Even & Odd byte (Duplicate) Even & Odd b yte (Duplicate)

1 0 1 0 xh 1001b Read Data HD[15:8] Write Data HD[15:8]

Odd b yte (Duplicate) Odd byte (Duplicate)

0 1 1 0 xh 1001b Read Data HD[7:0] Write Data HD[7:0]

Odd b yte (Duplicate) Odd byte (Duplicate)

0 0 1 0 xh 110xb Undefined HD[7:0] Undefined HD[7:0]

Error Status HD[15:8] Features HD[15:8]

(Duplicate) (Duplicate)

0 1 1 0 xh 1101b Error Status HD[7:0] Features HD[7:0]

(Duplicate) (Duplicate)

0 0 1 0 xh 111xb Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0]

Drive/Head HD[15:8] Undefined HD[15:8]

0 1 1 0 xh 1110b Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0]

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

* Independent I/O Mode Decode

CE1# CE2# REG# HA9:4 HA3:0 IOR# =0 IOW# = 0

0 0 0 xh 0000b Read Data Register HD[15:0] Write Data Register HD[15:0]

0 1 0 xh 0000b Read Data HD[7:0] Write Data HD[7:0]

Even & Odd b yte Even & Odd b yte

1 0 0 xh 0000b Error Status HD[15:8] Features HD[15:8]

0 1 0 xh 0001b Error Status HD[7:0] Features HD[7:0]

1 0 0 xh 0001b Error Status HD[15:8] Features HD[15:8]

0 1 0 xh 0010b Sector Count HD[7:0] Sector Count HD[7:0]

0 1 0 xh 0011b Sector Number HD[7:0] Sector Number HD[7:0]

1 0 0 xh 0011b Sector Number HD[15:8] Sector Number HD[15:8]

0 1 0 xh 0100b Cyl. Low HD[7:0] Cyl. Lo w HD[7:0]

0 1 0 xh 0101b Cly. High HD[7:0] Cly. High HD[7:0]

1 0 0 xh 0101b Cly. High HD[15:8] Cly. High HD[15:8]

0 1 0 xh 0110b Drive/Head HD[7:0] Driv e/Head HD[7:0]

0 1 0 xh 0111b Ctl. Status HD[7:0] Command HD[7:0]

1 0 0 xh 0111b Ctl. Status HD[15:8] Command HD[15:8]

0 0 0 xh 1000b Read Data Register Write Data Register

HD[15:0](Duplicate) HD[15:0](Duplicate)

0 1 0 xh 1000b Read Data HD[7:0] Write Data HD[7:0]

Even & Odd byte (Duplicate) Even & Odd b yte (Duplicate)

1 0 0 xh 1001b Read Data HD[15:8] Write Data HD[15:8]

Odd byte (Duplicate) Odd byte (Duplicate)

0 1 0 xh 1001b Read Data HD[7:0] Write Data HD[7:0]

Odd byte (Duplicate) Odd byte (Duplicate)

0 1 0 xh 1101b Error Status HD[7:0](Duplicate) Features HD[7:0](Duplicate)

0 1 0 xh 1110b Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0]

0 1 0 xh 1111b Drive/Head HD[7:0] Not Used

1 0 0 xh 1111b Drive/Head HD[15:8] Not Used

0 1 1 0 xh 1111b Drive/Head HD[7:0] Not Used

1 0 1 0 xh 1111b Drive/Head HD[15:8] Not Used

0 0 1 1 xh xxxxb Read Data Register HD[15:0] Write Data Register HD[15:0]

0 1 1 1 xh xxx0b Read Data HD[7:0] Write Data HD[7:0]

Even & Odd byte Even & Odd b yte

0 1 1 1 xh xxx1b Read Data HD[7:0]Odd byte Write Data HD[7:0]Odd b yte

1 0 1 1 xh xxx0b Read Data HD[15:8] Odd byte Write Data HD[15:8] Odd b yte

1 0 1 1 xh xxx1b Read Data HD[15:8] Odd byte Write Data HD[15:8] Odd b yte

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

* Primary ATA Mode Decode

CE1# CE2# REG# HA9:0 IOR# =0 IOW# = 0

0 0 0 1F0h Read Data Register HD[15:0] Write Data Register HD[15:0]

0 1 0 1F0h Read Data HD[7:0]Even & Odd b yte Write Data HD[7:0]Even & Odd b yte

1 0 0 1F0h Error Status HD[15:8] F eatures HD[15:8]

0 1 0 1F1h Error Status HD[7:0] Features HD[7:0]

1 0 0 1F1h Error Status HD[15:8] F eatures HD[15:8]

0 1 0 1F2h Sector Count HD[7:0] Sector Count HD[7:0]

0 1 0 1F3h Sector Number HD[7:0] Sector Number HD[7:0]

1 0 0 1F3h Sector Number HD[15:8] Sector Number HD[15:8]

0 1 0 1F4h Cyl. Low HD[7:0] Cyl. Low HD[7:0]

0 1 0 1F5h Cly. High HD[7:0] Cly. High HD[7:0]

1 0 0 1F5h Cly. High HD[15:8] Cly. High HD[15:8]

0 1 0 1F6h Drive/Head HD[7:0] Drive/Head HD[7:0]

0 1 0 1F7h Ctl. Status HD[7:0] Command HD[7:0]

1 0 0 1F7h Ctl. Status HD[15:8] Command HD[15:8]

0 1 0 3F6h Alternate Ctl. Status HD[7:0] Device Ctl. HD[7:0]

0 1 0 3F7h Drive/Head HD[7:0] Not Used

1 0 0 3F7h Drive/Head HD[15:8] Not Used

* Secondary ATA Mode Decode

CE1# CE2# REG# HA9:0 IOR# =0 IOW# = 0

0 0 0 170h Read Data Register HD[15:0] Write Data Register HD[15:0]

0 1 0 170h Read Data HD[7:0]Ev en & Odd byte Write Data HD[7:0]Even & Odd b yte

1 0 0 170h Error Status HD[15:8] F eatures HD[15:8]

0 1 0 171h Error Status HD[7:0] F eatures HD[7:0]

1 0 0 171h Error Status HD[15:8] F eatures HD[15:8]

0 1 0 172h Sector Count HD[7:0] Sector Count HD[7:0]

0 1 0 173h Sector Number HD[7:0] Sector Number HD[7:0]

1 0 0 173h Sector Number HD[15:8] Sector Number HD[15:8]

0 1 0 174h Cyl. Low HD[7:0] Cyl. Low HD[7:0]

0 1 0 175h Cly. High HD[7:0] Cly. High HD[7:0]

1 0 0 175h Cly. High HD[15:8] Cly. High HD[15:8]

0 1 0 176h Drive/Head HD[7:0] Drive/Head HD[7:0]

0 1 0 177h Ctl. Status HD[7:0] Command HD[7:0]

1 0 0 177h Ctl. Status HD[15:8] Command HD[15:8]

0 1 0 376h Alternate Ctl. Status HD[7:0] De vice Ctl. HD[7:0]

0 1 0 377h Drive/Head HD[7:0] Not Used

1 0 0 377h Drive/Head HD[15:8] Not Used

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

5-5. Automatic P o wer Saving Mode

There are four power saving modes defined in solid state

disk(SSD) system. These f our pow er sa ving modes are

executed by firmware which use DSP's soft-hold and

pow er do wn function and addition logic circuit to imple-

ment it.

Active mode : In Active mode the SSD is capable of

e x ecution to file read and write operation.

Idle mode : In Idle mode the SSD polls the events that

include command_in or time_out events. If read/write

command is asserted then the SSD will enter the Active

mode.

Standby mode : The SSD will enter the Standb y mode

after time_out(1.25ms) event occurs or standby com-

mand is asserted. The SSD controller MX9691L will en-

ter soft_hold condition. The MX9619 will stop program

execution and shut off most circuit activities to save many

power comsumption. The MX9691L will automatically

wake up and enter the Active mode if any command is

asserted.

Sleep mode : The SSD will enter the Sleep mode after

sleep command is asser ted. This is most power saving

mode. The SSD controller MX9691L will enter soft _hold

condition and stop main clock and then the all system

activities will stop. This mode can be waked up by H/W

reset, S/W reset or ATA command asserted. The H/W re-

set will reset all h/w circuits and the Host must reconfigure

the SSD before any command is assseted. The S/W re-

set will set the busy status until the SSD is ready for ac-

cepting command, the Host don't need any h/w

reinitialization. The duration of H/W and S/W reset must

keep enough f or main clock stabilization.

The ATA command asserted to wake-up latency need the

external RC circuit delay for clock stabilization while the

Solid State Disk(SSD) had entered sleep mode.

Power Saving Flow

Power_up

Reset

Initialize

Time-out1 or standby cmd

Standby

Idle

S/W Reset

Exit

Command in

Time-out2 or Sleep cmd Wake-up latency

Command_in

Command in

Sleep

H/W Reset Active

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

5-6. Register s definition

* Register s List

Type of Register Location

PCMCIA/ATA Interface 6000h, 6001h, 6002h, 6003h, 6004h, 6005h, 6006h, 6007h, 600Bh, 6010h,

6011h, 6012h, 6013h, 6019h, 601Ah, 601Bh, 601Ch

PC INTERR UPT CONTR OL 6009h, 600Ah

BUFFER MANAGER AND DMA 6008h, 6014h, 6015h, 6016h, 6017h, 6018h

ECC Control 600Ch, 600Dh, 600Eh, 600Fh

Flash Memory Interface 601Dh, 601Eh, 601Fh

* Register Description

Port 6000h :

Bit Function Description

AT CONTROL/STATUS REGISTER

Def ault reset v alue : 01h

7 R/W: DRIVE READY (drive 0)

6 R/W: DRIVE SEEK COMPLETE (drive 0)

5 R/W: CORRECTED D ATA

4 R: ATA INT. ENABLE

3 R: AT SOFTWARE RESET

2 R/W: HOST INTERR UPT

1 R/W: ERR OR BIT

0 R/W: BUSY BIT

Port 6001h :

Bit Function Description

Def ault reset v alue : 00h

7:0 R/W: ERROR REGISTER (map to command b lock 1f1h)

Port 6002h :

Bit Function Description

Def ault reset v alue : 01h

7:0 R/W: SECT OR COUNT REGISTER (map to command bloc k 1f2h)

Port 6003h :

Bit Function Description

Def ault reset v alue : 01h

7:0 R/W: SECTOR NUMBER REGISTER (map to command b lock 1f3h)

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

Port 6004h :

Bit Function Description

Def ault reset v alue : 00h

7:0 R/W: CYCLINDER LO W REGISTER (map to command b loc k 1f4h)

Port 6005h :

Bit Function Description

Def ault reset v alue : 00h

7:0 R/W: CYCLINDER HIGH REGISTER (map to command bloc k 1f5h)

Port 6006h :

Bit Function Description

Def ault reset v alue : A0h

7:0 R/W: DRIVE/HEAD REGISTER (map to command b lock 1f6h)

Port 6007h :

Bit Function Description

Def ault reset v alue : 00h

7:0 R: COMMAND REGISTER (map to command bloc k 1f7h)

Port 6008h :

Bit Function Description

BUFFER RAM SIZE CONTR OL REGISTER

Def ault reset v alue : 40h

7 R/W: TEST MODE 1 for HAP/D AP test

0 : DISABLE

1 : ENABLE

6 R/W: BIT WRITE GATE STATE OF DRIVE

0 : ENABLE

1 : DISABLE

5 R: PCMCIA or True IDE mode

0 : True IDE mode

1 : PCMCIA mode

4 R/W: A uto D AP increment

0 : Disable

1 : Enab le

3 R/W: Shado w ROM control

0 : Disable

1 : Enab le

2:0 R/W: BUFFER RAM SIZE CONTROL

00x : 32KW

010 : 16KW

011 : 8KW

100 : 4KW

101 : 2KW

110 : 1KW

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

111 : 512W

Port 6009h :

Bit Function Description

HOST INTERR UPT STATUS

Def ault reset value : 00h

7 R: Po wer-Down timer time-out detected

6 R: Card configur ation register write detected

5 R: CIS accessed detected

4 R: Hreset detected

3 R: PC SRST(or PCMCIA SRST) DETECTED

2 R: PC STATUS READ DETECTED

1 R: PC SELECTION

0 R: PC TRANSFER DONE

Port 600Ah :

Bit Function Description

HOST INTERR UPT ENABLE

Def ault reset value : 00h

7 R/W: Po wer-Down timer time-out detected enab le.

6 R/W: Card configuration register write detected enable

5 R/W: CIS accessed detected enab le

4 R/W: Hreset detected enab le

3 R/W: PC SRST(PCMCIA SRST) DETECTED ENABLE

2 R/W: PC STATUS READ DETECTED ENABLE

1 R/W: PC SELECTION ENABLE

0 R/W: PC TRANSFER DONE ENABLE

Port 600Bh :

Bit Function Description

Def ault reset v alue : 00h

7:0 R: Feature register (map to command bloc k 1f1h)

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

Port 600Ch :

Bit Function Description

ECC CONTROL REGISTER

Def ault reset v alue : 00h

7 R/W: ECC FUNCTION SUSPEND

0 : NORMAL

1 : SUSPEND

6 R/W: CORRECTION SPEED SELECT

0 : FULL SPEED (Max. Cloc k frequency)

1 : HALF SPEED (1/2 Max. Clock frequency)

5 R/W: ENCODE/DECODE FUNCTION SELECTION

0 : ENCODE

1 : DECODE

4 R/W: RESET ECC CIRCUIT

0 : RESET

1 : NORMAL

3 R: UNCORRECTABLE ERR OR FLA G

2 R: CORRECTABLE ERR OR FLA G

1 R: CORRECTION DONE FLA G

0 R/W: START ECC CORRECT FUNCTION ENABLE/DISABLE

0 : DISABLE

1 : ENABLE

Port 600Dh :

Bit Function Description

Def ault reset v alue : 0000h

15:0 R/W : ECC 0 REGISTER

Port 600Eh :

Bit Function Description

Def ault reset v alue : 0000h

15:0 R/W : ECC 1 REGISTER

Port 600Fh :

Bit Function Description

Def ault reset v alue : 0000h

15:0 R/W : ECC 2 REGISTER

Port 6010h :

Bit Function Description

Def ault reset v alue : 00h

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

7:0 R: Configuration Option register (map to attrib ute memory 200h)

Port 6011h :

Bit Function Description

Def ault reset value : 00h

7:0 R: Card Configuration and status register (map to attrib ute memory 202h)

Port 6012h :

Bit Function Description

Def ault reset v alue : 0Ch

7:0 R: Pin replacement register (map to attribute memory 204h)

Port 6013h :

Bit Function Description

Def ault reset v alue : 00h

7:0 R: Sock et and cop y register (map to attribute memory 206h)

Port 6014h :

Bit Function Description

Def ault reset v alue : 0000h

15:0 R/W : HOST ADDRESS POINTER

Port 6015h :

Bit Function Description

Def ault reset v alue : 00ffh

15:0 R/W : AT STOP POINTER

Port 6016h :

Bit Function Description

Def ault reset v alue : 0000h

15:0 R/W : DISK ADDRESS POINTER

Port 6017h :

Bit Function Description

DMA CONTROL REGISTER

Def ault reset v alue : 08h

7 R/W: DRIVE READY (drive 1)

6 R/W: DRIVE SEEK COMPLETE (drive 1)

5 R/W: set BSY upon XFER done

0 : DISABLE

1 : ENABLE

4 R/W: ENABLE AUTO INTERR UPTS - AT ONLY

0 : DISABLE

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

1 : ENABLE

Port6017h:

Bit Function Description

3 R/W: B UFFER RAM CHIP ENABLE

0 : ENABLE

1 : DISABLE

2 R/W: HOST B US DIRECTION

0 : START BUFFER ---> AT B US

1 : START AT BUS ---> BUFFER WHEN SET

1 R: A COMPLETION OF AT DMA XFER

0 R/W: STAR T DATA TRANSFER BETWEEN AT BUS AND BUFFER RAM

0 : DISABLE

1 : ENABLE

Port 6018h :

Bit Function Description

15:0 R/W : ACCESS PORT INTO BUFFER RAM

Port 6019h :

Bit Function Description

PCMCIA control register

7 R: True IDE mode

6 R: Common memory mode

5 R: I/O mode

4 R/W: host ready

3 R/W: no driv e address

2 R/W: Internal registers write pulse width

0 : 2 system clock

1 : 1 system clock

1 R/W: Reserv ed.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

0 R/W: Reserv ed.

Port 601Ah :

Bit Function Description

A uxi_ctl_1 reg.

Def ault reset value : 00h

7 R/W : D AS P

6 R/W : Host Interrupt le v el mode or pulse mode select

0: Le v el mode

1: Pulse mode

5 R/W : PDIAG

4 R/W : DASP output enab le

3 R/W: write protect enable

0: Disab le

1: Enab le

2 R/W: PDIA G output enable

1 R/W: master/slav e mode enable

0: Disab le

1: Enable

0 R/W: master/salv e of True IDE mode

0: master

1: slav e

Port 601Bh :

Bit Function Description

A uxi_ctl_2 reg.

Def ault reset value : 00h

7:4 Reserved.

3 R/W: Reserved.

2 R/W: Deep po wer down control for automatic wak e-up function from sleep mode .

0 : Disable

1 : Enable

1 R/W: Reserved.

0 R/W: Disk interrupt polarity

0: Low activ e

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

1: High active

Port 601Ch :

Bit Function Description

A uxi_ctl_3 reg.

Def ault reset v alue : 0000h

15 Reserved.

14 R/W : Test mode 2 f or timer

0 : Normal mode

1 : Test mode enable

13 R : DRQ

12 R : Time out status

1 : Time out event occurence

11 R/W: Timer enable/disable

0 : Disable

1 : Enab le

10:9 R/W: Power-do wn timer time-out select f or 25MHz main cloc k

00 : 16 x 1.28 = 20.48 sec.

01 : 8 x 1.28 = 10.24 sec.

10 : 4 x 1.28 = 5.12 sec.

11 : 2 x 1.28 = 2.56 sec.

8 R : ICE-deb ugging mode detected

0 : ICE-deb ugging mode

1 : F ree-run mode.

7 R/W : Inverted data bus for access flash memory.

0 : Inverted.

1 : Non-in v erted.

6 R: External ROM detect.

0: Firmware stored in e xternal ROM.

1: Firmware stored in linear type flash memory arra y.

5:4 R/W: Shado w R OM space control

00 : 512 bytes , Range: 7400h ~ 74ffh

01 : 1Kbytes , Range: 7400h ~ 75ffh

10 : 1.5Kb ytes , Range: 7400h ~ 76ffh

11 : 2Kbytes , Range: 7400h ~ 77ffh

3:2 R : Master/Sla v e mode detect in True IDE mode

00 : Master of two drives

10 : Slave of two drives

11 : One drive

1 R/W: PIO/DMA mode select

0: PIO mode.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

1: DMA mode .

0 R/W: LED output

Port 601Dh :

Bit Function Description

Def ault reset v alue : 0000h

9:0 R/W : Flash memory Read address FA[24:15] latch in linear mode When data space 8000h ~ ffffh is

read, the output of the flash memory read address latch will be used.

The definitions for this register in series mode

Def ault reset v alue : 0000h

9 Reserved.

8 Bank select in capacity extension mode

0 : Bank0 selected.

1 : Bank1 selected.

7:5 R/W: FCE select for series mode

000: FCE0

001: FCE2

010: FCE4

011: FCE6

100: FCE1

101: FCE3

110: FCE5

111: FCE7

4 R/W: Command latch enab le (FA19/CLE)

0 : Disable

1 : Enable

3 R/W: Address latch enab le (FA18/ALE)

0 : Disable

1 : Enable

2:0 Reserved

Port 601Eh :

Bit Function Description

Flash memory control register

Def ault reset v alue : 08Ah

7 R/W: Flash memory deep power down control 0 in linear mode or Write protect in series mode

0 : Enab le

1 : Disable

6 R : Ready / Busy status

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

0 : BUSY

1 : READY

Port 601Eh :

Bit Function Description

5:4 R/W: Flash memory type select

00 : Reserv ed.

01 : 16M flash memory /Bank 1 select in linear mode or capacity e xtension mode selected in series

mode .

10 : Reserved

11 : Reserved

3 R/W: Flash memory deep power down control 1 in linear mode or Spare area enab le in series mode.

0 : Enab le

1 : Disable

2 R/W: CE# enab le f or series mode

0 : Disable

1 : Enab le

1 R/W: Series or linear mode select

0 : linear mode

1 : Series mode

0 R/W: Flash memory write pulse width control

0 : 1 system clock

1 : 2 system clock

Port 601Fh :

Bit Function Description

Def ault reset v alue : 0000h

9 R/W : Flash memory Write address FA[24:15] latch in linear mode

When data space 8000h ~ ffffh is write or program space 8000h ~ ffffh is read, the output of the flash

memory write address latch will be used.

The definitions for this register in series mode

Reserved.

8 Bank select in capacity extension mode

0 : Bank0 selected.

1 : Bank1 selected.

7:0 Reserved.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

6. ELECTRICAL SPECIFICATIONS

6-1. DC Characteristics 1 : Ta = 0 oC to 70 oC, VCC = 5V±±

±±

±10%

Symbol Parameter Min Max Units Conditions

VCC P o wer Supply v oltage 4.5 5.5 V

VIL1 Input Low voltage (TTL) 0.8 V VCC=5V

VIH1 Input High v oltage (TTL) 2.0 V VCC=5V

VIL2 Input Low v oltage (CMOS) 1.2 V VCC=5V

VIH2 Input High v oltage (CMOS) 3.5 V VCC=5V

V OL Output Low voltage 0.4 V IOL=8mA

V OH Output High voltage 2.5 V IOH=-8mA

ICC1 Supply Current 1 40 mA f=25Mhz, Active mode , CL=0pf ,

VCC=5.5Volt, T emperature= 0oC

ICC2 Supply Current 2 30 m A f = 25Mhz, Idle mode, CL = 0pf,

VCC=5.5Volt, T emperature= 0oC

ICC3 Supply Currect 3 12 mA f = 25Mhz, Standb y mode , CL = 0pf ,

VCC=5.5Volt, T emperature= 0oC

ICC4 Supply Current 4 1 mA f = 0Mhz, Sleep mode, CL = 0pf ,

VCC=5.5Volt, T emperature= 0oC

IL Input Leakage ±10 uA 0< VIN < VCC

CIN Input Capacitance 14 pf VIN=0V

COUT Output Capacitance 16 pf V OUT=0V

Note : During transitions, inputs may undershoot to -2.0V for periods less than 20ns and overshoot to VCC + 2.0V for

periods less than 20ns.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

6-2. DC Characteristics 2 : Ta = 0 oC to 70 oC, VCC = 3.3V±±

±±

±5%

Symbol Parameter Min Max Units Conditions

VCC P o wer Supply v oltage 3.1 3.5 V

VIL1 Input Low voltage(TTL) 0.8 V VCC=3.3V

VIH1 Input High v oltage(TTL) 2.0 V VCC=3.3V

VIL2 Input Low voltage(CMOS) 0.9 V VCC=3.3V

VIH2 Input High v oltage(CMOS) 2.7 V VCC=3.3V

V OL Output Low voltage 0.4 V IOL=4mA

V OH Output High voltage 2.2 V IOH=-4mA

ICC1 Supply Current 1 20 mA f=16Mhz, Active mode , CL=0pf ,

VCC=3.5Volt, T emperature= 0oC

ICC2 Supply Current 2 15 m A f = 16Mhz, Idle mode, CL = 0pf,

CC=3.5V olt, T emperature= 0oC

ICC3 Supply Currect 3 5 mA f = 16Mhz, Standby mode, CL = 0pf,

VCC=3.5Volt, T emperature= 0oC

ICC4 Supply Current 4 0.5 mA f = 0Mhz, Sleep mode, CL = 0pf,

VCC=3.5Volt, T emperature= 0oC

IL Input Leakage ±10 uA 0< VIN < VCC

CIN Input Capacitance 14 pf VIN=0V

COUT Output Capacitance 16 pf V OUT=0V

Note : During transitions, inputs may undershoot to -2.0V f or periods less than 20ns and overshoot to VCC + 2.0V for

periods less than 20ns.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

6-3. A C Characteristics

Condition : Ta=0 oC to 70 oC , VCC = 5V±10% or VCC = 3.3V±5%

(1). DSP Interface Timing :

VCC = 5V±10%

Symbol Description Min. Typ. Max. Units

Tw In ICE mode, WR# pulse dur ation when the data are 4Tc

accessed by external DSP.

Trd In ICE mode, RD# to output delay when the data are 34 ns

accessed by external DSP.

Tcs Chip select access cycle 1.5Tc 4.5Tc ns

Taa Address access cycle 1.5Tc 4.5Tc ns

Trds Data setup time before RD# high 12 ns

Tdh Data hold time after RD# high 0 ns

VCC = 3.3V±5%

Symbol Description Min. Typ. Max. Units

Tw In ICE mode, WR# pulse dur ation when the data are 4Tc

accessed by external DSP.

Trd In ICE mode, RD# to output delay when the data are 34 ns

accessed by external DSP.

Tcs Chip select access cycle 1.5Tc 4.5Tc ns

Taa Address access cycle 1.5Tc 4.5Tc ns

Trds Data setup time before RD# high ns

Tdh Data hold time after RD# high ns

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

WR#

DCE#

A[15:0]

Tdh

Trds

Tcs

Taa

RD#

D[15:0]

A[15:0]

D[15:0]

DCE#/PCE#

RD#

DCE#

A[15:0]

Trd

D[15:0]

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

(2). Power Reset Timing

VCC = 5V±10% or VCC = 3.3V±5%

Symbol Description Min. Typ. Max. Units

Tw(rst) Reset low pulse width 3Tc ns

(3). Cloc k Timing

VCC = 5V±10%

Symbol Description Min. Typ. Max. Units

Tc(c) Clock cycle time 40 ns

Tlpd(c) Clock low pulse dur ation(Tc=40ns) 16 2 4 ns

Thpd(c) Cloc k high pulse duration(Tc=40ns) 1 6 24 ns

VCC = 3.3V±5%

Symbol Description Min. Typ. Max. Units

Tc(c) Clock cycle time 62.5 ns

Tlpd(c) Clock low pulse duration(Tc=62.5ns) 25 37.5 ns

Thpd(c) Cloc k high pulse duration(Tc=62.5ns) 25 37.5 ns

Tw(rst)

CLK IN

PWR RST# Tc

TlpdThp

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P/N:PM0546 REV. 1.1, JUL. 02, 1999

(4). Interrupt Timing

VCC = 5V±10%

Symbol Description Min. Typ. Max. Units

Tw INT1# low pulse duration 1.5Tc ns

Tf INT1# fall time 10 ns

VCC = 3.3V±5%

Symbol Description Min. Typ. Max. Units

Tw INT1# low pulse duration 1.5Tc ns

Tf INT1# fall time ns

(5). HOLD# Timing

VCC = 5V±10% or VCC = 3.3V±5%

Symbol Description Min. Typ. Max. Units

Td(al-h) HLD A# low to address tri-state 0 ns

Td(hh-ha) HOLD# high to HLD A# high 0 0.5Tc 0.5Tc+10 ns

Ten(ah-a) Address driven after HLD A# high 0.5Tc-10 0.5Tc Tc ns

HOLD#

INT1

Td(al-h)

Td(hh-ha)

HLDA#

A[15:0]

Ten(ah-a)

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P/N:PM0546 REV. 1.1, JUL. 02, 1999

(6). PCMCIA Bus Timing 1: Common Memory and Attribute memory Access Timing

VCC = 5V±10%

Symbol Par ameter Min (ns) Max (ns)

T1 Read cycle time 60

T2 Chip enable setup time bef ore output enab le 0

T3 Output data enable time from HOE# 31

T4 Chip disable hold time f ollowing output disab le 1.5

T5 Output data disable time f ollowing HOE# 10.5

T6 Write cycle time 60

T7 Chip enable setup time bef ore HWE# 0

T8 Write pulse width of HWE# 40

T9 Chip disable hold time f ollowing write disable 2

T10 Data setup time before HWE# 0

T11 Data hold time following HWE# 2.5

VCC = 3.3V±5%

Symbol Par ameter Min (ns) Max (ns)

T1 Read cycle time 90

T2 Chip enable setup time bef ore output enab le 0

T3 Output data enable time from HOE# 47

T4 Chip disable hold time f ollowing output disab le 3

T5 Output data disable time f ollo wing HOE# 17

T6 Write cycle time 90

T7 Chip enable setup time bef ore HWE# 0

T8 Write pulse width of HWE# 60

T9 Chip disable hold time f ollowing write disable 2.5

T10 Data setup time before HWE# 0

T11 Data hold time following HWE# 3

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

CE[2:1]#

HOE#

HA[10:0]

REG#

Common Memory and Attribute Memory Read Timing

HD[15:0]

CE[2:1]#

HWE#

HA[10:0]

REG#

Common Memory and Attribute Memory WriteTiming

HD[15:0]

T10

T11

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

(7). PCMCIA Bus Timing 2: I/O mode Access Timing

VCC = 5V±10%

Symbol Par ameter Min (ns) Max (ns)

T1 Address hold time follo wing IOR# 2

T2 REG# setup time before IOR# 0

T3 REG# hold time follo wing IOR# 0

T4 CE# setup time before IOR# 0

T5 IOR# pulse width 60

T6 CE# hold time follo wing IOR# 2

T7 Address setup time before IOR# 0

T8 INPACK dela y from IOR# f alling edge 10

T9 INPACK delay from IOR# rising edge 10.5

T10 IOIS16 falling dela y after Address changed 14

T11 Data delay after IOR# f alling 32

T12 IOIS16 rising dela y after Address changed 12.5

T13 Data hold time following IOR# 20

T14 Address hold time following IOW# 3

T15 REG# setup time before IO W# 0

T16 REG# hold time following IO W# 0

T17 CE# setup time before IO W# 0

T18 IOW# pulse with 60

T19 CE# hold time following IO W# 2

T20 Address setup time before IO W# 0

T21 IOIS16 rising dela y after Address changed 10.5

T22 IOIS16 falling dela y after Address changed 14

T23 Data setup time before IO W# 0

T24 Data hold time following IO W# 2.5

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P/N:PM0546 REV. 1.1, JUL. 02, 1999

VCC = 3.3V±5%

Symbol Par ameter Min (ns) Max (ns)

T1 Address hold time follo wing IOR# 2

T2 REG# setup time before IOR# 0

T3 REG# hold time follo wing IOR# 0

T4 CE# setup time before IOR# 0

T5 IOR# pulse width 90

T6 CE# hold time follo wing IOR# 2

T7 Address setup time before IOR# 0

T8 INPACK dela y from IOR# f alling edge 18

T9 INPACK delay from IOR# rising edge 18

T10 IOIS16 falling delay after Address changed 23.5

T11 Data delay after IOR# f alling 47

T12 IOIS16 rising dela y after Address changed 20

T13 Data hold time following IOR# 31

T14 Address hold time following IOW# 4

T15 REG# setup time before IO W# 0

T16 REG# hold time following IO W# 0

T17 CE# setup time before IO W# 0

T18 IOW# pulse with 90

T19 CE# hold time following IO W# 2.5

T20 Address setup time before IO W# 0

T21 IOIS16 rising dela y after Address changed 20

T22 IOIS16 falling delay after Address changed 23.5

T23 Data setup time before IO W# 0

T24 Data hold time following IOW# 3

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P/N:PM0546 REV. 1.1, JUL. 02, 1999

CE[2:1]#

INPACK#

HA[10:0]

ID Read Timing

IOIS16#

REG#

IOR#

HD[15:0]

T12

T13

T10 T11

I/O Write Timing

CE[2:1]#

HA[10:0]

IOIS16#

REG#

IOW# T20

T15

HD[15:0]

T14

T17

T18

T21

T24

T22

T23

T16

T19

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P/N:PM0546 REV. 1.1, JUL. 02, 1999

(8). Flash Memory Interface Timing

VCC = 5V±10%

Symbol Parameter Min Max Units

Tw(a-ce) FCE# fall time after DSP address decode when write 5.5 15 ns

Twas FCE# setup time before WRFLASH# f alling edge 10 29.5 ns

Tw(wrflash) WRFLASH# low pulse duration 1Tc *ns

Tr(a-ce) FCE# fall time after DSP address decode when read 5.5 15 ns

Tr(rd-oe) RDFLASH# fall time after RD# f alling edge 4.5 11.5 ns

VCC = 3.3V±5%

Symbol Parameter Min Max Units

Tw(a-ce) FCE# fall time after DSP address decode when write 8 24.5 ns

Twas FCE# setup time before WRFLASH# f alling edge 14.5 49 ns

Tw(wrflash) WRFLASH# low pulse duration 1Tc *ns

Tr(a-ce) FCE# fall time after DSP address decode when read 8 24.5 ns

Tr(rd-oe) RDFLASH# fall time after RD# f alling edge 6.5 20 ns

[* Note]: Theses timing are only for 1-system cloc k of flash memory write pulse is employed (601E[0]=0). If 2-system

clock of pulse width is selected (601E[0]=1), the minim um time of Tw(wrflash) is 2Tc.

WRFLASH#

A[15:0]

Flash memory write timing

FCE[7:0]

WR#

Tw(a-ce)

Twas

Tw(wrflash)

RDFLASH#

A[15:0]

Flash memory Read timing

FCE[7:0]

RD#

Tr(a-ce)

Tras

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

6-4. Latchup Characteristics

Min. Max.

Input Voltage with respect to GND on all VCC pins -2.0V 12.0V

Input Voltage with respect to GND on all I/O pins -2.0V VCC+2.0V

Current -100mA +100mA

Includes all pins expect GND. Test conditions:VCC=5.0V, one pin at a time.

MX9691L

P/N:PM0546 REV. 1.1, JUL. 02, 1999

REVISION HISTORY

Revision Destription Page Date

1. 1 Modify package type P1 JUL/02/1999

MX9691L

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