128K x 8 Static RAM
f
ax id: 1072
CY62128
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Jul
y
1996 - Revised June 18
,
1998
Features
•4.5V
− 5.5V operation
• CMOS for optimum speed/power
• Lo w active power (70 ns , LL version)
—330 mW (max.) (60 mA)
• Lo w standby po wer (70 ns, LL version)
—110 µW (m ax.) (20 µA)
• A utomatic power-down when desel ected
• TTL-compatibl e inputs and outputs
• Easy memory expansion with CE 1, CE2, and OE options
Functional Description
The CY62128 is a hig h-perf ormance CMO S static RAM orga-
nized as 131,072 wor ds by 8 bits. Easy memory expansion is
pro vided b y an activ e L OW chi p enab le (CE1), an active HIGH
chip enable (CE2), an active LOW output enable (OE), and
three-sta te drivers. This de vice has an automati c powe r- down
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE 1) and write e nab le (WE) i nputs L O W and chi p enabl e
tw o ( CE2) input HIGH. Data on t he eigh t I/ O pins ( I/O0 t hrough
I/O7) is then written into the l ocation specified on the address
pins (A0 through A16).
Reading from the device is accomplished by taking chip en-
able one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/ O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operati on (CE1 LOW, CE2 HIGH, a nd WE LOW) .
The CY62128 is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages .
14
15
Logic Block Diagram Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
2
I/O1
I/O2
I/O3
512x256x8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
A10
CE
1
A
A16
A9
62128-1
62128-2
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
12
13
29
32
31
30
16
15 17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I/ STSOP
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
SOIC
62128-2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
(not to scale)
Top View
Reverse Pinout
CY62128
2
Maximum Ratings
(Above which the usefu l l ife may be impaired. For user guide-
li nes, not tes ted.)
Sto ra g e Tem p e ra tu r e ......... ..... .... ........ ..... ..– 6 5°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Output s
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Current.............. .......................................>200 mA
Notes:
1. VIL (min.) = –2. 0V f or pulse dur at ions of l ess than 20 ns .
2. TA is the “ins tant on” cas e tempe ratur e.
Selec tio n Guid e CY62128-55 CY62128-70
Maximum Access Time (ns) 55 70
Maximum Operating Current Commercial L50 40
LL 50 40
Maximum CMOS St andby Current Commercial L80 80
LL 15 15
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C5V ± 10%
CY62128
3
Electrical Characte ristics Over the Operating Range
62128–55 62128–70
Parameter Description Test Conditions Min. Typ[3] Max. Min. Typ[3] Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1 .0 mA 2.4 2.4 V
VOL Output LOW Vol tage VCC = Min., IOL = 2.1m A 0.4 0.4 V
VIH Input HIGH Vol tage 2.2 VCC
+ 0.3 2.2 VCC
+ 0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V
IIX Input Load Curren t GND ≤ VI ≤ VCC –1 +1 –1 +1 µA
IOZ Output Leakage Cur-
rent GND ≤ VI ≤ VCC, Output Disabled +1 +1 +1 +1 µA
IOS Output Short Circui t
Current[4] VCC = Max., VOUT = G N D –300 –300 mA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l 40 115 40 110 mA
L30 70 30 60 mA
LL 30 70 30 60 mA
Ind.’l 40 115 40 110 mA
L30 70 30 70 mA
LL 30 70 30 70 mA
ISB1 Automatic CE
Po wer-Down Current
—TTL Input s
Max. VCC,
CE1 ≥ VIH
or CE2 < VIL,
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
Com’l 0.3 25 0.3 1 mA
L0.15 30.151mA
LL 0.1 20.11mA
Ind.’l 0.3 25 0.3 1 mA
L0.15 30.151mA
LL 0.1 20.11mA
ISB2 Automatic CE
Po wer-Down Current
—CMOS Inputs
Max. VCC,
CE1 ≥ VCC – 0.3V,
or CE 2 ≤ 0.3V,
VIN ≥ VCC – 0.3 V,
or VIN ≤ 0.3V, f=0
Com’l 0.4 500 0.4 500 µA
L100 100 µA
LL 20 20 µA
Ind 0.4 500 0.4 500 µA
L100 100 µA
LL 40 40 µA
Capacitance[5]
Parameter Description T est Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 9pF
COUT Output Capacitance 9pF
Notes:
3. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production
variations as measured at VCC = 5.0V, TA = 25°C, and tAA=70ns
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
CY62128
4
AC Test Loads and Wave forms
Swi tch i ng C h ara cter i sti cs [6] O ver the Operating Range
62128–55 62128–70
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 55 70 ns
tAA Address to Data Val id 55 70 ns
tOHA Da ta Hol d from Address Change 5 5ns
tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 20 35 ns
tLZOE OE LOW to Low Z 0 0ns
tHZOE OE HIGH to High Z[7,8] 20 25 ns
tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[8] 5 5 ns
tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[7,8] 20 25 ns
tPU CE1 LOW to Power-Up, CE2 HIGH to P ower-Up 0 0ns
tPD CE1 HIGH to Power-Down, CE2 LOW to Power-Down 55 70 ns
WRITE CY CLE[9]
tWC Write Cycle Time 55 70 ns
tSCE CE1 LOW to Write End, CE2 HIGH to Writ e E n d 45 60 ns
tAW Address Set-Up to Write End 45 60 ns
tHA Address Hold from Write End 0 0ns
tSA Address Set-Up to Write Start 0 0ns
tPWE WE Pulse Width 45 50 ns
tSD Data Set-Up to Write End 25 30 ns
tHD Data Hold from Write End 0 0ns
tLZWE WE HIGH to Low Z[8] 5 5 ns
tHZWE WE LO W to High Z[7, 8] 20 25 ns
Notes:
6. Tes t conditions assume signal transition time of 5ns or less, timing reference lev els of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100 pF load capac itance.
7. tHZOE, tHZCE, and tHZWE are spec ified with a load cap acitance of 5 pF as i n part (b) of A C Test Loads. Transition i s measur ed ±500 mV from ste ady -state v olta ge.
8. At any given temperature and voltage condition, tHZCE is less than t LZCE, tHZOE is less t han tLZOE, and tHZWE is less t han tLZWE for an y gi ven de vi ce.
9. The internal write time of the memory is defined by the overlap of CE1 LO W, C E2 HIGH, and WE LOW. CE1 and W E must b e LO W and CE2 HIGH to initiate a write,
and the tr a nsition of any of these signa ls can terminate the write . The i np ut dat a set-up an d hol d timing shoul d be ref er enced to the leading ed ge of the signa l that terminates
the write .
62128-3 62128-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT 100 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤ 5ns ≤5n
s
OUTPUT
R1 1800 ΩR1 1800 Ω
R2
990ΩR2
990Ω
639Ω
Equivalent to: THÉVENIN EQUIVALENT
1.77V
CY62128
5
Data Retention Characteristics (Over the Operating Range for “L” and “LL” version only)
Parameter Description Conditions[10] Min. Typ. Max. Unit
VDR VCC for Data Ret ention 2.0 V
ICCDR Data Retent ion Current Coml. L VCC=VDR=3.0V,
CE ≥VCC – 0.3V,
VIN ≥ VCC – 0.3V or,
VIN ≤ 0.3V 0.4
100 µA
LL 20 µA
Indl. L 100 µA
LL 20 µA
tCDR[3] Chip Desel ect to Data Retent ion Time 0 ns
tR[3] Operation Recover y Time tRC ns
Swi tch i ng Waveform s
Read Cycle No.1[11,12]
Read Cycle No. 2 (OE Controlled)[12,13]
Notes:
10. No input may exceed VCC + 0.5V.
11. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
12. WE is HI GH f or r ead cy cle.
13. Address valid prior to or coincident with CE1 trans ition LO W and CE2 transi tion H IGH.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
62128-5
ADDRESS
DATA OUT
62128-6
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
CY62128
6
Write Cycle No. 1 (CE1 or CE2 Controlled)[14,15]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14,15]
Notes:
14. Data I/O is high impedance if OE = VIH.
15. If C E1 goes HIGH or CE2 goe s LOW simul taneous ly wi th WE going HIGH, the out put r emains i n a hi gh-imp edance state .
16. During this period the I/Os are in the output state and input signals should not be applied.
Swi tch i ng Waveform s (continued)
62128-7
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
62128-8
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE16
CY62128
7
Write C ycle No .3 ( WE Controlled, OE LOW)[14,15]
Swi tch i ng Waveform s (continued)
62128-9
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZWE
CE1
ADDRESS
CE2
WE
DATAI/O NOTE 16
Truth Table
CE1CE2OE WE I/O0 – I/O 7Mode Power
H X X X High Z Power-Down Standby (ISB)
X L X X High Z Power-Down Standby (ISB)
L H L H Data Out Read Active (ICC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
CY62128
8
Document #: 38–00524–B
Ordering Information
Speed
(ns) Orderi ng Code Package
Name Package Type Operating
Range
55 CY62128–55SC S34 32-L ead 450-Mil SOIC Commercial
CY62128-55ZC Z32 32-Lead TSOP Type I
CY62128−55ZAC ZA32 32- Lead STSOP Type I
70 CY62128–70SC S34 32-L ead 450-Mil SOIC Commercial
CY62128−70ZC Z32 32-Lead TSOP Type I
CY62128-70ZAC ZA32 32-Lead STSOP Type I
CY62128-70ZRC ZR32 32-Lead Re verse TSOP Type I
CY62128–70SI S34 32-Lead 450-Mil SOIC Industrial
CY62128−70ZI Z32 32-Lead TSOP Type I
CY62128-70ZAI ZA32 32- Lead STSOP Type I
CY62128-70ZRI ZR32 32-Lead Reverse TSOP Type I
CY62128L−70SC S34 32-L ead 450-Mil SOIC Commercial
CY62128L−70ZC Z32 32-Lead TSOP Type I
CY62128L-70ZAC ZA32 32- Lead STSOP Type I
CY62128L-70ZRC ZR32 32-Lead Reverse TSOP Type I
CY62128L−70SI S34 32-L ead 450-Mil SOIC Industrial
CY62128L−70ZI Z32 32-Lead TSOP Type I
CY62128L-70ZAI ZA32 32-Lead STSOP Type I
CY62128L-70ZRI ZR32 32-Lead Rever se TSOP Type I
CY62128LL−70SC S34 32-Lead 450-Mil SOIC Commercial
CY62128LL−70ZC Z32 32-Lead TSOP Type I
CY62128LL-70ZAC ZA32 32- Lead STSOP Type I
CY62128LL-70ZRC ZR32 32-Lead Reverse TSOP Type I
CY62128LL−70SI Z32 32-Lead 450-Mil Type I Industrial
CY62128LL-70ZI Z32 32-Lead TSOP Type I
CY62128LL-70ZAI Z32 32-Lead STSOP Type I
CY62128LL-70ZRI ZR32 32-Lead Reverse TSOP Type I
CY62128
9
Package Di ag ra ms
32-Lead (450 MIL) Molded SOIC S34
51-85081-A
51-85056-B
32-Lead Thin Small Outline Package Z32
CY62128
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to c hange without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not author ize
its products for use as critical components in life-suppor t systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cy press Semiconductor against all charges.
Package Di ag ra ms (continued)
32-Lead Shrunk Thin Small Outline Package ZA32
51-85094
51-85089-A
32-Lead Reverse Thin Sm all Outline Package ZR32
