Data Sheet 2.7 V to 5.5 V, <100 A, 14-Bit nanoDAC, SPI Interface in LFCSP and SC70 AD5641 FEATURES FUNCTIONAL BLOCK DIAGRAM 6-lead LFCSP and SC70 packages Micropower operation: 100 A maximum at 5 V Power-down to typically 0.2 A at 3 V Single 14-bit DAC B version: 4 LSB INL A version: 16 LSB INL 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to 0 V with brownout detection 3 power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation SYNC interrupt facility VDD GENERAL DESCRIPTION The AD5641, a member of the nanoDAC(R) family, is a single, 14-bit, buffered, voltage-out DAC that operates from a single 2.7 V to 5.5 V supply, typically consuming 75 A at 5 V. The part comes in tiny LFCSP and SC70 packages. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The AD5641 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP interface standards. The reference for AD5641 is derived from the power supply inputs and, therefore, gives the widest dynamic output range. The part incorporates a power-on reset circuit, which ensures that the DAC output powers up to 0 V and remains there until a valid write to the device takes place. The AD5641 contains a power-down feature that reduces current consumption typically to 0.2 A at 3 V, and provides software-selectable output loads while in power-down mode. The part is put into power-down mode over the serial interface. The low power consumption of the part in normal operation makes it ideally suited to portable battery-operated equipment. The combination of small package and low power makes this nanoDAC device ideal for level-setting requirements such as generating bias or control voltages in space-constrained and power-sensitive applications. AD5641 POWER-ON RESET DAC REGISTER REF(+) 14-BIT DAC OUTPUT BUFFER POWER-DOWN CONTROL LOGIC VOUT RESISTOR NETWORK 04611-001 INPUT CONTROL LOGIC SYNC APPLICATIONS Voltage level setting Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GND SCLK SDIN Figure 1. Table 1. Related Devices Part Number AD5601 AD5611 AD5621 Description 2.7 V to 5.5 V, <100 A, 8-bit nanoDAC, SPI interface in LFCSP and SC70 packages 2.7 V to 5.5 V, <100 A, 10-bit nanoDAC, SPI interface in LFCSP and SC70 packages 2.7 V to 5.5 V, <100 A, 12-bit nanoDAC, SPI interface in LFCSP and SC70 packages PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Available in space-saving 6-lead LFCSP and SC70 packages. Low power, single-supply operation. The AD5641 operates from a single 2.7 V to 5.5 V supply and with a maximum current consumption of 100 A, making it ideal for battery-powered applications. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a typical slew rate of 0.5 V/s. Reference derived from the power supply. High speed serial interface with clock speeds up to 30 MHz. Designed for very low power consumption. The interface powers up only during a write cycle. Power-down capability. When powered down, the DAC typically consumes 0.2 A at 3 V. Power-on reset with brownout detection. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2005-2012 Analog Devices, Inc. All rights reserved. AD5641 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Resistor String ............................................................................. 13 Applications ....................................................................................... 1 Output Amplifier ........................................................................ 13 General Description ......................................................................... 1 Serial Interface ............................................................................ 13 Functional Block Diagram .............................................................. 1 Input Shift Register .................................................................... 13 Product Highlights ........................................................................... 1 SYNC Interrupt .......................................................................... 13 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 14 Specifications..................................................................................... 3 Power-Down Modes .................................................................. 14 Timing Characteristics ................................................................ 4 Microprocessor Interfacing ....................................................... 15 Absolute Maximum Ratings ............................................................ 5 Applications..................................................................................... 16 ESD Caution .................................................................................. 5 Choosing a Reference as Power Supply for the AD5641....... 16 Pin Configuration and Function Descriptions ............................. 6 Bipolar Operation Using the AD5641 ..................................... 16 Typical Performance Characteristics ............................................. 7 Using the AD5641 with a Galvanically Isolated Interface .... 17 Terminology .................................................................................... 12 Power Supply Bypassing and Grounding ................................ 17 Theory of Operation ...................................................................... 13 Outline Dimensions ....................................................................... 18 Digital-to-Analog Section ......................................................... 13 Ordering Guide .......................................................................... 19 REVISION HISTORY 2/12--Rev. C to Rev. D Added 6-Lead LFCSP ......................................................... Universal Changes to Title, Features Section, General Description Section, Table 1, and Product Highlights Section, ...................................... 1 Changes to Table 4 ............................................................................ 5 Added Figure 4; Renumbered Sequentially .................................. 6 Changes to Table 5 ............................................................................ 6 Change to Choosing a Reference as Power Supply for the AD5641 Section .............................................................................. 16 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 3/05--Rev. 0 to Rev. A Changes to Timing Characteristics .................................................4 Changes to Absolute Maximum Ratings ........................................5 Changes to Full-Scale Error Section ...............................................7 Changes to Figures 28 and 30 ....................................................... 12 Change to Resistor String Section ................................................ 13 Changes to Power-Down Mode Section ..................................... 14 1/05--Revision 0: Initial Version 10/07--Rev. B to Rev. C Added B Grade .................................................................... Universal Changes to Offset Error and Gain Error Specifications .............. 3 Changes to Table 4 ............................................................................ 5 Changes to Typical Performance Characteristics ......................... 7 Changes to Ordering Guide .......................................................... 18 7/05--Rev. A to Rev. B Change to Galvanically Isolated Interface Section ..................... 18 Changes to Figure 44 ...................................................................... 18 Rev. D | Page 2 of 20 Data Sheet AD5641 SPECIFICATIONS VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; -40C < TA < +125C; typical at +25C; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution Relative Accuracy 1 Differential Nonlinearity1 Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS 2 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Min 14 0 6 0.5 470 1000 120 2 Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current LOGIC INPUTS Input Current 3 VINL, Input Low Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V POWER EFFICIENCY IOUT/IDD Min B Grade Typ Max 14 0.5 0.63 0.5 0.004 5.0 2.0 Output Noise Spectral Density Noise VINH, Input High Voltage A Grade Typ Max 16 1 10 10 0.5 0.63 0.5 0.004 5.0 2.0 0.037 VDD 10 0 6 0.5 470 1000 120 2 4 1 10 10 0.037 VDD 10 Unit Bits LSB LSB mV mV mV % of FSR V/C ppm of FSR/C V s V/s pF pF nV/Hz V Test Conditions/Comments Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Code 1/4 scale to 3/4 scale, to 1 LSB 5 5 nV-s RL = RL = 2 k DAC code = midscale, 1 kHz DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 1 LSB change around major carry 0.2 0.5 15 0.2 0.5 15 nV-s mA VDD = 3 V/5 V 2 0.8 0.6 1.8 1.4 2 0.8 0.6 A V V V V pF 5.5 V 100 90 A A All digital inputs at 0 V or VDD DAC active and excluding load current VIH = VDD and VIL = GND VIH = VDD and VIL = GND 1.8 1.4 3 2.7 3 5.5 75 60 2.7 100 90 75 60 VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V 0.5 0.2 0.5 0.2 A A VIH = VDD and VIL = GND VIH = VDD and VIL = GND 96 96 % ILOAD = 2 mA and VDD = 5 V, full-scale loaded Linearity calculated using a reduced code range (Code 256 to Code 16,128). Guaranteed by design and characterization, not production tested. 3 Total current flowing into all pins. 1 2 Rev. D | Page 3 of 20 AD5641 Data Sheet TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2. Table 3. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 2 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK falling edge ignored All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 30 MHz. t4 t2 t9 t1 SCLK t8 t3 t7 SYNC t6 t5 SDIN D15 D14 D2 D1 Figure 2. Timing Diagram Rev. D | Page 4 of 20 D0 D15 D14 04611-002 1 Limit 1 33 5 5 10 5 4.5 0 20 13 Data Sheet AD5641 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 4. Parameter VDD to GND Digital Input Voltage to GND VOUT to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature SC70 Package JA Thermal Impedance JC Thermal Impedance LFCSP Package JA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature ESD Rating -0.3 V to +7.0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +125C -65C to +160C 150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 433.34C/W 149.47C/W 95C/W 260C 20 sec to 40 sec 2.0 kV Rev. D | Page 5 of 20 AD5641 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) SDIN 3 6 VDD 1 VOUT 5 GND 4 VDD SCLK 2 SDIN 3 AD5641 TOP VIEW (Not to Scale) 6 VOUT 5 GND 4 SYNC NOTES: 1. CONNECT THE EXPOSED PAD TO GND. 04611-045 SCLK 2 AD5641 04611-003 SYNC 1 Figure 4. 6-Lead LFCSP Pin Configuration Figure 3. 6-Lead SC70 Pin Configuration Table 5. Pin Function Descriptions SC70 Pin No. 1 LFCSP Pin No. 4 Mnemonic SYNC 2 2 SCLK 3 3 SDIN 4 1 VDD 5 6 5 6 GND VOUT EP Description Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the clocks that follow. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. Ground Reference Point for All Circuitry on the AD5641. Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. Exposed Pad. Connect to GND. Rev. D | Page 6 of 20 Data Sheet AD5641 TYPICAL PERFORMANCE CHARACTERISTICS 4 TUE ERROR (LSB) 2 1 0 -1 2 0 -2 -2 -4 -3 -6 -4 256 2256 4256 6256 8256 10256 DAC CODE 12256 14256 -8 256 04611-004 INL ERROR (LSB) VDD = VREF = 5V c TA = 25C 6 Figure 5. Typical INL 2.0 4256 -2 MAX INL @ VDD = VREF = 3V 14256 MAX TUE ERROR @ VDD = VREF = 5V TUE ERROR (LSB) -4 0.5 0 -0.5 MAX TUE ERROR @ VDD = VREF = 3V -6 -8 MIN TUE ERROR @ VDD = VREF = 5V -10 MIN INL @ VDD = VREF = 5V -1.0 12256 0 MAX INL @ VDD = VREF = 5V 1.0 6256 8256 10256 DAC CODE Figure 8. Typical Total Unadjusted Error (TUE) 1.5 INL ERROR (LSB) 2256 04611-007 3 8 VDD = VREF = 5V TA = 25C -12 -1.5 MIN TUE ERROR @ VDD = VREF = 3V -20 0 20 40 60 80 TEMPERATURE (C) 100 120 04611-005 MIN INL @ VDD = VREF = 3V -2.0 -40 140 Figure 6. INL Error vs. Temperature (3 V/5 V Supply) -14 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 Figure 9. Total Unadjusted Error (TUE) vs. Temperature (3 V/5 V Supply) 5 10 TA = 25C TA = 25C 4 3 5 TUE ERROR (LSB) MAX INL ERROR 1 0 -1 MIN INL ERROR -2 -3 0 MAX TUE ERROR -5 MIN TUE ERROR -10 -5 2.7 3.2 3.7 4.2 SUPPLY (V) 4.7 5.2 -15 2.7 Figure 7. INL Error vs. Supply at 25C 3.2 3.7 4.2 SUPPLY (V) 4.7 5.2 Figure 10. Total Unadjusted Error (TUE) vs. Supply at 25C Rev. D | Page 7 of 20 04611-009 -4 04611-006 INL ERROR (LSB) 2 04611-008 4 AD5641 Data Sheet 0.0025 0.6 0.0020 0.5 0.4 ZERO-CODE ERROR @ VDD = 5V DNL ERROR (LSB) ZERO-CODE ERROR @ VDD = 3V 0.0005 FULL-SCALE ERROR @ VDD = 5V 0 -0.0005 -0.0010 FULL-SCALE ERROR @ VDD = 3V 0.2 0 -0.1 -0.0020 -0.3 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 MAX DNL @ VDD = 5V 0.1 -0.2 -0.0025 -40 MAX DNL @ VDD = 3V 0.3 -0.0015 04611-010 MIN DNL @ VDD = 3V MIN DNL @ VDD = 5V -0.4 -40 -20 Figure 11. Zero-Code/Full-Scale Error vs. Temperature (3 V/5 V) 100 120 140 1.0 TA = 25C TA = 25C 0.8 0.0015 0.6 DNL ERROR (LSB) ZERO-CODE ERROR 0.0005 0 FULL-SCALE ERROR -0.0005 0.4 MAX DNL ERROR 0.2 0 -0.2 MIN DNL ERROR -0.4 -0.0010 -0.6 -0.0015 3.7 4.2 SUPPLY (V) 4.7 5.2 -1.0 2.7 Figure 12. Zero-Code/Full-Scale Error vs. Supply at 25C 3.2 3.7 4.2 SUPPLY (V) 4.7 5.2 04611-014 3.2 04611-011 -0.8 -0.0020 2.7 Figure 15. DNL Error vs. Supply at 25C 0.5 12 VDD = 5V 0.4 TA = 25C 10 NUMBER OF DEVICES 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 VDD = 3V VIH = DVDD VIL = GND TA = 25C VDD = 5V VIH = DVDD VIL = GND TA = 25C 8 6 4 2 IDD (mA) Figure 16. IDD Histogram (3 V/5 V) Figure 13. Typical DNL Rev. D | Page 8 of 20 04611-015 0 0.05885 0.06648 0.06710 0.06773 0.06835 0.06897 0.06960 0.07022 0.07084 0.07147 0.07209 0.07271 0.07334 6256 8256 10256 12256 14256 DAC CODE 0.05814 4256 0.05742 2256 0.05671 -0.5 256 0.05456 0.05527 -0.4 04611-012 DNL ERROR (LSB) ERROR (V) 20 40 60 80 TEMPERATURE (C) Figure 14. DNL Error vs. Temperature (3 V/5 V) 0.0020 0.0010 0 0.05599 ERROR (V) 0.0010 04611-013 0.0015 0.10 TA = 25C 0.09 0.08 0.07 IDD (mA) 0.06 0.05 0.04 0.03 VDD = VREF = 5V 0.02 VDD = VREF = 3V -20 0 20 40 60 80 0.01 100 120 140 TEMPERATURE (C) 0 2.7 Figure 17. Offset Error vs. Temperature (3 V/5 V Supply) 3.7 4.2 4.7 SUPPLY VOLTAGE (V) 5.2 Figure 20. Supply Current vs. Supply Voltage at 25C 0 0.8 -0.002 0.6 VDD = 5V TA = 25C DAC LOADED WITH ZERO-SCALE CODE -0.004 0.4 VDD = 5V -0.006 VOUT (V) -0.008 0.2 0 -0.010 VDD = 3V -0.2 -0.012 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 04611-017 -0.016 -40 DAC LOADED WITH FULL-SCALE CODE -0.4 -0.014 04611-020 GAIN ERROR (%FSR) 3.2 04611-019 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -40 AD5641 04611-016 OFFSET ERROR (mV) Data Sheet -0.6 -15 Figure 18. Gain Error vs. Temperature (3 V/5 V) -10 -5 0 I (mA) 5 10 15 Figure 21. Sink and Source Capability 70 0.10 VDD = 5V 0.09 60 0.08 50 0.07 VDD = 3V IDD (A) 0.06 0.05 VDD = 3V 0.04 0.03 40 30 20 0.02 10 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 0 0 Figure 19. Supply Current vs. Temperature (3 V/5 V Supply) 2000 4000 6000 8000 10000 12000 14000 16000 DIGITAL INPUT CODE Figure 22. Supply Current vs. Digital Input Code Rev. D | Page 9 of 20 04611-021 0.01 04611-018 IDD (mA) VDD = 5V AD5641 Data Sheet CH1 TA = 25C VDD = 5V VDD VDD = 5V TA = 25C CH1 = SCLK CH2 04611-022 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2s/DIV 04611-025 VOUT CH2 = VOUT CH1 1V, CH2 5V, TIME BASE = 50s/DIV Figure 23. Full-Scale Settling Time Figure 26. VDD vs. VOUT 2.458 TA = 25C VDD = 5V 2.456 CH1 = SCLK 2.454 CH2 = VOUT 2.450 2.448 2.446 2.444 2.442 TA = 25C VDD = 5V LOAD = 2k AND 220pF CODE 0x2000 TO 0x1FFF 10ns/SAMPLE NUMBER 2.440 04611-023 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2s/DIV 2.438 2.436 100 200 300 SAMPLE NUMBER 400 500 Figure 27. Digital-to-Analog Glitch Energy Figure 24. Midscale Settling Time VDD = 5V TA = 25C 0 04611-026 AMPLITUDE (V) 2.452 VDD = 5V TA = 25C VDD MIDSCALE LOADED CH1 CH1 CH1 1V, CH2 20mV, TIME BASE = 20s/DIV CH1 5V/DIV Figure 25. Power-On Reset to 0 V Figure 28. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth Rev. D | Page 10 of 20 04611-027 CH2 04611-024 VOUT = 70mV Data Sheet AD5641 700 VOUT 04611-028 CH2 CH1 5V, CH2 1V, TIME BASE = 2s/DIV VDD = 5V TA = 25C UNLOADED OUTPUT 600 500 400 ZERO SCALE 300 MIDSCALE 200 FULL SCALE 100 0 100 1000 10000 FREQUENCY (Hz) Figure 29. Exiting Power-Down Mode 140 Figure 31. Noise Spectral Density 450 3/4 SCALE FULL SCALE 120 MIDSCALE SCLK/SDIN DECREASING VDD = 5V 300 IDD (A) 80 ZERO SCALE SCLK/SDIN INCREASING VDD = 3V 250 200 150 40 100 20 50 0 0 5 10 15 FREQUENCY (MHz) 20 25 SCLK/SDIN DECREASING VDD = 3V 0 1 2 3 4 VLOGIC (V) Figure 32. SCLK/SDIN vs. Logic Voltage Figure 30. IDD vs. SCLK vs. Code Rev. D | Page 11 of 20 5 6 04611-044 0 04611-029 IDD (A) SCLK/SDIN INCREASING VDD = 5V 350 1/4 SCALE 60 TA = 25C 400 100 100000 04611-030 OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz) VDD = 5V TA = 25C CH1 AD5641 Data Sheet TERMINOLOGY Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. See Figure 5 for a plot of typical INL vs. code. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. See Figure 13 for a plot of typical DNL vs. code. Zero-Code Error Zero-code error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5641 because the output of the DAC cannot go below 0 V. Zero-code error is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. See Figure 11 for a plot of zero-code error vs. temperature. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed in mV. See Figure 11 for a plot of full-scale error vs. temperature. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal, expressed as a percent of the full-scale range. Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking the various errors into account. See Figure 8 for a plot of typical TUE vs. code. Zero-Code Error Drift Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in V/C. Gain Error Drift Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x2000 to 0x1FFF). See Figure 27. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Rev. D | Page 12 of 20 Data Sheet AD5641 THEORY OF OPERATION DIGITAL-TO-ANALOG SECTION OUTPUT AMPLIFIER The AD5641 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 33 is a block diagram of the DAC architecture. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to VDD. It is capable of driving a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 21. The slew rate is 0.5 V/s, with a midscale settling time of 8 s with the output loaded. VDD REF (+) SERIAL INTERFACE RESISTOR NETWORK REF (-) VOUT OUTPUT AMPLIFIER GND 04611-031 DAC REGISTER Figure 33. DAC Architecture Because the input coding to the DAC is straight binary, the ideal output voltage is given by D VOUT V DD 16,384 where D is the decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 16,384. RESISTOR STRING The resistor string structure is shown in Figure 34. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The AD5641 has a 3-wire serial interface (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the SDIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5641 compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked in and the programmed function is executed (a change in DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line can be kept low or brought high. In either case, it must be brought high for a minimum of 20 ns before the next write sequence, so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 1.8 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the part, as previously mentioned. However, it must be brought high again just before the next write sequence. INPUT SHIFT REGISTER R R TO OUTPUT AMPLIFIER R The input shift register is 16 bits wide (see Figure 35). The first two bits are control bits, which determine the operating mode of the part (normal mode or any one of three power-down modes). For a complete description of the various modes, see the PowerDown Modes section. The next 14 bits are the data bits, which are transferred to the DAC register on the 16th falling edge of SCLK. SYNC INTERRUPT R 04611-032 R In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 36). Figure 34. Resistor String Structure Rev. D | Page 13 of 20 AD5641 Data Sheet DB15 (MSB) PD1 PD0 DB0 (LSB) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 0 1 NORMAL OPERATION 1 0 1 1 100 k TO GND THREE-STATE 04611-033 1 k TO GND POWER-DOWN MODES Figure 35. Input Register Contents SCLK SDIN DB15 DB0 DB16 04611-034 SYNC DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 16TH FALLING EDGE INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 16TH FALLING EDGE Figure 36. SYNC Interrupt Facility The AD5641 contains a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with 0s and the output voltage is 0 V. It remains there until a valid write sequence is made to the DAC. This is useful in applications in which it is important to know the state of the DAC output while it is in the process of powering up. POWER-DOWN MODES Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options: the output is connected internally to GND through either a 1 k resistor or a 100 k resistor, or the output is left open-circuited (three-stated). Figure 37 shows the output stage. The AD5641 has four separate modes of operation. These modes are software programmable by setting two bits (DB15 and DB14) in the control register. Table 6 shows how the state of the bits corresponds to the operating mode of the device. RESISTOR STRING DAC POWER-DOWN CIRCUITRY Table 6. Operating Modes for the AD5641 DB15 0 DB14 0 0 1 1 1 0 1 AMPLIFIER Operating Mode Normal operation Power-down mode: 1 k to GND 100 k to GND Three-state VOUT RESISTOR NETWORK 04611-035 POWER-ON RESET Figure 37. Output Stage During Power-Down When both bits are set to 0, the part has normal power consumption of 100 A maximum at 5 V. However, for the three power-down modes, the supply current falls to typically 0.2 A at 3 V. The bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit powerdown is typically 13 s for VDD = 5 V and 16 s for VDD = 3 V. See Figure 29 for a plot. Rev. D | Page 14 of 20 Data Sheet AD5641 MICROPROCESSOR INTERFACING the SDIN pin of the AD5641, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0. Figure 38 shows a serial interface between the AD5641 and the ADSP-2101. The ADSP-2101 should be set up to operate in SPORT transmit alternate framing mode. The ADSP-2101 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT is enabled. ADSP-2101* ADSP-BF53x* AD5641* DT0PRI SDIN TSCLK0 SCLK TFS0 SYNC 04611-038 AD5641 to ADSP-2101 Interface *ADDITIONAL PINS OMITTED FOR CLARITY Figure 40. AD5641 to Blackfin ADSP-BF53x Interface AD5641* DT SDIN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 38. AD5641 to ADSP-2101 Interface AD5641 to 68HC11/68L11 Interface Figure 39 shows a serial interface between the AD5641 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5641, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that the CPOL bit is 0 and the CPHA bit is 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 are configured as previously described, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5641, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. 80C51/80L51* AD5641* P3.3 SYNC TxD SCLK RxD SDIN *ADDITIONAL PINS OMITTED FOR CLARITY Figure 41. AD5641 to 80C51/80L51 Interface AD5641* PC7 SYNC SCK SCLK MOSI SDIN AD5641 to MICROWIRE Interface 04611-037 68HC11/ 68L11* The 80C51/80L51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data LSB first. The AD5641 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. Figure 42 shows an interface between the AD5641 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5641 on the rising edge of SK. *ADDITIONAL PINS OMITTED FOR CLARITY MICROWIRE* Figure 39. AD5641 to 68HC11/68L11 Interface AD5641 to Blackfin(R) ADSP-BF53x Interface Figure 40 shows a serial interface between the AD5641 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5641, the setup for the interface is as follows: DT0PRI drives AD5641* CS SYNC SK SCLK SO SDIN *ADDITIONAL PINS OMITTED FOR CLARITY Rev. D | Page 15 of 20 Figure 42. AD5641 to MICROWIRE Interface 04611-040 SCLK Figure 41 shows a serial interface between the AD5641 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5641, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5641, P3.3 is taken low. 04611-039 SYNC 04611-036 AD5641 to 80C51/80L51 Interface TFS AD5641 Data Sheet APPLICATIONS The AD5641 comes in tiny LFCSP and SC70 packages with less than 100 A supply current. Because of this, the choice of reference depends on the application requirement. For space-saving applications, the ADR02 is available in an SC70 package and has excellent drift at 9 ppm/C (3 ppm/C in the R-8 package). It also provides very good noise performance at 3.4 V p-p in the 0.1 Hz to 10 Hz range. BIPOLAR OPERATION USING THE AD5641 The AD5641 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 44. The circuit in Figure 44 gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or OP295 as the output amplifier. R2 = 10k +5V +5V Because the supply current required by the AD5641 is extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended in this case. It requires less than 100 A of quiescent current and can, therefore, drive multiple DACs in one system, if required. It also provides very good noise performance at 8 V p-p in the 0.1 Hz to 10 Hz range. R1 = 10k AD820/ OP295 V V OUT DD 10F 0.1F +5V AD5641 -5V 3-WIRE SERIAL INTERFACE 7V 04611-042 CHOOSING A REFERENCE AS POWER SUPPLY FOR THE AD5641 Figure 44. Bipolar Operation with the AD5641 5V ADR395 SYNC SCLK AD 5641 D R1 R2 R2 VOUT V DD V DD R1 16,384 R1 VOUT = 0V TO 5V SDIN 04611-041 3-WIRE SERIAL INTERFACE The output voltage for any input code can be calculated as where D represents the input code in decimal (0 - 16384). With VDD = 5 V, R1 = R2 = 10 k, Figure 43. ADR395 as Power Supply to AD5641 10 D 5 V VOUT 16,384 Table 7 lists some recommended precision references for use as supplies to the AD5641. Table 7. Precision References for Use with AD5641 Part No. ADR435 ADR425 ADR02 ADR02 ADR395 Initial Accuracy (mV max) 2 2 3 3 5 Temperature Drift (ppm/C max) 3 (R-8) 3 (R-8) 3 (R-8) 3 (SC70) 9 (TSOT-23) 0.1 Hz to 10 Hz Noise (V p-p typ) 8 3.4 10 10 8 This is an output voltage range of 5 V with 0x0000 corresponding to a -5 V output, and 0x3FFF corresponding to a +5 V output. Rev. D | Page 16 of 20 Data Sheet AD5641 USING THE AD5641 WITH A GALVANICALLY ISOLATED INTERFACE POWER SUPPLY BYPASSING AND GROUNDING In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the DAC is functioning. iCoupler(R) provides isolation in excess of 2.5 kV. The AD5641 use a 3-wire serial logic interface, so the ADuM1300 three-channel digital isolator provides the required isolation (see Figure 45). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5641. 5V REGULATOR POWER 10F 0.1F VDD VOA VIA SCLK ADuM1300 AD5641 SDI VIB VOB SYNC DATA VIC VOC SDIN VOUT GND 04611-043 SCLK Figure 45. AD5641 with a Galvanically Isolated Interface When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5641 should have separate analog and digital sections, each having its own area of the board. If the AD5641 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5641. The power supply to the AD5641 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be physically as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor has low effective series resistance (ESR) and effective series inductance (ESI), such as in common ceramic types of capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. D | Page 17 of 20 AD5641 Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 6 5 4 1 2 3 2.40 2.10 1.80 PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 1.10 0.80 0.30 0.15 0.10 MAX 0.40 0.10 0.30 0.10 0.22 0.08 SEATING PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 46. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 1.50 1.40 1.30 2.10 2.00 1.90 0.65 REF 4 PIN 1 INDEX AREA EXPOSED PAD 0.45 0.40 0.35 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.203 REF 0.35 0.30 0.25 0.05 MAX 0.00 MIN 1 3 BOTTOM VIEW 0.20 MIN 1.70 1.60 1.50 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-229 Figure 47. 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] 2.00 x 3.00 mm Body, Very Very Thin, Dual Lead (CP-6-5) Dimensions shown in millimeters Rev. D | Page 18 of 20 10-18-2010-A 3.10 3.00 2.90 6 Data Sheet AD5641 ORDERING GUIDE Model 1 AD5641AKSZ-REEL7 Temperature Range -40C to +125C Description 16 LSB INL AD5641AKSZ-500RL7 -40C to +125C 16 LSB INL AD5641ACPZ-REEL7 -40C to +125C 16 LSB INL AD5641BKSZ-REEL7 -40C to +125C 4 LSB INL AD5641BKSZ-500RL7 -40C to +125C 4 LSB INL 1 Package Option KS-6 Branding D3Q KS-6 D3Q 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-6-5 8A 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3P KS-6 D3P Package Description 6-Lead Thin Shrink Small Outline Transistor Package [SC70] 6-Lead Thin Shrink Small Outline Transistor Package [SC70] Z = RoHS Compliant Part. Rev. D | Page 19 of 20 AD5641 Data Sheet NOTES (c)2005-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04611-0-2/12(D) Rev. D | Page 20 of 20