UA1 Series 0.35 m ULC Series Description The UA1 series of ULCs is well suited for conversion large sized CPLDs and FPGAs. Devices are implemented in high-performance CMOS technology with 0.35- m (drawn) channel lengths, and are capable of supporting flip-flop toggle rates of 600 MHz at 3.3V and 360 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V. The architecture of the UA1 series allows for efficient conversion of many PLD architecture and FPGA device types with higher IO count. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary-scan and scan-path testing. Conversion to the UA1 series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100mA or more even when not being clocked. The UA1 series has a very low standby consumption of 0.3 nA/gate typically commercial temp, which would yield a standby current of 0.3nA/gate, 42mA on a 144,000 gate design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared. The UA1 series provides several options for output buffers, including a variety of drive levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available as required. The UA1 series is designed to allow conversions of high performance 3.3V devices as well as 2.5V devices. Support of mixed supply conversions is also possible, allowing optimal trade-offs between speed and power consumption. Features High performance ULC family suitable for largesized CPLDs and FPGAs Conversions to over 1,000,000 FPGA gates Pin counts to over 976 pins Any pin-out matched due to limited number of dedicated pads Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA 2.5V and/or 3.3V operation Power on Reset Low quiescent current: 0.3 nA/gate Standard 2, 4, 6, 8,10, 12 and 18mA I/Os Available in commercial, industrial and automotive, grades CMOS/TTL/PCI Interface ESD (2 kV) and Latch-up Protected I/O High Noise & EMC Immunity: 0.35 m Drawn CMOS, 3 and 4 Metal Layers High System Frequency Skew Control: * Clock Tree Synthesis Software 2.5Volts & 3.3Volts Operation; Single or Dual Supply Modes Low Power Consumption: * 0.25 W/Gate/MHz @3.3 V * 0.18 W/Gate/MHz @2.5 V Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATPG) High Speed Performances: * Internal Decoupling * 150 ps Typical Gate Delay @3.3 V * Signal Filtering between Periphery & Core * I/O with Slew Rate Control * Typical 600 MHz Toggle Frequency @3.3V * Typical 360 MHz Toggle Frequency @2.5V Rev. A - 30 March, 2000 1 UA1 Series Array Organization Part Number Max Pad Count Full Programmable Usable Pads Routable Gates Equivalent FPGA Gates UA1044 UA1068 UA1084 UA1100 UA1120 UA1132 UA1144 UA1160 UA1184 UA1208 UA1228 UA1256 UA1304 UA1352 UA1388 UA1432 UA1484 UA1540 UA1600 UA1700 UA1800 UA1900 UA1976 44 68 84 100 120 132 144 160 184 208 228 256 304 352 388 432 484 540 600 700 800 900 976 36 60 76 92 112 124 136 152 176 200 220 240 288 336 372 416 468 516 576 676 776 876 952 3729 11760 19734 29760 42211 52222 63298 79866 107538 131324 160020 204552 292288 369164 451269 565431 658314 826353 1025460 1407636 1691906 2151765 2306609 14916 47044 78936 119040 168844 208888 253192 319464 430152 525296 640080 818208 1169152 1476656 1805076 2261724 2633256 3305412 4101840 5630544 6767624 8607060 9226436 Architecture The basic element of the UA1 family is called a cell. One cell can typically implement between one to four FPGA gates. Cells are located contiguously through out the core of the device, with routing resources provided in three to four metal layers above the cells. Some cell blockage does occur due to routing, and utilization will be significantly greater with three metal routing than two. The sizes listed in the Product Outline are estimated usable amounts using three metal layers. I/O cells are provided at each pad, and may be configured as inputs, outputs, I/Os, VDD or VSS as required to match any FPGA or PLD pinout. In order to improve noise immunity within the device, separate VDD and VSS busses are provided for the internal cells and the I/O cells. I/O buffer interfacing I/O Flexibility All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator could be located close to each buffer. I/O Options Inputs Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull up or pull down resistor. Fast Output Buffer Fast output buffers are able to source or sink 2 to 18mA at 3.3Vaccording to the chosen option. 36mA achievable, using 2 pads. 2 Rev. A - 30 March, 2000 UA1 Series Slew Rate Controlled Output Buffer In this mode, the p- and n-output transistor commands are delayed, so that they are never set "ON" simultaneously, resulting in a low switching current and low noise. These buffer are dedicated to very high load drive. 2.5-V Compatibility The UA1 series of ULC's is fully capable of supporting high-performance operation at 2.5 V or 3.3 V. The performance specifications of any given ULC design however, must be explicitly specified as 2.5 V, 3.3 V or both. Power Supply and Noise Protection The speed and density of the UA1 technology causes large switching current spikes for example either when: 16 high current output buffers switch simultaneously, or 10% of the 700 000 gates are switching within a window of 1ns. Sharp edges and high currents cause some parasitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the setting time of the current and causes voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the UA1 core matrix, several mechanisms have been implemented inside the UA1 arrays. Two kinds of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. I/O buffers switching protection Three features are implemented to limit the noise generated by the switching current: The power supplies of the input and output buffers are separated. The rise and fall times of the output buffers can be controlled by an internal regulator. A design rule concerning the number of buffers connected on the same power supply line has been imposed. Matrix switching current protection This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers. Absolute Maximum Ratings Max Supply Voltage (VDD) 3.6 V Max Supply Voltage (VDD5) 5.5 V Input Voltage (VIN)VDD + 0.5 V 5V Tolerant/CompliantVDD5 + 0.5 V Storage Temperature -65 to 150C Operating Ambient Temperature -55 to 125C Rev. A - 30 March, 2000 3 UA1 Series Recommended Operating Range VDD 2.5 V +/- 5% or 3.3 V +/- 5% Operating Temperature Commercial 0 to 70C Industrial -40 to 85C DC Characteristics 2.5V Specified at VDD = +2.5V +/- 5% Symbol Parameter Buffer Min Typ Max Unit TA VDD IIH Operating Temperature Supply Voltage All All -55 2.3 2.5 +125 2.7 C V High level input current IIL Low Level input current CMOS PCI CMOS PCI IOZ High-Impedance State Output Current All IOS Output short-circuit current PO11 VIH High-level Input Voltage VIL Low-Level Input Voltage Vhys Hysteresis PO11 CMOS PCI CMOS Schmitt CMOS PCI CMOS Schmitt CMOS Schmitt VOH High-Level output voltage PO11 0.7VDD PCI 0.9VDD VOL 4 Low-Level output voltage 10 10 -10 -10 10 9 Conditions A VIN=VDD,VDD=VDD(max) A VIN=VSS,VDD=VDD (max) A mA VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD= VDD (max) 6 0.7VDD 0.475VDD 0.7VDD V 1.5 1.0 0.5 0.3VDD 0.325VDD 0.3VDD V V PO11 0.4 PCI 0.1VDD V IOH = 1.4mA, VDD = VDD (min) IOH = -500 A V IOL = 1.4 mA, VDD = VDD (min) IOL = 1.5 mA Rev. A - 30 March, 2000 UA1 Series 3.3V Specified at VDD = +3.3 V +/- 5% Symbol Parameter Buffer Min TA VDD IIH Operating Temperature Supply Voltage High level input current -55 3.0 IIL Low Level input current All All CMOS PCI CMOS PCI IOZ High-Impedance State Output Current All IOS Output short-circuit current PO11 VIH High-level Input Voltage VIL Low-Level Input Voltage PO11 CMOS,LVTTL PCI CMOS Schmitt CMOS PCI -10 Conditions C V A VIN=VDD,VDD=VDD(max) A VIN=VSS,VDD=VDD (max) 10 A mA VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD= VDD (max) -9 2.0 0.475VDD 2.0 V 1.7 0.8 0.325VDD Hysteresis VOH High-Level output voltage PO11 0.7VDD PCI 0.9VDD Rev. A - 30 March, 2000 Unit +125 3.6 10 10 14 Vhys Low-Level output voltage 3.3 Max -10 CMOS/TTL-level Schmitt TTL-level Schmitt VOL Typ 1.1 V 0.8 0.6 V PO11 0.4 PCI 0.1VDD V IOH = 2mA, VDD = VDD (min) IOH = -500 A V IOL = 2 mA, VDD = VDD (min) IOL = 1.5 mA 5 UA1 Series 5V Specified at VDD = +5V +/- 5% Symbol Parameter Buffer Min TA VDD VDD5 IIH Operating Temperature Supply Voltage Supply Voltage High level input current -55 3.0 4.5 IIL Low Level input current All 5V Tolerant 5V Compliant CMOS PCI CMOS PCI IOZ High-Impedance State Output Current All -10 IOS Output short-circuit current PO11V VIH High-level Input Voltage VIL Low-Level Input Voltage PO11V PICV, PICV5 PCI CMOS/TTL-level Schmitt Typ 3.3 5.0 Max Unit Conditions +125 3.6 5.5 10 10 C V V A VIN=VDD,VDD=VDD(max) A VIN=VSS,VDD=VDD (max) -10 10 8 mA 2.0 0.475VDD -7 5.0 5.0 2.0 1.7 Vhys Hysteresis PICV, PICV5 PCI CMOS/TTL-level Schmitt TTL-level Schmitt VOH High-Level output voltage PO11V 0.7VDD Low-Level output voltage PO11V5 PO11V PO11V5 0.7VDD5 VOL A 5.5 5.5 V 0.5VDD 0.8 0.325VDD V 1.1 0.8 0.6 VIN = VDD or VSS, VDD = VDD (max), No Pull-up VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD= VDD (max) V 0.5 0.5 V IOH = -1.7mA IOH = -1.7mA V IOL = 1.7 mA I/O Buffer 6 Symbol Parameter Typ Unit Conditions C IN C OUT C I/O Capacitance, Input Buffer (Die) Capacitance, Output Buffer (Die) Capacitance, Bidirectional 2.4 5.6 6.6 PF PF PF 3.3V 3.3V 3.3V Rev. A - 30 March, 2000