LT1997-1
1
Rev 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Precision, High Voltage,
Gain Selectable Difference/Current Sense Amplifier
The LT
®
1997-1 is a difference amplifier that can be used to
amplify small differential signals while rejecting large com-
mon mode signals making it an ideal choice for current sense
applications. It combines a precision operational amplifier
with highly-matched resistors to form a one-chip solution to
amplify and level shift voltages accurately using no external
components. It comes with three standard pin-selectable
gain options (10, 20 and 50), which can be further combined
to form gains from 0.141 to 80 with accuracy of 0.012%
(120ppm). The LT1997-1 also operates with input voltages
between V– and V– + 76V (independent of V+), enabling
robust operation in demanding industrial environments.
Its excellent resistor matching results in a common mode
rejection ratio of greater than 109dB (Gain = 10).
The resistors maintain their excellent matching over tem-
perature; the matching temperature coefficient is guaranteed
less than 1ppm/°C. The resistors are extremely linear with
voltage, resulting in a gain nonlinearity of less than 2ppm.
The LT1997-1 is fully specified at 5V and ±15V supplies
and from –40°C to 125°C. The device is available in space
saving 16-lead MSOP and 4mm × 4mm DFN14 packages.
Precision Wide Voltage Range, Bidirectional Current Monitor Typical Distribution of CMRR
(G = 10)
n Precision Gain: Up to 80V/V
n Input Common Mode Voltage Range: V– to V– + 76V
n 109dB Minimum CMRR (Gain = 10)
n 0.012% (120ppm) Maximum Gain Error (Gain = 10)
n 1ppm/°C Maximum Gain Error Drift
n 2ppm Maximum Gain Nonlinearity
n Wide Supply Voltage Range: 3.3V to 50V
n Rail-to-Rail Output
n 350µA Supply Current
n 65µV Maximum Op Amp Offset Voltage
n 650kHz –3dB Bandwidth (Gain=10)
n Low Power Shutdown: 20µA
n Space-Saving MSOP and DFN Packages
All registered trademarks and trademarks are the property of their respective owners.
APPLICATIONS
n High Side or Low Side Current Sensing
n Bidirectional Wide Common Mode Range Current
Sensing
n High Voltage to Low Voltage Level Translation
n Industrial Data-Acquisition Front-Ends
n Replacement for Isolation Circuits
n Differential to Single-Ended Conversion
19971 TA01a
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
15V
VSOURCE = –15V TO 61V
–15V
VOUT = ±10mV/mA
RC
1Ω
–
+
RSENSE
1Ω
LOAD
LT1997-1
661 UNITS
FROM 2 RUNS
MS16(12)
V
S
= ±15V
V
CM
= –15V TO
CMRR (µV/V = ppm)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
50
100
150
200
250
NUMBER OF UNITS
19971 TA01b
LT1997-1
2
Rev 0
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TABLE OF CONTENTS
Features ............................................................................................................................ 1
Applications ....................................................................................................................... 1
Typical Application ............................................................................................................... 1
Description......................................................................................................................... 1
Absolute Maximum Ratings ..................................................................................................... 3
Pin Configuration ................................................................................................................. 3
Order Information ................................................................................................................. 3
Electrical Characteristics ........................................................................................................ 4
Typical Performance Characteristics .......................................................................................... 9
Pin Functions .....................................................................................................................14
Block Diagram ....................................................................................................................15
Applications Information .......................................................................................................16
Package Description ............................................................................................................28
Typical Application ..............................................................................................................30
Related Parts .....................................................................................................................30
LT1997-1
3
Rev 0
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (V+ to V–) ........................................ 60V
+INA, –INA, +INB, –INB,
+INC, –INC (Note 2) ..................(V– + 80V) to (V––0.3V)
REF, REF1, REF2..................... (V– + 60V) to (V– – 0.3V)
SHDN ..................................... (V+ + 0.3V) to (V– – 0.3V)
Output Current (Continuous) (Note 6) ....................50mA
Output Short-Circuit Duration
(Note 3) ..........................................Thermally Limited
(Note 1)
1
3
4
5
6
7
+INA
+INB
NC
+INC
SHDN
REF
–INA
–INB
NC
–INC
V+
OUT
15
V–
14
12
11
10
9
8
TOP VIEW
DF PACKAGE
14(12)-LEAD (4mm × 4mm) PLASTIC DFN
TJMAX = 150°C, θJA = 45°C/W , θJC = 3°C/W
EXPOSED PAD (PIN 15) IS V–, MUST BE SOLDERED TO PCB
1
3
5
6
7
8
+INA
+INB
+INC
REF1
REF2
V–
16
14
12
11
10
9
–INA
–INB
–INC
V+
SHDN
OUT
TOP VIEW
MS PACKAGE
VARIATION: MS16 (12)
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 130°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED
TEMPERATURE RANGE
LT1997IDF-1#PBF LT1997IDF-1#TRPBF 19971 14-Lead (4mm × 4mm) Plastic DFN –40°C to 85°C
LT1997HDF-1#PBF LT1997HDF-1#TRPBF 19971 14-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT1997IMS-1#PBF LT1997IMS-1#TRPBF 19971 16-Lead Plastic MSOP –40°C to 85°C
LT1997HMS-1#PBF LT1997HMS-1#TRPBF 19971 16-Lead Plastic MSOP –40°C to 125°C
*The temperature grade is identified by a label on the shipping container. Consult ADI Marketing for parts specified with wider operating temperature ranges.
Parts ending with PBF are RoHS and WEEE compliant.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Temperature Range (Notes 4, 5)
LT1997I-1 .................................................–40 to 85°C
LT1997H-1 .............................................–40 to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range ......................–65 to 150°C
MSOP Lead Temperature (Soldering, 10 sec) ........300°C
LT1997-1
4
Rev 0
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆G Gain Error
MS16 Package
VOUT=±10V
G=10
l
±0.005
±0.012
±0.014
%
%
G=20
l
±0.01 ±0.022
±0.028
%
%
G=50
l
±0.015 ±0.038
±0.04
%
%
∆G Gain Error
DF14 Package
VOUT=±10V
G=10
l
±0.005
±0.017
±0.019
%
%
G=20
l
±0.01 ±0.025
±0.03
%
%
G=50
l
±0.015 ±0.051
±0.053
%
%
∆G/∆T Gain Drift vs Temperature (Note 6) VOUT=±10V l±0.2 ±1 ppm/°C
GNL Gain Nonlinearity VOUT=±10V
l
±1 ±2
±3
ppm
ppm
VOS Op Amp Offset Voltage (Note 9) V– < VCMOP < V+ – 1.75V
l
±20 ±65
±200
µV
µV
∆VOS/∆T Op Amp Offset Voltage Drift (Note 6) V– < VCMOP < V+ – 1.75V l±0.5 ±1.5 µV/°C
IBOp Amp Input Bias Current V– + 0.25V < VCMOP < V+ – 1.75V
l
–5
–15
±2 5
15
nA
nA
IOS Op Amp Input Offset Current V– + 0.25V < VCMOP < V+ – 1.75V
l
–3
–10
±0.5 3
10
nA
nA
RIN Input Impedance (Note 8) Common Mode
G=10
G=20
G=50
l
l
l
69.3
66.1
64.2
82.5
78.75
76.5
95.7
91.4
88.8
kΩ
kΩ
kΩ
Differential
G=10
G=20
G=50
l
l
l
25.2
12.6
5
30
15
6
34.8
17.4
7
kΩ
kΩ
kΩ
CMRR Common Mode Rejection Ratio
MS16 Package
G = 10, VCM = –15V to +14.575V
l
109
107
126 dB
dB
G = 10, VCM = –15V to +61V, +INC = –INC = 0V
l
84
82
98 dB
dB
G = 20, VCM = –15V to +13.9125V
l
109
107
128 dB
dB
G = 50, VCM = –15V to +13.515V
l
116
114
130 dB
dB
CMRR Common Mode Rejection Ratio
DF14 Package
G = 10, VCM = –15V to +14.575V
l
107
100
123 dB
dB
G = 10, VCM = –15V to +61V, +INC = –INC = 0V
l
81
78
96 dB
dB
G = 20, VCM = –15V to +13.9125V
l
107
102
124 dB
dB
G = 50, VCM = –15V to +13.515V
l
111
107
125 dB
dB
The l denotes the specifications which apply over the full operating
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at
TA=25°C. Difference Amplifier Configuration, V+ = 15V, V– = –15V, VCM = VOUT = VREF = VREF1 = VREF2 = 0V. VCMOP is the common
mode voltage of the internal op amp.
LT1997-1
5
Rev 0
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Input Voltage Range (Note 7) +INA/–INA
+INA/–INA (+INC/–INC Connected to Ground)
+INB/–INB
+INC/–INC
l
l
l
l
–15
–15
–15
–15
14.575
61
13.9125
13.515
V
V
V
V
∆R/R Reference Divider Matching Error
∆R
R=
R
REF1
– R
REF2
RREF1 +RREF2
2
⎛
⎝
⎜⎞
⎠
⎟
Available in MS16 Package Only
l
±0.002 ±0.006
±0.008
%
%
PSRR Power Supply Rejection Ratio (Note 9) VS=±1.65V to ±25V, VCM=VOUT=Mid-Supply l114 124 dB
eni Input Referred Noise Voltage Density f=1kHz
G=10
G=20
G=50
31
26
22
nV/√Hz
nV/√Hz
nV/√Hz
Input Referred Noise Voltage f=0.1Hz to 10Hz
G=10
G=20
G=50
0.9
0.8
0.7
µVP-P
µVP-P
µVP-P
VOL Output Voltage Swing Low (Referred
to V–)
No Load
ISINK=5mA
l
l
30
280
150
500
mV
mV
VOH Output Voltage Swing High (Referred
to V+)
No Load
ISOURCE=5mA
l
l
30
400
150
900
mV
mV
ISC Short-Circuit Output Current 50Ω to V+
50Ω to V–
l
l
10
10
32
34
mA
mA
SR Slew Rate ∆VOUT=±5V l1.7 4 V/µs
BW Small Signal –3dB Bandwidth G=10
G=20
G=50
650
500
300
kHz
kHz
kHz
tSSettling Time G=10
0.1%, ∆VOUT=10V
0.01%, ∆VOUT=10V
6.3
21.3
µs
µs
G=20
0.1%, ∆VOUT=10V
0.01%, ∆VOUT=10V
7.5
15.4
µs
µs
G=50
0.1%, ∆VOUT=10V
0.01%, ∆VOUT=10V
8.6
23
µs
µs
VSSupply Voltage
l
3
3.3
50
50
V
V
tON Turn-On Time 16 µs
VIL SHDN Input Logic Low (Referred to V+) l–2.5 V
VIH SHDN Input Logic High (Referred to V+)l–1.2 V
ISHDN SHDN Pin Current l–10 –15 µA
ISSupply Current Active, VSHDN ≥ V+ – 1.2V
Active, VSHDN ≥ V+ – 1.2V
Shutdown, VSHDN ≤ V+ – 2.5V
Shutdown, VSHDN ≤ V+ – 2.5V
l
l
350
20
400
600
25
70
µA
µA
µA
µA
The l denotes the specifications which apply over the full operating
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at
TA=25°C. Difference Amplifier Configuration, V+ = 15V, V– = –15V, VCM = VOUT = VREF = VREF1 = VREF2 = 0V. VCMOP is the common
mode voltage of the internal op amp.
LT1997-1
6
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at
TA=25°C. Difference Amplifier Configuration, V+ = 5V, V– = 0V, VCM = VOUT = VREF = VREF1 = VREF2 = Mid-Supply. VCMOP is the
common mode voltage of the internal op amp.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆G Gain Error
MS16 Package
VOUT=1V to 4V
G=10
l
±0.005
±0.012
±0.014
%
%
G=20
l
±0.01 ±0.022
±0.028
%
%
G=50
l
±0.015 ±0.035
±0.037
%
%
∆G Gain Error
DF14 Package
VOUT=1V to 4V
G=10
l
±0.005
±0.017
±0.019
%
%
G=20
l
±0.01 ±0.024
±0.028
%
%
G=50
l
±0.015 ±0.048
±0.05
%
%
∆G/∆T Gain Drift vs Temperature (Note 6) VOUT=1V to 4V l±0.2 ±1 ppm/°C
GNL Gain Nonlinearity VOUT=1V to 4V ±1 ppm
VOS Op Amp Offset Voltage (Note 9) V–<VCMOP<V+ – 1.75V
l
±20 ±65
±240
µV
µV
∆VOS/∆T Op Amp Offset Voltage Drift (Note 6) V–<VCMOP<V+ – 1.75V l±0.5 ±1.5 µV/°C
IBOp Amp Input Bias Current V– + 0.25V<VCMOP<V+ – 1.75V
l
–5
–15
±2 5
15
nA
nA
IOS Op Amp Input Offset Current V– + 0.25V<VCMOP<V+ – 1.75V
l
–3
–10
±0.5 3
10
nA
nA
RIN Input Impedance (Note 8) Common Mode
G=10
G=20
G=50
l
l
l
69.3
66.1
64.2
82.5
78.75
76.5
95.7
91.4
88.8
kΩ
kΩ
kΩ
Differential
G=10
G=20
G=50
l
l
l
25.2
12.6
5
30
15
6
34.8
17.4
7
kΩ
kΩ
kΩ
CMRR Common Mode Rejection Ratio
MS16 Package
G=10, VCM = 0V to +3.325V
l
106
104
124 dB
dB
G=20, VCM = 0V to +3.2875V
l
109
106
125 dB
dB
G=50, VCM = 0V to +3.265V
l
112
109
126 dB
dB
CMRR Common Mode Rejection Ratio
DF14 Package
G=10, VCM = 0V to +3.325V
l
104
100
119 dB
dB
G=20, VCM = 0V to +3.2875V
l
105
102
120 dB
dB
G=50, VCM = 0V to 3.265V
l
107
105
121 dB
dB
∆R/R Reference Divider Matching Error
∆R
R=RREF1 – RREF2
RREF1+RREF2
2
⎛
⎝
⎜⎞
⎠
⎟
Available in MS16 Package Only
l
±0.002 ±0.006
±0.008
%
%
LT1997-1
7
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection Ratio (Note 9) VS=±1.65V to ±25V, VCM=VOUT=Mid-Supply l114 124 dB
eni Input Referred Noise Voltage Density f=1kHz
G=10
G=20
G=50
31
26
22
nV/√Hz
nV/√Hz
nV/√Hz
Input Referred Noise Voltage f=0.1Hz to 10Hz
G=10
G=20
G=50
0.9
0.8
0.7
µVP-P
µVP-P
µVP-P
VOL Output Voltage Swing Low (Referred to V–) No Load
ISINK=5mA
l
l
10
280 50
500 mV
mV
VOH Output Voltage Swing High (Referred to V+) No Load
ISOURCE=5mA
l
l
10
400 50
800 mV
mV
ISC Short-Circuit Output Current 50Ω to V+
50Ω to V–
l
l
10
10 30
28 mA
mA
SR Slew Rate ∆VOUT=3V l1.5 2.5 V/µs
BW Small signal –3dB Bandwidth G=10
G=20
G=50
650
500
300
kHz
kHz
kHz
tSSettling Time G=10
0.1%, ∆VOUT=2V
0.01%, ∆VOUT=2V
9
20.4
µs
µs
G=20
0.1%, ∆VOUT=2V
0.01%, ∆VOUT=2V
9.7
18.5
µs
µs
G=50
0.1%, ∆VOUT=2V
0.01%, ∆VOUT=2V
10.9
31.2
µs
µs
VSSupply Voltage
l
3
3.3 50
50 V
V
tON Turn-On Time 22 µs
VIL SHDN Input Logic Low (Referred to V+) l–2.5 V
VIH SHDN Input Logic High (Referred to V+)l–1.2 V
ISHDN SHDN Pin Current l–10 –15 µA
ISSupply Current Active, VSHDN ≥ V+ – 1.2V
Active, VSHDN ≥ V+ –1.2V
Shutdown, VSHDN ≤ V+ – 2.5V
Shutdown, VSHDN ≤ V+ – 2.5V
l
l
330
15
370
525
20
40
µA
µA
µA
µA
The l denotes the specifications which apply over the full operating
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at
TA=25°C. Difference Amplifier Configuration, V+ = 5V, V– = 0V, VCM = VOUT = VREF = VREF1 = VREF2 = Mid-Supply. VCMOP is the
common mode voltage of the internal op amp.
LT1997-1
8
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: See Common Mode Voltage Range in the Applications Information
section of this data sheet for other considerations when taking +INA/
–INA/+INB/–INB/+INC/–INC pins to V– + 80V.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum. This depends on the power supply, input
voltages and the output current.
Note 4: The LT1997I-1 is guaranteed functional over the operating
temperature range of –40°C to 85°C. The LT1997H-1 is guaranteed
functional over the operating temperature range of –40°C to 125°C.
Note 5: The LT1997I-1 is guaranteed to meet specified performance
from –40°C to 85°C. The LT1997H-1 is guaranteed to meet specified
performance from –40°C to 125°C.
Note 6: This parameter is not 100% tested.
Note 7: The input voltage range is guaranteed by the ±15V CMRR tests.
The Input Voltage Range numbers specified in the table guarantee that the
internal op amp operates in its normal operating region. The Input voltage
range can be higher if the internal op amp operates in its Over-The-Top
®
operating region. See Common Mode Voltage Range in the Applications
Information section to determine the valid input voltage range under
various operating conditions.
Note 8: Input impedance is tested by a combination of direct
measurements and correlation to the CMRR and gain error tests.
Note 9: Offset voltage, offset voltage drift and PSRR are defined as
referred to the internal op amp. The following shows the calculation of
output offset: In the case of balanced source resistance, VOS,OUT = (VOS
• NOISEGAIN) + (IOS • 150k) + (IB • 150k • (1– RP/RN)) where RP and
RN are the total resistance at the op amp positive and negative terminal,
respectively.
LT1997-1
9
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Distribution of CMRR
(G=10)
Typical Distribution of CMRR
(G=10)
Typical Distribution of CMRR
(G=10)
Typical Distribution of CMRR
(G=10)
Typical Distribution of CMRR
(G = 20)
Typical Distribution of CMRR
(G = 20)
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Typical Distribution of CMRR
(G = 50)
Typical Distribution of CMRR
(G = 50)
Typical Distribution of Gain Error
(G = 10)
661 UNITS
FROM 2 RUNS
MS16(12)
V
S
= ±15V
V
CM
= –15V TO
CMRR (µV/V = ppm)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
50
100
150
200
250
NUMBER OF UNITS
19971 G01
693 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±15V
V
CM
= –15V TO
CMRR (µV/V = ppm)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
50
100
150
200
250
NUMBER OF UNITS
19971 G02
652 UNITS
FROM 2 RUNS
MS16(12)
V
S
= ±15V
V
CM
= –15V TO +61V
+INC = –INC = 0V
CMRR (µV/V = ppm)
–100
–80
–60
–40
–20
0
20
40
60
80
100
0
50
100
150
200
250
NUMBER OF UNITS
19971 G03
684 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±15V
V
CM
= –15V TO +61V
+INC = –INC = 0V
CMRR (µV/V = ppm)
–100
–80
–60
–40
–20
0
20
40
60
80
100
0
50
100
150
200
250
NUMBER OF UNITS
19971 G04
661 UNITS
FROM 2 RUNS
MS16(12)
V
S
= ±15V
V
CM
= –15V TO
+13.9125V
CMRR (µV/V = ppm)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
50
100
150
200
250
NUMBER OF UNITS
19971 G05
693 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±15V
V
CM
= –15V TO
+13.9125V
CMRR (µV/V = ppm)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
50
100
150
200
250
NUMBER OF UNITS
19971 G06
652 UNITS
FROM 2 RUNS
MS16(12)
V
S
= ±15V
V
CM
= –15V TO
CMRR (µV/V = ppm)
–3
–2
–1
0
1
2
3
0
50
100
150
200
250
NUMBER OF UNITS
19971 G07
684 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±15V
V
CM
= –15V TO
CMRR (µV/V = ppm)
–3
–2
–1
0
1
2
3
0
50
100
150
200
250
NUMBER OF UNITS
19971 G08
1357 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±15V
V
OUT
= ±10V
GAIN ERROR (ppm)
–200
–160
–120
–80
–40
0
40
80
120
160
200
0
50
100
150
200
250
300
350
400
NUMBER OF UNITS
19971 G09
LT1997-1
10
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Distribution of Gain Error
(G = 20)
Typical Distribution of Gain Error
(G = 50)
Typical Distribution of Op Amp
PSRR
Typical Distribution of Gain
Nonlinearity
Typical Distribution of Op Amp
Offset Voltage
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Typical Gain Error for RL = 5kΩ
(G=10) (Curves Offset for
Clarity)
Typical Gain Error for RL = 10kΩ
(G=10) (Curves Offset for
Clarity)
CMRR vs Frequency
Typical Gain Error for RL=2kΩ
(G=10) (Curves Offset for
Clarity)
1357 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±15V
V
OUT
= ±10V
GAIN ERROR (ppm)
–250
–200
–150
–100
–50
0
50
0
50
100
150
200
250
300
350
NUMBER OF UNITS
19971 G10
1357 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±15V
V
OUT
= ±10V
GAIN ERROR (ppm)
–500
–400
–300
–200
–100
0
100
0
50
100
150
200
250
300
350
NUMBER OF UNITS
19971 G11
1357 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±15V
V
OUT
= ±10V
G = 10
GAIN NONLINEARITY (ppm)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
50
100
150
200
250
300
350
400
450
NUMBER OF UNITS
19971 G12
1388 UNITS
FROM 4 RUNS
BOTH PACKAGES
OFFSET VOLTAGE (µV)
–60
–40
–20
0
20
40
60
0
50
100
150
200
250
300
350
NUMBER OF UNITS
19971 G13
1365 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±1.65V to ±25V
PSRR (µV/V)
–1.5
–1
–0.5
0
0.5
1
1.5
0
50
100
150
200
250
300
350
NUMBER OF UNITS
19971 G14
G = 10
G = 20
G = 50
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0
20
40
60
80
100
120
140
COMMON MODE REJECTION RATIO (dB)
19971 G15
V
S
= ±18V
V
S
= ±15V
V
S
= ±10V
V
S
= ±12V
OUTPUT VOLTAGE (V)
–20
–16
–12
–8
–4
0
4
8
12
16
20
OUTPUT ERROR (2mV/DIV)
19971 G16
V
S
= ±18V
V
S
= ±15V
V
S
= ±10V
V
S
= ±12V
OUTPUT VOLTAGE (V)
–20
–16
–12
–8
–4
0
4
8
12
16
20
OUTPUT ERROR (2mV/DIV)
19971 G17
V
S
= ±18V
V
S
= ±15V
V
S
= ±10V
V
S
= ±12V
OUTPUT VOLTAGE (V)
–20
–16
–12
–8
–4
0
4
8
12
16
20
OUTPUT ERROR (2mV/DIV)
19971 G18
LT1997-1
11
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Gain Error vs Temperature CMRR vs Temperature
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Output Voltage vs Load Current
Maximum Power Dissipation
vs Temperature Gain vs Frequency
Frequency Response
vs Capacitive Load (G = 10)
Frequency Response
vs Capacitive Load (G = 20)
130°C
85°C
25°C
–45°C
OUTPUT CURRENT (mA)
0
5
10
15
20
25
30
–20
–15
–10
–5
0
5
10
15
20
OUTPUT VOLTAGE (V)
19971 G21
DF14(12) θ
JA
= 45°C/W
MS16(12) θ
JA
= 130°C/W
AMBIENT TEMPERATURE (°C)
–60
–40
–20
0
20
40
60
80
100
120
140
160
0
1
2
3
4
5
MAXIMUM POWER DISSIPATION (W)
19971 G22
Input Referred Noise Density
vs Frequency (G = 10)
Frequency Response
vs Capacitive Load (G = 50)
V
S
= ±15V
V
OUT
= ±10V
R
L
= 10kΩ
10 UNITS
G=10
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
–200
–160
–120
–80
–40
0
40
80
120
160
200
–20
–16
–12
–8
–4
0
4
8
12
16
20
GAIN ERROR (ppm)
GAIN ERROR (m%)
19971 G19
V
S
= ±15V
10 UNITS
G=10
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
–10
–8
–6
–4
–2
0
2
4
6
8
10
CMRR (µV/V = ppm)
19971 G20
G = 50
G = 20
G = 10
FREQUENCY (MHz)
0.001
0.01
0.1
1
2
0
5
10
15
20
25
30
35
40
GAIN (dB)
19971 G23
0pF
270pF
560pF
1000pF
1800pF
FREQUENCY (MHz)
0.001
0.01
0.1
1
10
–20
–10
0
10
20
30
40
GAIN (dB)
19971 G24
0pF
270pF
560pF
1000pF
1800pF
2200pF
FREQUENCY (MHz)
0.001
0.01
0.1
1
10
–20
–10
0
10
20
30
40
GAIN (dB)
19971 G25
0pF
270pF
560pF
1000pF
1800pF
2200pF
3300pF
FREQUENCY (MHz)
0.001
0.01
0.1
1
10
–20
–10
0
10
20
30
40
GAIN (dB)
19971 G26
FREQUENCY (Hz)
1
10
100
1k
10k
100k
0
10
20
30
40
50
60
VOLTAGE NOISE DENSITY (nV/√Hz)
19971 G27
LT1997-1
12
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Large-Signal Step ResponseSlew Rate vs Temperature
Input Referred 0.1Hz to 10Hz
Noise (G = 10)
Input Referred Noise Density
vs Frequency (G = 20)
Input Referred 0.1Hz to 10Hz
Noise (G = 20)
Input Referred Noise Density
vs Frequency (G = 50)
Input Referred 0.1Hz to 10Hz
Noise (G = 50) Positive PSRR vs Frequency
Negative PSRR vs Frequency
TIME (10s/DIV)
NOISE VOLTAGE (200nV/DIV)
19971 G28
FREQUENCY (Hz)
1
10
100
1k
10k
100k
0
10
20
30
40
50
60
VOLTAGE NOISE DENSITY (nV/√Hz)
19971 G29
TIME (10s/DIV)
NOISE VOLTAGE (200nV/DIV)
19971 G30
FREQUENCY (Hz)
1
10
100
1k
10k
100k
0
10
20
30
40
50
60
VOLTAGE NOISE DENSITY (nV/√Hz)
19971 G31
TIME (10s/DIV)
NOISE VOLTAGE (200nV/DIV)
19971 G32
G = 10
G = 20
G = 50
FREQUENCY (Hz)
10
100
1k
10k
100k
0
20
40
60
80
100
120
140
160
POWER SUPPLY REJECTION RATIO (dB)
19971 G33
G = 10
G = 20
G = 50
FREQUENCY (Hz)
10
100
1k
10k
100k
0
20
40
60
80
100
120
140
160
POWER SUPPLY REJECTION RATIO (dB)
19971 G34
R
L
= 10kΩ
V
OUT
= ±5V
Rising
Falling
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
1
2
3
4
5
6
7
SLEW RATE (V/µs)
19971 G35
G = 10
R
L
= 10kΩ
C
L
= 1000pF
TIME (4µs/DIV)
VOLTAGE (5V/DIV)
19971 G36
LT1997-1
13
Rev 0
For more information www.analog.com
Settling Time
Small-Signal Step Response Small-Signal Step Response Small-Signal Step Response
Settling Time
Op Amp Offset Voltage
vs Temperature
Quiescent Current vs Temperature Thermal Shutdown Hysteresis
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Quiescent Current
vs Supply Voltage
C
L
= 20pF
C
L
= 1000pF
C
L
= 330pF
G = 10
R
L
=10kΩ
C
L
= 470pF
TIME (µs)
0
5
10
15
20
25
30
35
40
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
140
VOLTAGE (mV)
19971 G37
C
L
= 20pF
C
L
= 1000pF
C
L
= 330pF
G = 20
R
L
=10kΩ
C
L
= 470pF
TIME (µs)
0
5
10
15
20
25
30
35
40
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
140
VOLTAGE (mV)
19971 G38
C
L
= 20pF
C
L
= 1000pF
C
L
= 330pF
G = 50
R
L
=10kΩ
C
L
= 470pF
TIME (µs)
0
5
10
15
20
25
30
35
40
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
140
VOLTAGE (mV)
19971 G39
G = 10
OUTPUT VOLTAGE
ERROR VOLTAGE
TIME (10µs/DIV)
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
ERROR VOLTAGE (mV)
OUTPUT VOLTAGE (V)
19971 G40
G = 10
OUTPUT VOLTAGE
ERROR VOLTAGE
TIME (10µs/DIV)
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
ERROR VOLTAGE (mV)
OUTPUT VOLTAGE (V)
19971 G41
40 UNITS
TEMPERATURE (°C)
–60
–40
–20
0
20
40
60
80
100
120
140
–200
–150
–100
–50
0
50
100
150
200
OP AMP OFFSET VOLTAGE (µV)
19971 G42
10 UNITS
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
200
250
300
350
400
450
500
550
QUIESCENT CURRENT (µA)
19971 G43
TEMPERATURE (°C)
145
150
155
160
165
170
0
100
200
300
400
500
600
SUPPLY CURRENT (µA)
19971 G44
T
A
= 150°C
T
A
= –55°C
PARAMETRIC SWEEP IN ~25°C
INCREMENTS
SUPPLY VOLTAGE (V)
0
10
20
30
40
50
0
100
200
300
400
500
600
QUIESCENT CURRENT (µA)
19971 G45
LT1997-1
14
Rev 0
For more information www.analog.com
PIN FUNCTIONS
V+ (Pin 9/Pin 11): Positive Supply Pin.
V– (EXPOSED PAD Pin 15/Pin 8): Negative Supply Pin.
OUT (Pin 8/Pin 9): Output Pin.
+INA (Pin 1/Pin 1): Noninverting Gain-of-10 Input Pin.
Connects a 15k internal resistor to the internal op amp’s
noninverting input.
+INB (Pin 3/Pin 3): Noninverting Gain-of-20 Input Pin.
Connects a 7.5k internal resistor to the internal op amp’s
noninverting input.
+INC (Pin 5/Pin 5): Noninverting Gain-of-50 Input Pin.
Connects a 3k internal resistor to the internal op amp’s
noninverting input.
–INA (Pin 14/Pin 16): Inverting Gain-of-10 input Pin.
Connects a 15k internal resistor to the internal op amp’s
inverting input.
–INB (Pin 12/Pin 14): Inverting Gain-of-20 input Pin.
Connects a 7.5k internal resistor to the internal op amp’s
inverting input.
–INC (Pin 10/Pin 12): Inverting Gain-of-50 input Pin.
Connects a 3k internal resistor to the internal op amp’s
inverting input.
REF (Pin 7/NA): Reference Input Pin. Sets the output level
when the difference between the inputs is zero.
REF1 (NA/Pin 6): Reference 1 Input Pin. With REF2, sets the
output level when the difference between the inputs is zero.
REF2 (NA/Pin 7): Reference 2 Input Pin. With REF1, sets the
output level when the difference between the inputs is zero.
SHDN (Pin 6/Pin 10): Shutdown Pin. Amplifier is active
when this pin is tied to V+ or left floating. Pulling the pin
more than 2.5V below V+ causes the amplifier to enter a
low power state.
(DFN/MSOP)
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Minimum Supply Voltage
Quiescent Current
vs SHDN Voltage
Shutdown Quiescent Current vs
Supply Voltage
V
SHDN
= 0V
150°C
125°C
85°C
25°C
–40°C
–55°C
SUPPLY VOLTAGE (V)
0
10
20
30
40
50
0
10
20
30
40
50
QUIESCENT CURRENT (µA)
19971 G46
150°C
125°C
85°C
25°C
–40°C
–55°C
SHDN
VOLTAGE (V)
0
5
10
15
0
50
100
150
200
250
300
350
400
450
500
550
QUIESCENT CURRENT (µA)
19971 G47
V
S
= ±15V
T
A
= 125°C
T
A
= 25°C
T
A
= –45°C
TOTAL SUPPLY VOLTAGE (V)
0
1
2
3
4
5
–20
–15
–10
–5
0
5
10
15
20
CHANGE IN OPAMP OFFSET VOLTAGE (µV)
19971 G48
LT1997-1
15
Rev 0
For more information www.analog.com
BLOCK DIAGRAM
MSOP
150k
300k
3k
7.5k
15k
10µA
3k
7.5k
15k
300k
–INC
–INA
–INB
REF2
SHDN
+INA
+INC
+INB
V
+
V
–
OUT
V
+
REF1
19971 BD01
DFN
150k
150k
3k
7.5k
15k
10µA
3k
7.5k
15k
–INC
–INA
–INB
SHDN
+INA
+INC
+INB
V
+
V
–
OUT
V
+
REF
19971 BD02
LT1997-1
16
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure1. Difference Amplifier with Dual-Supply
Operation (Gain=10)
Introduction
The LT1997-1 is a precision, high voltage, high gain ampli-
fier combined with a highly-matched resistor network. It
can easily be configured into many different gain circuits
without adding external components, as it will be shown
in this data sheet. The LT1997-1 provides the resistors
and op amp together in a small package in order to save
board space and reduce complexity. Highly accurate
measurement circuits can be easily constructed with the
LT1997-1. The circuits can be tailored to specific measure-
ment applications.
Common Mode Voltage Range
The common mode voltage range of the LT1997-1 is set
by the voltage range allowed on the LT1997-1’s input pins
and by the input voltage range of the internal op amp.
The internal op amp of LT1997-1 has 2 operating regions:
a) if the common mode voltage at the inputs of the
internal op amp (VCMOP) is between V– and V+ – 1.75V,
the op amp operates in its normal region;
b) If VCMOP is between V+–1.75V and V– + 76V, the op
amp continues to operate, but in its Over-The-Top (OTT)
region with degraded performance (see Over-The-Top
Operation section of this data sheet for more detail).
The LT1997-1 will not operate correctly if the common-
mode voltage at the inputs of the internal op amp (VCMOP)
is below V–, but the part will not be damaged as long as
VCMOP is greater than V––25V and the junction tempera-
ture of the LT1997-1 does not exceed 150ºC.
The voltage on LT1997-1’s input pins should never be
higher than V–+80V or lower than V––0.3V under any
circumstances.
The common mode voltage at the inputs of the internal
op amp (VCMOP) is determined by the voltages on pins
+INA, +INB, +INC and REF (see the Calculating Input Volt-
age Range section). This condition is true provided that
the internal op amp’s output is not clipped and feedback
maintains the internal op amp’s inputs at the same voltage.
In addition to the limits mentioned above, the common
mode input voltage of the amplifier should be chosen so
that the input resistors do not dissipate too much power.
The power dissipated in a 15k resistor must be less than
230mW. It must be less than 115mW for the 7.5k resistor
and less than 46mW for the 3k resistor. For most applica-
tions, the pin voltage limitations will be reached before
the resistor power limitation is reached.
Calculating Input Voltage Range
Figure 2 shows the LT1997-1 in the generalized case
of a difference amplifier, with the inputs shorted for the
common mode calculation. The values of RF and RG are
dictated by how the positive inputs (+INA, +INB, +INC)
and REF pin are connected.
By superposition we can write:
VCMOP =VEXT •
R
F
R
F
+R
G
+VREF •
R
G
R
F
+R
G
Or, solving for VEXT:
VEXT =VCMOP • 1+RG
R
F
⎛
⎝
⎜
⎞
⎠
⎟– VREF •RG
R
F
But valid VCMOP voltages are limited to VS+–1.75V (or
VS–+76V for OTT) on the high side and VS– on the low
side, so:
MAX VEXT =VS+–1.75
( )
• 1+RG
R
F
⎛
⎝
⎜
⎞
⎠
⎟– VREF •RG
R
F
19971 F01
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
VS+
VS–
VOUT
VREF
V–IN
V+IN
–
+
LT1997-1
LT1997-1
17
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
and:
MIN VEXT =VS–
( )
• 1+RG
R
F
⎛
⎝
⎜
⎞
⎠
⎟– VREF •RG
R
F
VREF
RG
RG
VS+
VS–
VCMOP
VOUT
VEXT
–
+
RF
RF
19971 F02
Figure2. Calculating the Common Mode Input Voltage Range
Exceeding the MAX VEXT limit will cause the amplifier to
transition into the Over-The-Top region. The maximum
input voltage for the Over-The-Top region is:
MAX VEXTOTT =VS–+76
( )
• 1+RG
RF
⎛
⎝
⎜
⎞
⎠
⎟– VREF •RG
RF
Keep in mind that the above MAX and MIN values for input
voltage range should not exceed (V– + 80V) to (V– – 0.3V),
the absolute maximum voltage range specified earlier for
LT1997-1’s input pins.
The negative inputs (–INA, –INB, –INC) are not limited by
the internal op amp common mode range (VCMOP) because
they do not affect it. They are limited by the output swing
of the amplifier (and obviously by the allowed voltage
range for the input pins).
Over-The-Top Operation
When the input common mode voltage of the internal op
amp (VCMOP) in the LT1997-1 is biased near or above the
V+ supply, the op amp is operating in the Over-The-Top
(OTT) region. The op amp continues to operate with an
input common mode voltage of up to 76V above V– (re-
gardless of the positive power supply voltage V+), but its
performance is degraded. The op amp’s input bias currents
change from under ±2nA to 14µA. The op amp’s input
offset current rises to ±50nA, which adds ±7.5mV to the
output offset voltage.
In addition, when operating in the Over-The-Top region,
the differential input impedance of the internal op amp
decreases from 1MΩ in normal operation to approximately
3.7kΩ in Over-The-Top operation. This resistance appears
across the summing nodes of the internal op amp and
boosts noise and offset while decreasing speed. Noise
and offset will increase by 33% to 76% depending on the
gain setting. The bandwidth will be reduced by 25% to
43%. For more detail on Over-The-Top operation, consult
the LT6015 data sheet.
Difference Amplifiers
The LT1997-1 is ideally suited to be used as a difference
amplifier. Figure3 shows the basic 4-resistor difference
amplifier and the LT1997-1. A difference gain of 20 is
shown, but can be altered by additional dashed connections.
By connecting the 3k resistors in parallel with the 150k
feedback resistors, the gain is reduced to 0.392. Of course
there are many possible gains and Figure4 shows circuit
schematics of some of those difference amplifier gains.
Note that the common mode voltage at the inputs of the
internal op amp (VCMOP) is set by the voltages at pins
+INA, +INB, +INC and REF.
Figure3. The LT1997-1 Configured as a Difference Amplifier.
Gain Is Set by Connecting the Correct Resistors or Combinations
of Resistors. Gain of 20 Is Shown, with Dashed Lines Modifying It
to a Gain of 0.392
19971 F03
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
V+IN
V–IN
V+IN
RG
RF
+
–
VOUT
RG
RF
DIFFERENCE AMPLIFIER CONFIGURATION
DIFFERENCE AMPLIFIER CONFIGURATION
IMPLEMENTED WITH THE LT1997-1, RF = 150k, RG = 7.5k, GAIN = 20
ADDING THE DASHED CONNECTIONS CONNECT THE
3k RESISTOR IN PARALLEL WITH RF, SO RF IS REDUCED TO 2.94k.
THE GAIN BECOMES 2.94k/7.5k = 0.392
VOUT = GAIN • (V+IN – V–IN)
GAIN = RF/RG
LT1997-1
LT1997-1
18
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure4. Many Difference Amplifier Gains Can Be Achieved by Strapping Pins
19971 F04
V+IN
V+IN V+IN
V+IN
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 10
LT1997-1
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 0.476
LT1997-1
V+IN
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 20
LT1997-1
V+IN
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 30
LT1997-1
V+IN
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 4.545
LT1997-1
V+IN
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 6.364
LT1997-1
V+IN
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 50
LT1997-1
V+IN
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 60
LT1997-1
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 70
LT1997-1
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 80
LT1997-1
V+IN
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 0.141
LT1997-1
LT1997-1
19
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Difference Amplifier: Additional Gains Using Cross-
Coupling
Figure5 shows the basic difference amplifier as well as
the LT1997-1 with cross-coupled inputs. The additional
dashed connections reduce the differential gain from 50
to 40. Using this method, additional gains are achievable
and a few example schematics of the difference amplifiers
using cross-coupling are shown in Figure6. To summarize,
Table1 shows a complete list of all difference amplifier
gains and how they are constructed using (both conven-
tional or cross-coupling) pin strapping. Note that there are
24 unique gains ranging from 0.141 to 80 which can be
achieved with the LT1997-1 using no external components.
Table1. Difference Amplifier Gains
GAIN V+IN V–IN GND (REF) OUT
0.141 +INA –INA +INB, +INC –INB, –INC
0.196 +INA –INA +INC –INC
0.323 +INA –INA –INB, +INC +INB, –INC
0.328 +INB –INB +INA, +INC –INA, –INC
0.392 +INB –INB +INC –INC
0.476 +INA –INA +INB –INB
0.488 +INB –INB –INA, +INC +INA, –INC
0.588 +INA, +INB –INA, –INB +INC –INC
1.613 +INC –INC +INA, +INB –INA, –INB
1.818 +INB –INB +INA –INA
1.905 –INA, +INC +INA, –INC +INB –INB
2.381 +INC –INC +INB –INB
2.727 –INB, +INC +INB, –INC +INA –INA
2.857 +INA, +INC –INA, –INC +INB –INB
4.545 +INC –INC +INA –INA
6.364 +INB, +INC –INB, –INC +INA –INA
10 +INA –INA
20 +INB –INB
30 +INA, +INB –INA, –INB
40 –INA, +INC +INA, –INC
50 +INC –INC
60 +INA, +INC –INA, –INC
70 +INB, +INC –INB, –INC
80 +INA, +INB, +INC –INA, –INB, –INC
Figure5. Cross-Coupling of the LT1997-1 Allows Additional
Gains to Be Constructed
19971 F05
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
V+IN
V–IN
V+IN
RG
RF
+
–
VOUT
RG
RF
DIFFERENCE AMPLIFIER CONFIGURATION
DIFFERENCE AMPLIFIER CONFIGURATION
IMPLEMENTED WITH THE LT1997-1, RF = 150k, RG = 3k, GAIN = 50
GAIN CAN BE ADJUSTED BY CROSS-COUPLING THE INPUTS.
MAKING THE DASHED CONNECTIONS REDUCES THE GAIN FROM 50 TO 40
VOUT = GAIN • (V+IN – V–IN)
GAIN = RF/RG
LT1997-1
LT1997-1
20
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Amplifiers for a Single-Ended Input
All of the difference amplifier configurations discussed
in the preceding section can be used as noninverting or
inverting amplifiers if the input is single-ended. For ex-
ample, to achieve a positive attenuation for a single-ended
input using the LT1997-1, simply ground V–IN and connect
the input signal to V+IN. Similarly, to achieve a negative
attenuation for a single-ended input using the LT1997-1 ,
simply ground V+IN and connect the input signal to V–IN.
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V
–IN
GAIN = 1.905
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 2.727
V
+IN V+IN
LT1997-1LT1997-1
19971 F06
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
V
OUT
V–IN
GAIN = 40
V+IN
LT1997-1
Figure6. Examples of More Difference Amplifier Gains That Can Be Achieved
Figure7. The LT1997-1 Reference Resistors: Split Resistors in the MSOP Package, Single
Resistor in the DFN Package
Reference Resistors
In the preceding discussions, the Reference resistor is
shown as a single 150k resistor. This is true in the DFN
package. In the MSOP package the reference resistor is
split into two 300k resistors (Figure7). Tying the REF1 and
REF2 pins to the same voltage produces the same reference
voltage as tying the VREF pin in the DFN package to that
voltage. Connecting REF1 and REF2 to different voltages
produces an effective reference voltage that is the average
of VREF1 and VREF2. This feature is especially useful when
the desired reference voltage is half way between the sup-
19971 F07
OUT
REF
15k
15k
3k
7.5k 150k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
V+IN
OUT
REF1
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
V
S
+
VS–
VOUT
V
REF
VREF1
V
–IN
V+IN
REF2
300k VREF2
LT1997-1 MSOP
LT1997-1 DFN
LT1997-1 LT1997-1
LT1997-1
21
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
plies. Tying REF1 to VS+ and REF2 to VS– produces the
desired mid-supply voltage without the help of another
external reference voltage (Figure7). The ratio of RREF1
to RREF2 is very precise:
∆R
R=RREF1 – RREF2
RREF1+RREF2
2
⎛
⎝
⎜⎞
⎠
⎟
<60ppm
Shutdown
The LT1997-1 has a shutdown pin (SHDN). Under normal
operation this pin should be tied to V+ or allowed to float.
Tying this pin 2.5V or more below V+ will cause the part
to enter a low power state. The supply current is reduced
to less than 25µA and the op amp output becomes high
impedance. The voltages at the input pins can still be
present even in shutdown mode.
Supply Voltage
The positive supply pin of the LT1997-1 should be bypassed
with a small capacitor (typically 0.1µF) as close to the supply
pins as possible. When driving heavy loads, an additional
4.7µF electrolytic capacitor should be added. When using
split supplies, the same is true for the V– supply pin.
Output
The output of the LT1997-1 can typically swing to within
30mV of either rail with no load and is capable of sourcing
and sinking approximately 30mA at 25°C. The LT1997-1 is
internally compensated to drive at least 2nF of capacitance
under any output loading conditions. For larger capacitive
loads, a 0.22µF capacitor in series with a 150Ω resistor
between the output and ground will compensate the ampli-
fier to drive capacitive loads greater than 2nF.
Distortion
The LT1997-1 features excellent distortion performance
when the internal op amp is operating in the normal op-
erating region. Operating the LT1997-1 with the internal
op amp in the over the top region will increase distortion
due to the lower loop gain of the op amp. Operating the
LT1997-1 with input common mode voltages that go from
the normal to Over-The-Top operation will significantly
degrade the LT1997-1’s linearity as the op amp must
transition between two different input stages. Driving
resistive loads significantly smaller than the 150k internal
feedback resistor will also degrade the amplifier’s linearity
performance.
High Voltage Pin Spacing
For applications with high input voltages, the LT1997-1
pinout eases the printed circuit board (PCB) layout burden.
Voltages at +INA, –INA, +INB, and –INB input pins are
separated from other pins by virtue of unpopulated pin
locations, as illustrated in the Pin Configuration section
of this data sheet.
Power Dissipation Considerations
Because of the ability of the LT1997-1 to operate on power
supplies up to ±25V, to withstand very high input volt-
ages and to drive heavy loads, there is a need to ensure
the die junction temperature does not exceed 150°C. The
LT1997-1 is housed in DF14 (θJA = 45°C/W, θJC = 3°C/W)
and MS16 (θJA = 130°C/W) packages.
In general, the die junction temperature (TJ) can be es-
timated from the ambient temperature (TA), the device’s
power dissipation (PD) and the thermal resistance of the
device and board (θJA).
TJ = TA + PD • θJA
The thermal resistance from the junction to the ambient
environment (θJA) is the sum of the thermal resistance
from the junction to the exposed pad (θJC) and the thermal
resistance from the exposed pad to the ambient environ-
ment (θCA). The θCA value depends on how much PCB
metal is connected to the exposed pad in the board. The
more PCB metal that is used, the lower θCA and θJA will be.
Power is dissipated by the amplifier’s quiescent current, by
the output current driving a resistive load, and by the input
current driving the LT1997-1’s internal resistor network.
PD=VS+– VS–
( )
•IS
( )
+POD +PRESD
LT1997-1
22
Rev 0
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APPLICATIONS INFORMATION
For a given supply voltage, the worst-case output power
dissipation POD(MAX) occurs with the output voltage at half
of either supply voltage. POD(MAX) is given by:
POD(MAX) =VS2
( )
2
R
LOAD
The power dissipated in the internal resistors (PRESD)
depends on the manner the input resistors have been
configured as well as the input voltage, the output voltage
and the voltage on the REF pin. The following equations
and Figure8 show the different components of PRESD
corresponding to the different groups of the LT1997-1’s
internal resistors, assuming that the LT1997-1 is used
with a dual supply configuration with REF pin at ground
(refer to Figure3 for resistor terminologies used in equa-
tions below).
P
RESDA =V+IN
( )
2
RG+RF
P
RESDB =
V–IN – V+IN •RF
RG+RF
⎛
⎝
⎜⎞
⎠
⎟
2
RG
P
RESDC =
V+IN •RF
RG+RF
– VOUT
⎛
⎝
⎜⎞
⎠
⎟
2
RF
PRESD = PRESDA + PRESDB + PRESDC
In general, PRESD increases with higher input voltage and
lower output and REF pin voltages.
Example: For an LT1997-1 in a DFN package mounted on
a PC board with a thermal resistance of 45°C/W, operating
on ±25V supplies and driving a 2.5kΩ load to 12.5V with
V+IN=51V and REF=0V, the total power dissipation is
given by:
P
D=50 • 0.6mA
( )
+12.5
2
2.5k +51
2
165k
+
49.75 – 51• 10
11
⎛
⎝
⎜⎞
⎠
⎟
2
15k +
51• 10
11 – 12.5
⎛
⎝
⎜⎞
⎠
⎟
2
150k
=
0.12W
Assuming a thermal resistance of 45°C/W, the die tem-
perature will experience an 5.4°C rise above ambient.
This implies that the maximum ambient temperature the
LT1997-1 should operate under the above conditions is:
TA = 150°C – 5.4°C = 144.6°C
It is recommended that the exposed pad of the DFN pack-
age have as much PCB metal connected to it as reasonably
available. The more PCB metal connected to the exposed
Figure8. Power Dissipation Example
19971 F08
OUT
REF
15k
15k
3k
7.5k
150k
7.5k
3k 150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
V
S
+
= 25V
VS–
= –25V
VOUT =
12.5V
2.5k
V–IN = 51V – VOUT/10
= 49.75V
V+IN
= 51V
–
+
PRESDA
PRESDC
PRESDB
LT1997-1
LT1997-1
23
Rev 0
For more information www.analog.com
19973 TA03
OUT
REF2
300k
REF1
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V–
V–
V+
V+
SHDN
–
+
LT1997-1
V–
V–
V–
V–
19971 F09
10µA
V–
V–
V–
V–V–
APPLICATIONS INFORMATION
pad, the lower the thermal resistance. Connecting a large
amount of PCB metal to the exposed pad can reduce the
θJA to even less than 45°C/W. Use multiple vias from the
exposed pad to the V– plane. The exposed pad is electrically
connected to the V– pin. In addition, a heat sink may be
necessary if operating near maximum junction temperature.
The MSOP package has no exposed pad and a higher
thermal resistance (θJA = 130°C/W). It should not be used
in applications which have a high ambient temperature,
require driving a heavy load, or require an extreme input
voltage.
Thermal Shutdown
For safety, the LT1997-1 will enter shutdown mode when
the die temperature rises to approximately 163°C. This
thermal shutdown has approximately 9°C of hysteresis
requiring the die temperature to cool 9°C before enabling
the amplifier again.
ESD Protection
The LT1997-1 is protected by a number of ESD structures.
The structures are shown in Figure9.
The ESD structures serve to protect the internal circuitry
but also limit signal swing on certain nodes. The structures
on the +INA, –INA, +INB, –INB, +INC, –INC pins and on the
internal op amp inputs limit the voltage on these nodes to
0.3V below V– and 80V above V–. The voltage on the REF
(DFN), REF1 (MSOP) and REF2 (MSOP) pins are limited
to 0.3V below V– and 60V above V–. The voltage on the
SHDN pin is limited to 0.3V below V– and 0.3V above V+.
Figure9. ESD Protection
LT1997-1
24
Rev 0
For more information www.analog.com
LT1997-1 Configured for Differential Output with Gain = 20
19971 TA02
OUT
REF
150k
15k
15k
3k
7.5k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
LT1997-1
V+
OUT
VOCM
V–
OUT
USE VOCM TO SET THE DESIRED
OUTPUT COMMON MODE LEVEL
10k
10k
–+
LT6015
V
S
+
VS–
V
+IN
V
–IN
Precision RRIO Single-Supply Difference Amplifier
19971 TA03
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
V
CM = –0.3V TO VBATTERY
V
BATTERY
= 3.3V TO 50V
V+IN
V–IN
–
+
LT1997-1
VCM
V
BATTERY
VOUT = + 50 • (V+IN – V–IN
)
VBATTERY
2
TYPICAL APPLICATIONS
LT1997-1
25
Rev 0
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TYPICAL APPLICATIONS
19971 TA04
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
LT1997-1
VS
VS
VDIFF
VS
VOUT = VS/2 + 50 • VDIFF
THE INPUT SIGNAL FLOATS. THE VOLTAGE AT THE REF INPUTS AND THE OUTPUT VOLTAGE
DETERMINE THE COMMON MODE VOLTAGE AT THE INPUT
19971 TA05
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V–
V+
SHDN
–
+
LT1997-1
V+
V+
VBATT
VCTRL
VOUT = VBATT + 10 • VCTRL
VOUT CONNECTS TO LOAD
+
–
THIS CIRCUIT USES A GROUND-REFERENCED CONTROL SIGNAL TO
CREATE A SUPPLY ON TOP OF AN EXISTING SUPPLY (VBATT)
Floating Input Difference Amplifier
Create a Supply Using Control Signal
LT1997-1
26
Rev 0
For more information www.analog.com
TYPICAL APPLICATIONS
19971 TA06
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
V
+
V+
SHDN
–
+
LT1997-1
VSENSE
VCM
VOUT = 80 • VSENSE
(e.g. 2.4V OUTPUT AT 30mV OF FAULT SIGNAL)
+
–
+
–
FAULT DETECTION AT HIGH COMMON MODE VOLTAGE: LOOK FOR AN
INCREASING VOLTAGE THAT MIGHT INDICATE BREAKAGE.
19971 TA07
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB
TO LOAD
–INC
+INA +INB +INC V–
V+
V+
SHDN
–
+
LT1997-1
RSENSE
VPRI
ILOAD
VSEC
VOUT = VSEC –10 • ILOAD • RSENSE
+
–
+
–
V+
THIS CONFIGURATION SHOWS SCALING AND GROUND DOMAIN
SHIFTING FROM VPRI TO VSEC. VSEC CAN, OF COURSE, BE GROUND.
Fault Detection
Scale and Shift
LT1997-1
27
Rev 0
For more information www.analog.com
19971 TA08
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB
TO LOAD
–INC
+INA +INB +INC V–
V–
V+
V+
SHDN
–
+
LT1997-1
RSENSE
VPRI
ILOAD VOUT = VPRI –10 • ILOAD • RSENSE
+
–
V+
THIS CONFIGURATION SCALES THE INPUT. THE OUTPUT SIGNAL IS REFERENCED TO THE SAME GROUND DOMAIN AS THE INPUT.
THUS THE CIRCUIT CAN OPERATE AS A LOW SIDE CURRENT SENSE IN THE PRIMARY DOMAIN.
RELATIVE TO THE INPUT GROUND DOMAIN, THE OUTPUT CAN BE TRULY DRIVEN TO "ZERO".
19971 TA09
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB
VCM = –0.3V TO 76V
–INC
+INA +INB +INC V–
V+
SHDN
–
+
LT1997-1
RSENSE
ILOAD VOUT =VS/2 –80 • ILOAD • RSENSE
VS = 3.3V TO 50V
VS
VS
VS
LOAD
OUTPUT OFFSET INCREASES WHEN VCM > VS
Scale and Not Shift
Bidirectional High Side Current Sense
TYPICAL APPLICATIONS
LT1997-1
28
Rev 0
For more information www.analog.com
PACKAGE DESCRIPTION
4.00 ±0.10
(4 SIDES)
NOTE:
1. PACKAGE OUTLINE DOES NOT CONFORM TO JEDEC MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
17
148
BOTTOM VIEW—EXPOSED PAD
1.70 ±0.10
0.75 ±0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
3.00 REF
3.38 ±0.10
0.200 REF
0.00 – 0.05
(DF14)(12) DFN 1113 REV 0
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
PIN 1 NOTCH
0.35 × 45°
CHAMFER
1.70 ±0.05
3.38 ±0.05
3.00 REF
1.00
BSC
1.00
BSC
DF Package
14(12)-Lead Plastic DFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1963 Rev Ø)
LT1997-1
29
Rev 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
MSOP (MS12) 0213 REV B
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
1.0
(.0394)
BSC
0.50
(.0197)
BSC
16 14 121110
1 3 5 6 7 8
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC
1.0
(.0394)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.1016 ±0.0508
(.004 ±.002)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.280 ±0.076
(.011 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
MS Package
16 (12)-Lead Plastic MSOP with 4 Pins Removed
(Reference LTC DWG # 05-08-1847 Rev B)
LT1997-1
30
Rev 0
For more information www.analog.com
10/18
www.analog.com
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TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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LT1990 ±250V Input Range Difference Amplifier 2.7V to 36V Operation, CMRR > 70dB, Input Voltage = ±250V, Gain = 1, 10
LT1991 Precision, 100µA Gain Selectable Amplifier 2.7V to 36V Operation, 50μV Offset, CMRR > 75dB, Input Voltage = ±60V
LT1996 Precision, 100µA Gain Selectable Amplifier Micropower, Pin Selectable Up to Gain = 118
AD8275 G = 0.2, Level Translation, 16-Bit ADC Driver 3.3V to 15V Operation, CMRR > 86dB, Input Voltage = –35V to 40V, Gain = 0.2
AD8475 Precision, Selectable Gain, Fully Differential Funnel
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Operational Amplifiers
LT6015/LT6016/
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LT6018 33V, Ultralow Noise, Precision Op Amp VOS: 50µV, GBW: 15MHz, SR: 30V/µs, en: 1.2nV/√Hz, IS: 7.2mA
LTC6090/LTC6091 Single and Dual 140V Operational Amplifier 50pA IB, 1.6mV VOS, 9.5V to 140V VS, 4.5mA IS, RR Output
Current Sense Amplifiers
LT1999 High Voltage, Bidirectional Current Sense Amplifier –5V to 80V, 750µV, CMRR 80dB at 100kHz, Gain = 10, 20, 50
LT6108 High Side Current Sense Amplifier with Reference and
Comparator with Shutdown 2.7V to 60V, 125µV, Resistor Set Gain, ±1.25% Threshold Error
LT1787/LT1787HV Precision, Bidirectional High Side Current Sense Amplifier 2.7V to 60V Operation, 75μV Offset, 60μA Current Draw
LT6100 Gain-Selectable High Side Current Sense Amplifier 4.1V to 48V Operation,
Pin-Selectable Gain: 10V/V, 12.5V/V, 20V/V, 25V/V, 40V/V, 50V/V
LTC6101/
LTC6101HV High Voltage High Side Current Sense Amplifier 4V to 60V/5V to 100V Operation, External Resistor Set Gain, SOT23
LTC6102/
LTC6102HV Zero Drift High Side Current Sense Amplifier 4V to 60V/5V to 100V Operation, ±10μV Offset, 1μs Step Response,
MSOP8/DFN Packages
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ANALOG DEVICES, INC. 2018
19971 TA10
OUT
REF1
300k
REF2
15k
15k
3k
7.5k 300k
7.5k
3k
150k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
LT1997-1
RSENSE
ILOAD VOUT =VS/2 –80 • ILOAD • RSENSE
VS
VS
VS
LOAD
THIS CIRCUIT PROVIDES BIDIRECTIONAL LOW SIDE CURRENT SENSE BECAUSE IT CAN
WORK AT SLIGHTLY NEGATIVE VOLTGES ON THE –INA/–INB/–INC INPUT PINS, AS DRAWN
Bidirectional Low Side Current Sense