LT1997-1
21
Rev 0
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APPLICATIONS INFORMATION
plies. Tying REF1 to VS+ and REF2 to VS– produces the
desired mid-supply voltage without the help of another
external reference voltage (Figure7). The ratio of RREF1
to RREF2 is very precise:
∆R
R=RREF1 – RREF2
RREF1+RREF2
2
⎛
⎝
⎜⎞
⎠
⎟
<60ppm
Shutdown
The LT1997-1 has a shutdown pin (SHDN). Under normal
operation this pin should be tied to V+ or allowed to float.
Tying this pin 2.5V or more below V+ will cause the part
to enter a low power state. The supply current is reduced
to less than 25µA and the op amp output becomes high
impedance. The voltages at the input pins can still be
present even in shutdown mode.
Supply Voltage
The positive supply pin of the LT1997-1 should be bypassed
with a small capacitor (typically 0.1µF) as close to the supply
pins as possible. When driving heavy loads, an additional
4.7µF electrolytic capacitor should be added. When using
split supplies, the same is true for the V– supply pin.
Output
The output of the LT1997-1 can typically swing to within
30mV of either rail with no load and is capable of sourcing
and sinking approximately 30mA at 25°C. The LT1997-1 is
internally compensated to drive at least 2nF of capacitance
under any output loading conditions. For larger capacitive
loads, a 0.22µF capacitor in series with a 150Ω resistor
between the output and ground will compensate the ampli-
fier to drive capacitive loads greater than 2nF.
Distortion
The LT1997-1 features excellent distortion performance
when the internal op amp is operating in the normal op-
erating region. Operating the LT1997-1 with the internal
op amp in the over the top region will increase distortion
due to the lower loop gain of the op amp. Operating the
LT1997-1 with input common mode voltages that go from
the normal to Over-The-Top operation will significantly
degrade the LT1997-1’s linearity as the op amp must
transition between two different input stages. Driving
resistive loads significantly smaller than the 150k internal
feedback resistor will also degrade the amplifier’s linearity
performance.
High Voltage Pin Spacing
For applications with high input voltages, the LT1997-1
pinout eases the printed circuit board (PCB) layout burden.
Voltages at +INA, –INA, +INB, and –INB input pins are
separated from other pins by virtue of unpopulated pin
locations, as illustrated in the Pin Configuration section
of this data sheet.
Power Dissipation Considerations
Because of the ability of the LT1997-1 to operate on power
supplies up to ±25V, to withstand very high input volt-
ages and to drive heavy loads, there is a need to ensure
the die junction temperature does not exceed 150°C. The
LT1997-1 is housed in DF14 (θJA = 45°C/W, θJC = 3°C/W)
and MS16 (θJA = 130°C/W) packages.
In general, the die junction temperature (TJ) can be es-
timated from the ambient temperature (TA), the device’s
power dissipation (PD) and the thermal resistance of the
device and board (θJA).
TJ = TA + PD • θJA
The thermal resistance from the junction to the ambient
environment (θJA) is the sum of the thermal resistance
from the junction to the exposed pad (θJC) and the thermal
resistance from the exposed pad to the ambient environ-
ment (θCA). The θCA value depends on how much PCB
metal is connected to the exposed pad in the board. The
more PCB metal that is used, the lower θCA and θJA will be.
Power is dissipated by the amplifier’s quiescent current, by
the output current driving a resistive load, and by the input
current driving the LT1997-1’s internal resistor network.
PD=VS+– VS–
( )
•IS
+POD +PRESD