. PRELIMINARY intel M27C128 128K (16K x 8) CHMOS PRODUCTION AND UV ERASABLE PROMs m CHMOS Microcontroller and m Fast Programming Microprocessor Compatible intgligent Programming Algorithm Quick-Pulse Programming m Low Power Consumption 100 .A Maximum Standby Current Algorithm (CMOS) w inteligent Identifier Mode m@ Maximum Latch-Up Immunity Through Automated Programming Operations EPI Processing m Compatible with M2732A, M27C64A, +1V input Protection M27C256 14V Vpp Protection w Avaliable in 28-Pin Cerdip Package m@ CHMOS II-E* Technology (See Packaging Spec. Order #231369) Intel's M27C128 CHMOS EPROM is a 128 K-bit, 5V-only memory, organized as 16,384 words of 8 bits each. The M27C128 is ideal for systems requiring low power, high performance, and noise immunity due to its CHMOS *II-E processing, and it is pin compatible with the HMOS intel M27128A. Several advanced features have been designed into the M27C128 that allows fast and reliable programming the intgligent Programming Algorithm and the intgligent Identifier Mode. Programming equipment that takes advantage of these innovations will electronically identify the M27C128 and then rapidly program it using an efficient programming method. The M27C128 can also be programmed using the Quick-Pulse Programming Algorithm. Intels unique EP! processing provides excellent latch-up immunity. Prevention of latch-up is guaranteed for stresses up to 100 mA on address and data pins from 1V to Voc + 1V and for Vpp voltage overshoot up to 14V. *HMOS and CHMOS are patented processes of Intel Corporation. DATA OUTPUTS Veo o_> Oo-07 GND o_> ee Vor o {ttt ttt OE ] OUTPUT ENABLE Me| CHIP ENABLE AND ~ CE"| proc Loaic_f] OUTPUT BUFFERS = Y ~~ Y-GATING S]__ pecoper 2p Ao-Ais b > ADDRESS x : 131,072-BIT INPUTS | = "MA : DECODER : CELL MATRIX e * P ~ 271094-1 Figure 1. Block Diagram February 1991 7-41 Order Number: 271094-002ntel uo7cize PRELIMINARY Pin Names Ao-Ai3 | ADDRESSES CE CHIP ENABLE OE OUTPUT ENABLE Op-07 | OUTPUTS PGM PROGRAM N.C. No Internal Connect D.U. Dont Use M27C128 - M27C256 | M27C64A | M2732A M2732A | M27C64A | M27C256 VS Vpp Vpp Vpp C1 28 Vee Voc Voc Ai2 Ayo Ayo 2 2715 PM PGM Ava A7 A7 A7 A7t13 26D A,3 Voc N.C. Aig Ag Ag Ag Ag (4 25 Ag Ag Ag Ag As As Ag AsC]s 2497) Ag Ag Ag Ag Ag Ag Ag A,C6 230 Ay An Ait Au Ag Ag Ag 45017 22 OE GE/Vpp | OE OE A2 A2 Aa As 21D Ajo Aio Ato Aio Ay Ai Ay Ago 20D CE CE CE CE Ao Ro Ao Ag] 10 iso, O7 O7 O7 Oo Oo Oo Oot 11 1855 06 O6 O06 Og ron 0; O1 0,12 1719 0, Os Os Os Og O2 O2 070413 te 0, O4 O4 O4 Gnd Gnd Gnd GND] 14 150s Og Og Og 271094-2 NOTE: intel Universal Site-Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent to the M27C128 Pins. Figure 2. Cerdip(D) Pin Configuration 7-42intel M27C128 PRELIMINARY ABSOLUTE MAXIMUM RATINGS* Case Temperature under Bias.........-.....06- 55C to + 125C Storage Temperature .......... 65C to + 150C Voltage on Any Pin with Respect to Ground............ 2,0V to + 7V11) Voltage on Pin Ag with Respect to Ground......... 2.0V to + 13.5V1) Vpp Supply Voltage with Respect to Ground During Programming 2.0V to + 14V(1) Voc Supply Voltage with Respect to Ground 2.0V to 7.0V1) NOTICE: This data sheet contains pretiminary infor- mation on new products in production. The specifica- tions are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. READ OPERATION D.C. CHARACTERISTICS 55C < To l) < + 125C and Voc = 5V +10% Symbol! Parameter Notes} Min |Typ(2)} Max [Unit] Test Condition lu Input Leakage Current 0.01 1.0 pA | Vin = OV to 5.5V ILo Output Leakage Current +10 pA |Vout = OV to 5.5V Ipp, Vpp Current Read 5 100 pA |Vpp = Voc Isp Voc Current Standby CMOS | 4 100 pA |CE = Vin with Igputs TIL 3 1.0 mA lect Voc Current Active 5 25 mA |CE = Vit f = 5 MHz, lout = OmA Vit Input Low Voltage 0.5 0.8 V iVpp = Voc (+ 10% Supply) (TTL) Input Low Voltage 0.2 0.2 (CMOS) Vin Input High Voltage (+ 10% 2.0 Voc + 0.5] V |Vpp = Voc Supply) (TTL) Input High Voltage Voc 0.2 Voc + 0.2 (CMOS) VoL Output Low Voltage 0.45 V jlo. = 2.1mA Vou Output High Voltage 3.5 V Hon = -2.5mA los Output Short Circuit Current 6 100 mA Vpp Vpp Read Voitage Voc 0.7 Voc Vv NOTES: 1. Minimum D.C. input voltage is 0.5V. During transitions, the inputs may undershoot to 2.0V for periods less than 20 ns. Maximum D.C. Voltage on output pins is Voc + 0.5V which may overshoot to Vcc + 2V for periods less than 20 ns. 2. Typical limits are at Voc = 5V, To = +25C. 3. ViL, Vin levels at TTL inputs. 4. CE is Voc + 0.2V. All other inputs can have any value within spec. 7-43 5. Maximum Active power usage is the sum Ipp + Ioc. The maximum current value is with Outputs Op to O7 unloaded. 6. Output shorted for no more than one second. No more than one output shorted at a time. log is sampled but not 100% tested. 7. Vpp may be one diode voltage drop below Vcc. It may be connected directly to Voc. 8. Case temperatures are instant on.intel M27C128 PRELIMINARY READ OPERATION A.C. CHARACTERISTICS 55C < Tc < + 125C Versions M27C 128-20 M27C 128-30 Unit Symbol Characteristic Min Max Min Max tacc Address to Output Delay 200 300 ns tcE CE to Output Delay 200 300 ns toe GE to Output Delay 75 100 ns tor (2) OE High to Output High Z 55 60 ns ton Output Hold from Addresses, CE or GE Change-Whichever 0 0 ns is First NOTES: 1. A.C. characteristics tested at Viy = 2.4V and Vi_ = 0.45V. Timing measurements made at Vo = 0.8V and Von = 2.0V. 2. Guaranteed and sampled. A.C. WAVEFORMS View /~ eoee aponedses ADDRESS ve K cease Vie ce Ven eoee I togl2l Ve oe Vin ja coos L tog lt] = tog |2] > lace tos|t? Vin pes Gee OUTPUT: wn LU VALID OUTPUT woz 271094-3 NOTES: 1. This parameter is only sampled and is not 100% tested. 2. OE may be delayed up to tog-tog after the falling edge of CE without impact on toe. 7-44intel M270128 PRELIMINARY CAPACITANCE(!) T, = 25C, f = 1.0 MHz Symbol Parameter Max | Unit | Conditions Cin Address/Control Capacitance} 6 | pF | Vin = OV Cout | Output Capacitance 12 | pF | Vout = OV NOTE: 1. Sampled. Not 100% tested. A.C. TESTING INPUT/OUTPUT WAVEFORM A.C, TESTING LOAD CIRCUIT 13v 1NO14 a4 2.0 5 2.0 weur X 3 => test Powrs <t os x OUTPUT aaKn 0.45 5S DEVICE 2710944 pe our C. = 100 pF A.C. Testing: Inputs are driven at 2.4V for a Logic t and 0.45V - L for a Logic 0. Timing measurements are made at 2.0V for a s Logic '1 and 0.8V tor a Logic 0. - 271084-5 Cy. = 100 pF C,, includes Jig Capacitance DEVICE OPERATION The modes of operation of the M27C128 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp and 12V on Ag for intgligent Identifier mode. Tabie 1. Mode Selection for M27C 128 - Pins CE OE PGM Ag Ao Vpp Vec Outputs Mode Read Vit Vit Vin x) xX Vcc 5.0V Dout Output Disable VIL Vin Vin x X Voc 5.0V High Z Standby Vin X xX x X Voc 5.0V High Z Program Verify Vit ViL ViIH x xX (4) (4) Dout Program Inhibit Vin x X xX xX (4) (4) High Z intgligent Identifier() Vit Vit VIH Vy(2) Vit Vcc Voc 89H -Manufacturer . intgligent Identifier() Vib Vit Vin Vy) Vin Voc Voc FCH Device inteligentt Programming Vit Vin ViL X X (4) (4) DIN NOTES: 1. X can be Vii or Vip. 2.VH = 12.0V + 0.5V. 3. A1Ag, Ayo-Ai3 = ViL- 4. See Table 2 for Vcc and Vpp voltages. 7-45intel M27C128 PRELIMINARY READ MODE The M27C128 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power contro! and should be used for device selection. Output En- able (OE) is the output contro! and should be used to gate data from the output pins, independent of device selection. Assuming that addresses are sta- bie, the address access time (tacc) is equal to the delay from CE to output (tc). Data is available at the outputs after the delay of tog from the falling edge of OF, assuming that CE has been low and addresses have been stable for at least tacc-tog. STANDBY MODE EPROMs can be placed in standby mode which re- duces the maximum current of the device by apply- ing a TTL-high signal to the CE input. When in stand- by mode, the outputs are in a high impedance state, independent of the OE input. Two Line Output Control Because EPRQMs are usually used in larger memo- ry arrays, Intel has provided 2 control lines which accommodate this multiple memory connection. The two control lines allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To use these two control lines most efficiently, CE should be decoded and used as the primary device selecting function, while OE should be made a com- mon connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devic- es are in their low power standby mode and that the output pins are active only when data is desired from a particular memory device. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. The supply current, Icc, has three segments that are of interest 7-46 to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The magnitude of these tran- sient and inductive current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed by complying with Intels Two-Line Control, and by properly selected decoupling capaci- tors. It is recommended that a 0.1 F ceramic ca- pacitor be used on every device between Voc and GND. This should be a high frequency capacitor for low inherent inductance and should be placed as close to the device as possible. in addition, a 4.7 1F bulk electrolytic capacitor should be used between Vec and GND for every eight devices. The bulk ca- pacitor should be located near where the power sup- ply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effect of PC board-traces. PROGRAMMING MODES Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all bits of the EPROM are in the 1 state. Data is introduced by selectively programming Os into the desired bit lo- cations. Although only Os will be programmed, both 1s and 0s can be present in the data word. The only way to change a 0 to a 1 is by ultravio- let light erasure. The device is in the programming mode when Vpp is raised to its programming voltage (See Table 2) and GE and PGM are both at TTL low and OE = Vin. The data to be programmed is applied 8 bits in paral- lel to the data output pins. The levels required for the address and data inputs are TTL. Program Inhibit Programming of multiple EPROMs in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE or PGM input inhibits the other devices from being programmed. Except for CE, all like inputs (including OE) of the parallel EPROMs may be common. A TTL low-level pulse applied to the PGM input with Vpp at its pro- gramming voltage and CE = Vj, will program the selected device.intel M27C128 PRELIMINARY Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they have been cor- rectly programmed. The verify is performed with OE and CE at Vi_, PGM at Vin, and Vcc and Vpp at their programming voltages. Data should be verified a minimum of tog after the falling edge of OE. inteligent Identifier Mode The intgligent Identifier Mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be pro- grammed with its corresponding programming algorithm. This mode is functional in the 25C +5C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line AQ of the EPROM. Two identifier bytes may then be se- quenced from the device outputs by toggling ad- dress line AO from Vi, to Vi}. Ail other address lines must be held at V;_ during the intgligent Identifier Mode. Byte 0 (AO = Vj.) represents the manufacturer code and byte 1 (AO = Vj) the device identifier code. These two identifier bytes are given in Table 1. inteligent Programming Algorithm The M27C128 intgligent Programming Algorithm rapidly programs Intel M27C128 using an efficient and reliable method particularly suited to the produc- tion programming environment. Typical program- ming time for individual devices is less than one and a half minutes. Programming reliability is also en- sured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed. A flow-chart of the M27C128 intgligent Programming Algorithm is shown in Figure 3. The intgligent Programming Algorithm utilizes two different pulse types: initial and overprogram. The duration of the initial CE pulse(s) is 1 ms, which will then be followed by a longer overprogram pulse of length 3X ms. X is an iteration counter and is equal to the number of the initial 1 ms pulses applied to a particular M27C128 location, before a correct verify occurs. Up to 25 1-ms pulses per byte are provided for before the overprogram pulse is applied. The entire sequence of program pulses and byte verifications is performed at Vcc = 6.0V and Vpp = 12.5V nominal When the intgligent Pro- gramming cycle has been completed, all bytes should be compared to the original data with Voc = Vpp = 5.0V. The M27C128 can also be programmed using the Quick Putse Programming Algorithm. ERASURE CHARACTERISTICS (FOR CERDIP EPROMS) The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 400 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range. Data shows that constant expo- sure to room level fluorescent lighting could erase the EPROM in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the device is to be ex- . posed to these types of lighting conditions for ex- 7-47 tended periods of time, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm?. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 .W/cm2 power rat- ing. The EPROM should be placed within 1 inch of the famp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12000 W/cm2). Exposure of the device to high in- tensity UV light for longer periods may cause perma- nent damage. HIGH RELIABILITY CHMOS Special EPI processing techniques have enabled In- tel to build CHMOS with features adding to system reliability. These include input/output protection to latch-up. Each of the data and address pins will not latch-up with currents up to 100 mA and voltages from 1V to Voc + 1V. Additionally, the Vpp (programming) pin is designed to resist latch-up to the 14V maximum device limit.M27C128 PRELIMINARY ADDRESS = FIRST LOCATION Voc = 6.0 Vpp = 12.5V PROGRAM ONE 1 MSEC PULSE INCREMENT X PROGRAM ONE PULSE OF 3X MSEC DURATION INCREMENT ADDRESS y DEVICE FAILED YES Voc = Vpp = 5.0 COMPARE ALL BYTES TO ORIGINAL DATA FAIL DEVICE PASSED 271094-6 Figure 3. intgligent Programming Algorithm 7-48M27C128 PRELIMINARY INCREMENT ADDRESS COMPARE ALL BYTES TO ORIGINAL ADORESS = FIRST LOCATION Vor = 6.25V Vpp =12.75V PROGRAM ONE 100 ss PULSE INCREMENT X Voc = Vpp = 5.0V . DEVICE FAILED FAIL DEVICE PASSED 271094-8 Figure 4. Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm Intel's M27C128 EPROM is programmed using the Quick-Pulse Programming Algorithm, developed by Intel to substantially reduce the throughput time in the production programming environment. The Quick-Pulse Programming Algorithm uses initial pulses of 100 microseconds followed by a byte veri- fication to determine when the address byte has been successfully programmed. Up to 25 100 ps 7-49 pulses per byte are provided before a failure is rec- ognized. A flow chart of the Quick-Pulse Program- ming Algorithm is shown in Figure 4. For the Quick-Pulse Programming Algorithm, the en- tire sequence of programming pulses and byte verifi- cations is performed at Vcc = 6.25V and Vpp at 12.75V (nominal). When programming of the EPROM has been completed, all bytes should be compared to the original data with Vcc 5.0V (Vpp < Voc).intel 270128 PRELIMINARY D.C. PROGRAMMING CHARACTERISTICS Te = 25C +5C Table 2 Symbol Parameter Limits Test eonavons Min Max Unit (Note 1) lu Input Current (All Inputs) 1.0 pA Vin = Vicor Vin Vit Input Low Level (All Inputs) -0.4 0.8 Vv Vin Input High level 2.0 Voc + 0.5 Vv VoL Output Low Voltage During Verify 0.45 Vv lo. = 2.1mMA VoH Output High Voltage During Verify 2.4 : v lon = 400 pA Ioc2) Vcc Supply Current 25 mA Ippol3) Vepp Supply Current (Program) 30 mA | CE=Vit Vip Ag intgligent identifier Voltage 11.5 12.5 Vv Vpp intgligent Programming Aigorithm 12.0 13.0 Vv CE = PGM = Vn Quick-Pulse Programming Algorithm 12.5 13.0 Vv Voc intgligent Programming Algorithm 5.75 6.25 Vv Quick-Pulse Programming Algorithm 6.0 6.5 Vv A.C. PROGRAMMING CHARACTERISTICS To = 25C +5C, See Table 2 for Voc and Vpp Voltages Symbol Parameter Limits on onions Min | Typ | Max | Unit (Note 1) tas Address Setup Time 2 pS toes OE Setup Time 2 ps tos Data Setup Time 2 ps taH Address Hold Time 0 pS toy Data Hold Time 2 ps toFP GE High to Output Float Delay | 0 130 | ns (Note 2) types Vpp Setup Time 2 ys tvcs Voc Setup Time 2 ps toes CE Setup Time 2 ps tpw PGM Intitial Program 0.95] 1.0 | 1.05 | ms | inteligent Programming Algorithm Pulse Width 95 | 100] 105 | ys | Quick-Pulse Programming Algorithm topw PGM Overprogram arr : . Pulse Width 2.85 78.75 | ms | intgligent Programming Algorithm toe Data Valid from OE 150 | ns NOTES: . A.C. CONDITIONS OF TEST 1. Voc must be applied simultaneously or before Vpp and . removed simultaneously or after Vpp. Input Rise and Fall Times (10% to 90%)...... 20 ns 2. This parameter is only sampled and is not 100% tested. Input Pulse Levels...........-...65- 0.45V to 2.4V Output Float is defined as the point where data is no long- 5 at er drivensee timing diagram. Input Timing Reference Level ....... 0.8V and 2.0V 3. The maximum current value is with outputs Op to O7 Un- Output Timing Reference Level ...... 0.8V and 2.0V loaded. 7-50intel M270128 PRELIMINARY PROGRAMMING WAVEFORMS PROGRAM VERIFY Vin + ADDRESSES x ADDRESS STABLE x Vv >>) Ik mee tas - b tay mt 3 Vin HIGH Z pze DATA _{ DATA IN STABLE DATA OUT VALID \+ Van 7 2 \e tog o} *oH tpg?) (4) (Ss) 12.5V/12.75 ve Vpp / 5.0V ' (4) (5) y vPS*] 6.0V/6.25V =~ = Yec 5.0V bo tyes | _ Vin CE Vit v2 x. toes __ Q oy y 2 PGM Vit tow foes a] fe tor?) _ nm nr OE N / Vi cn 271094-9 NOTES: 1. The Input Timing Reference Level is 0.8V for Vi_ and 2V for a Vix. 2. tog and tprp are characteristics of the device but must be accommodated by the programmer. 3. When programming the M27C128, a.0.1 uF capacitor is required across Vpp and ground to suppress spurious voltage transients which can damage the device. 4. intgligent Programming Algorithm voltage levels. 5. Quick-Pulse Prograrhming Algorithm voltage levels. 7-51