ATMEGA88A-AUR - Atmel - Datasheet.Live

Features

•High Pe rformance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 131 Po we rful Instructions – Most Single Clock Cy cle Execu tion

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Thro ug hp ut at 20 MHz

– On-chip 2-cycle Multiplier

•High Endurance Non-volatile Memory Segments

– 4/8/16K Bytes of In-System Self-Programmable Flash progam memory

(ATmega48P/88P/168P)

– 256/512/512 Bytes EEPROM (ATmega48P/88P/168P)

– 512/1K/1K Bytes Internal SRAM (ATm ega48P/88P/168P)

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

•Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

Temperature Measurement

– 6-channel 10-bit ADC in PDIP Package

Temperature Measurement

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I2C compatible)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

•Special Microcontroller Features

– Power -on Reset and Pr ogrammab le Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, A DC Noise Reduction, Power-save, Power-down, Standby,

and Extended Standby

•I/O and Packages

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

•Operating Voltage:

– 1.8 - 5.5V for ATmega48P/88P/168PV

– 2.7 - 5.5V for ATmega48P/88P/16 8P

•Temperature Range:

–-40

°C to 85°C

•Speed Grade:

– ATmega48P/88P/168PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATmega48P/88P/168P: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

•Low Power Consumption at 1 MHz, 1.8V, 25°C for ATmega48P/88P/168P:

– Active Mode: 0.3 mA

– Power-down Mode: 0.1 µA

– Power-save Mode: 0.8 µA (Including 32 kHz RTC)

Note: 1. See ”Data Retenti on” on page 7 for details.

8-bit

Microcontroller

with 4/8/16K

Bytes In-System

Programmable

Flash

ATmega48P/V*

ATmega88P/V*

ATmega168P/V*

* Not recommended for new designs.

Use:

ATmega48PA/88PA/168PA/328P

Rev. 8025KS–AVR–10/09

8025KS–AVR–10/09

ATmega48P/88P/168P

1. Pin Configurations

Figure 1-1. Pinout ATmega48P/88P/168P

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

GND

VCC

GND

VCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK/PCINT5)

(PCINT21/OC0B/T1) PD5

(PCINT22/OC0A/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

(PCINT3/OC2A/MOSI) PB3

(PCINT4/MISO) PB4

PD2 (INT0/PCINT18)

PD1 (TXD/PCINT17)

PD0 (RXD/PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

TQFP T op View

(PCINT14/RESET) PC6

(PCINT16/RXD) PD0

(PCINT17/TXD) PD1

(PCINT18/INT0) PD2

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

GND

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

(PCINT21/OC0B/T1) PD5

(PCINT22/OC0A/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

AREF

AVCC

PB5 (SCK/PCINT5)

PB4 (MISO/PCINT4)

PB3 (MOSI/OC2A/PCINT3)

PB2 (SS/OC1B/PCINT2)

PB1 (OC1A/PCINT1)

PDIP

32 MLF Top View

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

GND

VCC

GND

VCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK/PCINT5)

(PCINT21/OC0B/T1) PD5

(PCINT22/OC0A/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

(PCINT3/OC2A/MOSI) PB3

(PCINT4/MISO) PB4

PD2 (INT0/PCINT18)

PD1 (TXD/PCINT17)

PD0 (RXD/PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

NOTE: Bottom pad should be soldered to ground.

28 MLF Top View

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

GND

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

(PCINT21/OC0B/T1) PD5

(PCINT22/OC0A/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

(PCINT3/OC2A/MOSI) PB3

(PCINT4/MISO) PB4

PD2 (INT0/PCINT18)

PD1 (TXD/PCINT17)

PD0 (RXD/PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

AREF

AVCC

PB5 (SCK/PCINT5)

NOTE: Bottom pad should be soldered to ground.

8025KS–AVR–10/09

ATmega48P/88P/168P

1.1 Pin Descriptions

1.1.1 VCC Digital supply voltage.

1.1.2 GND Ground.

1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/T OSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. Th e Port B pins are tri-stated when a reset co ndition becomes active,

even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-

lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting

Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1

input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page

79 and ”System Clock and Clock Options” on page 26.

1.1.4 Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PC5..0 output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

1.1.5 PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-

acteristics of PC6 differ fro m those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is use d as a Reset input. A low level on this pin

for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in Table 28-3 on page 313. Sho rter pulses are not guaran-

teed to generate a Reset.

The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page

82.

1.1.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both hig h sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

8025KS–AVR–10/09

ATmega48P/88P/168P

The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page

85.

1.1.7 AVCC AVCC is the supply volta ge pin for the A/D Conver ter, PC3 :0, and ADC7:6. It should be extern ally

connected to VCC, even if the ADC is not u sed. If the ADC is used, it should be conne cted to V CC

through a low-pass filter. Note that PC6..4 use digital supply voltage, V CC.

1.1.8 AREF AREF is the analog reference pin for the A/D Converter.

1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.

These pins are powered from the analog supply and serve as 10-bit ADC channels.

2. Overview The ATmega48P/88P/168P is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega48P/88P/168P a ch ieves thr oug hp uts a pp roaching 1 M IPS per MHz a llowing th e syst em

designer to optimize power consumption versus processing speed.

8025KS–AVR–10/09

ATmega48P/88P/168P

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achiev ing throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega48P/88P/168P provides the following features: 4K/8K/16K bytes of In-System Pro-

grammable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM,

512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers,

three flexible Timer/Counters with compare modes, internal and external interrupts, a serial pro-

grammable USART, a byte-oriented, 2-wire Serial Interface, an SPI serial port, a 6-channel 10-

bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with

PORT C (7)PORT B (8)PORT D (8)

USART 0

8bit T/C 2

16bit T/C 18bit T/C 0 A/D Conv.

Internal

Bandgap

Analog

Comp.

SPI TWI

SRAMFlash

EEPROM

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

Power

Supervision

POR / BOD &

RESET

VCC

GND

PROGRAM

LOGIC

debugWIRE

GND

AREF

AVCC

D ATA BU S

ADC[6..7]PC[0..6]PB[0..7]PD[0..7]

RESET

XTAL[1..2]

CPU

8025KS–AVR–10/09

ATmega48P/88P/168P

internal Oscillator, and five software selectable power saving modes. The Idle mode stops the

CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and

interrupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset.

In Power-save mode, the asynchronous timer continues to run, allowing the use r to maintain a

timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the

CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise dur-

ing ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest

of the device is sleeping. This allows very fast start-up combined with low power consumpt ion.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot program can use any interface to download the

application program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8 -bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega48P/88P/168P is a powerful microcontroller that provides a

highly flexible and cost effective solution to many embedded control applications.

The ATmega48P/88P/168P AVR is supported with a full suite of program and system develop-

ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit

Emulators, and Evaluation kits.

2.2 Comparison Between ATmega48P, ATmega88P and ATmega168P

The ATmega48P, ATmega88P and ATmega168P differ only in memory sizes, boot loader sup-

port, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector

sizes for the three devices.

ATmega88P and ATm ega168P sup port a real Read -While-Wr ite Se lf-Progra mming mechanism.

There is a separate Boot Loader Section, and the SPM instruction can only execute from there.

In ATmega48P, there is no Read-While-Write support and no separate Boot Loader Section.

The SPM instruction can execute from the entire Flash.

Table 2-1. Memory Size Summary

Device Flash EEPROM RAM Interrupt Vector Size

ATme ga48P 4K Bytes 256 Bytes 512 Bytes 1 instruction word/vector

ATme ga88P 8K Bytes 512 Bytes 1K Bytes 1 instruction word/vector

ATme ga168P 16K Bytes 512 Bytes 1K Bytes 2 instruction words/vector

8025KS–AVR–10/09

ATmega48P/88P/168P

3. Resources A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentatio n contains simple co de examples that br iefly sh ow how to u se various parts of

the device. These code examp les assume that the part specific header file is included b efore

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt ha ndlin g in C is com piler d epe nd ent. Please con firm wit h the C com piler d ocume n-

tation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

8025KS–AVR–10/09

ATmega48P/88P/168P

6. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved – – – – – – – –

(0xFE) Reserved – – – – – – – –

(0xFD) Reserved – – – – – – – –

(0xFC) Reserved – – – – – – – –

(0xFB) Reserved – – – – – – – –

(0xFA) Reserved – – – – – – – –

(0xF9) Reserved – – – – – – – –

(0xF8) Reserved – – – – – – – –

(0xF7) Reserved – – – – – – – –

(0xF6) Reserved – – – – – – – –

(0xF5) Reserved – – – – – – – –

(0xF4) Reserved – – – – – – – –

(0xF3) Reserved – – – – – – – –

(0xF2) Reserved – – – – – – – –

(0xF1) Reserved – – – – – – – –

(0xF0) Reserved – – – – – – – –

(0xEF) Reserved – – – – – – – –

(0xEE) Reserved – – – – – – – –

(0xED) Reserved – – – – – – – –

(0xEC) Reserved – – – – – – – –

(0xEB) Reserved – – – – – – – –

(0xEA) Reserved – – – – – – – –

(0xE9) Reserved – – – – – – – –

(0xE8) Reserved – – – – – – – –

(0xE7) Reserved – – – – – – – –

(0xE6) Reserved – – – – – – – –

(0xE5) Reserved – – – – – – – –

(0xE4) Reserved – – – – – – – –

(0xE3) Reserved – – – – – – – –

(0xE2) Reserved – – – – – – – –

(0xE1) Reserved – – – – – – – –

(0xE0) Reserved – – – – – – – –

(0xDF) Reserved – – – – – – – –

(0xDE) Reserved – – – – – – – –

(0xDD) Reserved – – – – – – – –

(0xDC) Reserved – – – – – – – –

(0xDB) Reserved – – – – – – – –

(0xDA) Reserved – – – – – – – –

(0xD9) Reserved – – – – – – – –

(0xD8) Reserved – – – – – – – –

(0xD7) Reserved – – – – – – – –

(0xD6) Reserved – – – – – – – –

(0xD5) Reserved – – – – – – – –

(0xD4) Reserved – – – – – – – –

(0xD3) Reserved – – – – – – – –

(0xD2) Reserved – – – – – – – –

(0xD1) Reserved – – – – – – – –

(0xD0) Reserved – – – – – – – –

(0xCF) Reserved – – – – – – – –

(0xCE) Reserved – – – – – – – –

(0xCD) Reserved – – – – – – – –

(0xCC) Reserved – – – – – – – –

(0xCB) Reserved – – – – – – – –

(0xCA) Reserved – – – – – – – –

(0xC9) Reserved – – – – – – – –

(0xC8) Reserved – – – – – – – –

(0xC7) Reserved – – – – – – – –

(0xC6) UDR0 USART I/O Data Register 192

(0xC5) UBRR0H USART Baud Rate Register High 196

(0xC4) UBRR0L USART Baud Rate Register Low 196

(0xC3) Reserved – – – – – – – –

(0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 /UDORD0 UCSZ00 / UCPHA0 UCPOL0 194/209

8025KS–AVR–10/09

ATmega48P/88P/168P

(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 193

(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 192

(0xBF) Reserved – – – – – – – –

(0xBE) Reserved – – – – – – – –

(0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 –241

(0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE 238

(0xBB) TWDR 2-wire Serial Interface Data Register 240

(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 241

(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 –TWPS1TWPS0 240

(0xB8) TWBR 2-wire Serial Interface Bit Rate Register 238

(0xB7) Reserved – – – – – – –

(0xB6) ASSR – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 161

(0xB5) Reserved – – – – – – – –

(0xB4) OCR2B Timer/Counter2 Output Compare Register B 159

(0xB3) OCR2A Timer/Counter2 Output Compare Register A 159

(0xB2) TCNT2 Timer/Counter2 (8-bit) 159

(0xB1) TCCR2B FOC2A FOC2B –– WGM22 CS22 CS21 CS20 158

(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 ––WGM21WGM20 155

(0xAF) Reserved – – – – – – – –

(0xAE) Reserved – – – – – – – –

(0xAD) Reserved – – – – – – – –

(0xAC) Reserved – – – – – – – –

(0xAB) Reserved – – – – – – – –

(0xAA) Reserved – – – – – – – –

(0xA9) Reserved – – – – – – – –

(0xA8) Reserved – – – – – – – –

(0xA7) Reserved – – – – – – – –

(0xA6) Reserved – – – – – – – –

(0xA5) Reserved – – – – – – – –

(0xA4) Reserved – – – – – – – –

(0xA3) Reserved – – – – – – – –

(0xA2) Reserved – – – – – – – –

(0xA1) Reserved – – – – – – – –

(0xA0) Reserved – – – – – – – –

(0x9F) Reserved – – – – – – – –

(0x9E) Reserved – – – – – – – –

(0x9D) Reserved – – – – – – – –

(0x9C) Reserved – – – – – – – –

(0x9B) Reserved – – – – – – – –

(0x9A) Reserved – – – – – – – –

(0x99) Reserved – – – – – – – –

(0x98) Reserved – – – – – – – –

(0x97) Reserved – – – – – – – –

(0x96) Reserved – – – – – – – –

(0x95) Reserved – – – – – – – –

(0x94) Reserved – – – – – – – –

(0x93) Reserved – – – – – – – –

(0x92) Reserved – – – – – – – –

(0x91) Reserved – – – – – – – –

(0x90) Reserved – – – – – – – –

(0x8F) Reserved – – – – – – – –

(0x8E) Reserved – – – – – – – –

(0x8D) Reserved – – – – – – – –

(0x8C) Reserved – – – – – – – –

(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 135

(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 135

(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 135

(0x88) OCR1AL Timer/Counter1 - Out put Compare Register A Low Byte 135

(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 136

(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 136

(0x85) TCNT1H Timer/Counter1 - Counter Re gister High Byte 135

(0x84) TCNT1L Timer/Counter1 - Counter Re gister Low Byte 135

(0x83) Reserved – – – – – – – –

(0x82) TCCR1C FOC1A FOC1B – – – – – –134

(0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 133

(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 ––WGM11WGM10 131

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8025KS–AVR–10/09

ATmega48P/88P/168P

(0x7F) DIDR1 – – – – – –AIN1DAIN0D 246

(0x7E) DIDR0 –– ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 263

(0x7D) Reserved – – – – – – – –

(0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 259

(0x7B) ADCSRB –ACME– – – ADTS2 ADTS1 ADTS0 262

(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 260

(0x79) ADCH ADC Data Register High byte 262

(0x78) ADCL ADC Data Register Low byte 262

(0x77) Reserved – – – – – – – –

(0x76) Reserved – – – – – – – –

(0x75) Reserved – – – – – – – –

(0x74) Reserved – – – – – – – –

(0x73) Reserved – – – – – – – –

(0x72) Reserved – – – – – – – –

(0x71) Reserved – – – – – – – –

(0x70) TIMSK2 – – – – – OCIE2B OCIE2A TOIE2 160

(0x6F) TIMSK1 ––ICIE1 –– OCIE1B OCIE1A TOIE1 136

(0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 108

(0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 71

(0x6C) PCMSK1 – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 71

(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 71

(0x6A) Reserved – – – – – – – –

(0x69) EICRA – – – –ISC11ISC10ISC01ISC00 68

(0x68) PCICR – – – – – PCIE2 PCIE1 PCIE0

(0x67) Reserved – – – – – – – –

(0x66) OSCCAL Oscillator Calibration Register 37

(0x65) Reserved – – – – – – – –

(0x64) PRR PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC 42

(0x63) Reserved – – – – – – – –

(0x62) Reserved – – – – – – – –

(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 37

(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 54

0x3F (0x5F) SREG I T H S V N Z C 9

0x3E (0x5E) SPH – – – – – (SP10) 5. SP9 SP8 12

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12

0x3C (0x5C) R ese r ved – – – – – – – –

0x3B (0x5B) Reserved – – – – – – – –

0x3A (0x5A) Reserved – – – – – – – –

0x39 (0x59) Reserved – – – – – – – –

0x38 (0x58) Reserved – – – – – – – –

0x37 (0x57) SPMCSR SPMIE (RWWSB)5. – (RWWSRE)5. BLBSET PGWRT PGERS SELFPRGEN 288

0x36 (0x56) Reserved – – – – – – – –

0x35 (0x55) MCUCR – BODS BODSE PUD –– IVSEL IVCE 44/65/89

0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 54

0x33 (0x53) SMCR – – – –SM2SM1SM0SE 40

0x32 (0x52) Reserved – – – – – – – –

0x31 (0x51) Reserved – – – – – – – –

0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 244

0x2F (0x4F) Reserved – – – – – – – –

0x2E (0x4E) SPDR SPI Data Register 172

0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 171

0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 170

0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 25

0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 25

0x29 (0x49) Reserved – – – – – – – –

0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B

0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A

0x26 (0x46) TCNT0 Timer/Counter0 (8-bit)

0x25 (0x45) TCCR0B FOC0A FOC0B –– WGM02 CS02 CS01 CS00

0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 ––WGM01WGM00

0x23 (0x43) GTCCR TSM – – – – – PSRASY PSRSYNC 140/162

0x22 (0x42) EEARH (EEPROM Address Register High Byte) 5. 21

0x21 (0x41) EEARL EEPROM Address Register Low Byte 21

0x20 (0x40) EEDR EEPROM Data Register 21

0x1F (0x3F) EECR –– EEPM1 EEPM0 EERIE EEMPE EEPE EERE 21

0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 25

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8025KS–AVR–10/09

ATmega48P/88P/168P

Note: 1. For compatibili ty with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48P/88P/168P

is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for

the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used.

5. Only valid for ATmega88P/168P.

0x1D (0x3D) EIMSK – – – – – –INT1INT0 69

0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 69

0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0

0x1A (0x3A) Reserved – – – – – – – –

0x19 (0x39) Reserved – – – – – – – –

0x18 (0x38) Reserved – – – – – – – –

0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 160

0x16 (0x36) TIFR1 ––ICF1 –– OCF1B OCF1A TOV1 137

0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0

0x14 (0x34) Reserved – – – – – – – –

0x13 (0x33) Reserved – – – – – – – –

0x12 (0x32) Reserved – – – – – – – –

0x11 (0x31) Reserved – – – – – – – –

0x10 (0x30) Reserved – – – – – – – –

0x0F (0x2F) Reserved – – – – – – – –

0x0E (0x2E) Reserved – – – – – – – –

0x0D (0x2D) Reserved – – – – – – – –

0x0C (0x2C) Reserved – – – – – – – –

0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 90

0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 90

0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 90

0x08 (0x28) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 89

0x07 (0x27) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 89

0x06 (0x26) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 89

0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 89

0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 89

0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 89

0x02 (0x22) Reserved – – – – – – – –

0x01 (0x21) Reserved – – – – – – – –

0x0 (0x20) Reserved – – – – – – – –

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8025KS–AVR–10/09

ATmega48P/88P/168P

7. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immedia te from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Sign ed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP(1) k Direct Jump PC ← kNone3

RCALL k Relative Su broutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← ZNone3

CALL(1) k Direct Subr outine Call PC ← kNone4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2 /3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s ) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Sta tus Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 N one 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

8025KS–AVR–10/09

ATmega48P/88P/168P

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O (P ,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displace ment (Y + q) ← Rr None 2

ST Z, Rr Store Indire ct (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displace ment (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-In c Rd ← (Z), Z ← Z+1 None 3

SPM S tore Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

Mnemonics Operands Description Operation Flags #Clocks

8025KS–AVR–10/09

ATmega48P/88P/168P

Note: 1. These instructions are only available in ATmega168P.

POP Rd Pop Register from St ack Rd ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

8025KS–AVR–10/09

ATmega48P/88P/168P

8. Ordering Information

8.1 ATmega48P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restrictio n of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-1 on page 311 and Figure 28-2 on page 311.

Speed (MHz) P ower Supply (V) Ordering Code(2) Package(1) Operational Range

10(3) 1.8 - 5.5

ATmega48PV-10AU

ATmega48PV-10MMU

ATmega48PV-10MU

ATmega48PV-10PU

32A

28M1

32M1-A

28P3

Industrial

(-40°C to 85°C)

20(3) 2.7 - 5.5

ATmega48P-20AU

ATmega48P-20MMU

ATmega48P-20MU

ATmega48P-20PU

32A

28M1

32M1-A

28P3

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

8025KS–AVR–10/09

ATmega48P/88P/168P

8.2 ATmega88P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restrictio n of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-1 on page 311 and Figure 28-2 on page 311.

Speed (MHz) P ower Supply (V) Ordering Code(2) Package(1) Operational Range

10(3) 1.8 - 5.5 ATmega88PV-10AU

ATmega88PV-10MU

ATmega88PV-10PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

20(3) 2.7 - 5.5 ATmega88P-20AU

ATmega88P-20MU

ATmega88P-20PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

8025KS–AVR–10/09

ATmega48P/88P/168P

8.3 ATmega168P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restrictio n of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-1 on page 311 and Figure 28-2 on page 311.

Speed (MHz)(3) Power Suppl y (V) Ordering Code(2) Package(1) Operational Range

10 1.8 - 5.5 ATmega168PV-10AU

ATmega168PV-10MU

ATmega168PV-10PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

20 2.7 - 5.5 ATmega168P-20AU

ATmega168P-20MU

ATmega168P-20PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

8025KS–AVR–10/09

ATmega48P/88P/168P

9. Packaging Information

9.1 32A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B

32A

10/5/2001

PIN 1 IDENTIFIER

0˚~7˚

PIN 1

A1 A2 A

eE1 E

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 8.75 9.00 9.25

D1 6.90 7.00 7.10 Note 2

E 8.75 9.00 9.25

E1 6.90 7.00 7.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

8025KS–AVR–10/09

ATmega48P/88P/168P

9.2 28M1

TITLE DRAWING NO. GPC REV.

Package Drawing Contact:

packagedrawings@atmel.com 28M1ZBVB

28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,

2.4 x 2.4 mm Exposed Pad, Thermally Enhanced

Plastic Very Thin Quad Flat No Lead Package (VQFN)

10/24/08

SIDE VIEW

Pin 1 ID

BOTTOM VIEW

TOP VIEW

Note: The terminal #1 ID is a Laser-marked Feature.

0.45 COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 0.00 0.02 0.05

b 0.17 0.22 0.27

C 0.20 REF

D 3.95 4.00 4.05

D2 2.35 2.40 2.45

E 3.95 4.00 4.05

E2 2.35 2.40 2.45

e 0.45

L 0.35 0.40 0.45

y 0.00 – 0.08

K 0.20 – –

R 0.20

0.4 Ref

(4x)

8025KS–AVR–10/09

ATmega48P/88P/168P

9.3 32M1-A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, E

32M1-A

5/25/06

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

E1 E

0.08 C

A 0.80 0.90 1.00

A1 – 0.02 0.05

A2 – 0.65 1.00

A3 0.20 REF

b 0.18 0.23 0.30

D2 2.95 3.10 3.25

4.90 5.00 5.10

4.70 4.75 4.80

4.90 5.00 5.10

E2 2.95 3.10 3.25

e 0.50 BSC

L 0.30 0.40 0.50

P – – 0.60

– – 12o

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Pin 1 ID

Pin #1 Notch

(0.20 R)

K 0.20 – –

8025KS–AVR–10/09

ATmega48P/88P/168P

9.4 28P3

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP) B

28P3

09/28/01

REF

SEATING PLANE

0º ~ 15º

(4 PLACES)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 4.5724

A1 0.508 – –

D 34.544 – 34.798 Note 1

E 7.620 – 8.255

E1 7.112 – 7.493 Note 1

B 0.381 – 0.533

B1 1.143 – 1.397

B2 0.762 – 1.143

L 3.175 – 3.429

C 0.203 – 0.356

eB – – 10.160

e 2.540 TYP

Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

8025KS–AVR–10/09

ATmega48P/88P/168P

10. Errata

10.1 Errata ATmega48P

The revision letter in this section refers to the revision of the ATmega48P device.

10.1.1 Rev. C No known errata.

10.1.2 Rev. B No known errata.

10.1.3 Rev. A Not Sampled.

10.2 Errata ATmega88P

The revision letter in this section refers to the revision of the ATmega88P device.

10.2.1 Rev. C Not sampled.

10.2.2 Rev. B No known errata.

10.2.3 Rev. A No known errata.

10.3 Errata ATmega168P

The revision lette r in this section refers to the revision of the ATmega168P device.

10.3.1 Rev B No known errata.

10.3.2 Rev A No known errata.

8025KS–AVR–10/09

ATmega48P/88P/168P

11. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring re visio n in th is section are referring to the document revision.

11.1 Rev. 8025K-10/09

11.2 Rev. 8025J-05/09

11.3 Rev. 8025I-02/09

11.4 Rev. 8025H-02/09

11.5 Rev. 8025G-01/09

1. Updated “Low Frequency Crystal Oscillator” with the Table 8-8 on page 32

2. Editorial updates.

1. Removed the “About” section.

2. Removed ATmega328P device and its reference from the data sheet.

3. Editorial updates.

1. Removed “preliminary” from ATmega48P/88P/168P.

1. Added Power-save Maximum values and footnote to ”ATmega48P DC Characteris-

tics” on page 309.

2. Added Power-save Maximum values and footnote to ”ATmega88P DC Characteris-

tics” on page 310.

3. Added Power-save Maximum values and footnote to ”ATmega168P DC Characteris-

tics” on page 310.

4. Added Power-save Maximum values and footnote to ”” on page 311.

5. Added errata for revision A, ”” on page 408.

1 ATmega48P/88P not recommended for new designs.

2. Updated the footnote Note1 of the Table 8-3 on page 29.

3. Updated the Table 8-5 on page 30 by removing a footnote Note1.

4. Updated the Table 8-10 on page 33 by removing a footnote Note1.

5. Updated the footnote Note1 of the Table 8-12 on page 34.

6. Updated the footnote Note2 of the ”ATmega48P DC Characteristics” on pag e 309

and removed TBD from the table.

7. Updated the footnote Note2 of the ”ATmega88P DC Characteristics” on pag e 310

and removed TBD from the table.

8. Updated the footnote Note2 of the ”ATmega168P DC Characteristics” on page 310

and removed TBD from the table.

9. Updated the footnote Note2 of the ”” on page 311 and removed TBD from the table.

8025KS–AVR–10/09

ATmega48P/88P/168P

11.6 Rev. 8025F-08/08

11.7 Rev. 8025E-08/08

11.8 Rev. 8025D-03/08

10. Updated the footnote Note1 of the Table 28-4 on page 313 .

11. Replaced the Figure 29-69 on page 358 by a correct one.

12. Replaced the Figure 29-173 on page 419 by a correct one.

13. Updated ”Errata ” on page 408.

14. Updated ”MCUCR – MCU Control Register” on page 44.

15. Updated ”TCCR2B – Timer/Counter Control Register B” on page 158.

1. Updated ”Register Summary” on page 394 with Power-save numbers.

2. Added ATmega328P ”Standby Supply Current” on page 408.

1. Updated description of ”Stack Pointer” on page 12.

2. Updated description of use of external capacitors in ”Low Frequency Crystal Oscilla-

tor” on page 32.

3. Updated Table 8-9 in ”Low Frequency Crystal Oscillator” on page 32.

4. Added note to ”Address Match Un it” on page 219.

5. Added section ”Reading the Signature Row from Software” on page 282.

6. Updated ”Program And Data Memory Lock Bits” on page 290 to include

ATmega328P in the de scr ipt ion .

7. Added ”” on page 311.

8. Updated ”Speed Grades” on page 311 for ATmega328P.

9. Removed note 6 and 7 from the table ”2-wire Serial Interface Characteristics” on

page 316.

10. Added figure ”Minimum Reset Pulse width vs. VCC.” on page 345 for ATmega48P.

11. Added figure ”Minimum Reset Pulse width vs. VCC.” on page 369 for ATmega88P.

12. Added figure ”Minimum Reset Pulse width vs. VCC.” on page 393 for ATmega168P.

13. Added ”Register Summary” on page 394.

14. Updated Ordering Info rmation for ”Packaging Information” on page 404.

1. Updated figures in ”Speed Grad es” on page 311 .

2. Updated note in Table 28-4 in ”System and Reset Characteristics” on page 313.

3. Ordering codes for ”Packaging Informat ion” on page 404 updated.

- ATmega328P is offered in 20 MHz op tion only.

4. Added Errata for ATmega328P rev. B, ”” on page 408.

8025KS–AVR–10/09

ATmega48P/88P/168P

11.9 Rev. 8025C-01/08

11.10 Rev. 8025B-01/08

11.11 Rev. 8025A-07/07

1. Power-save Maximum values removed form ”ATmega48P DC Characteristics” on

page 309, ”ATmega88P DC Characteristics” on page 310, and ”ATmega168P DC

Characteristics” on page 310.

1. Updated ”Features” on page 1.

2. Added ”Data Retention” on page 7.

3. Updated Table 8-2 on page 28.

4. Removed “Low-frequency Crystal Oscillator Internal Load Capacitance“ table

from”Low Frequency Crystal Oscillator” on page 32.

5. Removed JTD bit from ”MCUCR – MCU Control Register” on page 44.

6. Updated typical and ge ner al pr og ra m setu p f or Reset an d I nt erru pt Ve cto r Add resses

in ”Interrupt Vectors in ATmega168P” on page 62 and ”Interrupt Vectors in

ATmega328P” on page 65.

7. Updated Interrupt Vectors Start Address in Table 11-5 on page 63 and Table 11-7 on

page 66.

8. Updated ”Temperature Measurement” on page 258.

9. Updated ATmega328P ”Fuse Bits” on page 291.

10. Removed VOL3/VOH3 rows from ”DC Characteristics” on page 308.

11. Updated condition for VOL in ”DC Characteristics” on page 308.

Updated max value for VIL2 in ”DC Characteristics” on page 308.

12. Added ” ATmega48P DC Char acteristics” on p age 309, ”ATmega88P DC Character is-

tics” on page 310, and ”ATmega168P DC Characteristics” on page 310.

13. Updated ”System and Reset Characteristics” on page 313.

14. Added ”ATmega48P Typical Characteristics” on page 322, ”ATmega88P Typical

Characteristics” on page 346, and ”ATmega168P Typical Characteristics” on page

370.

15. Updated note in ”Instruction Set Summary” on page 398.

1. Initial revision.

8025KS–AVR–10/09

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