1
File Number 3117.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Americas Inc. |Copyright © Intersil Americas Inc. 2001
DG201A, DG202
Quad SPST, CMOS Analog Switches
The DG201A and DG202 quad SPST analog switches are
designed using Intersil’s 44V CMOS process. These
bidirectional switches are latch-proof and feature break-
before-make switching. Designed to block signals up to
30VP-P in the OFF state, the DG201A and DG202 offer the
advantages of low ON resistance (≤175Ω), wide input signal
range (±15V) and provide both TTL and CMOS compatibility.
The DG201A and DG202 are specification and pinout
compatible with the industry standard devices.
Pinout DG201A, DG202
(CERDIP, PDIP, SOIC)
TOP VIEW
Features
• Input Signal Range.......................... ±15V
• Low rDS(ON) (Max).......................... 175Ω
• TTL, CMOS Compatible
• Latch-Up Proof
• True Second Source
• MaximumSupplyRatings ..................... 44V
• Logic Inputs Accept Negative Voltages
Functional Block Diagrams
DG201A
DG202
Part Number Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
DG201AAK -55 to 125 16 Ld CERDIP F16.3
DG201ABK -25to85 16LdCERDIP F16.3
DG201ACJ 0to70 16LdPDIP E16.3
DG201ACY 0to70 16LdSOIC M16.3
DG202AK -55 to 125 16 Ld CERDIP F16.3
DG202CJ 0 to 70 16 Ld PDIP E16.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
D1
S1
V-
GND
S4
IN4
D4
IN2
S2
V+ (SUB-
NC
S3
D3
IN3
D2
STRATE)
-
TRUTH TABLE
LOGIC DG201A DG202
0ONOFF
1OFFON
Logic “0” ≤0.8V, Logic “1” ≥2.4V
IN1
S1
D1
IN2
S2
D2
IN3
S3
D3
IN4
S4
D4
IN1
S1
D1
IN2
S2
D2
IN3
S3
D3
IN4
S4
D4
SWITCHES SHOWN FOR LOGIC “1” INPUT
Data Sheet May 2001
itle
G20
,202
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a-
itch
utho
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ey-
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ter-
rpo-
ion,
i-
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itch
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OBSOLETEPRODUCT
POSSIBLESUBSTITUTEPRODUCT
HI1-0201(CERDIP),DG441(PDIP),
HI9P0201HS(SOIC),DG442
2
Absolute Maximum Ratings Thermal Information
V+toV-........................................... 44V
V-toGround........................................-25V
VIN toGround(Note1)...................(V-)-2Vto(V+)+2V
VSor VDtoV+(Note1)........................+2to(V-)-2V
VSor VDtoV-(Note1)....................... -2to(V+)+2V
Current,anyTerminalExceptSorD....................30mA
ContinuousCurrent,SorD...........................20mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 70mA
Operating Conditions
Temperature Range
“A”Suffix................................-55
oCto125
oC
“B”Suffix.................................-25
oCto85
oC
“C”Suffix ..................................0
oCto70
oC
Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
CERDIPPackage................. 75 20
PDIPPackage................... 100 N/A
SOICPackage................... 100 N/A
Maximum Junction Temperature
CeramicPackage................................ 175
oC
PlasticPackage................................. 150
oC
MaximumStorageTemperatureRange.......... -65
oCto150
oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on VS,V
D,orV
IN exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, TA=25
oC
PARAMETER TEST CONDITIONS
“A” SUFFIX “B” AND “C” SUFFIX
UNITSMIN (NOTE 3)
TYP MAX MIN (NOTE 3)
TYP MAX
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON See Figure 1 - 480 600 - 480 - ns
Turn-OFF Time, tOFF See Figure 1 - 370 450 - 370 - ns
Charge Injection, Q CL=1nF,R
S=0,V
S= 0V - 20 - - 20 - pC
OFF Isolation, OIRR VIN =5V,R
L=75Ω,V
S=2.0V,
f = 100kHz -70--70-dB
Crosstalk (Channel to Channel), CCRR - -90 - - -90 - dB
Source OFF Capacitance, CS(OFF) f = 140kHz, VIN =5V,V
S=V
D=0V - 5.0 - - 5.0 - pF
Drain OFF Capacitance, CD(OFF) -5.0--5.0-pF
Channel ON Capacitance,
CD(ON) +C
S(ON) -16--16-pF
DIGITAL INPUT CHARACTERISTICS
Input Current with Voltage High, IIH VIN = 2.4V -1.0 -0.0004 - -1.0 -0.0004 - µA
VIN = 15V - 0.003 1.0 - 0.003 1.0 µA
Input Current with Voltage Low, IIL VIN = 0V -1.0 -0.0004 - -1.0 -0.0004 - µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG -15 - 15 -15 - 15 V
Drain-Source ON Resistance, rDS(ON) VD=±10V, VIN = 0.8V (DG201A)
IS=1mA,V
IN = 2.4V (DG202) - 115 175 - 115 200 Ω
Source OFF Leakage Current, IS(OFF) VIN =2.4V
(DG201A)
VIN =0.8V
(DG202)
VS= 14V, VD= -14V - 0.01 1.0 - 0.01 5.0 nA
VS=-14V,V
D= 14V -1.0 -0.02 - -5.0 -0.02 - nA
Drain OFF Leakage Current, ID(OFF) VS=-14V,V
D= 14V - 0.01 1.0 - 0.01 5.0 nA
VS= 14V, VD= -14V -1.0 -0.02 - -5.0 -0.02 - nA
DG201A, DG202
3
Drain ON Leakage Current, ID(ON)
(Note 5) VIN =0.8V
(DG201A)
VIN =2.4V
(DG202)
VD=V
S= 14V - 0.1 1.0 - 0.1 5.0 µA
VD=V
S= -14V -1.0 -0.15 - -5.0 -0.15 - µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ All Channels ON or OFF - 0.9 2 - 0.9 2 mA
Negative Supply Current, I- -1 -0.3 - -1 -0.3 - mA
Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, TA=25
oC(Continued)
PARAMETER TEST CONDITIONS
“A” SUFFIX “B” AND “C” SUFFIX
UNITSMIN (NOTE 3)
TYP MAX MIN (NOTE 3)
TYP MAX
Electrical Specifications V+ = 15V, V- = -15V, GND = 0V, TAOver Operating Temperature Range
PARAMETER TEST CONDITIONS
“A” SUFFIX
UNITSMIN (NOTE 3)
TYP MAX
DIGITAL INPUT CHARACTERISTICS
Input Current with Voltage High, IIH VIN =2.4V -10 - - µA
VIN =15V - - 10 µA
Input Current with Voltage Low, IIL VIN =0V -10 - - µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG -15 - 15 V
Drain-Source ON Resistance, rDS(ON) VD=±10V, VIN = 0.8V (DG201A)
IS=1mA,V
IN =2.4V(DG202) --250Ω
Source OFF Leakage Current, IS(OFF) VIN = 2.4V (DG201A)
VIN = 0.8V (DG202) VS=14V,V
D= -14V - - 100 nA
VS=-14V,V
D= 14V -100 - - nA
Drain OFF Leakage Current, ID(OFF) VS=-14V,V
D= 14V - - 100 nA
VS=14V,V
D= -14V -100 - - nA
Drain ON Leakage Current, ID(ON) (Note 5) VIN = 0.8V (DG201A)
VIN = 2.4V (DG202) VD=V
S=14V - - 200 µA
VD=V
S=-14V -200 - - µA
NOTES:
3. Typical values are for design aid only, not guaranteed and not subject to production testing.
4. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet.
5. ID(ON) is leakage from driver into ON switch.
DG201A, DG202
4
Test Circuits and Waveforms
FIGURE 1. tON AND tOFF SWITCHING TEST CIRCUIT AND MEASUREMENT POINTS
NOTES:
6. ∆VO= Measured voltage error due to charge injection.
7. The error in coulombs is Q = CLx∆VO.
FIGURE 2. CHARGE INJECTION TEST CIRCUIT AND MEASUREMENT POINTS
C = 0.001µF||0.1µF
Chip Capacitors
FIGURE 3. OFF ISOLATION TEST CIRCUIT
C=0.001µF||0.1µF
Chip Capacitors
FIGURE 4. CHANNEL TO CHANNEL CROSSTALKTEST
CIRCUIT
LOGIC“0”=SWITCHON
50%
90%
tOFF
LOGIC†
INPUT
SWITCH
OUTPUT
VS
3V
tON
tr<20ns
tf< 20ns VO
S1
IN1
LOGIC
INPUT
GND
VS=2V
RL
1kΩ
CL
35pF
SWITCH
OUTPUT
15VV+
-15V
V-
SWITCH
INPUT
(REPEAT TEST FOR
IN2,IN
3AND IN4)
VO=V
SRL
RL+r
DS(ON)
90%
SWITCH
INPUT
†Logic shown for DG201A, invert for DG202.
D1
RSSX
CL=1nF
VO
DX
INX
VS
INX
∆VO
ON OFF ON
SWITCH
OUTPUT
ANALYZER
RL
SIGNAL
GENERATOR V+
C
V-
-15V
C
VS
VD
INX
GND
CHAN A
CHAN B
VIN
+15V
VS
OIRR 20 Log VS
VD
--------
=
0V,
V+
VS1
RL
GND
IN1
VD1
IN2
50Ω
0V, 2.4V
NC
V-
-15V
VD2
ANALYZER
CHAN A
CHAN B
SIGNAL
GENERATOR
VS2
2.4V
C
C
+15V
3
VS
CCRR 20Log VS1
VD2
-----------
=
DG201A, DG202
5
DG201A, DG202
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. ControllingDimensions:INCH.In caseofconflictbetweenEnglishand
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1,and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eBand eCare measured at the lead tips with the leads unconstrained.
eCmust be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
6
DG201A, DG202
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. DimensionQshallbemeasuredfromtheseatingplanetothe
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA-B
MD
SS
eA
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.840 - 21.34 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N16 168
Rev. 0 4/94
7
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished byIntersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100,RuedelaFusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
DG201A, DG202
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamferon the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) orgreater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
hx45
o
C
H
µ
0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0o8o0o8o-
Rev. 0 12/93
