2005-2015 Microchip Technology Inc. DS40001262F-page 1
PIC16F631/677/685/687/689/690
High-Performance RISC CPU
• Only 35 Instru ctions to Lear n:
- All single-cycle instructions except branches
• Ope rati ng Sp eed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
S pecial Microcontroller Features
• Precision Internal Oscillator:
- Factory calibrated to ± 1%
- Software selectable frequency range of
8 MHz to 32 kHz
- Softwa re tu nable
- Two-Speed Start-up mode
- Crystal fail detect for critical applications
- Clock mode switching during operation for
power savings
• Power-Saving Sleep mode
• Wide Operating Voltage Range (2.0V-5.5V)
• Indus tri al and Extended Temperatu r e Range
• Power-on Reset (POR)
• Power-up Timer (PWRTE) and Oscillator Start-up
Timer (OST)
• Brown-ou t Reset (BOR) with Softwa re Control
Option
• Enhanced Low-Current Watchdog Timer (WDT)
with On-Ch ip Os ci ll ator (Sof tware selec t ab le
nominal 268 Seconds with Full Prescaler) with
Software Enable
• Multiplexed Master Clear/Input Pin
• Programmable Code Protection
• High Endurance Flash/EEPROM Cell:
- 10 0,000 wri te Flash e ndur ance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
• Enhanced USART Module:
- Supports RS-485, RS-232 and LIN 2.0
- Auto-Baud Detec t
- Auto-wake-up on Start bit
Low-Power Features
• Standby Current:
- 50 nA @ 2.0V, typical
• Operating Current:
-11A @ 32 kHz, 2.0V, typical
-220A @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
-<1A @ 2.0V, typical
Peripheral Feat ures
• 17 I/O Pins and 1 Input-Only Pin:
- High current source/sink for direct LED drive
- Interrupt-on-Change pin
- Individually programmable weak pull-ups
- Ultra Low-Power Wake-up (ULPWU)
• Analog Comparator Module with:
- Two analog compara tors
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- Comparator inputs and outputs externally
accessible
- SR Latch mode
- Timer 1 Gate Sync Latch
- F ixed 0.6V VREF
• A/D Converter:
- 10-bit resolution and 12 channels
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enab le )
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode
selected
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Enhanced Capture, Compare, PWM+ Module:
- 1 6-bit Capture, max resolut ion 12.5 ns
- Compare, max resolution 200 ns
- 10-bit PWM with 1, 2 or 4 output channels,
programmable “dead time”, max frequency
20 kHz
- PWM output steering control
• Synchronous Serial Port (SSP):
- SPI mode (Master and Slave)
•I
2C™ (Master/Slave modes):
-I
2C™ address mask
• In-C ircuit Seri al Prog ram mingTM (ICSPTM) via Two
Pins
20-Pin Flash-Based, 8-Bit CMOS Microcontrollers
PIC16F631/677/685/687/689/690
DS40001262F-page 2 2005-2015 Mic rochip Technology Inc.
PIC16F631 Pin Diagram
TABLE 1: PIC16F631 PIN SUMMARY
Device
Program
Memory Data Memory I/O 10-bit A/D
(ch) Comparators Timers
8/16-bit SSP ECCP+ EUSART
Flash
(words) SRAM
(bytes) EEPROM
(bytes)
PIC16F631 1024 64 128 18 — 2 1/1 No No No
PIC16F677 2048 128 256 18 12 2 1/1 Yes No No
PIC16F685 4096 256 256 18 12 2 2/1 No Yes No
PIC16F687 2048 128 256 18 12 2 1/1 Yes No Yes
PIC16F689 4096 256 256 18 12 2 1/1 Yes No Yes
PIC16F690 4096 256 256 18 12 2 2/1 Yes Yes Yes
I/O Pin Analog Comparators Timers Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ —IOC YICSPDAT
RA1 18 AN1 C12IN0- — IOC Y ICSPCLK
RA2 17 —C1OUT T0CKI IOC/INT Y —
RA3 4 — — — IOC Y(1) MCLR/VPP
RA4 3 — — T1G IOC YOSC2/CLKOUT
RA5 2 — — T1CKI IOC Y OSC1/CLKIN
RB4 13 — — — IOC Y —
RB5 12 — — — IOC Y —
RB6 11 — — — IOC Y —
RB7 10 — — — IOC Y —
RC0 16 AN4 C2IN+ — — — —
RC1 15 AN5 C12IN1- — — — —
RC2 14 AN6 C12IN2- — — — —
RC3 7 AN7 C12IN3- — — — —
RC4 6 — C2OUT — — — —
RC55— ———— —
RC6 8 — — — — — —
RC79— ———— —
— 1 — — — — — VDD
—20— ———— VSS
Note 1: Pull-up enabled only with external MCLR configuration.
20-pin PDIP, SOIC, SSOP
PIC16F631
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5
RC4/C2OUT
RC3/C12IN3-
RC6
RC7
RB7
VSS
RA0/C1IN+/ICSPDAT/ULPWU
RA1/C12IN0-/ICSPCLK
RA2/T0CKI/INT/C1OUT
RC0/C2IN+
RC1/C12IN1-
RC2/C12IN2-
RB4
RB5
RB6
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
2005-2015 Microchip Technology Inc. DS40001262F-page 3
PIC16F631/677/685/687/689/690
PIC16F677 Pin Diagram
TABLE 2: PIC16F631 PIN SUMMARY
I/O Pin Analog Comparators Timers Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ —IOC YICSPDAT
RA1 18 AN1 C12IN0- — IOC Y ICSPCLK
RA2 17 —C1OUT T0CKI IOC/INT Y —
RA3 4 — — — IOC Y(1) MCLR/VPP
RA4 3 — — T1G IOC YOSC2/CLKOUT
RA5 2 — — T1CKI IOC Y OSC1/CLKIN
RB4 13 — — — IOC Y —
RB5 12 — — — IOC Y —
RB6 11 — — — IOC Y —
RB7 10 — — — IOC Y —
RC0 16 AN4 C2IN+ — — — —
RC1 15 AN5 C12IN1- — — — —
RC2 14 AN6 C12IN2- — — — —
RC3 7 AN7 C12IN3- — — — —
RC4 6 — C2OUT — — — —
RC55— ———— —
RC6 8 — — — — — —
RC79— ———— —
— 1 — — — — — VDD
—20— ———— VSS
Note 1: Pull-up enabled only with external MCLR configuration.
20-pin PDI P, SOIC, SSO P
PIC16F677
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5
RC4/C2OUT
RC3/AN7C12IN3-
RC6/AN8/SS
RC7/AN9/SDO
RB7
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-
RB4/AN10/SDI/SDA
RB5/AN11
RB6/SCK/SCL
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
PIC16F631/677/685/687/689/690
DS40001262F-page 4 2005-2015 Mic rochip Technology Inc.
PIC16F685 Pin Diagram
TABLE 3: PIC16F685 PIN SUMMARY
I/O Pin Analog Comparators Timers ECCP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ — — IOC YICSPDAT
RA1 18 AN1/VREF C12IN0- — — IOC Y ICSPCLK
RA2 17 AN2 C1OUT T0CKI —IOC/INT Y —
RA3 4 — — — — IOC Y(1) MCLR/VPP
RA4 3AN3 —T1G —IOC YOSC2/CLKOUT
RA5 2 — — T1CKI — IOC Y OSC1/CLKIN
RB4 13 AN10 — — — IOC Y —
RB5 12 AN11 — — — IOC Y —
RB6 11 — — — — IOC Y —
RB7 10 — — — — IOC Y —
RC0 16 AN4 C2IN+ — — — — —
RC1 15 AN5 C12IN1- — — — — —
RC2 14 AN6 C12IN2- —P1D — — —
RC3 7 AN7 C12IN3- — P1C — — —
RC4 6 — C2OUT —P1B — — —
RC5 5 — — — CCP1/P1A — — —
RC6 8AN8 — — — — — —
RC7 9 AN9 — — — — — —
— 1 — — — — — — VDD
—20 — — — — — — VSS
Note 1: Pull-up activated only with external MCLR configura t io n.
20-pin PDIP, SOIC, SSOP
PIC16F685
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5/CCP1/P1A
RC4/C2OUT/P1B
RC3/AN7/C12IN3-/P1C
RC6/AN8
RC7/AN9
RB7
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-/P1D
RB4/AN10
RB5/AN11
RB6
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
2005-2015 Microchip Technology Inc. DS40001262F-page 5
PIC16F631/677/685/687/689/690
PIC16F687/689 Pin Diagram
TABLE 4: PIC16F687/689 PIN SUMMARY
20-pin PDIP, SOIC, SSOP
PIC16F687/689
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5
RC4/C2OUT
RC3/AN7/C12IN3-
RC6/AN8/SS
RC7/AN9/SDO
RB7/TX/CK
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
I/O Pin Analog Comparators Timers EUSART SSP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ — — — IOC YICSPDAT
RA1 18 AN1/VREF C12IN0- — — — IOC Y ICSPCLK
RA2 17 AN2 C1OUT T0CKI — — IOC/INT Y
RA3 4 — — — — — IOC Y(1) MCLR/VPP
RA4 3AN3 —T1G — — IOC YOSC2/CLKOUT
RA5 2 — — T1CKI — — IOC Y OSC1/CLKIN
RB4 13 AN10 — — — SDI/SDA IOC Y —
RB5 12 AN11 — — RX/DT — IOC Y —
RB6 11 — — — — SCL/SCK IOC Y —
RB7 10 — — — TX/CK — IOC Y —
RC0 16 AN4 C2IN+ — — — — — —
RC1 15 AN5 C12IN1- — — — — — —
RC2 14 AN6 C12IN2- — — — — — —
RC3 7 AN7 C12IN3- — — — — — —
RC4 6 — C2OUT — — — — — —
RC5 5 — — — — — — — —
RC6 8AN8 — — — SS — — —
RC7 9 AN9 — — — SDO — — —
— 1 — — — — — — — VDD
—20 — — — — — — — VSS
Note1: Pull-up activated only with external MCLR config ura tion.
PIC16F631/677/685/687/689/690
DS40001262F-page 6 2005-2015 Mic rochip Technology Inc.
PIC16F690 Pin Diagram (PDIP, SOIC, SSOP)
TABLE 5: PIC16F690 PIN SUMMARY
I/O Pin Analog Comparators Timers ECCP EUSART SSP Interrupt Pull-up Basic
RA0 19 AN0/ULPWU C1IN+ — — — — IOC YICSPDAT
RA1 18 AN1/VREF C12IN0- — — — — IOC Y ICSPCLK
RA2 17 AN2 C1OUT T0CKI — — — IOC/INT Y
RA3 4 — — — — — — IOC Y(1) MCLR/VPP
RA4 3AN3 —T1G — — — IOC YOSC2/CLKOUT
RA5 2 — — T1CKI — — — IOC Y OSC1/CLKIN
RB4 13 AN10 — — — — SDI/SDA IOC Y —
RB5 12 AN11 — — — RX/DT — IOC Y —
RB6 11 — — — — SCL/SCK IOC Y —
RB7 10 — — — — TX/CK — IOC Y —
RC0 16 AN4 C2IN+ — — — — — — —
RC1 15 AN5 C12IN1- — — — — — — —
RC2 14 AN6 C12IN2- —P1D — — — — —
RC3 7 AN7 C12IN3- — P1C — — — — —
RC4 6 — C2OUT —P1B — — — — —
RC5 5 — — — CCP1/P1A — — — — —
RC6 8AN8 — — — — SS — — —
RC7 9 AN9 — — — — SDO — — —
— 1 — — — — — — — — VDD
—20 — — — — — — — — VSS
Note 1: Pull-up activated only with external MCLR configuration.
20-pin PDIP, SOIC, SSOP
PIC16F690
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5/CCP1/P1A
RC4/C2OUT/P1B
RC3/AN7/C12IN3-/P1C
RC6/AN8/SS
RC7/AN9/SDO
RB7/TX/CK
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-/P1D
RB4/AN10/SDI/SDA
RB5/AN11/RX/DT
RB6/SCK/SCL
1
2
3
4
20
19
18
17
5
6
7
16
15
14
8
9
10
13
12
11
2005-2015 Microchip Technology Inc. DS40001262F-page 7
PIC16F631/677/685/687/689/690
PIC16F631/677/685/687/689/690 Pin Diagram (QFN)
20-pin QF N
RA4/AN3/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
VDD
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RC7/AN9/SDO(2)
RB7/TX/CK(3)
RB6/SCK/SCL(2)
RB5/AN11/RX/DT(3)
RB4/AN10/SDI/SDA(2)
RA3/MCLR/VPP
RC5/CCP1/P1A(1)
RC4/C2OUT/P1B(1)
RC3/AN7/C12IN3-/P1C(1)
RC6/AN8/SS(2)
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-/P1D(1)
PIC16F631/677/
685/687/689/690
20
19
18
17
16
6
7
8
9
10
15
14
13
12
11
1
2
3
4
5
Note 1: CCP1/P1A, P1B, P1C and P1D are available on PIC16F685/PIC16F690 only.
2: SS, SDO, SDI/SDA and SCL/SCK are available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
3: RX/DT and TX/CK are available on PIC16F687/PIC16F689/PIC16F6 90 only.
PIC16F631/677/685/687/689/690
DS40001262F-page 8 2005-2015 Mic rochip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Memory O rganization................................................................................................................................................................. 24
3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 45
4.0 I/O Ports ............................................................. ............................................. ........................................................................... 57
5.0 Timer0 Module ........................................................................................................................................................................... 79
6.0 Timer1 Module with Gate Control............................................................................................................................................... 82
7.0 Timer2 Module ........................................................................................................................................................................... 89
8.0 Comparator Module..................... ......... .... .... .... ......... .... .... .. .... ........... .. .... .... ......... .... .... ............................................................. 91
9.0 Analog-to-Digital Converter (AD C) Module .............................................................................................................................. 105
10.0 Data EEPROM and Flash Program Memory Control......................................................................... ...................................... 117
11.0 Enhanced Capture/Compare/PWM Module.......................... ......... .... .. .... .... ......... .... .. .... ......... .... .... .. . ..................................... 125
12.0 Enhanced Universal Sync hronous As ynchr onous Receiver Transmitter (EUSART)............................................................... 148
13.0 SSP Module Overview ............................................................................................................................................................. 175
14.0 Special Feature s of th e CPU... ................................................................................................................................................. 193
15.0 Instruction Set Summary.......................................................................................................................................................... 212
16.0 Development Support. .............................................................................................................................................................. 221
17.0 Electrical Specifications............................................................................................................................................................ 225
18.0 DC and AC Characteristics Graphs and Tables.......................................................... .... ........... .... ... ....................................... 258
19.0 Packa g i n g In fo rmation....... ....................................................................................................................................................... 285
The Micro chip Web Site........ .................................................. ............................................ ............................................................... 295
Customer Change Notification Service .............................................................. ................... ............................................................. 295
Customer Support......................................................................... ............... ........ .............................................................................. 295
Product Identification System............................................................................................................................................................. 296
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2005-2015 Microchip Technology Inc. DS40001262F-page 9
PIC16F631/677/685/687/689/690
1.0 DEVICE OVERVIEW
The PIC16F631/677/685/687/689/690 devices are
covered by this dat a sheet. The y are availab le in 20-pin
PDIP, SOIC, TSSOP and QFN packages.
Block Diagrams and pinout descriptions of the devices
are as follows:
• PIC16F631 (Figure 1-1, Table 1-1)
• PIC16F677 (Figure 1-2, Table 1-2)
• PIC16F685 (Figure 1-3, Table 1-3)
• PIC16F687/PIC16F689 (Figure 1-4, Table 1-4)
• PIC16F690 (Figure 1-5, Table 1-5)
FIGURE 1-1: PI C16F63 1 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
8
8
8
3
8-Level Stack (13-bit) 64 bytes
1K x 14
VDD
INT
Configuration
Internal
Oscillator
MCLR
Block
VSS
2
Timer0 Timer1 Analog Comparators
C1IN- C1IN+ C1OUT
and Reference
8
C2IN- C2IN+ C2OUT
T1G T1CKIT0CKI
Data
EEPROM
128 Bytes
EEDAT
EEADR
RB4
RB5
RB6
RB7
PORTA
RA0
RA1
RA2
RA3
RA4
RA5
PORTC RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
Ultra Low-Power
Wake-up
ULPWU
PIC16F631/677/685/687/689/690
DS40001262F-page 10 2005-2015 Microchip Technology Inc.
FIGURE 1-2: PI C16F67 7 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB4
RB5
RB6
RB7
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bit) 128 bytes
2K x 14
VDD
RA0
RA1
RA2
RA3
RA4
RA5
INT
Configuration
Internal
Oscillator
MCLR
Block
PORTC RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
VSS
2
Timer0 Timer1
Analog Comparators
Analog-to-Digital Converter
C1IN- C1IN+ C1OUT
VREF
and Reference
8
C2IN- C2IN+ C2OUT
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN8 AN9 AN10 AN11
AN7
T1G T1CKIT0CKI
Data
EEPROM
256 Bytes
EEDAT
EEADR
SDO SDI/ SCK/ SS
Synchronous
Serial Port
SDA SCL
Ultra Low-Power
Wake-up
ULPWU
2005-2015 Microchip Technology Inc. DS40001262F-page 11
PIC16F631/677/685/687/689/690
FIGURE 1-3: PI C16F68 5 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB4
RB5
RB6
RB7
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-L evel Stack (13-bit) 2 56 bytes
4K x 14
VDD
RA0
RA1
RA2
RA3
RA4
RA5
INT
Configuration
Internal
Oscillator
MCLR
Block
PORTC RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
VSS
8
ECCP+
CCP1/P1B P1C P1DP1A
Data
EEPROM
256 Bytes
EEDAT
EEADR
2
Timer0 Timer1
Analog Comparators
Analog-to-Digital Converter
C1IN- C1IN+ C1OUT
VREF
and Reference
C2IN- C2IN+ C2OUT
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN8 AN9 AN10 AN11
AN7
T1G T1CKIT0CKI
Timer2
Ultra Low-Power
Wake-up
ULPWU
PIC16F631/677/685/687/689/690
DS40001262F-page 12 2005-2015 Microchip Technology Inc.
FIGURE 1-4: PI C16F68 7/PIC16F689 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB4
RB5
RB6
RB7
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Progr am Coun ter
Direct Addr 7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bit)
2K(1)/4K x 14
VDD
RA0
RA1
RA2
RA3
RA4
RA5
INT
Configuration
Internal
Oscillator
MCLR
Block
PORTC RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
VSS
8
SDO SDI/ SCK/ SS
Synchronous
Seri al Por t
SDA SCL
Data
EEPROM
256 By tes
EEDAT
EEADR
RAM
File
Registers
128(1)/256 bytes
Note 1: PIC16F687 only.
2
Timer0 Timer1
Analog Comparators
Analog-to-Digital Converter
C1IN- C1IN+ C1OUT
VREF
and Reference
C2IN- C2IN+ C2OUT
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN8 AN9 AN10 AN11
AN7
T1G T1CKIT0CKI
EUSART
TX/CK
Ultra Low - Pow er
Wake-up
ULPWU RX/DT
2005-2015 Microchip Technology Inc. DS40001262F-page 13
PIC16F631/677/685/687/689/690
FIGURE 1-5: PI C16F69 0 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB4
RB5
RB6
RB7
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode and
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bi t) 256 bytes
4k x 14
VDD
RA0
RA1
RA2
RA3
RA4
RA5
INT
Configuration
Internal
Oscillator
MCLR
Block
PORTC RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTB
VSS
8
ECCP+
CCP1/
P1B P1C P1D
EUSART
P1A
TX/CK RX/DT SDO SDI/ SCK/ SS
Synchronous
Serial Port
SDA SCL
Data
EEPROM
256 By tes
EEDAT
EEADR
2
Timer0 Timer1
Analog C om parato rs
Analog-to-Digital Converter
C1IN- C1IN+ C1OUT
VREF
and Reference
C2IN- C2IN+ C2OUT
AN0 AN1 AN2 AN3 AN4 AN5 AN6
AN8 AN9 AN10 AN11
AN7
T1G T1CKI
T0CKI
Ultra Low-Power
Wake-up
ULPWU
Timer2
PIC16F631/677/685/687/689/690
DS40001262F-page 14 2005-2015 Microchip Technology Inc.
TABLE 1-1: PINOUT DESCRIPTION – PIC16F631
Name Function Input
Type Output
Type Description
RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
C1IN+ AN — Comparator C1 non-inverting input.
ICSPDAT ST CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1/C12IN0-/ICS PCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
C12IN0- AN — Comparator C1 or C2 inverting input.
ICSPCLK ST — ICSP™ clock.
RA2/T0CKI/INT /C1OUT RA2 ST CMOS G eneral purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
T0CKI ST — Timer0 clock input.
INT ST — External interrupt pin.
C1OUT — CMOS Comparator C1 output.
RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-
change.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
RA4/T1G/OSC2/CLK OUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
T1G ST — Timer1 gate input.
OSC2 — XTAL Crystal/Resonator.
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI/OSC1/CLK IN RA5 TTL CMO S General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST — External clock input/RC oscillator connection.
RB4 RB4 TTL CMOS G eneral purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
RB5 RB5 TTL CMOS G eneral purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
RB6 RB6 TTL CMOS G eneral purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
RB7 RB7 TTL CMOS G eneral purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
RC0/C2IN+ RC0 ST CMOS General purpose I/O.
C2IN+ AN — Comparator C2 non-inverting input.
RC1/C12IN1- RC1 ST CMOS General purpose I/O.
C12IN1- AN — Comparator C1 or C2 inverting input.
RC2/C12IN2- RC2 ST CMOS General purpose I/O.
C12IN2- AN — Comparator C1 or C2 inverting input.
RC3/C12IN3- RC3 ST CMOS General purpose I/O.
C12IN3- AN — Comparator C1 or C2 inverting input.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Comparator C2 output.
RC5 RC5 ST CMOS General purpose I/O.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
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PIC16F631/677/685/687/689/690
RC6 RC6 ST CMOS General purpose I/O.
RC7 RC7 ST CMOS General purpose I/O.
VSS VSS Power — Ground reference.
VDD VDD Power — Positive supply.
TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL com patible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
PIC16F631/677/685/687/689/690
DS40001262F-page 16 2005-2015 Microchip Technology Inc.
TABLE 1-2: PINOUT DESCRIPTION – PIC16F677
Name Function Input
Type Output
Type Description
RA0/AN0/C1IN+/ICSPDAT/
ULPWU RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN0 AN — A/D Channel 0 input.
C1IN+ AN — Comparator C1 non-inverting input.
ICSPDAT ST CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1/AN1/C12IN0-/VREF/
ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN1 AN — A/D Channel 1 input.
C12IN0- AN — Comparator C1 or C2 inverting input.
VREF AN — External Voltage Reference for A/D.
ICSPCLK ST — ICSP™ clock.
RA2/AN2/T0CKI/INT /C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN2 AN — A/D Channel 2 input.
T0CKI ST — Timer0 clock input.
INT ST — External interrupt pin.
C1OUT — CMOS Comparator C1 output.
RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-
change.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
RA4/AN3/T1G/OSC 2/CLK OUT RA4 TTL CMO S General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN3 AN — A/D Channel 3 input.
T1G ST — Timer1 gate input.
OSC2 — XTAL Crystal/Resonator.
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI/OSC1/CLK IN RA5 TTL CMO S General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST — External clock input/RC oscillator connection.
RB4/AN10/SDI/SDA RB4 T TL CMO S General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN10 AN — A/D Channel 10 input.
SDI ST — SPI data input.
SDA ST OD I2C™ data input/output.
RB5/AN11 RB5 T TL CMO S General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN11 AN — A/D Channel 11 input.
RB6/SCK/SCL RB6 TTL CMOS G eneral purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
SCK ST CMOS SP I clock .
SCL ST OD I2C™ clock.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
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PIC16F631/677/685/687/689/690
RB7 RB7 TTL CMOS G eneral purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
C2IN+ AN — Comparator C2 non-inverting input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN — A/D Channel 5 input.
C12IN1- AN — Comparator C1 or C2 inverting input.
RC2/AN6/C12IN2- RC2 ST CMOS General purpose I/O.
AN6 AN — A/D Channel 6 input.
C12IN2- AN — Comparator C1 or C2 inverting input.
RC3/AN7/C12IN3- RC3 ST CMOS General purpose I/O.
AN7 AN — A/D Channel 7 input.
C12IN3- AN — Comparator C1 or C2 inverting input.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Comparator C2 output.
RC5 RC5 ST CMOS General purpose I/O.
RC6/AN8/SS RC6 ST CMOS General purpose I/O.
AN8 AN — A/D Channel 8 input.
SS ST — Slave Select input.
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
AN9 AN — A/D Channel 9 input.
SDO — CMOS SPI data output.
VSS VSS Power — Ground reference.
VDD VDD Power — Positive supply.
TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL com patible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
PIC16F631/677/685/687/689/690
DS40001262F-page 18 2005-2015 Microchip Technology Inc.
TABLE 1-3: PINOUT DESCRIPTION – PIC16F685
Name Function Input
Type Output
Type Description
RA0/AN0/C1IN+/ICSPDAT/
ULPWU RA0 TTL CMOS General purpose I/O . Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN0 AN — A/D Channel 0 input.
C1IN+ AN — Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1/AN1/C12IN0-/VREF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN1 AN — A/D Channel 1 input.
C12IN0- AN — Comparator C1 or C2 negative input.
VREF AN — External Voltage Reference for A/D.
ICSPCL K S T — ICSP™ clock.
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN2 AN — A/D Channel 2 input.
T0CKI ST — Timer0 clock input.
INT ST — External interrupt pin.
C1OUT — CMOS Comparator C1 output.
RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-
change.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN3 AN — A/D Channel 3 input.
T1G ST — Timer1 gate input.
OSC2 — XTAL Crystal/Resonator.
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN S T — External clock input/RC oscillator connection.
RB4/AN10 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN10 AN — A/D Channel 10 input.
RB5/AN11 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN11 AN — A/D Channel 11 input.
RB6 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN — A/ D Channel 4 input.
C2IN+ AN — Comparator C2 positive input.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
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PIC16F631/677/685/687/689/690
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN — A/ D Channel 5 input.
C12IN1- AN — Comparator C1 or C2 negative input.
RC2/AN6/C12IN2-/P1D RC2 ST CMOS General purpose I/O.
AN6 AN — A/ D Channel 6 input.
C12IN2- AN — Comparator C1 or C2 negative input.
P1D — CMOS PWM output.
RC3/AN7/C12IN3-/P1C RC3 ST CMOS General purpose I/O.
AN7 AN — A/ D Channel 7 input.
C12IN3- AN — Comparator C1 or C2 negative input.
P1C — CMOS PWM output.
RC4/C2OUT/P1B RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Comparator C2 output.
P1B — CMOS PWM output.
RC5/CCP1/P1A RC5 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare input.
P1A ST CMOS PWM output.
RC6/AN8 RC6 ST CMOS General purpose I/O.
AN8 AN — A/D Channel 8 input.
RC7/AN9 RC7 ST CMOS General purpose I/O.
AN9 AN — A/D Channel 9 input.
VSS VSS Power — Ground reference.
VDD VDD Power — Positive supply.
TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL = TTL com patible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
PIC16F631/677/685/687/689/690
DS40001262F-page 20 2005-2015 Microchip Technology Inc.
TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689
Name Function Input
Type Output
Type Description
RA0/AN0/C1IN+/ICSPDAT/
ULPWU RA0 TTL CMOS General purpose I/O . Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN0 AN — A/D Channel 0 input.
C1IN+ AN — Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1/AN1/C12IN0-/VREF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN1 AN — A/D Channel 1 input.
C12IN0- AN — Comparator C1 or C2 negative input.
VREF AN — Externa l Voltage Reference for A/D.
ICSPCL K S T — ICSP™ clock.
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN2 AN — A/D Channel 2 input.
T0CKI ST — Timer0 clock input.
INT S T — Ex te r nal Int e rru p t .
C1OUT — CMOS Comparator C1 output.
RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled
interrupt-on-change.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN3 AN — A/D Channel 3 input.
T1G ST — Timer1 gate input.
OSC2 — XTAL Crystal/Resonator.
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN S T — External clock input/RC oscillator connection.
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN10 AN — A/D Channel 10 input.
SDI ST — SPI data input.
SDA ST OD I2C™ data input/output.
RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN11 AN — A/D Channel 11 input.
RX S T — EUSART asynchronous input.
DT ST CMOS EUSART synchronous data.
Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
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PIC16F631/677/685/687/689/690
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt -on-
change. Individually enabled pull-up.
SCK ST CMOS SP I clock .
SCL ST OD I2C™ clock.
RB7/TX/CK RB7 TTL CMOS General purpose I/O. Individually controlled interrupt -on-
change. Individually enabled pull-up.
TX — CMOS EUSART asynch ronous output.
CK S T CMOS EUSART synchronous clock.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
C2IN+ AN — Comparator C2 positive input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN — A/D Channel 5 input.
C12IN1- AN — Comparator C1 or C2 negative input.
RC2/AN6/C12IN2- RC2 ST CMOS General purpose I/O.
AN6 AN — A/D Channel 6 input.
C12IN2- AN — Comparator C1 or C2 negative input.
RC3/AN7/C12IN3- RC3 ST CMOS General purpose I/O.
AN7 AN — A/D Channel 7 input.
C12IN3- AN — Comparator C1 or C2 negative input.
RC4/C2OUT RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Comparator C2 output.
RC5 RC5 ST CMOS General purpose I/O.
RC6/AN8/SS RC6 ST CMOS General purpose I/O.
AN8 AN — A/D Channel 8 input.
SS ST — Slave Select input.
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
AN9 AN — A/D Channel 9 input.
SDO — CMOS SPI data output.
VSS VSS Power — Ground reference.
VDD VDD Power — Positive supply.
TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain
TTL = TTL com patible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
PIC16F631/677/685/687/689/690
DS40001262F-page 22 2005-2015 Microchip Technology Inc.
TABLE 1-5: PINOUT DESCRIPTION – PIC16F690
Name Function Input
Type Output
Type Description
RA0/AN0/C1IN+/ICSPDAT/
ULPWU RA0 TTL CMOS General purpose I/O . Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN0 AN — A/D Channel 0 input.
C1IN+ AN — Comparator C1 positive input.
ICSPDAT TTL CMOS ICSP™ Data I/O.
ULPWU AN — Ultra Low-Power Wake-up input.
RA1/AN1/C12IN0-/VREF/ICSPCLK RA1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN1 AN — A/D Channel 1 input.
C12IN0- AN — Comparator C1 or C2 negative input.
VREF AN — Externa l Voltage Reference for A/D.
ICSPCL K S T — ICSP™ clock.
RA2/AN2/T0CKI/INT/C1OUT RA2 ST CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN2 AN — A/D Channel 2 input.
T0CKI ST — Timer0 clock input.
INT S T — Ex te r n al inter rupt.
C1OUT — CMOS Comparator C1 output.
RA3/MCLR/VPP RA3 TTL — General purpose input. Individually controlled interrupt-on-
change.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
RA4/AN3/T1G/OSC2/CLKOUT RA4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN3 AN — A/D Channel 3 input.
T1G ST — Timer1 gate input.
OSC2 — XTAL Crystal/Resonator.
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI/OSC1/CLKIN RA5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
T1CKI ST — Timer1 clock input.
OSC1 XTAL — Crystal/Resonator.
CLKIN S T — External clock input/RC oscillator connection.
RB4/AN10/SDI/SDA RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN10 AN — A/D Channel 10 input.
SDI ST — SPI data input.
SDA ST OD I2C™ data input/output.
RB5/AN11/RX/DT RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up.
AN11 AN — A/D Channel 11 input.
RX S T — EUSART asynchronous input.
DT ST CMOS EUSART synchronous data.
Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain
TTL = TTL compatible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
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PIC16F631/677/685/687/689/690
RB6/SCK/SCL RB6 TTL CMOS General purpose I/O. Individually controlled interrupt -on-
change. Individually enabled pull-up.
SCK ST CMOS SP I clock .
SCL ST OD I2C™ clock.
RB7/TX/CK RB7 TTL CMOS General purpose I/O. Individually controlled interrupt -on-
change. Individually enabled pull-up.
TX — CMOS EUSART asynch ronous output.
CK S T CMOS EUSART synchronous clock.
RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O.
AN4 AN — A/D Channel 4 input.
C2IN+ AN — Comparator C2 positive input.
RC1/AN5/C12IN1- RC1 ST CMOS General purpose I/O.
AN5 AN — A/D Channel 5 input.
C12IN1- AN — Comparator C1 or C2 negative input.
RC2/AN6/C12IN2-/P1D RC2 ST CMOS General purpose I/O.
AN6 AN — A/D Channel 6 input.
C12IN2- AN — Comparator C1 or C2 negative input.
P1D — CMOS PWM output.
RC3/AN7/C12IN3-/P1C RC3 ST CMOS General purpose I/O.
AN7 AN — A/D Channel 7 input.
C12IN3- AN — Comparator C1 or C2 negative input.
P1C — CMOS PWM output.
RC4/C2OUT/P1B RC4 ST CMOS General purpose I/O.
C2OUT — CMOS Comparator C2 output.
P1B — CMOS PWM output.
RC5/CCP1/P1A RC5 ST CMOS General purpose I/O.
CCP1 ST CMOS Capture/Compare input.
P1A ST CMOS PWM output.
RC6/AN8/SS RC6 ST CMOS General purpose I/O.
AN8 AN — A/D Channel 8 input.
SS ST — Slave Select input.
RC7/AN9/SDO RC7 ST CMOS General purpose I/O.
AN9 AN — A/D Channel 9 input.
SDO — CMOS SPI data output.
VSS VSS Power — Ground reference.
VDD VDD Power — Positive supply.
TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS=CMOS compatible input or outputOD= Open Drain
TTL = TTL com patible input ST= Schmitt Trigger input with CMOS levels
HV = High Voltage XTA L= Crystal
PIC16F631/677/685/687/689/690
DS40001262F-page 24 2005-2015 Microchip Technology Inc.
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC16F631/677/685/687/689/690 has a 13-bit
program counter capable of addressing an 8K x 14
program m em ory space. Onl y th e fi rst 1 K x 14 (0000h-
03FFh) is physically implemented for the PIC16F631,
the first 2K x 14 (0000h-07FFh) for the PIC16F677/
PIC16F687, and the first 4K x 14 (0000h-0FFFh) for
the PIC16F685/PIC16F689/PIC16F690. Accessing a
location above these boundaries will cause a wrap-
around. The Reset vector is at 0000h and the interrupt
vector is at 0004h (see Figures 2-1 through 2-3).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F631
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F685/689/690
FIGURE 2-3: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F677/PIC16F687
PC<12:0>
13
0000h
0004h
0400h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Access 0-3FFh
0005h
03FFh
Page 0
On-Chip
Memory
PC<12:0>
13
0000h
0004h
1000h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Access 0-FFFh
0005h
07FFh
0800h
Page 0
Page 1 0FFFh
On-Chip
Program
Memory
PC<12:0>
13
0000h
0004h
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Access 0-7FFh
0005h
07FFh
Page 0
On-Chip
Memory
2005-2015 Microchip Technology Inc. DS40001262F-page 25
PIC16F631/677/685/687/689/690
2.2 Dat a Memory Organizat ion
The data memory (see Figures 2-6 through 2-8) is
partitioned into four banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). The Special Function Registers are
located in the first 32 locations of each bank. The
General Purpose Registers, implemented as static
RAM, are loca ted in the l ast 96 locat ions o f ea ch Bank .
Register locations F0h-FFh in Bank 1, 170h-17Fh in
Bank 2 and 1F0h-1FFh in Bank 3 point to addresses
70h-7Fh in Bank 0. The actual number of General
Purpose Resisters (GPR) in each Bank depends on the
device. Details are shown in Figures 2-4 through 2-8.
All other RAM is unimplemented and returns ‘0’ when
read. RP<1:0> of the STATUS register are the bank
select bits:
RP1 RP0
00Bank 0 is selected
01Bank 1 is selected
10Bank 2 is selected
11Bank 3 is selected
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 128 x 8 in the
PIC16F687 and 256 x 8 in the PIC16F685/PIC16F689/
PIC16F690. Each register is accessed, either directly or
indirectly, through the File Select Register (FSR) (see
Section 2.4 “Indirect Addressing, INDF and FSR
Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1
through 2-4). These regist e rs are st atic RA M.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
assoc iated with th e “core” are described in this sec tion.
Registers related to the operation of peripheral features
are describ ed in the section of that periphe ral feature.
PIC16F631/677/685/687/689/690
DS40001262F-page 26 2005-2015 Microchip Technology Inc.
FIGURE 2-4: PIC16F631 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
11h 91h 111h 191h
12h 92h 112h 192h
13h 93h 113h 193h
14h 94h 114h 194h
15h WPUA 95h WPUB 115h 195h
16h IOCA 96h IOCB 116h 196h
17h WDTCON 97h 117h 197h
18h 98h VRCON 118h 198h
19h 99h CM1CON0 119h 199h
1Ah 9Ah CM2CON0 11Ah 19Ah
1Bh 9Bh CM2CON1 11Bh 19Bh
1Ch 9Ch 11Ch 19Ch
1Dh 9Dh 11Dh 19Dh
1Eh 9Eh ANSEL 11Eh SRCON 19Eh
1Fh 9Fh 11Fh 19Fh
20h
3Fh
A0h 120h 1A0h
General
Purpose
Registers
64 Bytes
40h
6Fh EFh 16Fh 1EFh
70h accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2005-2015 Microchip Technology Inc. DS40001262F-page 27
PIC16F631/677/685/687/689/690
FIGURE 2-5: PIC16F677 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh 10Fh 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
11h 91h 111h 191h
12h 92h 112h 192h
SSPBUF 13h SSPADD(2) 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
15h WPUA 95h WPUB 115h 195h
16h IOCA 96h IOCB 116h 196h
17h WDTCON 97h 117h 197h
18h 98h VRCON 118h 198h
19h 99h CM1CON0 119h 199h
1Ah 9Ah CM2CON0 11Ah 19Ah
1Bh 9Bh CM2CON1 11Bh 19Bh
1Ch 9Ch 11Ch 19Ch
1Dh 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh
ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh
General
Purpose
Register
96 Bytes
20h General
Purpose
Register
32 Bytes
A0h
BFh
120h 1A0h
C0h
EFh 16Fh 1EFh
accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.
See Registers 13-2 and 13-3 for more details.
PIC16F631/677/685/687/689/690
DS40001262F-page 28 2005-2015 Microchip Technology Inc.
FIGURE 2-6: PIC16F685 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
TMR2 11h 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
13h 93h 113h 193h
14h 94h 114h 194h
CCPR1L 15h WPUA 95h WPUB 115h 195h
CCPR1H 16h IOCA 96h IOCB 116h 196h
CCP1CON 17h WDTCON 97h 117h 197h
18h 98h VRCON 118h 198h
19h 99h CM1CON0 119h 199h
1Ah 9Ah CM2CON0 11Ah 19Ah
1Bh 9Bh CM2CON1 11Bh 19Bh
PWM1CON 1Ch 9Ch 11Ch 19Ch
ECCPAS 1Dh 9Dh 11Dh PSTRCON 19Dh
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh
ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh
General
Purpose
Register
96 Bytes
20h
General
Purpose
Register
80 Bytes
A0h
General
Purpose
Register
80 Bytes
120h 1A0h
EFh 16Fh
accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2005-2015 Microchip Technology Inc. DS40001262F-page 29
PIC16F631/677/685/687/689/690
FIGURE 2-7: PIC16F687/PIC16F689 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH(3) 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH(3) 10Fh 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
11h 91h 111h 191h
12h 92h 112h 192h
SSPBUF 13h SSPADD(2) 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
15h WPUA 95h WPUB 115h 195h
16h IOCA 96h IOCB 116h 196h
17h WDTCON 97h 117h 197h
RCSTA 18h TXSTA 98h VRCON 118h 198h
TXREG 19h SPBRG 99h CM1CON0 119h 199h
RCREG 1Ah SPBRGH 9Ah CM2CON0 11Ah 19Ah
1Bh BAUDCTL 9Bh CM2CON1 11Bh 19Bh
1Ch 9Ch 11Ch 19Ch
1Dh 9Dh 11Dh 19Dh
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh
ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh
General
Purpose
Register
96 Bytes
20h General
Purpose
Register
32 Bytes
A0h
BFh
General
Purpose
Register
80 Bytes
(PIC16F689
only)
120h 1A0h
48 Bytes
(PIC16F689
only)
C0h
EFh
accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0Bank 1Bank 2Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.
See R egister s 13-2 and 13-3 for more details.
3: PIC16F689 only.
PIC16F631/677/685/687/689/690
DS40001262F-page 30 2005-2015 Microchip Technology Inc.
FIGURE 2-8: PIC16F690 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h PORTA 105h TRISA 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h PORTC 107h TRISC 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDAT 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADR 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh
T1CON 10h OSCTUNE 90h 110h 190h
TMR2 11h 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD(2) 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h WPUA 95h WPUB 115h 195h
CCPR1H 16h IOCA 96h IOCB 116h 196h
CCP1CON 17h WDTCON 97h 117h 197h
RCSTA 18h TXSTA 98h VRCON 118h 198h
TXREG 19h SPBRG 99h CM1CON0 119h 199h
RCREG 1Ah SPBRGH 9Ah CM2CON0 11Ah 19Ah
1Bh BAUDCTL 9Bh CM2CON1 11Bh 19Bh
PWM1CON 1Ch 9Ch 11Ch 19Ch
ECCPAS 1Dh 9Dh 11Dh PSTRCON 19Dh
ADRESH 1Eh ADRESL 9Eh ANSEL 11Eh SRCON 19Eh
ADCON0 1Fh ADCON1 9Fh ANSELH 11Fh 19Fh
General
Purpose
Register
96 Bytes
20h
General
Purpose
Register
80 Bytes
A0h
General
Purpose
Register
80 Bytes
120h 1A0h
EFh 16Fh
accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.
See Registe rs 13-2 and 13-3 for more details.
2005-2015 Microchip Technology Inc. DS40001262F-page 31
PIC16F631/677/685/687/689/690
TABLE 2-1: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
01h TMR0 Timer0 Module Register xxxx xxxx 79,200
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
03h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 35,200
04h F SR Indirect Data Memory Address Pointer xxxx xxxx 43,200
05h PORTA(7) —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 57,200
06h PORTB(7) RB7 RB6 RB5 RB4 — — — — xxxx ---- 67,200
07h PORTC(7) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 74,200
08h —Unimplemented — —
09h —Unimplemented — —
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 43,200
0Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 37,200
0Ch PIR1 —ADIF
(4) RCIF(2) TXIF(2) SSPIF(5) CCP1IF(3) TMR2IF(3) TMR1IF -000 0000 40,200
0Dh PIR2 OSFIF C2IF C1IF EEIF — — — — 0000 ---- 41,200
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 85,200
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 85,200
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 87,200
11h TMR2(3) Timer2 Module Register 0000 0000 89,200
12h T2CON(3) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 90,200
13h SSPBUF(5) Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 178,200
14h SSPCON(5, 6) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 177,200
15h CCPR1L(3) Cap tur e/C o mpare /P WM Regi st er 1 (LS B) xxxx xxxx 126,200
16h CCPR1H(3) Capture/C o mpare /P WM R egist er 1 (MS B) xxxx xxxx 126,200
17h CCP1CON(3) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 125,200
18h RCSTA(2) SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 158,200
19h TXREG(2) EUSAR T Transmit Data Register 0000 0000 150
1Ah RCREG(2) EUSART Receive Data Register 0000 0000 155
1Bh —Unimplemented — —
1Ch PWM1CON(3) PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 143,200
1Dh ECCPAS(3) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 140,200
1Eh ADRESH(4) A/D Result Register High Byte xxxx xxxx 113,200
1Fh ADCON0(4) ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 111,200
Legend: – = Unimplem ented locatio ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F687/PIC16F689/PIC16F690 only.
3: PIC16F68 5/PIC16F690 only.
4: PIC16F6 77 / PIC 16F 68 5/PIC 1 6F 68 7/P IC1 6F 689 /P IC16 F6 90 only.
5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
6: When SSPCON register b its SS PM<3:0> = 1001, any reads or writes to the SSP ADD SFR address are accessed through the SSPMSK
register. See Registers 13-2 and 13-3 for more detail.
7: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
PIC16F631/677/685/687/689/690
DS40001262F-page 32 2005-2015 Microchip Technology Inc.
TABLE 2-2: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
81h OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 36,200
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 35,200
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200
85h TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 57,200
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 68,201
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 74,200
88h —Unimplemented — —
89h —Unimplemented — —
8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200
8Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 37,200
8Ch PIE1 —ADIE
(4) RCIE(2) TXIE(2) SSPIE(5) CCP1IE(3) TMR2IE(3) TMR1IE -000 0000 38,201
8Dh PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 39,201
8Eh PCON —— ULPWUE SBOREN ——PORBOR --01 --qq 42,201
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 46,201
90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 50,201
91h —Unimplemented — —
92h PR2(3) Timer2 Pe riod Registe r 1111 1111 89,201
93h SSPADD(5, 7) Synchronous Serial Port (I2C mode) Address Register 0000 0000 184,201
93h SSPMSK(5, 7) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 187,201
94h SSPSTAT(5) SMP CKE D/A PSR/WUA BF 0000 0000 176,201
95h WPUA(6) ——WPUA5WPUA4— WPUA2 WPUA1 WPUA0 --11 -111 60,201
96h IOCA —— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 60,201
97h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 208,201
98h TXSTA(2) CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 157,201
99h SPBRG(2) BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 160,201
9Ah SPBRGH(2) BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 160,201
9Bh BAUDCTL(2) ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 159,201
9Ch —Unimplemented — —
9Dh —Unimplemented — —
9Eh ADRESL(4) A/D Result Register Low Byte xxxx xxxx 113,201
9Fh ADCON1(4) — ADCS2 ADCS1 ADCS0 — — — — -000 ---- 112,201
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F687/PIC16F689/PIC16F690 only.
3: PIC16F685/PIC16F690 only.
4: PIC16F6 77/PIC16F 68 5/P IC1 6F 687 /P IC1 6F6 89/PIC16 F6 90 onl y.
5: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
6: RA3 pull-up is enabled when pin is configured as MCLR in Configuration W ord .
7: Accessible only when SSPCON register bits SSPM<3:0> = 1001.
2005-2015 Microchip Technology Inc. DS40001262F-page 33
PIC16F631/677/685/687/689/690
TABLE 2-3: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
101h TMR0 Timer0 Module Register xxxx xxxx 79,200
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
103h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 35,200
104h FSR Indirect Data Memo ry Address Pointe r xxxx xxxx 43,200
105h PORTA(4) —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 57,200
106h PORTB(4) RB7 RB6 RB5 RB4 — — — — xxxx ---- 67,200
107h PORTC(4) RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 74,200
108h —Unimplemented — —
109h —Unimplemented — —
10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200
10Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 37,200
10Ch EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 118,201
10Dh EEADR EEADR7(3) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 118,201
10Eh EEDATH(2) — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 118,201
10Fh EEADRH(2) — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 118,201
110h —Unimplemented — —
111h —Unimplemented — —
112h —Unimplemented — —
113h —Unimplemented — —
114h —Unimplemented — —
115h WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 68,201
116h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 68,201
117h —Unimplemented — —
118h VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 103,201
119h CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 96,201
11Ah CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 97,201
11Bh CM2CON1 MC1OUT MC2OUT ———— T1GSS C2SYNC 00-- --10 99,201
11Ch —Unimplemented — —
11Dh —Unimplemented — —
11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3(3) ANS2(3) ANS1 ANS0 1111 1111 59,201
11Fh ANSELH(3) — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 113,201
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown , q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F685/PIC16F689/PIC16F690 only.
3: PIC16F6 77 / PIC 16F 68 5/PIC 1 6F 68 7/P IC1 6F 689 /P IC16 F6 90 only.
4: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
PIC16F631/677/685/687/689/690
DS40001262F-page 34 2005-2015 Microchip Technology Inc.
TABLE 2-4: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
181h OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 36,200
182h PCL P ro gr am Coun ter’s (PC) Least Significa nt Byte 0000 0000 43,200
183h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 35,200
184h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200
185h TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 57,200
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 68,201
187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 74,201
188h —Unimplemented — —
189h —Unimplemented — —
18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200
18Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF(1) 0000 000x 37,200
18Ch EECON1 EEPGD(2) — — — WRERR WREN WR RD x--- x000 119,201
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 117,201
18Eh —Unimplemented — —
18Fh —Unimplemented — —
190h —Unimplemented — —
191h —Unimplemented — —
192h —Unimplemented — —
193h —Unimplemented — —
194h —Unimplemented — —
195h —Unimplemented — —
196h —Unimplemented — —
197h —Unimplemented — —
198h —Unimplemented — —
199h —Unimplemented — —
19Ah —Unimplemented — —
19Bh —Unimplemented — —
19Ch —Unimplemented — —
19Dh PSTRCON(2) — — — STRSYNC STRD STRC STRB STRA ---0 0001 144,201
19Eh SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 101,201
19Fh —Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F685/PIC16F690 only.
2005-2015 Microchip Technology Inc. DS40001262F-page 35
PIC16F631/677/685/687/689/690
2.2.2.1 STATUS Register
The S TATUS re gi ste r, show n i n Register 2-1, co ntains :
• the arit hmetic status of the A LU
• the Reset status
• the bank select bits for data memory (GPR and
SFR)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For exam ple, CLRF STATUS, will clear the uppe r three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Sta tus b it s , s ee Se ction 15.0 “Instruction Set
Summary”
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS: STATUS REGIST ER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Se lect bit (used for in dire ct addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After po wer-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rot ate (RRF, RLF) instructi ons, this bit is loaded with either the high-orde r or low-o rder
bit of the source register.
PIC16F631/677/685/687/689/690
DS40001262F-page 36 2005-2015 Microchip Technology Inc.
2.2.2.2 OPTION Register
The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:
• Timer0/WDT prescaler
• Extern al R A2/INT interrup t
•Timer0
• Weak pull-ups on PORTA/PORTB
Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit of t he OP T IO N r eg i ste r
to ‘1’. See Section 6.3 “Timer1 Pres-
caler”.
REGISTER 2-2: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RABPU: PORTA/PORTB Pull-up Enable bit
1 = PORTA/PORTB pull-ups are disabled
0 = PORTA/PORTB pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/INT pin
0 = Interrupt on falling edge of RA2/INT pin
bit 5 T0CS: Timer0 Cloc k Source Select bit
1 = Transit ion on RA2/ T0CKI pin
0 = Internal instr uction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/ T0CKI pin
0 = Increment on low-to-high transition on RA2/T0CKI pin
bit 3 PSA: Prescaler Assig nm ent bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
2005-2015 Microchip Technology Inc. DS40001262F-page 37
PIC16F631/677/685/687/689/690
2.2.2.3 INTCON Register
The INTCON register, shown in Register 2-3, is a
readable and writable register , which contains the various
enable and flag bits for TMR0 register overflow, PORTA
change and external RA2/AN2/T0CKI/INT/C1OUT pin
interrupts.
Note: Interru pt flag bit s are set w hen an interr upt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RABIE(1,3) T0IF(2) INTF RABIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: T imer0 Ov erfl ow Interru pt Enab le bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3 RABIE: PORTA/PORTB Change Interrupt Enable bit(1,3)
1 = Enables the PORTA/PORTB change interrupt
0 = Disables the PORTA/PORTB change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = TM R0 register ha s overflowed (must be cleared i n software)
0 = TM R0 register did not over flow
bit 1 INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0 RABIF: PORTA/PORTB Change Interrupt Flag bit
1 = When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be
cleared in software)
0 = None of the PORTA or PORTB general purpose I/O pins have changed state
Note 1: IOCA or IOCB register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
3: Includes ULPWU interrupt.
PIC16F631/677/685/687/689/690
DS40001262F-page 38 2005-2015 Microchip Technology Inc.
2.2.2.4 PIE1 Regist er
The PIE1 regis te r con t ai ns th e in terrupt enable bi t s, a s
shown in Register 2-4.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE(5) RCIE(3) TXIE(3) SSPIE(4) CCP1IE(2) TMR2IE(1) TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit(5)
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit(3)
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit(5)
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit(4)
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit(2)
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1)
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note 1: PIC16F685/PIC16F690 only.
2: PIC16F685/PIC16F689/PIC16F690 only.
3: PIC16F687/PIC16F689/PIC16F690 only.
4: PIC16F6 77/PIC16F 687/PIC16F689/PIC16F6 90 onl y.
5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
2005-2015 Microchip Technology Inc. DS40001262F-page 39
PIC16F631/677/685/687/689/690
2.2.2.5 PIE2 Register
The PIE2 regis te r con t ai ns th e in terrupt enable bi t s, a s
shown in Register 2-5.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
OSFIE C2IE C1IE EEIE — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
bit 4 EEIE: EE Write Operation Interrupt Enable bit
1 = Enables write operation interrupt
0 = Disables write ope rati on inte rrupt
bit 3-0 Unimplemented: Read as ‘0’
PIC16F631/677/685/687/689/690
DS40001262F-page 40 2005-2015 Microchip Technology Inc.
2.2.2.6 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.
Note: Interru pt flag bit s are set when an interr upt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User sof tware sh ould ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIF(5) RCIF(3) TXIF(3) SSPIF(4) CCP1IF(2) TMR2IF(1) TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit(5)
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: EUSART Receive Interrupt Flag bit(3)
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
bit 4 TXIF: EUSART Transmit Interrupt Flag bit(3)
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit(4)
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit(2)
Capture mode:
1 = A TMR1 register c apture occurred (must be cleared in soft ware)
0 = No TMR1 register capture oc curred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit(1)
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
Note 1: PIC16F685/PIC16F690 only.
2: PIC16F685/PIC16F689/PIC16F690 only.
3: PIC16F687/PIC16F689/PIC16F690 only.
4: PIC16F6 77/PIC16F 687/PIC16F689/PIC16F6 90 onl y.
5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
2005-2015 Microchip Technology Inc. DS40001262F-page 41
PIC16F631/677/685/687/689/690
2.2.2.7 PIR2 Register
The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.
Note: Interru pt flag bit s are set w hen an interr upt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User sof tware sh ould ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
OSFIF C2IF C1IF EEIF — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 4 EEIF: EE Write Operation Inter rupt Flag bit
1 = Write operation completed (must be cleared in software)
0 = Write operation has not completed or has not started
bit 3-0 Unimplemented: Read as ‘0’
PIC16F631/677/685/687/689/690
DS40001262F-page 42 2005-2015 Microchip Technology Inc.
2.2.2.8 PCON Regist er
The Power Control (PCON) register (see Register 2-8)
cont ains flag bits to differentia te betw e en a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOR.
REGISTER 2-8: PCON: POWER CONTROL REGISTER
U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x
—— ULPWUE SBOREN(1) ——PORBOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 ULPWUE: Ultra Low-Power Wake-up Enable bit
1 = Ultra Low-Power Wa ke-up enabled
0 = Ultra Low-Power Wake-up disabled
bit 4 SBOREN: Software BOR Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 3-2 Unimplemented: Read as ‘0’
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
2005-2015 Microchip Technology Inc. DS40001262F-page 43
PIC16F631/677/685/687/689/690
2.3 PCL and PCLATH
The Program Counte r (PC) is 13 bit s wide. The lo w byte
comes from the PCL register, which is a readable and
writable register . The hig h byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-9 shows the two
situ at i o ns fo r t he l o ad i n g of t h e PC . T he u p per e x am pl e
in Figure 2-9 shows how the PC is loaded on a write to
PCL (PCLATH<4:0> PCH). The lower example in
Figure 2-9 sho ws how the PC is loaded during a CALL or
GOTO instructi on (PC L ATH<4 :3> PCH).
FIGURE 2-9: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
content s of th e PCLATH register. This allo ws the enti re
contents of the program counter to be changed by
writing the desired upper five bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 13 bits of the program counter will
change to the values conta ined in the PCLATH register
and those being written to the PCL register.
A comput ed GOTO is a ccom pli shed by addi ng a n offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instru ction s or if the low er eight bit s of the memo ry
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2.3.2 STACK
The PIC16F631/677/685/687/689/690 devices have an
8-level x 13-bit wide hardware stack (see Figures 2-2
and 2-3). The stac k space is not part of eit her program
or data space and the Stack Pointer is not readable or
writable. The PC is PUSHed onto the stack when a
CALL instruction is executed or an interrupt causes a
branch. The stack is POPed i n the e vent of a RETURN,
RETLW or a RETFIE inst ructio n executi on. PC LATH is
not affected by a PUSH or POP operation.
The st ack operates as a circular buf fer . This means th at
af ter the st ack ha s be en PUSHed ei ght time s, th e nin th
push ove rwr ites the va lu e that was s tored fro m the firs t
push. The tenth p us h overw ri t es the seco nd p us h (an d
so on).
2.4 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physica l register . Addr essing
the INDF register w ill cause indirect addressing.
Indirect addressing is possible by using the INDF
register . Any instruction using the INDF register actually
accesses data pointed to by the File Select Register
(FSR) . Reading INDF itself in directly w ill produc e 00h.
Writing to the INDF register indirectly results in a no
operation (although Status bits may be affected). An
eff ectiv e 9-bi t address is obta ined by concat enatin g the
8-bit FSR and the IRP bit of the STATUS register, as
shown in Figure 2-10.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESS ING
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU Result
GOTO, CALL
OPCODE<10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interr upt add res s.
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
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FIGURE 2-10: DIRECT/INDI RECT ADDRE SS ING PIC16F631/677/685/687/689/690
For memory map detail, see Figures 2-6,2-7 and 2-8.
Data
Memory
Indirect AddressingDirect Addressing
Bank Select Locat ion Select
RP1 RP0 6 0
From Opcode IRP File Select Register
70
Bank Select Location Select
00 01 10 11 180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
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3.0 OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
3.1 Overview
The Oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applicati ons while maximizing perfor-
mance and minimizing power consumption. Figure 3-1
illustrates a block diagram of the Oscillator module.
Clock sources can be configured from external
oscilla tors, quartz crystal resonators , ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two
internal oscillators, with a choice of speeds selectable via
softw are . Add itio nal clo ck feat ures inc lud e:
• Selectable system clock source between external
or inter nal via software.
• Two-Speed Start - up mo de, w hich min im iz es
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
The Os cillator mod ule can be c onfigured in one of eig ht
clock modes.
1. EC – External clock with I/O on O SC2/CLKOU T.
2. LP – 32 kHz Low-Power Crystal mode.
3. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
4. HS – High Gain Crystal or Ceramic Resonator
mode.
5. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
6. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
7. INTOSC – Internal oscillator with FOSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
Clock Source modes are configured by the FOSC<2:0>
bits in the Configuration Word register (CONFIG). The
internal clock can be generated from two internal
oscillators. The HFINTOSC is a calibrated high-
frequenc y osci llator. The L FINT OSC is an un calib rate d
low-frequency oscillator.
FIGURE 3-1: SI MPLI FI ED P IC® MCU CLOCK SOURCE BLOCK DIAGRAM
(CP U and Peripherals)
OSC1
OSC2
Sleep
External Oscillator
LP, XT, HS, RC, RCIO, EC
System Clock
Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
IRCF<2:0>
111
110
101
100
011
010
001
000
31 kHz
Power-up Timer (PWRT)
FOSC<2:0>
(Configuration Word Register)
SCS<0>
(OSCCON Register)
Internal Oscillator
(OSCCON Register)
Watchdog Timer (WDT )
Fail-Safe Clock Monitor (FSCM)
HFINTOSC
8 MHz
LFINTOSC
31 kHz
INTOSC
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3.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 3-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• Frequency Status bits (HTS, LTS)
• System clock control bits (OSTS, SCS)
REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
— IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 =8MHz
110 =4MHz (default)
101 =2MHz
100 =1MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (LFINTOSC)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the clock defined by FOSC<2:0> of the C ONFIG register
0 = Device is running from the internal oscillat or (HFINTOSC or LFINTOSC)
bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINTOSC is stable
0 = LFINT OSC is not st abl e
bit 0 SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the CONFIG register
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
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3.3 Clock Source Modes
Clock Source modes can be classified as external or
internal.
• Extern al C lock m odes re ly on exte rnal c ircuitry fo r
the clock source. Examples are: Oscillator mod-
ules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor- Capac itor (RC) mode circuits.
• Internal clock sources are contained internally
within the Oscillator module. The Oscillator
module has two internal oscillators: the 8 MHz
High-Frequency Internal Oscillator (HFINTOSC)
and the 31 kHz Low- Frequency Internal Os cillator
(LFINTOSC).
The syste m cl oc k can be selected between ex tern al or
internal clock sources via the System Clock Select
(SCS) bit of the OSCCON register. See Section 3.6
“Clock Switching” for additional information.
3.4 External Clock Modes
3.4.1 OSCILLATOR START-UP TIMER (OST)
If the Oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
cryst al res onator o r ce ramic res onator, has started and
is providing a stable system clock to the Oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 3-1.
In order to mi nimize laten cy between externa l oscillator
start-up and code execution, the Two-Speed Clock
S tart -up mode can be s elected (see Section 3.7 “T wo-
Speed Clock Start-up Mode”).
TABLE 3-1: OSCILLATOR DELAY EXAMPLES
3.4.2 EC MO DE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 3-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 3-2: EXTERNAL CLOCK (EC)
MODE OPERATION
Switch From Switch To Frequency Oscillator Delay
Sleep/POR LFINTOSC
HFINTOSC 31 kHz
125 kHz to 8 MHz Oscillator Warm-up Delay (TWARM)
Sleep/POR EC, RC DC – 20 MHz 2 cycles
LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each
Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)
LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 s (approx.)
OSC1/CLKIN
OSC2/CLKOUT(1)
I/O
Clock from
Ext. System PIC® MCU
Note 1: Alternat e pin functions are listed in the
Section 1.0 “Device Overview”.
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3.4.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 3-3). The mo de select s a low ,
medium or high gain setting of the internal inverter-
amplifi er to support vari ous resonator typ es and spee d.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier . LP mode current consumption
is the least of the three mo des. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current c onsumption is the medium of the three mo des.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier . HS mode current consumption
is the highest of the three modes. This mode is best
suited fo r reso nato rs that require a h igh driv e s ettin g.
Figure 3-3 and Figure 3-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
.
FIGURE 3-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 3-4: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
Note 1: Quartz crystal characteristics vary accord-
ing to t ype, p ackage and manuf acturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
2: Always verify osc illato r perform ance over
the VDD and temperature range that is
expected for the application.
3: For oscillator desig n assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Y our Oscillator Work”
(DS00949)
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
C1
C2
Quartz
RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
Crystal
OSC2/CLKOUT
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
C1
C2 Ceramic RS(1)
OSC1/CLKIN
RF(2) Sleep
To Internal
Logic
PIC® MCU
RP(3)
Resonator OSC2/CLKOUT
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3.4.4 EXTERN AL RC MODES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 3-5 shows the
external RC mode connections.
FIGURE 3-5: EXTERNAL RC MODES
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resis tor (REXT) and cap aci tor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packa ging variation s in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
3.5 Internal Cloc k Modes
The Oscillator module has two independent, internal
oscillators that can be configured or selected as the
system clock source .
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
8 MHz. The f requenc y o f t he HFIN T OSC c an b e
user-adjusted via software using the OSCTUNE
register (Register 3-2).
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
The sy stem clock s peed can be selecte d via software
using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
The syste m cl oc k can be select ed betw ee n ext ernal or
inte rnal cloc k sources via the S ystem Clo ck Select ion
(SCS) bit of the OSCCON register. See Section 3.6
“Clock Switching” for more information.
3.5.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the devi ce is pr ogrammed using the o scillato r selectio n
or the FOSC<2:0> bits in the Configuration Word
register (C ONFI G).
In INTOSC mode, O SC1/CLKIN i s available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator fre quency divide d by 4. The CLKO UT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
3.5.2 HFINTOSC
The Hig h-Frequency Int ernal Oscil lator (HFINT OSC) i s
a factory calibrated 8 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 3-2).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). One of seven
frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 3.5.4 “Frequency Select Bits (IRCF)” for
more information.
The HFINTOSC is enabled by selecting any frequency
betwee n 8 MHz and 125 kHz b y set ting th e IRCF <2:0>
bits of the OSCCON register 000. Then, set the
System Clock Source (SCS) bit of the OSCCON
register to ‘1’ or en abl e Two-Speed Start-up by settin g
the IESO bit in the Configuration Word register
(CONFIG) to ‘1’.
The HF Internal Oscillator (HTS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.
OSC2/CLKOUT(1)
CEXT
REXT
PIC® MCU
OSC1/CLKIN
FOSC/4 o r
Internal
Clock
VDD
VSS
Recommended values: 10 k REXT 100 k, <3V
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Alternate pin functions are listed in the
Section 1.0 “Device Overview”.
2: Output depends upon RC or RCIO Clock
mode.
I/O(2)
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3.5.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the OSCTUNE
register (Register 3-2).
The default value of the OSCTUNE register is ‘0’. T he
value is a 5-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. Code execution continues during this shift.
There is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and p eripherals, are not affected by the
change in frequency.
REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximu m frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the factory-calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
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3.5.3 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). Select 31 kHz, via
software, using the IRCF<2:0> bits of the OSCCON
register. See Section 3.5.4 “Frequency Select Bits
(IRCF)” for more inform ation. The LFINTOSC is also the
frequency for the Power-up Timer (PWRT), Watchdog
Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<2:0> bit s of the OSCCON regis ter = 000) as the
system clock source (SCS bit of the OSCCON
register = 1), or when any of the follo wing ar e enable d:
• Two-Speed Star t-up IESO bi t of the Con figuration
Word register = 1 and IRCF<2:0> bit s of the
OSCCON regis ter = 000
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The LF Internal Oscillator (LTS) bit of the OSCCON
register indicates whether the LFINTOSC is stable or
not.
3.5.4 FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 3-1). The Internal Oscillator Frequency
Select bits IRCF<2:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
eight frequencies can be selected via software:
•8 MHz
• 4 MHz (Default after Reset)
•2 MHz
•1 MHz
• 500 kHz
• 250 kHz
• 125 kHz
• 31 kHz (LFINTOSC)
3.5.5 HFINTOSC AND LFINTOSC CLOCK
SWITCH TIMING
When switching between the LFINTOSC and the
HFINTOSC, the new oscillator may already be shut
down to save power (see Figure 3-6). If this is the case,
there is a delay after the IRCF<2:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The LTS and HTS bits of the
OSCCON register will reflect the current active status
of the LFINTOSC and HFINTOSC oscillators. The
timing of a frequency selection is as follows:
1. IRCF<2:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock swit ch circui try waits for a falling e dge of
the cu rrent clock.
4. CLKOUT is held low and the clock switch
circuit ry w ai t s for a rising edg e in t he ne w clo ck .
5. CLKOUT is now connected with the new clock.
LTS and HTS bi ts of the OS CCON regi ster are
updated as require d.
6. Clock swit ch is co mplete.
See Figure 3-1 for more details.
If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
the new frequency is selected. This is because the old
and new frequencies are derived from the HFINTOSC
via the post s ca ler and multiple xe r.
Start-up delay specifications are located in the
oscillator tables of Section 17.0 “Electrical
Specifications”.
Note: Following any Reset, the IRCF<2:0> bits
of the OSCCON register are set to ‘110’
and the frequency selection is set to
4 MHz. The user can modif y the IRCF bi ts
to select a different frequency.
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FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC
LFINTOSC
IRCF <2:0>
System Clock
HFINTOSC
LFINTOSC
IRCF <2:0>
System Clock
00
00
Start-up Time 2-cyc le Sync Running
2-cycle Sync Running
HFINTOSC LFINTOSC (FSCM and WDT disabled)
HFINTOSC LFINTOSC (Either FSCM or WDT enabled)
LFINTOSC
HFINTOSC
IRCF <2:0>
System Clock
= 0¼ 0
Start-up Time 2-cycle Sync Running
LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled
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3.6 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit of the OSCCON
register.
3.6.1 SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• Whe n the SCS bit of the OSCCON register = 0,
the system clock source is determined by
configuration of the FOSC<2:0> bits in the
Conf iguration Word register (CONF IG).
• Whe n the SCS bit of the OSCCON register = 1,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<2:0>
bits of the OSCCON register. After a Reset, the
SCS bit of the OSCCON register is alw ays
cleared.
3.6.2 OSCIL LA TOR START-UP TIME-OU T
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word register (CONFIG), or from the internal clock
source. In particular , OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.
3.7 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 3.4.1 “Oscillator Start-up Timer
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
executi on switches to the external oscillator.
3.7.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Word register) = 1;
Internal/ E xte rnal Switc hov er b it (Two-Speed Sta rt-
up mode enabled).
• SCS (of the OSCCON register) = 0.
• FOSC<2:0> bits in the Configuration Word
register (CONFIG) configured for LP, XT or HS
mode.
Two-Speed Start-up mode is entered after:
• Pow er-on Reset (POR) and, if en abled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Two-
speed S tart-up is disabled. This is because the external
clock oscillator does not require any stabilization time
after POR or an ex it from Sleep.
3.7.2 TWO-SPEED START-UP
SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of th e O SCCON re giste r.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System cloc k held lo w until the next fallin g edg e
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS bit of the OSCCON register. The user
can monitor the OSTS bit of the OSCCON
register to determine the current system
clock sour ce.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
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3.7.3 CHECKIN G TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word register
(CONFIG), or the internal oscillator.
FIGURE 3-7: TWO-SPEED START-UP
0 1 1022 1023
PC + 1
TOSTT
HFINTOSC
OSC1
OSC2
Program Counter
System Clock
PC - N PC
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3.8 Fail-Safe Clock Monitor
The Fail-Saf e Cl oc k Mo nit or (FSC M) al lows the dev ic e
to continue operating sh oul d th e e xte rna l os ci ll ator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word register (CONFIG). The FSCM is
applic abl e to a ll ex ternal Osci lla tor m od es (LP, XT, HS,
EC, RC and RCIO).
FIGURE 3-8: FSCM BLOCK DIAGRAM
3.8.1 FAIL-SAFE DETECTI ON
The FSCM module detects a failed oscillator by
compari ng the extern al osci llat or to the FSCM sa mple
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 3-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock cle ars the latch on each ris ing edge of th e
sample c loc k. A fail ure is d ete cte d w h en an entire half-
cycle of the sample clock elapses before the primary
clock goes low.
3.8.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
devi ce clock to an interna l clock s ource and s ets the b it
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
3.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset,
executing a SLEEP instruction or toggling the SCS bit
of the OSCCON register. Wh e n th e S CS b i t i s t og gl ed ,
the OST is restarted. While the OST is running, the
device co ntinue s to op erate fro m the I NT OSC sele cted
in OSCCON. When the OST times out, the Fail-Safe
condition is cleared and the device will be operating
from the ex ternal cl ock s ource. The Fai l-Saf e condi tion
must be c le ared bef ore th e O SFIF flag can be cle are d.
3.8.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled . Therefore, the device will always be executing
code while the OST is operating.
External
LFINTOSC ÷ 64
S
R
Q
31 kHz
(~32 s) 488 Hz
(~2 ms)
Clock Monitor
Latch
Clock
Failure
Detected
Oscillator
Clock
Q
Sample Clock
Note: Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
the oscillator start-up and that the system
clock switchover has successfully
completed.
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FIGURE 3-9: FSCM TIMING DIAGRAM
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The syste m clock is normally at a m uch higher frequency than the sam ple clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Test Test Test
Clock Monitor Output
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000
OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power -up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word register (Register 14-1) for operation of all register bits.
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4.0 I/O PORTS
There are as many as eighteen general purpose I/O
pins available. Depending on which peripherals are
enabled , some or all of the pins may not be a vailable as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
4.1 PORTA and the TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 4-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables output
driver and puts the contents of the output latch on the
selected pin). The exception is RA3, which is input only
and its TRIS bit will always read as ‘1’. Example 4-1
shows how to initialize PORTA.
Reading the PORTA register (Register 4-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1.
The TRISA register controls the PORTA pin output
drivers, even when they are being used as analog inputs.
The user should ensure the bits in the TRISA register are
maintained set when using them as analog inputs. I/O
pins configured as analog input always read ‘0’.
EXAMPLE 4-1: INITIALIZI NG PORTA
Note: The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
BCF STATUS,RP0;Bank 0
BCF STATUS,RP1;
CLRF PORTA ;Init PORTA
BSF STATUS,RP1;Bank 2
CLRF ANSEL ;digital I/O
BSF STATUS,RP0;Bank 1
BCF STATUS,RP1;
MOVLW 0Ch ;Set RA<3:2> as inputs
MOVWF TRISA ;and set RA<5:4,1:0>
;as outputs
BCF STATUS,RP0;Bank 0
REGISTER 4-1: PORTA: PORTA REGISTER
U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-x R/W-x
—— RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RA<5:0>: PORTA I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 4-2: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
—— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TRISA<5:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TR ISA<3> always reads ‘1’.
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
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4.2 Additional Pin Functions
Every POR T A pin on this device family has an interrupt-
on-change option and a weak pull-up option. RA0 also
has an Ultra Low-Power Wake-up option. The next
three sections describe these functions.
4.2. 1 ANSEL AND ANSEL H REGISTE R S
The ANSEL and ANSELH registers are used to disable
the input buffers of I/O pins, which allow analog voltages
to be applied to those pins without causing excessive
current. Setting the ANSx bit of a corresponding pin will
cause all digi tal rea ds of that pi n to return ‘0’ and als o
permit analog functions of that pin to operate correctly.
The state of the ANSx bit has no effect on the digital
output function of its corresponding pin. A pin with the
TRISx bit clear and ANSx bit set will operate as a digital
output, together with the analog input function of that
pin. Pins with the ANSx bit set always read ‘0’, which
can cause unexpected behavior when executing read
or write oper ations on the port due to the r ead-modify-
write sequence of all such operations.
4.2.2 WEAK PULL-UPS
Each of the PORTA pins, except RA3, has an
individually configurable internal weak pull-up. Control
bits WPUAx enable or disable each pull-up. Refer to
Register 4-4. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the
RABPU bit of the OPTION register. A weak pull-up is
automatically enabled for RA3 when configured as
MCLR and disabled when RA3 is an I/O. There is no
software control of the MCLR pull-up .
4.2.3 INTERRUPT-ON-CHANGE
Each PORTA pin is individually configurable as an
interrupt-on-change pin. Control bits IOCAx enable or
disable the interrupt function for each pin. Refer to
Register 4-6. Th e i nt er r upt - on- c ha n ge is di sa bl e d o n a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
comp ared with the old val ue latch ed on the la st read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d tog ether to set the PO RTA Change Interrupt Flag
bit (RABIF) in the INTCON register (Register 2-6).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by :
a) Any read or write of PORTA. This will end the
mismatch condition, then,
b) Clear the flag bit RABIF.
A mismatch condition will continue to set flag bit RABIF.
Reading PORTA will end the mismatch condition and
allow flag bit RABIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After thes e Res ets, the RABIF f lag w il l cont inue
to be set if a mismatch is present.
Note: If a change on the I/O pin should occur
when the read operation is being exe-
cuted (start of the Q2 cycle), then the
RABIF inter rupt flag may not get set.
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REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANS<7:0>: Analog Select bits
Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
REGISTER 4-4: ANSELH: ANALOG SELECT HIGH REGISTER(2)
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — ANS11 ANS10 ANS9 ANS8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 ANS<11:8>: Analog Select bits
Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
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REGISTER 4-5: WPUA: PORTA REGISTER
U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
—— WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 WPUA<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 WPUA<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RABPU bit of the OPTION register must be en able d for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
REGISTER 4-6: IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IOCA<5:0>: Interrupt-on-change PORTA Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
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4.2.4 ULTRA LOW-POWER WAKE-UP
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows
a slow falling voltage to generate an interrupt-on-change
on RA0 without exces s current c onsum ption. The m ode
is selected by setting the ULPWUE bit of the PCON
register. This enables a small curre nt sink, which can be
used to discharge a cap ac itor on RA0.
Follow these steps to use this feature:
a) Charge the capacitor on RA0 by configuring the
RA0 pin to output (= 1).
b) Configure RA0 as an input.
c) Enable interrupt-on-change for RA0.
d) Set the ULPWUE bit of the PCON register to
begin the capacitor discharge.
e) Execute a SLEEP instruction.
When the v oltage on R A0 drops bel ow VIL, an in terrupt
will be generated which will cause the device to wake-
up and execute the next instruction. If the GIE bit of the
INTCON register is set, the device will then call the
interrupt vector (0004h). See Section 4.4.2 “ Interrupt-
on-change” and Section 14.3.3 “PORTA/PORTB
Interrupt” for more information.
This feature provides a low-power technique for
periodically waking up the device from Sleep. The
time-out is dependent on the discharge time of the RC
circuit on RA0. See Example 4-2 for initializing the
Ultra Low-Power Wake-up module.
A series resistor between RA0 and the external
capacitor provides overcurrent protection for the RA0/
AN0/C1IN+/ICSPDAT/ULPWU pin and can allow for
software calibration of the time-out (see Figure 4-1). A
timer can be used to measure the charge time and
discharge time of the capacitor. The charge time can
then be ad jus t ed to pro vi de th e de si red i nterrupt dela y.
This technique will compensate for the affects of
temperature, voltage and component accuracy. The
Ultra Low-Power Wake-up peripheral can also be
configured as a simple Programmable Low-Voltage
Detect or temperature sensor.
EXAMPLE 4-2: ULTRA LOW-POWER
WAKE-UP INITIALIZATION
Note: For more information, refer to Application
Note AN879, “Using the Microchip Ultra
Low-Pow er Wake -up Module ” (DS00879).
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
BSF PORTA,0 ;Set RA0 data latch
BSF STATUS,RP1 ;Bank 2
BCF ANSEL,0 ;RA0 to digital I/O
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
BCF TRISA,0 ;Output high to
CALL CapDelay ;charge capacitor
BSF PCON,ULPWUE ;Enable ULP Wake-up
BSF IOCA,0 ;Select RA0 IOC
BSF TRISA,0 ;RA0 to input
MOVLW B’10001000’ ;Enable interrupt
MOVWF INTCON ;and clear flag
BCF STATUS,RP0 ;Bank 0
SLEEP ;Wait for IOC
NOP ;
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4.2.5 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORT A pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D Converter (ADC),
refer to the appropriate section in this dat a shee t.
4.2.5.1 RA0/AN0/C1IN+/ICSPDAT/ULPWU
Figure 4-2 shows the diagram for this pin. The RA0/
AN0/C1IN+/ICSPDAT/ULPWU pin is configurable to
function as one of the following:
• a genera l purpo se I/O
• an analog input for the ADC (except PIC16F631)
• an analog input to Comparator C1
• In-Circuit Serial Prog ramming™ data
• an analog input for the Ultra Low-Power Wake-up
FIGURE 4-1: BLOCK DIAGRAM OF RA0
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
RD PORTA
RD
WR
WR
RD
WR
IOCA
RD
IOCA
Interrupt-on-Change
To Comparator
Analog(1)
Input Mode
RABPU
Analog(1)
Input Mode
Q3
WR
RD
01
IULP
WPUA
Data Bus
WPUA
PORTA
TRISA
TRISA
PORTA
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
-
+V
T
ULPWUE
To A/D Converter (2)
VSS
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4.2.5.2 RA1/AN1/C12IN0-/VREF/ICSPCLK
Figure 4-2 shows the diagram for this pin. The RA1/
AN1/C12IN0-/VREF/ICSPCLK pin is configurable to
function as one of the follow ing:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• an analog input to Comparator C1 or C2
• a voltage reference input for the ADC
• In-Circuit Serial Program ming clock
FIGURE 4-2: BLOCK DIAGRAM OF RA1
4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT
Figure 4-3 shows th e diagram fo r this pin. Th e RA2/AN2/
T0CKI /INT /C1OUT pin is con figura ble t o func tion as on e
of t he fo ll ow i ng :
• a genera l purpo se I/O
• an analog input for the ADC (except PIC16F631)
• the clock input for Timer0
• an external edge triggered interrupt
• a di gital output from Comparator C1
FIGURE 4-3: BLOCK DIAGRAM OF RA2
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUA
RD
WPUA
RD PORTA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
Interrupt-on-
To Comparator
Analog(1)
Input Mode
RABPU
Analog(1)
Input Mode
Change
Q3
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
To A/D Converter(2)
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog(1)
Input Mode
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
To A/D Converter(2)
0
1
C1OUT
C1OUT
Enable
To INT
To Timer0
Analog(1)
Input Mode
RABPU
RD PORTA
Interrupt-on-
Change
Q3
Note 1: ANSEL determines Anal og Input mode.
2: Not implemented on PIC16F631.
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4.2.5.4 RA3/MCLR/VPP
Figure 4-4 shows the diagram for this pin. The RA3/
MCLR/VPP pin is con figurable to function as one of the
following:
• a general purpose inpu t
• as Master Clear Reset with weak pull-up
FIGURE 4-4: BLOCK DIAGRAM OF RA3
4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure 4-5 shows the diagram for this pin. The RA4/
AN3/T1G/OSC2/CLKOUT pin is configurable to
function as one of the following:
• a genera l purpo se I/O
• an analog input for the ADC (except PIC16F631)
• a Timer1 gate input
• a crystal/reso na tor con nec tio n
• a cl oc k outpu t
FIGURE 4-5: BLOCK DIAGRAM OF RA4
Input
VSS
D
Q
CK
Q
D
EN
Q
Data Bus
RD PORTA
RD
PORTA
WR
IOCA
RD
IOCA
Reset MCLRE
RD
TRISA VSS
D
EN
Q
MCLRE
VDD
Weak
MCLRE
Interrupt-on-
Change
Pin
Q3
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
FOSC/4
To A/D Converter(4)
Oscillator
Circuit
OSC1
CLKOUT
0
1
CLKOUT
Enable
Enable
Analog(3)
Input Mode
RABPU
RD PORTA
To T1G
INTOSC/
RC/EC(2)
CLK(1)
Modes
CLKOUT
Enable
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
3: ANSEL determines Anal og Input mode.
4: Not implemented on PIC16F631.
Interrupt-on-
Change
Q3
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4.2.5.6 RA5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the diagram for this pin. The RA5/
T1CKI/OSC1/CLKIN pin is configurable to function as
one of the following:
• a general purpose I/O
• a Timer1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 4-6: BLOCK DIAGRAM OF RA5
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
To TMR1 or CLKGEN
INTOSC
Mode
RD PORTA
INTOSC
Mode
RABPU
OSC2
(2)
Note 1:Timer1 LP Oscillator enabled.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
TMR1LPEN(1)
Interrupt-on-
Change
Oscillator
Circuit
Q3
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DS40001262F-page 66 2005-2015 Microchip Technology Inc.
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all ot her
Resets
ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
IOCA —— IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000
OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
TRISA —— TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
WPUA —— WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 --11 -111 --11 -111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shad ed cells are not used by PORTA.
2005-2015 Microchip Technology Inc. DS40001262F-page 67
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4.3 PORTB and TRISB Registers
PORTB is a 4-bit wide, bidirectional port. The
correspon ding dat a direct ion regist er is TRISB (Register
4-6). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clea ring a TRI SB bi t (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 4-3 shows how to initialize PORTB. Reading
the PORTB register (Register 4-5) reads the status of the
pins, whe reas wri ting to it will wri te to the POR T latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value i s modified a nd then wr itten to the PORT
data l atc h.
The TRISB register controls the PORTB pin output
drivers, even when they are being used as analog inputs.
The user should ensure the bits in the TRISB register are
maintained set when using them as analog inputs. I/O
pins configured as analog input always read ‘0’.
EXAMPLE 4-3: INITIALIZING PORTB
4.4 Additional PORTB Pin Functions
PORT B pins RB<7 :4> on the device family device have
an interrupt-on-change option and a weak pull-up
option. The following three sections describe these
PORTB pin functions.
4.4.1 WEAK PULL-UPS
Each of the POR TB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:4> enable or
disable each pull-up (see Register 4-9). Each weak
pull up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RABPU bit of the OPTION
register.
4.4.2 INTERRUPT-ON-CHANGE
Four of the POR TB pins are individually configurable as
an interrupt-on-change pin. Control bits IOCB<7:4>
enable or disable the interrupt function for each pin.
Refer to Register 4-10. The interrupt-on-change feature
is disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present
value is comp ared with the ol d value latche d on the last
read of PORTB to determine which bits have changed
or mismatch the old value. The ‘mismatch’ outputs are
OR’d together to set the PORTB Change Interrupt flag
bit (RABIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the inte rrupt by:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear the flag bit RABIF.
A mismatch condi tion will cont inue to set f lag b it RAB IF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RABIF to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Re set. After these Resets, the RABIF flag will
continue to be set if a mismatch is present.
Note: The ANSELH register must be initialized
to conf igure an analo g channel as a di gital
input. Pins configured as analog inputs
will read ‘0’.
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTB ;Init PORTB
BSF STATUS,RP0 ;Bank 1
MOVLW FFh ;Set RB<7:4> as inputs
MOVWF TRISB ;
BCF STATUS,RP0 ;Bank 0
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set. Fur thermore,
since a read or write on a port affects all bits
of that port, care must be taken when using
multiple pi ns in Interrupt- on-Change mode.
Changes on one pin may not be seen while
servicing changes on another pin.
REGISTER 4-7: PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 RB<7:4>: PORTB I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 3-0 Unimplemented: Read as ‘0’
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DS40001262F-page 68 2005-2015 Microchip Technology Inc.
REGISTER 4-8: TRISB: PORTB TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
TRISB7 TRISB6 TRISB5 TRISB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 TRISB<7:4>: PORTB Tri-State Control bit
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0 Unimplemented: Read as ‘0’
REGISTER 4-9: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
WPUB7 WPUB6 WPUB5 WPUB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 WPUB<7:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0 Unimplemented: Read as ‘0’
Note 1: Global RABPU bit of the OPTION register must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISB<7:4> = 0).
REGISTER 4-10: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
IOCB7 IOCB6 IOCB5 IOCB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 IOCB<7:4>: Interrupt-on-Change PORTB Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 3-0 Unimplemented: Read as ‘0’
2005-2015 Microchip Technology Inc. DS40001262F-page 69
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4.4.3 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I2C™ or interrupts, refer to the
appropriate section in this data sheet.
4.4.3.1 RB4/AN10/SDI/SDA
Figure 4-7 shows the diagram for this pin. The RB4/
AN10/SDI/SDA(1) pi n is configu rable to funct ion as one
of the follow ing:
• a genera l purpo se I/O
• an analog input for the ADC (except PIC16F631)
• a SPI data I/O
•an I
2C data I/O
FIGURE 4-7: BLOCK DIAGRAM OF RB4
Note 1: SDI and SDA are available on
PIC16F677/PIC16F687/PIC16F689/
PIC16F690 only.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
To SSPSR
Analog(1)
Input Mode
RABPU
Analog(1)
Input Mode
Change
Q3
To A/D Converter(2)
ST
SSPEN
0
1
1
0
Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690
only.
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PIC16F631.
0
1
1
0
SSPSR
From
SSP
PIC16F631/677/685/687/689/690
DS40001262F-page 70 2005-2015 Microchip Technology Inc.
4.4.3.2 RB5/AN11/RX/DT(1, 2)
Figure 4-8 shows the diagram for this pin. The RB5/
AN11/RX/DT pin is configurable to function as one of
the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• an asynchronous serial input
• a synchronous serial data I/O
FIGURE 4-8: BLOCK DIAGRAM OF RB5
Note 1: RX an d DT are av ail abl e on P IC16 F68 7/
PIC16F689/PIC16F690 only.
2: AN11 is not i mp lem en ted o n PIC1 6F6 31.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
To EUSART RX/DT
Analog(1)
Input Mode
RABPU
Analog(1)
Input Mode
Change
Q3
To A/D Converter(2)
SYNC
ST
EUSART
DT
SPEN
Available on PIC16F687/PIC16F689/PIC16F690 only.
Note 1: ANSEL determines Analog Input mode.
2: Not impl emented on PIC16F631.
0
1
1
0
0
1
1
0
From
EUSART
2005-2015 Microchip Technology Inc. DS40001262F-page 71
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4.4.3.3 RB6/SCK/SCL
Figure 4-9 shows the diagram for this pin. The RB6/
SCK/SCL(1) pin is configurabl e to functio n as one o f the
following:
• a general purpose I/O
• a SPI clock
•an I
2C™ clock
FIGURE 4-9: BLOCK DIAGRAM OF RB6
Note 1: SCK and SCL are available on
PIC16F677/PIC16F687/PIC16F689/
PIC16F6 90 onl y.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
To SSP
RABPU
Change
Q3
SSPEN
ST
0
1
1
0
Available o n PIC16 F677/PIC 16F687/ PIC16F 689/PIC16F 690
only.
0
1
1
0
From
SSP
SSP
Clock
PIC16F631/677/685/687/689/690
DS40001262F-page 72 2005-2015 Microchip Technology Inc.
4.4.3.4 RB7/TX/CK
Figure 4-10 shows the diagram for this pin. The RB7/
TX/CK(1) pin is configurable to function as one of the
following:
• a general purpose I/O
• an asynchronous serial output
• a synchronous clock I/O
FIGURE 4-10: BLOCK DIAGRAM OF RB7
Note 1: TX and CK are available on PIC16F687/
PIC16F689/PIC16F690 only.
I/O Pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUB
RD
WPUB
RD PORTB
RD
PORTB
WR
PORTB
WR
TRISB
RD
TRISB
WR
IOCB
RD
IOCB
Interrupt-on-
RABPU
Change
Q3
SPEN
TXEN
CK
TX
SYNC
EUSART
EUSART
0
1
1
0
0
1
1
0
Available on PIC16F687/PIC16F689/PIC16F690 only.
0
1
1
0
‘1’
2005-2015 Microchip Technology Inc. DS40001262F-page 73
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TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ----
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----
WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ----
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PORTB.
PIC16F631/677/685/687/689/690
DS40001262F-page 74 2005-2015 Microchip Technology Inc.
4.5 PORTC and TRISC Registers
PORTC is a 8-bit wide, bidirectional port. The
corres po nding dat a directi on regi s ter is TRISC (Re gi ste r
4-10). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corr esponding o utput dr iver in a Hi gh-Impeda nce mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pi n an outp ut ( i.e. , enab le th e out put dri ver and
put th e co nte nts of t he ou tp ut l atc h on t h e se le cted pi n) .
Example 4-4 shows how to initialize PORTC. Reading
the POR TC register (Register 4-9) reads the st atus of the
pins, wherea s writing to it will write to the PO RT latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the PORT
data latch.
The TRISC register controls the PORTC pin output
driver s, even when they are being used as analo g inputs.
The user should ensure the bits in the TRISC register are
maintained set when using them as analog inputs. I/O
pins co nfigured a s analog i np ut alway s read ‘0’.
EXAMPLE 4-4: INITIALIZI NG PORTC
Note: The ANSEL and ANSELH registers must
be initialized to configure an analog
channel as a di gital input. Pins conf igu r ed
as analog inputs will read ‘0’.
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTC ;Init PORTC
BSF STATUS,RP1 ;Bank 2
CLRF ANSEL ;digital I/O
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
MOVLW 0Ch ;Set RC<3:2> as inputs
MOVWF TRISC ;and set RC<5:4,1:0>
;as outputs
BCF STATUS,RP0 ;Bank 0
REGISTER 4-11: PORTC: PORTC REGISTER
R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 4-12: TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bit
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
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4.5.1 RC0/AN4/C2IN+
The RC0 is configurable to function as one of the
following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• an analog input to Comparator C2
4.5.2 RC1/AN5/C12IN1-
The RC1 is configurable to function as one of the
following:
• a general purpose I/O
• an analog input for the ADC
• an analog input to Comparator C1 or C2
FIGURE 4-1 1: BLOCK DIAGRAM OF RC0
AND RC1
4.5.3 RC2/AN6/C12IN2-/P1D
The RC2/AN6/P1D(1) is configurable to function as
one of the following:
• a genera l purpo se I/O
• an analog input for the ADC (except PIC16F631)
• a PWM output
• an analog input to Comparator C1 or C2
4.5.4 RC3/AN7/C12IN3-/P1C
The RC3/AN7/P1C(1) is configurable to function as one
of the follow ing:
• a genera l purpo se I/O
• an analog input for the ADC (except PIC16F631)
• a PWM output
• a PWM output
• an analog input to Comparator C1 or C2
FIGURE 4-12: BLOCK DIAGRAM OF RC2
AND RC3
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter(2)
RD
PORTC
Analog Input
Mode(1)
To Comparators
Note 1: ANSEL determines Analog Input mode.
2: Not implemented on PI C16F631.
I/O Pin
Note 1: P1D is available on PIC16F685/
PIC16F690 only.
Note 1: P1C is available on PIC16F685/
PIC16F690 only.
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To Comparators
RD
PORTC
Analog Input
Mode(1)
CCP1OUT
CCP1OUT
Enable
Available o n PIC16F685/PIC16F690 on ly.
Note 1: ANSEL determines Analog Input mode.
2: Not implem ented on PIC16F 63 1.
0
1
1
0I/O Pin
To A/D Converter(2)
PIC16F631/677/685/687/689/690
DS40001262F-page 76 2005-2015 Microchip Technology Inc.
4.5.5 RC4/C2OUT/P1B
The RC4/C2OUT/P1B(1, 2) is configurable to function
as one of the following:
• a general purpose I/O
• a digital output from Comparator C2
• a PWM output
FIGURE 4-13: BLOCK DIAGRAM OF RC4
4.5.6 RC5/CCP1/P1A
The RC5/CCP1/P1A(1) is configurable to function as
one of the following:
• a genera l purpo se I/O
• a digital input/output for the Enhanced CCP
• a PWM output
FIGURE 4-14: BLOCK DIAGRAM OF RC5
Note 1: Enabling both C2OUT and P1B will cause
a conflict on RC4 and create
unpredictable results. Therefore, if
C2OUT is enabled, the ECCP+ can not be
used in Half-Bridge or Full-Bridge mode
and vise-versa.
2: P1B is available on PIC16F685/
PIC16F6 90 onl y.
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
RD
PORTC
Available on P I C 16F 68 5/PIC1 6F 690 only.
C2OUT EN
CCP1OUT EN
C2OUT EN
C2OUT
CCP1OUT EN
CCP1OUT
I/O Pin
0
1
1
0
Note 1: CCP1 and P1A are available on
PIC16F685/PIC16F690 only.
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data bus
WR
PORTC
WR
TRISC
RD
TRISC
To Enhanced CCP
RD
PORTC
Available on PIC16F685/PIC16F690 only.
CCP1OUT
CCP1OUT
Enable
0
1
1
0I/O Pin
2005-2015 Microchip Technology Inc. DS40001262F-page 77
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4.5.7 RC6/AN8/SS
The RC6/AN8/SS(1,2) is con figurable to fun ction as one
of the following:
• a general purpose I/O
• an analog input for the ADC (except PIC16F631)
• a slave select input
FIGURE 4-15: BLOCK DIAGRAM OF RC6
4.5.8 RC7/AN9/SDO
The RC7/AN9/SDO(1,2) is configurable to function as
one of the following:
• a genera l purpo se I/O
• an analog input for the ADC (except PIC16F631)
• a serial data output
FIGURE 4-16: BLOCK DIAGRAM OF RC7
Note 1: SS is available on PIC16F687/PIC16F689/
PIC16F690 only.
2: AN8 is not implemented on PIC16F631.
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter(2)
RD
PORTC
Analog Input
Mode(1)
To SS Input
Available on PI C 16F685/P IC16F69 0 only.
Note 1: ANSEL determines Analog Input mode.
2: Not impl emented on PIC16F631.
I/O Pin
Note 1: SDO is available on PIC16F687/
PIC16F689/PIC16F690 only.
2: AN9 is not implemented on PIC16F631.
0
1
1
0
SDO
PORT/SDO
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
Data Bus
WR
PORTC
WR
TRISC
RD
TRISC
To A/D Converter (2)
RD
PORTC
Analog Input
Mode(1)
Available o n PIC16F685/PIC16F690 on ly.
Note 1: ANSEL determines Analog Input mode.
2: Not implem ented on PIC16F 63 1.
I/O Pin
Select
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TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Va lue on
all other
Resets
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111
CCP1CON(2) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000
CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001
SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 0000 00--
SSPCON(1) WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shad ed cells are not used by PORTC.
Note 1: PIC16F687/PIC16F689/PIC16F690 only.
2: PIC16F68 5/PIC16F690 only.
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5.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (shared with Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
Figure 5-1 is a block diagram of the Timer0 module.
5.1 Timer0 Operation
When use d as a tim er, the T im er0 mo dule ca n be use d
as either an 8-bit timer or an 8-bit counter.
5.1.1 8-BIT TIMER MODE
When used as a timer, the Timer0 module will
increment every instruction cycle (without prescaler).
Timer mode is selected by clearing the T0CS bit of the
OPTION register to ‘0’.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
5.1.2 8-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register . Counter mode is selected by
setting the T0CS bit of the OPTION register to ‘1’.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
T0CKI
T0SE
pin
TMR0
Watchdog
Timer
WDT
Time-out
PS<2:0>
WDTE
Data Bus
Set Flag bi t T0 IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION regis ter.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word register.
0
1
0
1
0
1
Sync 2
cycles
8
8
8-bit
Prescaler
0
1
FOSC/4
PSA
PSA
PSA
16-bit
Prescaler 16
WDTPS<3:0>
31 kHz
INTOSC
SWDTEN
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5.1.3 SOFTWARE PROGRAMMA BLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignme nt is contro lled by the PSA bit o f the OPTION
register. To assign the presca ler t o Timer0, the PSA b it
must be cleared to a ‘0’.
There are eight prescaler options for the Timer0 mod-
ule ranging from 1:2 to 1:256. The prescale values are
select able via th e PS<2:0> bits of the OPTION registe r .
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When the
prescaler is assigned to the Timer0 module, all
instructions writing to the TMR0 register will clear the
prescaler.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
5.1.3.1 Switching Prescaler Between
Timer0 and WDT Modules
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values . When chan gin g th e presca le r ass ig nme nt fro m
Timer0 to the WDT module, the instruction sequence
shown in Example 5-1, must be executed.
EXAMPLE 5-1: CHANGING PRESCALER
(TIMER0 WDT)
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
EXAMPLE 5-2: CHANGING PRESCALER
(WDT TIMER0)
5.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
5.1.5 USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer 0 is in Coun ter mo de, t he synchronizatio n
of the T0CKI input and the Timer0 register is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, the
high and low peri od s of the ex tern al cl oc k so urc e mus t
meet the timing requirements as shown in
Section 17.0 “Electrical Specifications”.
BANKSEL TMR0 ;
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA;Select WDT
CLRWDT ;
;
MOVLW b’11111000’;Mask prescaler
ANDWF OPTION_REG,W; bits
IORLW b’00000101’;Set WDT prescaler
MOVWF OPTION_REG ; to 1:32
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
CLRWDT ;Clear WDT and
;prescaler
BANKSEL OPTION_REG ;
MOVLW b’11110000’;Mask TMR0 select and
ANDWF OPTION_REG,W; prescaler bits
IORLW b’00000011’;Set prescale to 1:16
MOVWF OPTION_REG ;
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TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
REGISTER 5-1: OPTION_REG: OPTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RABPU: PORTA/PORTB Pull-up Enable bit
1 = Pull-ups on PORTA/PORTB are disabled
0 = Pull-ups on PORTA/PORTB are disabled by individual WPUAx control bits
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Sele ct bit
1 = Transit ion on T0CKI pin
0 = Internal instr uction cycle clock (FOSC/4)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assig nme nt bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: A dedicated 16-bit WDT postscaler is available. See Section 14.5 “Watchdog Timer (WDT)” for more
information.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
BIT VALUE TMR0 R A TE WDT RATE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000
OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Legend: – = Un im pl em ente d l oc ati ons, read as ‘ 0’, u = unchanged, x = unknown. Shad ed cells a r e no t u sed by th e
Timer0 module.
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6.0 TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/coun ter register p air (TMR1H:T MR1L)
• Programmable internal or external clock source
• 3-bit prescaler
• Optional LP oscilla tor
• Synchronous or asynchronous operation
• Timer1 gate (count enable) via comparator or
T1G pin
• Interrupt on overflow
• Wake-up on overflow (external cl ock,
Asynchronous mode only)
• Time base for the Capture/Compare function
(PIC16F685/PIC16F690 only)
• Special Event Trigger (with ECCP)
(PIC16F685/PIC16F690 only)
• Comparator output synchronization to Timer1
clock
Figure 6-1 is a block diagram of the Timer1 module.
6.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When us ed with an interna l clock source, t he modul e is
a time r. W hen us ed with an exter nal clo ck sour ce, the
module can be used as either a timer or counter.
6.2 Clock Source Selection
The TMR1CS bit of the T1CON register is used to select
the clock source. When TMR1CS = 0, the clock source
is FOSC/4. When TMR1CS = 1, the clock source is
supplied externally.
Clock
Source T1OSCEN FOSC
Mode TMR1CS
FOSC/4 x xxx 0
T1CKI pin 0 xxx 1
T1LPOSC 1LP or
INTOSCIO 1
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FIGURE 6-1: TIMER1 BLOCK DIAGRAM
TMR1H TMR1L
Oscillator T1SYNC
T1CKPS<1:0>
Prescaler
1, 2, 4, 8 Synchronize(3)
det
1
0
0
1
Synchronized
clock input
2
Set flag bit
TMR1IF on
Overflow TMR1(2)
TMR1GE
TMR1ON
T1OSCEN
1
0
SYNCC2OUT(4)
T1GSS
T1GINV
To C2 Comparator Module
Timer1 Clock
TMR1CS
OSC2/T1G
OSC1/T1CKI
Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: SYNCC2OUT is synchronized when the C2SYNC bit of the CM2CON1 register is set.
(1)
EN
INTOSC
Without CLKOUT
FOSC/4
Internal
Clock
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6.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
6.2.2 EXTERN AL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may wo rk as a timer or a cou nter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run async hronously.
If an external clock oscillator is needed (and the
microc ontroller is using the INT OSC withou t CLKOUT),
Timer1 can use the LP oscillator as a clock source.
6.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however , the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
6.4 Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in
between pins OSC1 (input) and OSC2 (amplifier
output). The oscillator is enabled by setting the
T1OSCEN control bit of the T1CON register. The
oscillator will continue to run during Sleep.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can us e this mode only when
the primary system clock is derived from the internal
oscillator or when the oscillator is in the LP mode. The
user must provide a software time delay to ensure
proper oscillator start-up.
TRISA5 and TRISA4 bits are set when the Timer1
oscill ato r is enabled. RA 5 an d R A4 b its read a s ‘0’ and
TRIS A5 and TRISA4 bits read as ‘1’.
6.5 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected then the
timer will continue to run during Sleep and can
generate an interru pt on overflow, which will w ake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
6.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an e xternal asyn chronous cl ock will ens ure a valid
read (taken care of in hardware). However, the user
should keep i n mind that rea ding t he 16-bi t ti mer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes , it is re commend ed that th e user s imply sto p
the timer and write the desired values. A write
conte ntion may occ ur by writin g to th e time r regi sters,
while the register is incrementing. This may pro duce an
unpredictable value in t he TMR1H:TMR1L re gister pair .
6.6 Timer1 Gate
The T i mer1 gate (when enable d) allows Timer1 to count
when Timer1 gate is active. Timer1 gate source is
software configurable to be the T1G pin or the output of
Comparator C2. This allows the device to directly time
external events using T1G or analog events using
Comparator C2. See the CM2CON1 register
(Register 8-3) for selecting the T imer1 gate source. This
feature can simplify the software for a Delta-Sigma A/D
converter and many other applic ations .
Note 1: In Counter mode, a falling edge must be
registered by the counter prior to the first
incr ementing ri sing edg e af ter any one or
more of the following conditions:
•Timer1 enabled after POR reset
•Write to TMR1H or TMR1L
•Timer1 is disabled
•T im er1 is dis abled (TMR1O N 0) when
T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI
is lo w.
2: See Figure 6-2
Note: The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
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Timer1 gate can be inverted using the T1GINV bit of
the T1CON register, whether it origin ates from the T1G
pin or Comparator C2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.
6.7 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the T ime r1 interru pt flag bi t of the PIR 1 register i s
set. To enable the interrupt on rollover, you must set
these bits:
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
6.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynch ronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
• TMR1CS bit of the T1CON register must be set
• T1OSCEN bit of the T1CON register (can be set)
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
6.9 ECCP Capture/Comp are Time Base
The ECCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For more information, see Section 11.0 “Enhanced
Capture/Compare/PWM Module”.
6.10 ECCP Special Event Trigger
When the ECCP is configured to trigger a special
event, the trigger will clear the TMR1H:TMR1L register
pair. This special event does not cause a Timer1 inter-
rupt. The ECCP module may still be configured to
generate a ECCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized to the FOSC to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
In the eve nt that a wri te to TMR1H or TMR1L coi ncides
with a Special Event Trigger from the ECCP, the write
will take precedence.
For more information, see Section 11.2.4 “Special
Event Trigger”.
6.11 Comparator Synchronization
The same clock used to increment Timer1 can also be
used to synchronize the comparator output. This
feature is enabled in the Comparator module.
When using the comparator for Timer1 gate, the
comparator output should be synchronized to Timer1.
This ensures Timer1 does not miss an increment if the
comp ara tor changes.
For more information, see Section 8.8.2
“Synchron izing Comparator C2 output to Timer1”.
Note: TMR1GE bit of the T1CON register must
be set to us e eit her T1G or C2OU T as the
Timer1 gate source. See the CM2CON1
register (Register 8-3) for more informa-
tion on selecting the Timer1 gate source.
Note: The TMR1H:TTMR1L register pair and
the TMR1IF bit should be cleared before
enabling interrupts.
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FIGURE 6-2: TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter incremen ts.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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6.12 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 6-1: T1CON: TIMER 1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 T1GINV: Timer1 Gate Invert bit(1)
1 = Timer1 gate is active-high (Timer1 counts when Timer1 gate signal is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 6 TMR1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 Gate function
0 = Timer1 is always counting
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3 T1OSCEN: LP Oscilla tor Enab le C ontro l bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchroniz e exte rnal cloc k inp ut
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock
bit 1 TMR1CS: Timer1 Clock Sourc e Sele ct bit
1 = External clock from T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE b it must be set to us e eithe r T1G pin or C2OUT, as selec ted b y the T1GSS bit o f the C M2CO N1
register, as a Timer1 gate source.
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TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Va lue on
all other
Resets
CM2CON1 MC1OUT MC2OUT ———— T1GSS C2SYNC ---- --10 ---- --10
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
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7.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
• 8-bit timer register (TMR2)
• 8-bit period register (PR2)
• Interrupt on TMR2 match with PR2
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
See Figure 7-1 for a block diagram of Timer2.
7.1 Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescal er is then used to
increm ent the TM R2 regis ter.
The val ues of T MR2 and PR2 are co nstan tly com pared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented
The matc h o utp ut of the Timer2/PR2 c omparator i s fed
into the Timer2 postscaler. The postscaler has
post scal e options of 1:1 to 1: 16 inclus ive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
The TMR2 and PR2 registers are both fully readable
and w rita ble. O n any Rese t, the TMR2 regis ter is set to
00h and the PR2 register is set to FFh.
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Tim er2 is turned off by clearing
the TMR2ON bit to a ‘0’.
The Timer2 prescaler is controlle d by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
• A write to TMR2 occurs.
• A write to T2CON occurs.
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset or Brown-out
Reset).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
Note: TMR2 is not cleared when T2CON is
written.
Comparator
TMR2 Sets Flag
TMR2
Output
Reset
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
TOUTPS<3:0>
T2CKPS<1:0>
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TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2(1) REGISTERS
REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER(1)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 =1:1 Postscaler
0001 =1:2 Postscaler
0010 =1:3 Postscaler
0011 =1:4 Postscaler
0100 =1:5 Postscaler
0101 =1:6 Postscaler
0110 =1:7 Postscaler
0111 =1:8 Postscaler
1000 =1:9 Postscaler
1001 =1:10 Postscaler
1010 =1:11 Postscaler
1011 =1:12 Postscaler
1100 =1:13 Postscaler
1101 =1:14 Postscaler
1110 =1:15 Postscaler
1111 =1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
1x =Prescaler is 16
Note 1: PIC16F685/PIC16F690 only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all ot her
Resets
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
Note 1: PIC16F68 5/PIC16F690 only.
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8.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The Analog
Comparator module includes the following features:
• Independent comparator control
• Programmable input selection
• Comp arator ou tput is avail able internall y/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
•PWM shutdown
• Ti mer 1 gate (co unt ena ble )
• Output synchronization to Timer1 clock input
•SR Latch
• Programmable and Fixed Voltage Reference
8.1 Comparator Overview
A single comparator is shown in Figure 8-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the outp ut of the comp arat or is a digit al high le vel.
FIGURE 8-1: SINGLE COMPARATOR
Note: Only Comparator C2 can be linked to
Timer1.
–
+
VIN+
VIN-Output
Output
VIN+
VIN-
Note: The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
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FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C1POL
C1OUT
RD_CM1CON0
Set C1IF
To
DQ
EN
Q1 Data Bus
C1POL
DQ
EN
CL
Q3*RD_CM1CON0
NRESET
MUX
C1
0
1
2
3
C1ON(1)
C1CH<1:0> 2
C1VIN-
C1VIN+
C12IN0-
C12IN1-
C12IN2-
C12IN3-
+
-
Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
0
1
C1R
MUX
C1IN+
0
1
MUX
To other peripherals
C1OUT (to SR latch)
CVREF
C1VREN
FixedRef
MUX C2
C2POL
C2OUT
0
1
2
3
C2ON(1)
C2CH<1:0> 2
From TMR1
Clock
DQ
EN
DQ
EN
CL
DQ
RD_CM2CON0
Q3*RD_CM2CON0
Q1
Set C 2 IF
To
NRESET
C2VIN-
C2VIN+
C12IN0-
C12IN1-
C12IN2-
C12IN3-
0
1
C2SYNC
C2POL Data Bus
MUX
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-ph ase system clock (FOSC).
3: Q1 is held high during Sleep mode.
0
1
C2R
CVREF
MUX
C2IN+
0
1
MUX
SYNCC2OUT
to Timer1 Ga te, SR latch
C2VREN
FixedRef
and other peripherals
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8.2 Comparator Control
Each comparator has a separate control and
Configuration register: CM1CON0 for Comparator C1
and CM2CON0 for Comparator C2. In addition,
Comparator C2 has a second control register,
CM2CON1, for controlling the interaction with Timer1 and
simultaneous reading of both comparator outputs.
The CM1CON0 and CM2CON0 registers (see Registers
8-1 and 8-2, respectively) contain the control and S tatus
bits for the following:
• Enable
• Input selection
• Reference selection
•Output selection
• Output polarity
8.2.1 COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
8.2.2 COMPARATOR INPUT SELECTION
The CxCH<1:0> bits of the CMxCON0 register direct
one of four analog input pins to the comparator
inverting input.
8.2.3 COMPARATOR REFERENCE
SELECTION
Setting the CxR bit of the CMxCON0 register directs an
internal voltage reference or an analog input pin to the
non-inv erting i nput of the comp arat or. See Section 8.9
“Comparator SR Latch” for more information on the
Internal Volt age Reference module.
8.2.4 COMPA RATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CM2CON1 register. In order
to make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
8.2.5 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 8-1 shows the output state versus input
conditions, including polarity control.
8.3 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new refe rence volta ge. This period is refer red to as
the response time. The response time of the
comparator differs from the settling time of the voltage
reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See the Comparator and
Voltage Reference Specifications in Section 17.0
“Electrical Specifications” for more details.
Note: To use CxIN+ and C 12INx- pin s as analog
inputs, the appropriate bits must be set in
the ANSEL register and the
corr esp on di n g TR IS b i ts mus t al so b e se t
to disable the output drivers.
Note 1: The CxOE bit overrides the PORT data
latch. Se tting the Cx ON has no impa ct on
the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
TABLE 8-1: COMPARATOR OUTPUT
ST ATE VS. INPUT CONDITIONS
Input Condition CxPOL CxOUT
CxVIN- > CxVIN+00
CxVIN- < CxVIN+01
CxVIN- > CxVIN+11
CxVIN- < CxVIN+10
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8.4 Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a chang e in the o utput val ue of the compa rator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gate (see Figure 8-2 and Figure 8-3). One latch is
updated with the comparator output level when the
CMxCO N0 regi ster is read . This latc h re t ai ns the value
until the next read of the CMxCON0 register or the
occurre nce of a Reset. The other la tch of the mism atch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMxCON0 register is read or the comparator
output returns to the previous state.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the inter-
rupt flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator ’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register , to determine
the actual change that has occ urred.
The CxIF bit of the PIR1 register is the comparator
interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Sinc e it i s als o poss ible t o writ e a ‘1’ to
this register, an interrupt can be generated.
The CxIE bi t of the PIE1 re gister and the PEIE and G IE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interru pt is not en abled, alt hough the Cx IF bit of the
PIR1 register will still be set if an interrupt condition
occurs.
FIGURE 8-4: COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
FIGURE 8-5: COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate
correctly regardless of the state of CxOE.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF of the PIR1
register interrupt flag may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 s for bias settling
then clear the mismatch condition and
interrupt flags before enabling
comp ara tor int errup ts.
Q1
Q3
CxIN+
Cxout
Set CxIF (edge)
CxIF
TRT
reset by software
Q1
Q3
CxIN+
Cxout
Set CxIF (edge)
CxIF
TRT
reset by software
cleared by CMxCON0 read
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8.5 Operation During Sleep
The compa rator , if enabled b efore entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comp arator is show n separately in the
Section 17.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comp arator. Each comparator is turned off
by clearing the CxON bit of the CMxCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the devic e from Sle ep, the CxIE bit of the PIE1 reg ister
and the PEIE bit of the INTCON register must be set.
The instruction following the Sleep instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
8.6 Effects of a Reset
A device Reset forces the CMxCON0 and CM2CON1
registers to their Reset states. This forces both
comparators and the voltage references to their OFF
states.
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REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
C1ON C1OUT C1OE C1POL —C1R C1CH1 C1CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C1ON: Comparator C1 Enable bit
1 = Comparator C1 is enabled
0 = Comparator C1 is disabled
bit 6 C1OUT: Comparator C1 Output bit
If C1POL = 1 (inverted polarity):
C1OUT = 0 when C1VIN+ > C1VIN-
C1OUT = 1 when C1VIN+ < C1VIN-
If C1POL = 0 (non-inverted polarity):
C1OUT = 1 when C1VIN+ > C1VIN-
C1OUT = 0 when C1VIN+ < C1VIN-
bit 5 C1OE: Comparator C1 Output Enable bit
1 = C1OUT is present on the C1OUT pin(1)
0 = C1OUT is internal only
bit 4 C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 3 Unimplemented: Read as ‘0’
bit 2 C1R: C ompara tor C1 Reference Select bit (non-inverting input)
1 = C1VIN+ connects to C1VREF output
0 = C1VIN+ connects to C1IN+ pin
bit 1-0 C1CH<1:0>: Comparator C1 Channel Select bit
00 = C1VIN- of C1 connects to C12IN0- pin
01 = C1VIN- of C1 connects to C12IN1- pin
10 = C1VIN- of C1 connects to C12IN2- pin
11 = C1VIN- of C1 connects to C12IN3- pin
Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding
PORT TRIS bit = 0.
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REGISTER 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0
R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
C2ON C2OUT C2OE C2POL —C2R C2CH1 C2CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C2ON: Comparator C2 Enable bit
1 = Compar ator C2 is enabled
0 = Comparator C2 is disabled
bit 6 C2OUT: Comparator C2 Output bit
If C2POL = 1 (inverted polarity):
C2OUT = 0 when C2VIN+ > C2VIN-
C2OUT = 1 when C2VIN+ < C2VIN-
If C2POL = 0 (non-inverted polarity):
C2OUT = 1 when C2VIN+ > C2VIN-
C2OUT = 0 when C2VIN+ < C2VIN-
bit 5 C2OE: Comparator C2 Output Enable bit
1 = C2OUT is present on C2OUT pin(1)
0 = C2OUT is internal only
bit 4 C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 3 Unimplemented: Read as ‘0’
bit 2 C2R: Comparator C2 Reference Select bits (non-inverting input)
1 = C2VIN+ connects to C2VREF
0 = C2VIN+ connects to C2IN+ pin
bit 1-0 C2CH<1:0>: Comparator C2 Channel Select bits
00 = C2VIN- of C2 connects to C12IN0- pin
01 = C2VIN- of C2 connects to C12IN1- pin
10 = C2VIN- of C2 connects to C12IN2- pin
11 = C2VIN- of C2 connects to C12IN3- pin
Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding
PORT TRIS bit = 0.
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8.7 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 8-6. Since the analog i nput pins sh are thei r con-
nection with a digital input, they have reverse biased
ESD protection diodes to VDD and VSS. The analog
input, therefore, must be between VSS and VDD. If the
input voltage deviates from this range by more than
0.6V in either direction, one of the diodes is forward
biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an anal og inpu t pin, such as a capacitor or
a Zener diode, should h ave very little leakage curr ent to
minimize inaccuracies introduced.
FIGURE 8-6: ANALOG INPUT MODEL
Note 1: When reading a PORT register, all pins
configu red as analog in puts w ill read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digit al input, may cause th e input buffer to
consume more current than is specified.
VA
Rs < 10K
CPIN
5 pF
VDD
VT 0.6V
VT 0.6V
RIC
ILEAKAGE(1)
Vss
AIN
Legend: CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA= Analog Voltag e
VT= Threshold Voltage
To Comparator
Note 1: See Section 17.0 “Electri cal Specifications”
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8.8 Additional Comparator Features
There are three additional comparator features:
• Timer1 count enable (gate)
• Synchronizing output with Ti mer1
• Simultaneous read of comparator outputs
8.8.1 COMPARATOR C2 GATING TIMER1
This feat ure can be used to time the d uration or inte rval
of analog events. Clearing the T1GSS bit of the
CM2CON1 register will enable Timer1 to increment
based on the output of Comparator C2. This requires
that Timer1 is on and gating is enabled. See
Section 6.0 “Timer1 Module with Gate Control” for
details.
It is recommended to synchronize the comparator with
Timer1 by setting the C2SYNC bit when the comparator
is us ed as t he T imer1 gate sou rce. Thi s ensur es T imer1
does not miss a n incr eme nt if the compar a tor ch an ges
during an increment.
8.8.2 SYNCHRONIZING COMPARATOR
C2 OUTPUT TO TIMER1
The Comparator C2 output can be synchronized with
Timer1 by setting the C2SYNC bit of the CM2CON1
register . When enabled, the C2 output is latched on the
falling edge of the Timer1 clock source. If a prescaler is
used with T imer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator o utput is latch ed on the falling e dge of th e
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 8-3) and the Timer1 Block
Diagram (Figure 6-1) fo r more information.
8.8.3 SIMULTANEOUS COMPARATOR
OUTPUT READ
The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate registers.
Note 1: Obtaining the status of C1OUT or
C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.
REGISTER 8-3: CM2CON1: COMPARATOR C2 CONTROL REGISTER 1
R-0 R-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0
MC1OUT MC2OUT — — — — T1GSS C2SYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MC1OUT: Mirror Copy of C1OUT bit
bit 6 MC2OUT: Mirror Copy of C2OUT bit
bit 5-2 Unimplemented: Read as ‘0’
bit 1 T1GSS: Timer1 Gate Source Select bit(1)
1 = Timer1 gate source is T1G
0 = Timer1 gate source is SYNCC2OUT.
bit 0 C2SYNC: Comparator C2 Output Synchronization bit(2)
1 = Output is synchronous to falling edge of Timer1 clock
0 = Output is asynchronous
Note 1: Refer to Section 6.6 “Timer1 Gate”.
2: Refer to Figure 8-3.
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8.9 Comparator SR Latch
The SR Latch module provides additional control of the
comparator outputs. The module consists of a single
SR latch and output multiplexers. The SR latch can be
set, reset or toggled by the comparator outputs. The SR
latch may also be set or reset, independent of
comparator output, by control bit s in the SRCON control
register. The SR latch output multiplexers select
whether the latch output s or the com p arator output s are
directed to the I/O port log ic for ev entual outpu t to a pin.
8.9.1 LATCH OPERATION
The latch is a Set-Reset latch that does not depend o n a
clock source. Each of the Set and Reset inputs are
active-high. Each latch input is connected to a
comparator output and a software controlled pulse
generator . The latch can be set by C1OUT or the PULSS
bit of the SRCON register. The latch can be reset by
C2OUT or the PULSR bit of the SRCON register. The
latch is reset-dominant, therefore, if both Set and Reset
inputs are hig h, the latch wil l go to the Reset st ate. Both
the PULSS and PULSR bits are self resetting which
means that a single write to either of the bits is all that is
necessary to compl ete a latch set or reset operation.
8.9.2 LATCH OUTPUT
The SR<1:0> bits of the SRCON register control the
latch output multiplexers and determine four possible
output configurations. In these four configurations, the
CxOUT I/O port logic is connected to:
• C1OUT and C2OUT
• C1OUT and SR latch Q
• C2OUT and SR latch Q
• SR latch Q and Q
After any Reset, the default output configuration is the
unlatched C1OUT and C2OUT mode. This maintains
compatibility with devices that do not have the SR latch
feature.
The applicable TRIS bits of the corresponding ports
must be cleared to enable the port pin output drivers.
Additionally, the CxOE comparator output enable bits of
the CMxCON0 registers must be set in order to make the
comparator or latch output s available on the output pins.
The latch configuration enable states are completely
independent of the enable states for the comp arators.
FIGURE 8-7: SR LATCH SIMPLIFIED BLOCK DIAGRAM
C2OE
C1SEN
SR0
PULSS
S
R
Q
Q
C2REN
PULSR SR1
Note 1: If R = 1 and S = 1 simultaneously, Q = 0, Q =1
2: Pulse generator causes a 1/2 Q-state (1 Tosc) pulse width.
3: Output shown for reference only. See I/O port pin block diagram for more detail.
Pulse
Gen(2)
Pulse
Gen(2)
SYNCC2OUT (from comparator)
C1OUT (from comparator)
C2OUT pin(3)
C1OE
C1OUT pin(3)
0
1
MUX
1
0
MUX
SR
Latch(1)
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REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 U-0
SR1(2) SR0(2) C1SEN C2REN PULSS PULSR — —
bit 7 bit 0
Legend: S = Bit is set only
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SR1: SR Latch Configuration bit(2)
1 = C2OUT pin is the latch Q output
0 = C2OUT pin is the C2 comparator output
bit 6 SR0: SR Latch Configuration bits(2)
1 = C1OUT pin is the latch Q output
0 = C1OUT pin is the Comparator C1 out put
bit 5 C1SEN: C1 Set Enable bit
1 = C1 comparator output sets SR latch
0 = C1 comparator output has no effect on SR latch
bit 4 C2REN: C2 Reset Enable bit
1 = C2 comparator output res ets SR latch
0 = C2 comparator output has no effect on SR latch
bit 3 PULSS: Pulse the SET Input of the SR Latch bit
1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 2 PULSR: Pulse the Reset Input of the SR Latch bit
1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.
0 = Does not trigger pulse generator
bit 1-0 Unimplemented: Read as ‘0’
Note 1: The CxOUT bit in the CMxCON0 register will always reflect the actual c omp arator output (not the lev el on
the pin), regardless of the SR latch operation.
2: To enable an SR lat ch ou tput to th e p in, th e a ppro pri ate C xOE and TRIS bit s must be properly c onfi gured.
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8.10 Comparator Voltage Reference
The comparator voltage reference module pr ovides an
internally generated voltage reference for the compara-
tors. The following features are available:
• Independent from Comparator operation
• Two 16-level voltage ranges
• Output clamped to VSS
• Ratiometric with VDD
• Fix ed Ref erence (0.6)
The VRCON register (Register 8-5) controls the
Voltage Reference module shown in Figure 8-8.
8.10.1 INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
8.10.2 OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has two ranges with 16
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR<3:0> bits of the VRCON
register.
The CVREF output voltage is determined by the following
equations:
EQUATION 8-1: CVREF OUTPUT VOLTAGE
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 8-8.
8.10.3 OUTPUT CLAMPED TO VSS
The CVREF output voltage can be set to Vss with no
power consumption by clearing the VP6EN bit of the
VRCON register.
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module curren t.
8.10.4 OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 17.0
“Electr ical Specific ations”.
VRR 1 (low range):=
VRR 0 (high range):=
CVREF (VDD/4) + =
CVREF (VR<3:0>/24) VDD=
(VR<3:0> VDD/32)
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8.10.5 FIXED VOLTAGE REFERENCE
The Fixed Voltage Reference is independent of VDD,
with a nominal output voltage of 0.6V. This reference
can be enabled by setting the VP6EN bit of the VRCON
register to ‘1’. This reference is always enabled when
the HFINTOSC oscillator is active.
8.10.6 FIXED VOLTAGE REFERENCE
STABIL IZATION PE RIOD
When the Fixed Voltage Reference mo dule is enabled,
it will require some time for the reference and its
amplifier circuits to stabilize. The user program must
include a small delay routine to allow the module to
settle. See the electrical specifications section for the
minimum delay requirement.
8.10.7 VOLTAGE REFERENCE
SELECTION
Multiplexers on the output of the Voltage Reference
module enable selection of either the CVREF or Fixed
Voltage Reference for use by the comparators.
Setting the C1VREN bit of the VRCON register enables
current to flow in the CV REF volt age d ivide r and s elects
the CV REF voltage for use by C1. Clearing the C1VREN
bit selects the fixed voltage for use by C1.
Setting the C2VREN bit of the VRCON register enables
current to flow in the CV REF volt age d ivide r and s elects
the CV REF voltage for use by C2. Clearing the C2VREN
bit selects the fixed voltage for use by C2.
When bo th the C1VREN and C2VREN b its are cle ared,
current flow in the CVREF voltage divider is disabled
minimizing the power drain of the voltage reference
peripheral.
FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VRR
8R
VR<3:0>(1)
Analog
8RRR RR
16 Stages
VDD
MUX
Fixed Voltage
C2VREN
C1VREN
CVREF(1)
Reference
EN
VP6EN
Sleep
HFINTOSC enable
0.6V
Fixed Ref
To Com parators
and ADC Module
To Comparators
and ADC Module
Note 1: Care should be taken to ensure VREF remains
within the comparator Common mode input
range. See Section 17.0 “Electrical Specifica-
tions” for more detail.
15
0
4
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T ABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMP ARATOR AND V OLT AGE
REFERENCE MODULES
REGISTER 8-5: VRCON: VOLT AGE REFERENCE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit
1 = CVREF circuit powered on and routed to C1VREF input of Comparator C1
0 = 0.6 Volt constant reference routed to C1VREF input of Comparator C1
bit 6 C2VREN: Comparator 2 Voltage Reference Enable bit
1 = CVREF circuit powered on and routed to C2VREF input of Comparator C2
0 = 0.6 Volt constant reference routed to C2VREF input of Comparator C2
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 VP6EN: 0 .6V Refer ence Enable bit
1 = Enabled
0 = Disabled
bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0 VR<3:0> 15)
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0> /32) * VDD
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Valu e on
all other
Resets
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 0000
CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000
CM2CON1 MC1OUT MC2OUT ———— T1GSS C2SYNC 00-- --10 00-- --10
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 0000 ----
PIR2 OSFIF C2IF C1IF EEIF — — — — 0000---- 0000----
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 0000 00--
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.
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9.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to be
either internally gene rated or externally s upplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt ca n be used to wake-up the
device from Sleep.
Figure 9-1 shows the block diagram of the ADC.
FIGURE 9-1: ADC BLOCK DIAGRAM
Note: The ADC module applies to PIC16F677/
PIC16F685/PIC16F687/PIC16F689/
PIC16F6 90 dev ic es only.
VDD
VREF
ADON
GO/DONE
VCFG = 1
VCFG = 0
CHS
VSS
RA0/AN0/C1IN+/ICSPDAT/ULPWU
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RA4/AN3/T1G/OSC2/CLKOUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-
RC2/AN6/C12IN2-/P1D(1)
RC3/AN7/C12IN3-/P1C(1)
RC6/AN8/SS(2)
RC7/AN9/SDO(2)
RB4/AN10/SDI/SDA(2)
RB5/AN11/RX/DT(2)
CVREF
VP6 Reference
Note 1: P1C and P1D available on PIC16F685/PIC16F690 only.
2: SS, SDO, SDA, RX and DT available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
3: ADC module applies to the PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 devices only.
ADRESH ADRESL
10
10
ADFM 0 = Left Justify
1 = Right Ju stify
ADC
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9.1 ADC Configuration
When configuring and using the ADC the following
functio ns must be considere d:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conv ersion clock source
• Interrupt control
• Results formatting
9.1.1 PORT CONFIGURATION
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding port
section for more information.
9.1.2 CHANNEL SELECTION
The CHS bits of the ADCON0 r egister det ermine whic h
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Operation” for more information.
9.1.3 ADC VOLTAGE REFERENCE
The VCFG bit of the ADCON0 registe r provides contro l
of the positive voltage reference. The positive voltage
reference can be either VDD or an external voltage
source. The negative voltage reference is always
connected to the ground reference.
9.1.4 CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
•F
OSC/2
•F
OSC/4
•FOSC/8
•FOSC/16
•F
OSC/32
•FOSC/64
•FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One ful l 1 0-b it c on ve rsi on requires 11 TAD periods
as shown in Figure 9-2.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
Section 17.0 “Electrical Specifications” for more
information. Table 9-1 gives examples of appropriate
ADC clock selections.
Note: Analo g v ol tages on any pin that is d efined
as a digital input may cause the i nput buf-
fer to conduct excess current.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
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TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V,
VREF > 2.5V)
FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
9.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 reg ister. The ADC i nterrupt enabl e is the ADIE b it
in the PIE1 register. The ADIF bit must be cleared in
software.
This interrupt can be generated while the device is
operatin g or while in Sle ep. If the device is in Sle ep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruc tio n is alw ays executed. If th e use r i s attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
inter rupt se rvi ce rout ine.
Please see Section 9.1.5 “Interrupts” for more
information.
ADC Clock Period (TAD) Device Freque ncy (FOSC)
ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz
FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 200 ns(2) 500 ns(2) 1.0 s(2) 4.0 s
FOSC/8 001 400 ns(2) 1.0 s(2) 2.0 s8.0 s(3)
FOSC/16 101 800 ns(2) 2.0 s4.0 s16.0 s(3)
FOSC/32 010 1.6 s4.0 s8.0 s(3) 32.0 s(3)
FOSC/64 110 3.2 s8.0 s(3) 16.0 s(3) 64.0 s(3)
FRC x11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
TAD1TAD2 TAD3TAD4TAD5 TAD6 TAD7 TAD8TAD9
Set GO/DONE bit
Holding Capacitor is disconnected from analog input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2
TAD10 TAD11
b1 b0
TCY to TAD
Conversion Starts
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
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9.1.6 RESULT FORMATTING
The 10-bit A/D conversion res ult can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 9-3 shows the two output formats.
FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL
(ADFM = 0)MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1)MSB LSB
bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result
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9.2 ADC Operation
9.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
9.2.2 COMPLETION OF A CONVERSION
When the convers ion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH:A DRESL regis ters with new
conversion result
9.2.3 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion. Addi-
tionall y, a 2 TAD delay is requir ed before anothe r acqui-
sition can be initiated. Following this delay, an input
acquisition is automatically started on the selected
channel.
9.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC wa its on e additio nal instru ction bef ore sta rting th e
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
9.2.5 SPECIAL EVENT TRIGGER
An ECCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 counter resets to zero.
Using the S pecial Event T rigger does not assure prop er
ADC timi ng. I t is the user’s resp onsib ility t o ensu re that
the ADC timing requirements are met.
See Section 11.0 “Enhanced Capture/Compare/
PWM Module” for more information.
9.2.6 A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digita l convers ion:
1. Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
2. Configure the ADC module:
• Select ADC conversion clock
• Configure volt ag e refere nc e
• Select ADC input channel
• Select result format
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2).
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DO NE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC interrup t flag (requi red if interrupt
is enabled).
Note: The GO/DONE bit shou ld not be se t in the
same instruction that turns on the ADC.
Refe r to Section 9.2.6 “A/D Conversion
Procedure”.
Note: A devi ce Rese t forces all reg is ters to th eir
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
Note 1: The glob al interru pt can be disabl ed if the
user is att empting to w ake-u p from Sleep
and resume in-line code execution.
2: See Section 9.3 “A/D Acquisition
Requirements”.
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EXAMPLE 9-1: A/D CONVERSION
9.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the
operati on of the AD C.
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSELADCON1;
MOVLWB’01110000’;ADC Frc clock
MOVWFADCON1;
BANKSELTRISA;
BSF TRISA,0;Set RA0 to input
BANKSELANSEL;
BSF ANSEL,0;Set RA0 to analog
BANKSELADCON0;
MOVLWB’10000001’;Right justify,
MOVWFADCON0; Vdd Vref, AN0, On
CALLSampleTime;Acquisiton delay
BSF ADCON0,GO;Start conversion
BTFSCADCON0,GO;Is conversion done?
GOTO$-1 ;No, test again
BANKSELADRESH;
MOVFADRESH,W;Read upper 2 bits
MOVWFRESULTHI;store in GPR space
BANKSELADRESL;
MOVFADRESL,W;Read lower 8 bits
MOVWFRESULTLO;Store in GPR space
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REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Conversion Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 VCFG: V oltage Referen ce bit
1 = V REF pin
0 = VDD
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 = AN0
0001 = AN1
0010 = AN2
0011 = AN3
0100 = AN4
0101 = AN5
0110 = AN6
0111 = AN7
1000 = AN8
1001 = AN9
1010 = AN10
1011 = AN11
1100 = CVREF
1101 = 0.6V Fixed Voltage Reference
1110 = Reserved. Do not use.
1111 = Reserved. Do not use.
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
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REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— ADCS2 ADCS1 ADCS0 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0 Unimplemented: Read as ‘0’
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REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2
bit 7 bit 0
Legend:
R = Readable bit W = Wri t able bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<9:2>: ADC Result Register bits
Upper eight bits of 10-bit conversion result
REGISTER 9-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES1 ADRES0 — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Wri t able bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 ADRES<1:0>: ADC Result Register bits
Lower two bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.
REGISTER 9-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — — — — — ADRES9 ADRES8
bit 7 bit 0
Legend:
R = Readable bit W = Wri t able bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Reserved: Do not use.
bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result
REGISTER 9-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Wri t able bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: ADC Result Register bits
Lower eight bits of 10-bit conversion result
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9.3 A/D Acquisition Requirements
For the A DC t o meet its specif ied accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 9-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 9-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 9-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb erro r is the maximum er ror allow ed
for the ADC to meet its specified resolution.
EQUATION 9-1: ACQUISITION TIME EXAMPLE
TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=
TAMP TCTCOFF++=
2µs TCTemperature - 25°C0.05µs/°C++=
TCCHOLD RIC RSS RS++ ln(1/2047)–=
10pF 1k
7k
10k
++– ln(0.0004885)=
1.37
=µs
TACQ 2ΜS1.37ΜS50°C- 25°C0.05ΜS/°C++=
4.67ΜS=
VAPPLIED 1e
Tc–
RC
---------
–
VAPPLIED 11
2n1+
1–
--------------------------–
=
VAPPLIED 11
2n1+
1–
--------------------------–
VCHOLD=
VAPPLIED 1e
TC–
RC
----------
–
VCHOLD=
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Temperature 50°C and external impedance of 10k
5.0V VDD=
Assumptions:
Note: Where n = number of bits of the ADC.
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FIGURE 9-4: ANALOG INPUT MODEL
FIGURE 9-5: ADC TRANSFER FUNCTION
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
CPIN
VA
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I LEAKAGE(1)
RIC 1k
Sampling
Switch
SS Rss
CHOLD = 10 pF
VSS/VREF-
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold V oltage
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
various junctions
RSS
Note 1: See Section 17.0 “Electrical Specifications”.
3FFh
3FEh
ADC Output Code
3FDh
3FCh
004h
003h
002h
001h
000h
Full-Scale
3FBh
1 LSB ideal
VSS/VREF-Zero-Scale
Transition VDD/VREF+
Transition
1 LSB ideal
Full-Scale Range
Analog Input Voltage
PIC16F631/677/685/687/689/690
DS40001262F-page 116 2005-2015 Microchip Technology Inc.
TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n
POR, BOR
Value on
all other
Resets
ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
ANSELH — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 —ADIERCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIFRCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ----
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
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10.0 DATA EEPROM AND FLASH
PROGRAM MEMORY
CONTROL
Data EEPROM memory is readable and writable and
the Flash program memory (PIC16F685/PIC16F689/
PIC16F690 only) is readable during normal operation
(full VDD range). These memories are not directly
mapped in the register file sp ace. Instead, they are indi-
rectly addressed through the Special Function Regis-
ters (SFRs). There are six SFRs used to access these
memories:
• EECON1
• EECON2
• EEDAT
• EEDATH (PIC16F685/PIC16F689/PIC16F690 only)
• EEADR
• EEADRH (PIC16F685/PIC16F689/PIC16F690 only)
When interfacing the data memory block, EEDA T holds
the 8-bit data for read/write, and EEADR holds the
address o f the EEDAT l oca tio n bei ng access ed . T hes e
devices, except for the PIC16F631, have 256 bytes of
data EEPROM wit h an address range from 0 h to 0FFh.
The PIC16F631 has 128 bytes of data EEPROM with
an address range from 0h to 07Fh.
When accessing the program memory block of the
PIC16F685/PIC16F689/PIC16F690 devices, the EEDA T
and EEDATH registers form a 2-byte word that holds the
14-bit data for read/write, and the EEADR and EEADRH
registers form a 2-byte word that holds the 12-bit ad dress
of the EEPROM location being read. These devices
(PIC16F685/PIC16F689/PIC16F690) have 4K words of
program EEPROM with an address range from 0h to
0FFFh. The program memory allows one-word reads.
The EEPROM dat a memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge p ump rated to op erate over the v oltage ran ge of
the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the data EEPROM memory
and r ead th e p rogr am m emor y. When c ode- pro tec ted,
the device programmer can no longer access data or
program memory.
10.1 EEADR and EEADRH Registers
The EEADR and EEADRH registers can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 4K words of program EEPROM.
When selecting a program address value, the MSB of
the address is written to the EEADRH register and the
LSB is w ritten to t he EEADR register. When s electing a
data address value, only the LSB of the address is
written to the EEADR register.
10.1.1 EECON1 AND EECON2 REGISTERS
EECON1 is the control register for EE memory
accesses.
Control bit EEPGD (PIC16F685/PIC16F689/PIC16F690)
determines if the access will be a program or data mem-
ory access. W hen clear, as it is when r es et, any subse-
quent operations will operate on the data memory. When
set, any subsequent operations will operate on the pro-
gram memory. Program memory can only be read.
Control bits RD and WR initiate read and write,
resp ec ti v el y. Thes e bits ca nn o t be cl ea r ed, on l y s et , in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, w ill all ow a write op eratio n to
data EEPROM. On power-up, the WREN bit is clear.
The WRERR bit is set when a write operation is
interrupted by a MCLR or a WDT Time-out Reset
during normal operati on. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location.
Interrupt flag bit EEIF of the PIR2 register is set when
write is complete. It must be cleared in the software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
PIC16F631/677/685/687/689/690
DS40001262F-page 118 2005-2015 Microchip Technology Inc.
REGISTER 10-1: EEDAT: EEPROM DATA REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EEDAT<7:0>: Eight L ea st Signif i cant Addr ess bit s to Write to or Re ad from data EEPROM o r Read from pro gram
memory
REGISTER 10-2: EEADR: EEPROM ADDRESS REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEADR7(1) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EEADR<7:0>: Eight Least Significant Address bits for EEPROM Read/Write Operation(1) or Read from program
memory
Note 1: PIC16F 677/PIC16 F685/PIC16F687/ P IC 16F689/PIC16F690 only.
REGISTER 10-3: EEDATH: EEPROM DATA HIGH BYTE REGISTER(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 EEDATH<5:0>: Six Most Significant Data bits from program memory
Note 1: PIC16F685/PIC16F689/PIC16F690 only.
REGISTER 10-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER(1)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 EEADRH<3:0>: Specifies the four Most Significant Address bits or high bits for program memory reads
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Note 1: PIC16F685/PIC16F689/PIC16F690 only.
REGISTER 10-5: EECON1: EEPROM CONTROL REGISTER
R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD(1) — — — WRERR WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Program/Data EEPROM Select bit(1)
1 = Accesses program memory
0 = Accesses data memory
bit 6-4 Unimplemented: Read as ‘0’
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR Reset)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycle s
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
EEPGD = 1:
This bit is ignored
EEPGD = 0:
1 = Initiates a wr ite cycl e (The bit is cle ared by hardw are o nce wr ite is co mplet e. The WR b it ca n only
be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in
software.)
0 = Does not initiate a memory read
Note 1: PIC16F685/PIC16F689/PIC16F690 only.
REGISTER 10-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER(1) (CONTINUED)
PIC16F631/677/685/687/689/690
DS40001262F-page 120 2005-2015 Microchip Technology Inc.
10.1.2 READING THE DATA EEPROM
MEMORY
To read a dat a memory location , the user must write the
address to the EEADR register, clear the EEPGD
control bit of the EECON1 register, and th en set co ntrol
bit RD. The data is available at the very next cycle, in
the EEDA T register; therefore, it can be read in the next
instruction. EEDAT will hold this value until another
read or until it is written to by the user (during a write
operation).
EXAMPLE 10-1: DATA EEPROM READ
10.1.3 WRITING TO THE DATA EEPROM
MEMORY
To write an EEPROM data location, the user must first
wri te t he addres s to the EE ADR regi ster and t he data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the specific sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit wil l not af fect this wr ite cycle. T he WR bit wil l
be inhib ited from bei ng s et unless the W R EN bit is se t.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
EXAMPLE 10-2: DATA EEPROM WRITE
BANKSEL EEADR ;
MOVF DATA_EE_ADDR, W;
MOVWF EEADR ;Data Memory
;Address to read
BANKSEL EECON1 ;
BCF EECON1, EEPGD;Point to DATA memory
BSF EECON1, RD ;EE Read
BANKSEL EEDAT ;
MOVF EEDAT, W ;W = EEDAT
BANKSEL PORTA ;Bank 0
BANKSELEEADR ;
MOVFDATA_EE_ADDR, W;
MOVWFEEADR ;Data Memory Address to write
MOVFDATA_EE_DATA, W;
MOVWFEEDAT ;Data Memory Value to write
BANKSELEECON1 ;
BCF EECON1, EEPGD;Point to DATA memory
BSF EECON1, WREN;Enable writes
BCF INTCON, GIE ;Disable INTs.
BTFSCINTCON, GIE;SEE AN576
GOTO$-2
MOVLW55h ;
MOVWFEECON2 ;Write 55h
MOVLWAAh ;
MOVWFEECON2 ;Write AAh
BSF EECON1, WR ;Set WR bit to begin write
BSF INTCON, GIE ;Enable INTs.
SLEEP ;Wait for interrupt to signal write complete (optional)
BCF EECON1, WREN;Disable writes
BANKSEL0x00 ;Bank 0
Required
Sequence
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10.1.4 READING THE FLASH PROGRAM
MEMORY (PIC16F685/PIC16F689/
PIC16F690)
To read a program memory location, the user must
write the Least an d Most Si gnific ant add ress bit s to the
EEADR and EEADRH registers, set the EEPGD con-
trol bit of th e EEC ON 1 reg ist er, and then s et c ont rol b it
RD. Once the read cont rol bit is set, the program mem-
ory Flash controller will use the second instruction
cycle to read th e data . Th is ca us es the seco nd ins tru c-
tion immediately following the “BSF EECON1,RD”
instruction to be ignored. The data is available in the
very ne xt cycle, in the EEDAT and EEDATH regist ers;
therefore, it can be read as two bytes in the following
instructions.
EEDAT and EEDATH registers will hold this value until
another read or until it is written to by the user.
EXAMPLE 10-3: FLASH PROGRAM READ
Note 1: The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction
af ter the RD bit is set.
2: If the WR bit is set when EEPGD = 1, it
will be immediately reset to ‘0’ and no
operation will take place.
BANKSEL EEADR ;
MOVF MS_PROG_EE_ADDR, W ;
MOVWF EEADRH ;MS Byte of Program Address to read
MOVF LS_PROG_EE_ADDR, W ;
MOVWF EEADR ;LS Byte of Program Address to read
BANKSELEECON1 ;
BSF EECON1, EEPGD ;Point to PROGRAM memory
BSF EECON1, RD ;EE Read
;
NOP ;First instruction after BSF EECON1,RD executes normally
NOP ;Any instructions here are ignored as program
;memory is read in second cycle after BSF EECON1,RD
;BANKSELEEDAT ;
MOVF EEDAT, W ;W = LS Byte of Program Memory
MOVWF LOWPMBYTE ;
MOVF EEDATH, W ;W = MS Byte of Program EEDAT
MOVWF HIGHPMBYTE ;
BANKSEL0x00 ;Bank 0
Required
Sequence
PIC16F631/677/685/687/689/690
DS40001262F-page 122 2005-2015 Microchip Technology Inc.
FIGURE 10-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Table 0-1:
Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4
BSF EECON1,RD
execut ed her e INSTR(PC + 1)
executed here Forced NOP
execut ed her e
PC
PC + 1 EEADRH,EEADR PC+3 PC + 5
Flash ADDR
RD bit
EEDATH,EEDAT
PC + 3 PC + 4
INSTR (PC + 1)
INSTR(PC - 1)
executed here INSTR(PC + 3)
executed here INSTR(PC + 4)
executed here
Flas h Data
EEDATH
EEDAT
Register
EERHLT
INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)
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10.2 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verifie d (see Example 10-4) to th e
des i red valu e to be writ ten.
EXAMPLE 10- 4: WRITE VERIFY
10.2.1 USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
total number of write cycles to a single byte
(specifications D120 and D120A). If this is the case,
then a refr esh of the array must be per form ed. F or th is
reason, variables that do not change (such as
constants, IDs, calibration, etc.) should be stored in
Flas h prog r am m e m ory.
10.3 Protection Agai nst Spurious W rite
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been buil t in. On power-u p, WREN is cleare d. Also, the
Power-up Timer (64 ms duration) prevents
EEPROM write.
The wri te in iti ate sequence an d the WR EN bi t together
help prevent an acci dental write dur ing:
• Brown-out
•Power Glitch
• Software Malfun ction
10.4 Dat a EEPROM Operat ion During
Code-Protect
Data me mory can be co de-prote cted by pr ogrammi ng
the CPD bit in the Configuration Word register
(Register 14-1) to ‘0’.
When the data memory is code-protected, only the CPU
is able to read and write data to the data EEPROM. It is
recommended to code-protect the program memory
when code-protecting data memory and programming
unused program memory with NOP instructions.
BANKSEL EEDAT ;
MOVF EEDAT, W ;EEDAT not changed
;from previous write
BANKSEL EECON1 ;
BSF EECON1, RD ;YES, Read the
;value written
BANKSEL EEDAT ;
XORWF EEDAT, W ;
BTFSS STATUS, Z ;Is data the same
GOTO WRITE_ERR ;No, handle error
: ;Yes, continue
BANKSEL 0x00 ;Bank 0
PIC16F631/677/685/687/689/690
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TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
EECON1 EEPGD(1) — — — WRERR WREN WR RD x--- x000 0--- q000
EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
EEADR EEADR7(2) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
EEADRH(1) — — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 ---- 0000
EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEDATH(1) —— EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000
PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 0000 ----
PIR2 OSFIF C2IF C1IF EEIF — — — — 0000 ---- 0000 ----
Legend: x = unknown , u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPRO M module.
Note 1: PIC16F685/PIC16F689/PIC16F690 only.
2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
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11.0 ENHANCED CAP TURE/
COMPARE/PWM MODULE
The Enhanced Capture/Compare/PWM module is a
peripheral which allows the user to time and control
different events. In Capture mode, the peripheral
allows the timing of the duration of an event. The
Compare mode allows the user to trigger an external
event when a predetermined amount of time has
expired. The PWM mode can generate a Pulse-Width
Modulated signal of varying frequency and duty cycle.
Table 11-1 shows the timer resources required by the
ECCP module.
TABLE 11-1: ECCP MODE – TIMER
RESOURCES REQUIR ED
ECCP Mode Timer Resource
Capture Timer1
Compare Timer1
PWM Timer2
REGISTER 11-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 P1M<1:0>: PW M Ou tp ut Co nf igu rat ion bits
If CCP1M<3:2> = 00, 01, 10:
xx =P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins
If CCP1M<3:2> = 11:
00 =Sing le ou tpu t; P1 A mo du la ted ; P1B , P1 C, P1 D as sig ne d as port pin s
01 =Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10 =Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11 =Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0 CCP1M<3:0>: EC CP Mod e Se lec t bits
0000 =Capture/Compare/PWM off (resets ECCP module)
0001 =Unused (rese rve d)
0010 =Compare mode, toggle output on match (CCP1IF bit is set)
0011 =Unused (rese rve d)
0100 =Capture mode, every falling edge
0101 =Capture mode, every rising edge
0110 =Capture mode, every 4th rising edge
0111 =Capture mode, every 16th rising edge
1000 =Compare mode, set output on match (CCP1IF bit is set)
1001 =Compare mode, clear output on match (CCP1IF bit is set)
1010 =Co mpar e mode, gener ate sof twa re int erru pt on ma tch (C CP1IF b it is set, CCP1 pin i s un aff ected )
1011 =Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2, and starts
an A/D conversion, if the ADC module is enabled)
1100 =PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 =PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 =PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 =PWM mode; P1A, P1C active-low; P1B, P1D active-low
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11.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit val ue of the TMR1 register when an event occu rs
on pin CCP1. An event is defined as one of the
following and is configured by the CCP1M<3:0> bits of
the CCP1CON register:
• Every falling edge
• Every rising edge
• Ever y 4th rising edge
• Every 16th rising edge
When a cap ture i s m ade, the I nterrupt Re quest Flag bit
CCP1IF of the PIR1 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPR1H, CCPR1L register pair
is read, the old captured value is overwritten by the new
captured value (see Figure 11-1).
11.1.1 CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit.
FIGURE 11-1: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
11.1.2 TIMER1 MODE SELECTION
T imer1 must be running in T imer mode or Synchroni zed
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
11.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE i nterrupt en able bit of the PIE1 regis ter clear to
avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR1 register
following any change in operating mode.
11.1.4 CCP PRESCALER
There are four prescaler settings specified by the
CCP1M<3:0> bits of the CCP1CON register.
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCP1CON register before changing the
prescaler (see Example 11-1).
EXAMPLE 11-1: CHANGING B ETWEE N
CAPTURE PRESCALERS
Note: If the C CP1 pin is co nfigured as an output,
a write to the port can cause a capture
condition.
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF
(PIR1 reg ister )
Capture
Enable
CCP1CON<3:0>
Prescaler
1, 4, 16
and
Edge Detect
pin
CCP1
System Clock (FOSC)
BANKSEL CCP1CON ;Set Bank bits to point
; to CCP1CON
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
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11.2 Compare Mode
In C ompare mo de, t he 16 -bit CC PR1 r egist er va lue is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP module may:
• To ggle the CC P1 ou tput
• Set the CCP1 output
• Clear the CCP1 output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register.
All Compare modes can generate an interrupt.
FIGURE 11-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
11.2.1 CCP1 PIN CONFIGURATION
The user m us t co nfi gure the C CP 1 pin a s an out put b y
clearing the associated TRIS bit.
11.2.2 TIMER1 MODE SELECTION
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
11.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP module does not
assert control of the CCP1 pin (see the CCP1CON
register).
11.2.4 SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP module does the
following:
• Resets Timer1
• Starts an ADC conver sion if ADC is enabl ed
The CCP module does not assert control of the CCP1
pin in this mode (see the CCP1CON register).
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L
register pair. The TMR1H, TMR1L register pair is not
reset until th e next r ising ed ge of the T imer1 clock. This
allows the CCPR1H, CCPR1L register pair to
effectively provide a 16-bit programmable period
register for Timer1.
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the port I/O
data l atch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set CCP1IF Interrupt Flag
(PIR1)
Match
TRIS
CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special Event T rigger will:
• Clear TMR1H and TMR1L registers.
• NOT set interrupt flag bit TMR1IF of the PIR1 register.
• Set the GO/DONE bit to start the ADC conversion.
CCP1 4
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 registe r.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.
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11.3 PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCP1 pin. The duty cycle, period and
resolution are determined by the following registers:
•PR2
•T2CON
• CCPR1L
• CCP1CON
In Pulse-Width Modulation (PWM) mode, the CCP
module produce s up to a 10 -bit resol ution PWM outp ut
on the CCP1 pin. Since the CCP1 pin is multiplexed
with the POR T dat a latch, the TRIS for that pi n must be
cleared to enable the CCP1 pin output driver.
Figure 11-3 shows a simplified block diagram of PWM
operation.
Figure 11-4 shows a typical waveform of the PWM
signal.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 11.3.7
“Setup for PWM Operation”.
FIGURE 11-3: SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM output (Figure 11-4) has a time base
(period) and a time that the output stays high (duty
cycle).
FIGURE 11-4: CCP PWM OUTPUT
Note: Clearing the CCP1CON register will
relinquish CCP1 control of the CCP1 pin.
CCPR1L
CCPR1H(2) (Slave)
Comparator
TMR2
PR2
(1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer2 ,
toggle CCP1 pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
two bits of the prescaler, to create the 10-bit
time base.
2: In PWM mode, CCPR1H is a read-only register .
TRIS
CCP1
Comparator
Period
Pulse Width
TMR2 = 0
TMR2 = CCPR1L:CCP1CON<5:4>
TMR2 = PR2
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11.3.1 PW M PE RIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
EQUATION 11 -1: PWM PERIOD
When TMR 2 is equal t o PR2, the following three event s
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is se t. (Ex cep tio n: If t he PWM du ty
cycle = 0%, the pin will not be set.)
• The PWM duty cycl e is lat ched from CCP R1L into
CCPR1H.
11.3.2 PWM DUTY CYCL E
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
DC1B<1:0> bits of the CCP1CON register. The
CCPR1L contains the eight MSbs and the DC1B<1:0>
bits of the CCP1CON register contain the two LSbs.
CCPR1L and DC1B<1:0> bits of the CCP1CON
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
register is read-only.
Equation 11-2 is used to calculate the PWM pulse
width.
Equation 11-3 is used to calculate the PWM duty cy cl e
ratio.
EQUATION 11-2: PUL SE WIDTH
EQUATION 11-3: DUTY CYCLE RATIO
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is essential for glitchl ess PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the T imer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR1H and
2-bit latch, then the CCP1 pin is cleared (see Figure 11-
3).
11.3.3 PWM RES O LUTION
The res olution de termines the number of avai lable dut y
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolu ti on will re su lt in 256 di sc re te duty cycl es .
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 11-4.
EQUATION 11-4: PWM RESOLUTION
TABLE 11-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
Note: The Timer2 postscaler (see Section 7.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
PWM Period PR21+4TOSC =
(TMR2 Prescale Value)
Note: TOSC = 1/FOSC
Note: If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
Pulse Width CCPR1L:CCP1CON<5:4>
=
TOSC
(TMR2 Prescale Value)
Duty Cycle Ratio CCPR1L:CCP1CON<5:4>
4PR2 1+
-----------------------------------------------------------------------=
Resolution 4PR2 1+log
2log
------------------------------------------ bits=
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6
PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resol ution ( bits) 8 8 8 6 5 5
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11.3.4 OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the st ate of the module will not change. If the CCP1
pin is dri ving a value , it wi ll cont inue to d rive th at valu e.
When the device wakes up, TMR2 wil l continue from it s
previous state .
11.3.5 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 3.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
11.3.6 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
11.3.7 SE TUP F OR PWM OP ERA TIO N
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pin (CCP1) output driver by
setting the associated TRIS bit.
2. Set the PWM period by loading the PR2 register .
3. Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
4. Set the PWM duty cycle by loading the CCPR1L
register and DC1B<1:0> bits of the CCP1CON
register.
5. Configure and start Timer2:
•Clear the TMR2IF interrupt flag bit of the PIR1
register.
•Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
•Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Enable PWM ou tput after a new PWM cycle has
started:
•Wait until Timer2 overflows (TMR2IF bit of the
PIR1 regist er is set).
• Enable the CCP 1 pin outp ut dri ver by clea ring
the associated TRIS bit.
11.4 PWM (Enhanced Mode)
The Enhanced PWM Mode can generate a PWM signal
on up to four different output pins with up to ten bits of
resolution. It can do this through four different PWM
Output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be se t appropriately.
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CC P1CON register appropriately.
Table 11-4 shows the pin assignments for each
Enhanced PWM mode.
Figure 11-5 shows an example of a simplified block
diagram of the Enhanced PWM module .
Note: To prevent the generation of an
incomplete waveform when the PWM is
first enab led, the ECCP mo dule wait s until
the start of a new PWM period before
generating a PWM signal.
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FIGURE 11-5: EXAMPLE SIMPLIFI ED B LOCK DIA GRAM O F T HE E NH ANCED PWM MO DE
TABLE 11-4: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
RQ
S
Duty Cycle Registers DC1B<1:0>
Clear Timer2,
toggle PWM pin and
latch duty cycle
Note 1: The 8-b i t tim er T MR2 re gister is con c ate na ted wi th the 2- bit i nte rna l Q clock, or 2 bits of the p res caler to cr eate the 10- bi t
time base.
TRIS
CCP1/P1A
TRIS
P1B
TRIS
P1C
TRIS
P1D
Output
Controller
P1M<1:0> 2CCP1M<3:0>
4
PWM1CON
CCP1/P1A
P1B
P1C
P1D
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions
ECCP Mode P1M<1:0> CCP1/P1A P1B P1C P1D
Single 00 Yes(1) Yes(1) Yes(1) Yes(1)
Half-Bridge 10 Yes Yes No No
Full-Bridg e, Forward 01 Yes Yes Yes Yes
Full-Bridg e, Reve rse 11 Yes Yes Yes Yes
Note 1: Pulse Steering enables outputs in Single mode.
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FIGURE 11-6: EXAMP LE PW M (ENHANCED MODE) OUTPUT RELATIONSHIP S (ACTIVE-HIGH
STATE)
0
Period
00
10
01
11
Signal PR2+1
P1M<1:0>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Pulse
Width
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Peri od = 4 * TOSC * (PR2 + 1) * (TM R2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay
mode”).
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FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIP S (ACTIVE-LOW STATE)
0
Period
00
10
01
11
Signal PR2+1
P1M<1:0>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inact ive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inact ive
Pulse
Width
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Peri od = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay
mode”).
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11.4.1 HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull lo ads. The PWM out put s ign al is o utp ut
on the C CP1/P1 A pin, whi le the co mpleme ntary PWM
outp ut signa l is out put on t he P1B pin ( see Figure 11-
6). This mode ca n be used for Half-Bridge applications ,
as shown in Figure 11-9, or for Full-Bridge a pplications ,
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in Half-
Bridge power devices. The value of the PDC<6:0> bits of
the PWM1CON register sets the number of instruction
cycles before the output is driven active. If the value is
greater than the duty cycle, the corresponding output
remains inactive during the entire cycle. See
Section 11.4.6 “Programmable Dead-Band Delay
mode” for more details of the dead-band delay
operations.
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
FIGURE 11-8: EXAMPLE OF HALF-
BRIDGE PWM OUTPUT
FIGURE 11-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS
Period
Pulse Width
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, t he TMR2 reg ister is equal to t he
PR2 register.
2: Output signals are shown as active-high.
P1A
P1B
FET
Driver
FET
Driver
Load
+
-
+
-
FET
Driver
FET
Driver
V+
Load
FET
Driver
FET
Driver
P1A
P1B
Standard Half-Bridge Circuit (“Push-P ull”)
Half-Bridge Output Driving a Full-Bridge Circuit
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11.4.2 FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs.
An example of Full-Bridge application is shown in
Figure 11-10.
In the Forward mode, pin CCP1/P1A is driven to its active
state, p in P1 D is m odul ated, whil e P1B and P1C will be
driven to their inactive state as shown in Figure 11-11.
In the Reverse mode, P1C is driven to its active state,
pin P1B is modulated, while P1A and P1D wi l l be dri ven
to their inactive state as shown Figure 11-11.
P1A, P1B, P1C and P1D outputs are multiplexed with
the POR T dat a latc hes. The a ssoc iated T RIS bit s mus t
be cleared to configure the P1A, P1B, P1C and P1D
pins as outputs.
FIGURE 11-10: EXAMPLE OF FULL-BRID GE APPLICA TION
P1A
P1C
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
P1B
P1D
QA
QB QD
QC
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FIGURE 11-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Period
Pulse Width
P1A(2)
P1B(2)
P1C(2)
P1D(2)
Forw a r d M o de
(1)
Period
Pulse Width
P1A(2)
P1C(2)
P1D(2)
P1B(2)
Reverse Mode
(1)
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as active-high.
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11.4.2.1 Direction Change in Full-Bridge
Mode
In the Full-Bridge mode, the P1M1 bit in the CCP1CON
register allows users to control the forward/reverse
direction. When the application firmware changes this
direction co ntrol bit, the modu le will change to the new
direction on the next PWM cycle.
A direction change is initiated in software by changing
the P1M1 bit of the CCP1CON register. The following
sequence occurs prior to the end of the current PWM
period:
• The modulate d outputs (P 1B and P1D) are placed
in their inactive state.
• The associated unmodulated outputs (P1A and
P1C) are switched to drive in the opposite
direction.
• PWM modulati on resumes at the begin nin g of the
next period.
See Figure 11-12 for an illustration of this sequence.
The Full-Bridge mode does not provide dead-band
delay. As one outpu t is modulated at a tim e, dead-band
delay is generally not required. There is a situation
where dead-band delay is required. This situation
occurs when both of the following conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on tim e.
Figure 11-13 shows an example of the PWM direction
chan gi ng from for w ar d to rev ers e , at a ne ar 100% duty
cycle. In this example, at time t1, the output P1A and
P1D become inactive, while output P1C becomes
active. Since the turn-off time of the power devices is
longer than the turn-on time, a shoot-through current
will flow through power devices QC and QD (see
Figure 11-10) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM di rec t io n ch an ge from reve rs e to forwa r d.
If changing PWM direction at high duty cycle is required
for an app lication, two possible solutions f or eliminatin g
the shoot-through current are:
1. Reduce PWM duty cycle for one PWM period
before changing directions.
2. Use switch drivers that can drive th e switches of f
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 11-12: EXAMPLE OF PWM DIRECTION CHANGE
Pulse Width
Period(1)
Signal
Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM c ycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is (1/Fosc) TMR2 prescale
value.
Period
(2)
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
P1D (Active-High)
Pulse Width
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FIGURE 11-13: EXAMPL E OF PWM DIRECT ION CHANGE AT NEAR 100% DUTY CYCLE
11.4.3 START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
The CCP1M<1:0> bits of the CCP1CON register allow
the us er t o ch oose whe the r th e P WM output si gna ls are
active-high or active-low for each pair of PWM output pins
(P1A/P1C and P1B/P1D). The PWM output polarities
must be selecte d bef ore the PWM pi n output driv ers ar e
enabled. Changing the polarity configuration while the
PWM pin output drivers are enabled is not recommended
since it may result in damage to the application circuits.
The P1A, P1B, P1C and P1D ou tput latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the applic ati on circuit. The Enhanced PWM
modes must be enabled in the proper Outp ut mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMR2IF bit of the PIR1 register
being set as the second PWM period begins.
Forward Period Reverse Period
P1A
TON
TOFF
T = TOFF – TON
P1B
P1C
P1D
External Switch D
Potential
Shoot-Through Current
Note 1: All signals are shown as active-high.
2: TON is the turn-on delay of power switch QC and its driver.
3: TOFF is the turn-off delay of power switch QD and its driver.
External Switch C
t1
PW
PW
Note: When the mi crocon troller is r eleas ed fr om
Reset, all of the I/O pins are in the high-
impedance state. The external circuits
must ke ep the power s witch devices in the
OFF state until the microcontroller drives
the I/O pins with the proper signal levels or
activates the PWM output(s).
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11.4.4 ENHANCED PWM AUTO-
SH UTDOWN MODE
The PWM mode supports an Auto-Shut down m ode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
The auto-shutdown sources are selected using the
ECCPASx bits of the ECCPAS register. A shutdown
event may be generated by:
•A logic ‘0’ on the INT pin
• Comparator C1
• Comparator C2
• Setting the ECCPASE bit in firmware
A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCPAS
register. If the bit is a ‘0’, th e PWM p ins a re op erati ng
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
When a shutdow n event oc curs, two things ha ppen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 1 1.4.5 “Auto-Restart Mode”).
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSSAC and
PSSBD bits of the ECCPAS register. Each pin pair may
be placed into one of three st ates:
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
FIGURE 11-14: AUTO-SHUTDOWN BLOCK DIAGRAM
PSSAC<1>
TRISx P1A
0
1
P1A_DRV
PSSAC<0>
PSSBD<1>
TRISx P1B
0
1
PSSBD<0>
P1B_DRV
PSSAC<1>
TRISx P1C
0
1
PSSAC<0>
P1C_DRV
PSSBD<1>
TRISx P1D
0
1
PSSBD<0>
P1D_DRV
000
001
010
011
100
101
110
111
Fro m Comparator C2
From Comparator C1
ECCPAS<2:0>
R
DQ
S
ECCPASE
From Data Bus
Write to ECCPASE
PRSEN
INT
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REGISTER 11-2: ECCPAS: ENHANCED CAPTURE/C OMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating
bit 6-4 ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits
000 =Auto-Shutdown is disabled
001 =Comparat or C1 output high
010 =Comparat or C2 output high(1)
011 =Either Comparators output is high
100 =VIL on INT pin
101 =VIL on INT pin or Compara tor C1 output high
110 =VIL on INT pin or Compara tor C2 output high
111 =VIL on INT pin or either Comparators output is high
bit 3-2 PSSACn: Pins P1A and P1C Shutdown State Control bits
00 = Drive pins P1A and P1C to ‘0’
01 = Drive pins P1A and P1C to ‘1’
1x = Pins P1A and P1C tri-state
bit 1-0 PSSBDn: Pins P1B and P1D Shutdown State Control bits
00 = Drive pins P1B and P1D to ‘0’
01 = Drive pins P1B and P1D to ‘1’
1x = Pins P1B and P1D tri-state
Note 1: If C2SYNC is enabled, the shutdown will be delayed by Timer1.
Note 1: The auto-shutdown condition is a level-
based signal, not an edge-based signal.
As long as the level is present, the auto-
shutdown will persist.
2: Writing to the ECCPASE bit is disabled
while an auto-shutdown condition
persists.
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
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FIGURE 11-15: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
11.4.5 AUTO-RESTART MODE
The Enhanced PWM can be configured to automati-
cally restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PRSEN bit in the PWM1CON register.
If auto-restart is enabled, the ECCPASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
ECCPASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 11-16: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs Shutdown
Event Clears PWM
Resumes
PWM Period
Start of
PWM Period
ECCPASE
Cleared by
Firmware
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs Shutdown
Event Clears PWM
Resumes
PWM Period
Start of
PWM Period
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11.4.6 PROGRAMMABLE DEAD-BAN D
DELAY MODE
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If b oth the u pper and lowe r power swit ches ar e
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
During this brief interval, a very high current (shoot-
through c urre nt) wi ll flow throu gh bot h po w er s witc hes ,
shorting the bridge supply. To avoid this potentially
destructive shoot-through current from flowing during
switching, turning on either of the power switches is
normally delayed to allow the other switch to
completely tu rn off.
In Half-Bridge mode, a digitally programmable dead-
band delay is available to avoid shoot-through current
from destroying the bridge power switches. The delay
occurs at the si gnal tra nsition fro m the no n-acti ve st ate
to the active state. See Figure 11-8 for il lust r at io n . The
lower sev en b it s of th e as s oci ate d PWM 1CO N reg ist er
(Register 11-3) sets the delay period in terms of
microcontroller instr uction cycl es (TCY or 4 TOSC).
FIGURE 11-17: EXAMPLE OF HALF-
BRIDGE PWM OUTPUT
FIGURE 11-18: EXAMPL E OF HALF-BRIDGE APPLICATIONS
Period
Pulse Width
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
P1A
P1B
FET
Driver
FET
Driver
V+
V-
Load
+
V
-
+
V
-
Standard Half-Bridge Circuit (“Push-P ull”)
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REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PRSEN: PWM Rest art Enab le bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0 PDC<6:0>: PWM Delay Count bits
PDCn =Number of FOSC/4 (4 * TOSC) cycles be tween the sc heduled ti me when a PWM si gnal should
transition active and the actual time it transitions active
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11.4.7 PULSE STEERING MODE
In Sing le Output mode, pul se steering all ows any of the
PWM pins to be t he modulated sig nal . Addi tionally, the
same PWM signal can be simultaneously available on
multiple pins.
Once the Single Output mode is selected
(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits of the
PSTRCON register, as shown in Figure 11-19.
While th e PWM Steerin g m ode is ac ti ve, C CP1M <1:0 >
bits of the CCP1CON register select the PWM output
polarity for the P1<D:A> pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 11.4.4
“Enhanced PWM Auto-shutdown mode”. An auto-
shutdown event will only affect pins that have PWM
outputs enabled.
Note: The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order t o see the PWM signa l on th e pin.
REGISTER 11-4: PSTRCON: PULSE STEERING CONTROL REGISTER(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — STRSYNC STRD STRC STRB STRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 STRSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3 STRD: S t eeri ng Enab le bit D
1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1D pin is assigned to port pin
bit 2 STRC: S t eeri ng Enab le bit C
1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1C pin is assigned to port pin
bit 1 STRB: S t eeri ng Enab le bit B
1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1B pin is assigned to port pin
bit 0 STRA: S t eeri ng Enab le bit A
1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1A pin is assigned to port pin
Note 1: The PWM Steeri ng mode is av ailable only when th e CCP1CON re gister bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.
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FIGURE 11-19: SIMPL I FI ED STEE R ING
BLOCK DIAGRAM
1
0TRIS
P1A pin
PORT Data
P1A Signal
STRA
1
0TRIS
P1B pin
PORT Data
STRB
1
0TRIS
P1C pin
PORT Data
STRC
1
0TRIS
P1D pin
PORT Data
STRD
Note 1: Port outputs are configured as shown when
the CCP1CON register bits P1M<1:0> = 00
and CCP1M<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
CCP1M1
CCP1M0
CCP1M1
CCP1M0
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11.4.7.1 S teering Synchronization
The STRSYNC bit of the PSTRCON register gives the
user two selections of when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRCON register. In this case, the
output signal at the P1<D:A> pins may be an
incomplete PWM waveform. This operation is useful
when the user firmware needs to immediately remove
a PWM signal from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures 11-20 and 11-21 illustrate the ti ming diagram s
of the PWM steering depending on the STRSYNC
setting.
FIGURE 11-20: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
FIGURE 11-21: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION
(STRSYNC = 1)
PWM
P1n = PWM
STRn
P1<D:A> PO RT Da ta
PWM Period
PORT Data
PWM
PORT Data
P1n = PWM
STRn
P1<D:A> PORT Data
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TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMP ARE AND PWM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Valu e on
all other
Resets
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000
CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000
CM2CON1 MC1OUT MC2OUT — — — —T1GSSC2SYNC 00-- --10 00-- --10
CCPR1L Capture/Compare/PW M Register 1 Low Byte xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PW M Register 1 High Byte xxxx xxxx uuuu uuuu
ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
PSTRCON — — — STRSYNC STRD STRC STRB STRA ---0 0001 ---0 0001
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR2 T imer2 Module Register 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture,
Compare and PWM.
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12.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These device s typ icall y do n ot have inter nal cl ocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
The EUSART m odule includes the follow ing capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character out put buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex sync hron ous mas ter
• Half-duplex sync hron ous slav e
• Programmable clock polarity in synchronous
modes
• Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automa tic detection and c alibration of the baud rate
• Wake-up on Break recepti on
• 13-bit Break character trans m it
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 12-1 and Figure 12-2.
FIGURE 12-1: EUSART TRANSMIT BLOCK DIAGRAM
TXIF
TXIE
Interrupt
TXEN
TX9D
MSb LSb
Data Bus
TXREG Register
Transmit Shift Register (TSR)
(8) 0
TX9
TRMT SPEN
TX/CK pin
Pin Buffer
and Control
8
SPBRG
SPBRGH
BRG16
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 1X00 0
BRGH X110 0
BRG16 X101 0
Baud Rate Generator
•••
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FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These registers are detailed in Register 12-1,
Register 12-2 an d Register 12-3, respectively.
RX/DT pin
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR
FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt
RCIF
RCIE
Data Bus
8
Stop START
(8) 7 1 0
RX9
• • •
SPBRGSPBRGH
BRG16
RCIDL
FOSC ÷ n
n
+ 1 Multiplier x4 x16 x64
SYNC 1X00 0
BRGH X110 0
BRG16 X101 0
Baud Rate Generato r
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12.1 EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output l evel of that bit wi thout returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eig ht
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 12-5
for examples of baud rate configurations.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
indepen dent, but share th e sa me dat a format and bau d
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data b it.
12.1.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 12-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
12.1.1.1 Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
•TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCST A register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
12.1.1.2 Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then tran sferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the S tart bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
12.1.1.3 Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new char acter ha s been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execut ion. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE i nterrupt en able bi t upon w riting the last charact er
of the transmission to the TXREG.
Note 1: When the SPEN bit is set the RX/DT I/O
pin is automatically configured as an input,
regardless of the state of the correspond-
ing TRIS bit and whether or not the
EUSART receiver is enabled. The RX/DT
pin data can be read via a normal PORT
read but PORT latch data output is pre-
cluded.
2: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
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12.1.1.4 T SR Status
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
12.1.1.5 Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
EUSAR T will shift nine bits out for each character trans-
mitted. Th e TX9D bit of the TXSTA register is the nint h,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the eigh t Leas t Signi ficant bit s into the TXRE G. All nin e
bits of d ata wi ll be tran sfer red to th e TSR shift regist er
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 12.1.2.7 “Address
Detection” for more in formation on the Addre ss mode.
12.1.1.6 Asynchronous Transmission Set-up:
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 12.3 “EUSART Baud
Rate Generator (BRG)”).
2. Enable the asy nch ron ous seri al port by clearin g
the SYNC bit and setting the SPEN bit.
3. If 9-bit tran sm ission is des ire d, s et th e TX9 con-
trol bit. A set ninth data bit will indicate that the
eight Least Significant data bits are an address
when the receiver is set for address detection.
4. Enable the transmission by setting the TXEN
contr ol bit . Thi s wi ll c aus e th e TXI F i nte rrup t bi t
to be set.
5. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
6. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
7. Load 8-bit data into the TXREG register. This
will start the transmission.
FIGURE 12-3: ASYNCHRONOUS TRANSMISSION
FIGURE 12-4: ASYNCHR ON OUS TR ANSM IS SION (BACK TO BACK)
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
Word 1 S top bit
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
TX/CK
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Tran smi t Sh ift
Reg. Empty Flag)
1 TCY
pin
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Wo rd 2
Word 1 Word 2
Start bit Stop bit Start bit
Transmit Shift Reg
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
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TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Value on
all other
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynch ronous Transmission.
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12.1.2 EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 12-2. The d ata is rec eived on th e RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are imm edi ate ly tran sfe rred to a tw o c har act er Fi rst-In-
First-Out (FIFO) memory. The FIFO buffering allows
receptio n of two compl ete cha rac ters and the s t art of a
third cha rac ter be fore software must start servicing the
EUSART receiver. The FIFO and RSR registers are not
direc tly ac cessible by sof tware. Access to t he re ceived
data is via the RCREG register.
12.1.2.1 Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operatio n by configuring the fol lowing three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCST A register enables the EUSART and automatically
configures the R X/DT I/O pin as an input. If the RX/D T
pin is shared with an analog peripheral the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
12.1.2.2 Receiving Data
The receiver data recovery circuit initiates character
receptio n o n the fallin g edge of the first bit. The f irst bi t,
also known as the Start bit, is always a zero. The data
recovery circuit co unt s one-h alf bi t time to the c enter of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit c ounts a full bit time to the ce nter of the
next bit. The bit is then sampled by a majority detect
circuit and the resultin g ‘0’ or ‘1’ is shif ted into the RS R.
This repeats until all data bits have been sampled and
shif ted into the RSR. One final bit time is measured and
the le ve l samp le d . Thi s is th e Sto p bit , wh ic h is alwa ys
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
charact er , otherwise th e framing error is c leared for thi s
character. See Section 12.1.2.4 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
12.1.2.3 Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSAR T receiver i s enabled an d there is
an unread character in the receive FIFO. The RCIF
interrupt fla g bit is read-o nly, it ca nnot b e set or cl eared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE peripheral interrupt enab le bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread c haracter in the FIFO, regardless of the st ate of
interrupt enable bits.
Note: When the SPEN bit is set the TX/CK I/O
pin is automatically configured as an
output, regardless of the state of the
corresponding TRIS bit and whether or
not the EUSART transmitter is enabled.
The PORT latch is disconnected from the
output dri ver so it is not possible to use the
TX/CK pin as a general purpose output.
Note: If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 12.1.2.5
“Receive Overrun Error” for more
information on overrun errors.
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12.1.2.4 Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indic ates t hat a St op bit w as not seen at the exp ected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represen ts the s ta tus o f the top u nread charac ter in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
12.1.2.5 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun erro r will be generated If a thi rd character, in it s
entirety , is rece ived before the FIFO is accessed. When
this happens the OERR bit o f the RCST A register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
12.1.2.6 R ecei vi ng 9-bit Characters
The EUS ART support s 9-bit c haracter rece ption. When
the RX9 bit of the RCSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
charact er in the recei ve FIFO. When read ing 9- bit dat a
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
12.1.2. 7 Addr ess Detecti on
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
rece iv e FI F O bu ffe r, there by s et t i ng th e R CI F i nte r r up t
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit oc cu rs. W hen user s oftware de tec ts the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
Note: If all receive characters in the receive
FIFO hav e fram ing erro rs, repe ated rea ds
of the RCREG will not clear the FERR bit.
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12.1.2.8 Asynchronous Reception Set-up:
1. Initialize the SPBRGH, SPBRG reg ister pair and
the BRGH and BRG16 bits to achieve the
des i red baud rate (see Section 12.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3. If inter rupts are de sired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
5. Enable reception by setting the CREN bit.
6. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
7. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data b it.
8. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
9. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12.1.2.9 9-bit Address Detection Mode Set-up
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH, SPBRG reg ister pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 12.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4. Enable 9-bit reception by setting the RX9 bit.
5. Enable a ddress d etection by setting the ADDEN
bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will b e gener ated if t he RCIE inte rrupt en able b it
was also set.
8. Read t he R CSTA regi ste r to get the erro r f lags.
The ninth data bit will always be set.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 12-5: ASYNCHRONOUS RECEPTION
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit Start
bit
bit 7/8 Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timin g diagram sho ws three words appearing on the RX input. The RCREG (receive buffer) is r ead after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
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TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Value on
all other
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynch ronous Recept ion.
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12.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block out-
put (INTOSC). However, the INTOSC frequency may
drift as VDD or temperature changes, and this directly
af fects the asynch ronous baud rate. T wo methods ma y
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 3.5
“Internal Clock Modes” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 12.3.1 “Auto-
Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Sync hronous mode
0 = Asy nchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transm ission (cleared by hardware upon completion)
0 = Sync Break transmiss ion completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode :
Unused in this mode
bit 1 TRMT: Trans mit Sh ift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transm it Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
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REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = En ables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Rec eiv e Enab le bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode :
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuou s receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be update d by reading RCREG regi ster and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
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REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER
R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode :
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode :
Don’t care
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous C lock Polarity Select bi t
Asynchronous mode:
1 = Transmit inverted data to the RB7/TX/CK pin
0 = Transmit non-inverted data to the RB7/TX/CK pin
Synchronous mode :
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Gener ator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiv er is waiting fo r a falling ed ge. No charac ter will be received byte R CIF will b e set. WUE will
automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode :
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enab le bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode :
Don’t care
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12.3 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By defau lt, the BRG ope rates in 8-bit mode . Setting th e
BRG16 bit of the BAUDCTL register selects 16-bit
mode.
The SPBRGH, SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXST A
register and the BRG16 bit of the BAUDCTL register. In
Synchronous mode, the BRGH bit is ignored.
Table 12-3 contains the formulas for determining the
baud rate . Example 12-1 provides a s ample calcul ation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 12-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the b aud ra te
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRG register
pair c auses the BRG timer to be reset (or cleared). Thi s
ensures that the BRG do es not wait fo r a timer overf low
before outputting the new baud rate.
If the s ys tem c lo ck is changed duri ng an activ e receive
operation, a receive error or data loss may result. To
avoid thi s problem , check the status of the RCID L bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 12-1: CALCULATIN G B AUD
RATE ERROR
TABLE 12-3: BAUD RATE FORMULAS
TABLE 12-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
For a devi ce w ith FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BR G:
Solving for SPBRGH:SPBRG:
X
FOSC
Desired Baud Rate
---------------------------------------------
64
--------------------------------------------- 1–=
Desired Baud Rate FOSC
64 [SPBRGH:SPBRG] 1+
---------------------------------------------------------------------=
16000000
9600
------------------------
64
------------------------1–=
25.04225 decimal==
Calculated Baud Rate 16000000
64 25 1+
---------------------------=
9615=
Error Calc. Baud Rate Desired Baud Rate –
Desired Baud Rate
--------------------------------------------------------------------------------------------=
9615 9600–
9600
---------------------------------- 0 . 1 6 %==
Configuration Bits BRG/EUSART Mode Ba ud R a te Formula
SYNC BRG16 BRGH
000 8-bit/Asynchronous FOSC/[64 (n+1)]
001 8-bit/Asynchronous FOSC/[16 (n+1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous
FOSC/[4 (n+1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH, SPBRG register pair
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Value on
all other
Resets
BAUDCTL ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
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TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300—— — —— — —— — —— —
1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103
2400 2404 0.16 129 2400 0.00 119 2400 0.00 71 2404 0.16 51
9600 9470 -1.36 32 9600 0.00 29 9600 0.00 17 9615 0.16 12
10417 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 10417 0.00 11
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 — — —
57.6k — — — 57.60k 0.00 7 57.60k 0.00 2 — — —
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 300 0.16 207 300 0.00 191 300 0.16 103 300 0.16 51
1200 1202 0.16 51 1200 0.00 47 1202 0.16 25 1202 0.16 12
2400 2404 0.16 25 2400 0.00 23 2404 0.16 12 — — —
9600 — — — 9600 0.00 5 — — — — — —
10417 10417 0.00 5 — — — 10417 0.00 2 — — —
19.2k — — — 19.20k 0.00 2 — — — — — —
57.6k — — — 57.60k 0.00 0 — — — — — —
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 —— — —— — —— — —— —
1200 — — — — — — — — — — — —
2400 — — — — — — —— —2404 0.16 207
9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19231 0.16 25
57.6k 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
115.2k 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —
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BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 — — — — — — — — — 300 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —
10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.2k 19.23k 0.16 12 19.2k 0.00 11 — — — — — —
57.6k — — — 57.60k 0.00 3 — — — — — —
115.2k — — — 115.2k 0.00 1 — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 299.9 -0.02 1666
1200 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 1199 -0.08 416
2400 2399 -0.03 520 2400 0.00 479 2400 0.00 287 2404 0.16 207
9600 9615 0.16 129 9600 0.00 119 9600 0.00 71 9615 0.16 51
10417 10417 0.00 119 10378 -0.37 110 10473 0.53 65 10417 0.00 47
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 19.23k 0.16 25
57.6k 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 55556 -3.55 8
115.2k 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 300.1 0.04 832 300.0 0.00 767 299.8 -0.108 416 300.5 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 103 1202 0.16 51
2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.16 25
9600 9615 0.16 25 9600 0.00 23 9615 0.16 12 — — —
10417 10417 0.00 23 10473 0.53 21 10417 0.00 11 10417 0.00 5
19.2k 19.23k 0.16 12 19.20k 0.00 11 — — — — — —
57.6k — — — 57.60k 0.00 3 — — — — — —
115.2k — — — 115.2k 0.00 1 — — — — — —
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
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BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 300.0 0.00 6666
1200 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 1200 -0.02 1666
2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832
9600 9597 -0.03 520 9600 0.00 479 9600 0.00 287 9615 0.16 207
10417 10417 0.00 479 10425 0.08 441 10433 0.16 264 10417 0 191
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 19.23k 0.16 103
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 57.14k -0.79 34
115.2k 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 117.6k 2.12 16
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
Actual
Rate %
Error
SPBRG
value
(decimal)
300 300.0 0.01 3332 300.0 0.00 3071 299.9 -0.02 1666 300.1 0.04 832
1200 1200 0.04 832 1200 0.00 767 1199 -0.08 416 1202 0.16 207
2400 2398 0.08 416 2400 0.00 383 2404 0.16 207 2404 0.16 103
9600 9615 0.16 103 9600 0.00 95 9615 0.16 51 9615 0.16 25
10417 10417 0.00 95 10473 0.53 87 10417 0.00 47 10417 0.00 23
19.2k 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 25 19.23k 0.16 12
57.6k 58.82k 2.12 16 57.60k 0.00 15 55.56k -3.55 8 — — —
115.2k 111.1k -3.55 8 115.2k 0.00 7 — — — — — —
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
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12.3.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a receiv ed 55h (ASCII “U ”) which is the Sync charac ter
for the LIN bus. The unique feature of this character is
that it has five rising edges in cluding the S top bit ed ge.
Setting the ABDEN bit of the BAUDCTL register starts
the auto-baud calibration sequence (Figure 12-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 12-6. The fifth rising edge will occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH, SPBRG register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the
SPBRG register did not o verflow by check ing for 00h i n
the SPBRGH register.
The BRG au to-baud clock is d etermined by the BRG1 6
and BRGH bits as shown in Table 12-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
and SPBRG registers are clocked at 1/8th the BRG
base clo ck rate. The resu lting byte meas urement is the
average bit time when clocked at full speed.
TABLE 12-6: BRG COUNTER CLOCK RATES
FIGURE 12-6: AUTOMATIC BAUD RATE CALIBRATION
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 12.3.2 “Auto-Wake-up on
Break”).
2: It is up to the user to determine that the
incoming character baud r ate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the auto-
baud counter starts counting at 1. Upon
completion of the auto-baud sequence, to
achieve maximum accuracy, subtract 1
from the SPBRGH:SPBRG register pair.
BRG16 BRGH BRG Base
Clock BRG ABD
Clock
00FOSC/64 FOSC/512
01FOSC/16 FOSC/128
10FOSC/16 FOSC/128
11 FOSC/4 FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter , independent of BRG16 setting.
BRG Value
RX pin
ABDEN bit
RCIF bit
bit 0 bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Auto Cleared
Set by User
XXXXh 0000h
Edge #1 bit 2 bit 3
Edge #2 bit 4 bit 5
Edge #3 bit 6 bit 7
Edge #4 Stop bit
Edge #5
001Ch
Note 1: The A BD seq uen ce requ ire s the EUSART mo dule to be confi gur ed in Asynchr ono us mod e
SPBRG XXh 1Ch
SPBRGH XXh 00h
RCIDL
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12.3.2 AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controll er to w ake -up due to ac tiv ity on the R X/DT line.
This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCTL regis ter. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a wake-
up event independent of the CPU mode. A wake-up
event consists of a high-to-low transition on the RX/DT
line. (This coincides with the start of a Sync Break or a
wake-up si gnal character fo r the LIN pro toc ol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated s ynchronously to the Q clocks in normal CPU
operating modes (Figure 12-7), and asynchronously if
the device is in Sleep mode (Figure 12-8). The interrupt
condition is cleared by read ing the R CREG regis ter.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
12.3.2.1 Special Considerations
Brea k Charact er
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
receive d, the low time from the S tart bit to the first ris ing
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the ini tial cha racter in the transmi ssion mus t
be all ‘0’s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Startup Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval , to allow eno ugh ti me fo r the se lecte d osc illat or
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before set ting the WU E bit. If a recei ve opera tion is n ot
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
FIGURE 12-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2Q3 Q4Q1 Q2Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2 Q3Q4
OSC1
WUE bit
RX/DT Line
RCIF
Bit set by user Auto Cleared
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
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FIGURE 12-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
12.3.3 BREAK CHARACTER SEQUENCE
The EUSART module has t he c apabili ty of s en din g th e
special Break chara cter sequ ences that are required by
the LIN bus standard. A Break character consists of a
Start bit, follow ed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character trans-
mission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware af ter
the correspon din g Stop b it is s ent . Th is al lows the us er
to preloa d the trans mit FIFO with the n ext transm it byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or Idle, jus t as it does during
normal transmission. See Figure 12-9 for the timing of
the Break character sequence.
12.3.3.1 Br ea k and Sync Trans mit Seque nce
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desir ed mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transm it FIFO buf f er.
5. After the Break has been se nt, the SEND B bit is
reset by hardware and the Sync character is
then transm itte d.
When the TXREG bec om es empty, as indi cated by th e
TXIF, the next data byte can be written to TXREG.
12.3.4 RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Rece ived dat a
as indicated by RCREG. The Baud Rate Generator is
assum ed to ha ve been initi ali ze d to the exp e ct ed bau d
rate.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 12.3.2 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interru pt, and recei ve th e n ex t d at a by te fol lowe d
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCTL register before placing the EUSART in
Sleep mode.
Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3Q4Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4
OSC1
WUE bit
RX/DT Line
RCIF
Bit Set by User Auto Clear ed
Cleared due to User Read of RCREG
Sleep Command Executed
Note 1
Note 1: If the wake-up even t requires long o scillator warm-u p time, the a utomatic cle aring of the WUE bit can o ccur while th e stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
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FIGURE 12-9: SEND BREAK CHARACTE R SEQUENCE
Write to TXREG Dummy Write
BRG Output
(Shift Clock)
S tart bit bit 0 bit 1 bit 11 S top bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TX (pin)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
SENDB Sam ple d Here Auto Cleared
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12.4 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuit ry for b aud rate ge neration and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a bidi-
rectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
Start and Stop bits are not used in synchronous
transmissions.
12.4.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for Synchronous Master operation:
• SYNC = 1
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the de vi c e f or sy n ch ronous operation. Sett ing t he C SR C
bit of the TXSTA register co nfigures t he device a s a mas-
ter . Clearing the SREN and CREN bits of the RCST A reg-
ister ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSAR T. If the RX/DT or TX/CK pi ns are shared with an
analog peripheral the analog I/O functions must be
disab le d by c le ar ing t he c orre s pon di ng ANSEL bits.
12.4.1.1 Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmit s the c lock on the TX/CK lin e.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the le ading edg e to ensure they are v alid at the trail-
ing edge of each clock. One clock cycle is generated
for each data bit. Only as many clock cycles are
generated as there are data bits.
12.4.1.2 Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCTL register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cle ared, the da ta ch anges on the rising
edge of each clock.
12.4.1.3 Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/C K pi n outp ut driv ers ar e aut oma t-
ically enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG reg is ter. If the TSR st ill co ntains al l or part of a
previous character the new character dat a is held in the
TXREG until the last bit of the previous character has
been tr ansmitted. If this i s the first charac ter , or the pre-
vious character has been completely flushed from the
TSR, the d ata in th e TXREG is im mediatel y transferre d
to the TSR. The transmission of the character com-
mences immediately following the transfer of the data
to the TSR from the TXREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
12.4.1.4 Synchronous Master Transmission
Set-up:
1. Initialize the SPBRGH, SPBRG reg ister pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 12.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. S tart transmission by loading data to the TXREG
register.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
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FIGURE 12-10: SYNCHRONOUS TRANSMISSION
FIGURE 12-11: SYNCHRONOUS TRANSM ISSION (THROUGH TXEN)
TABLE 12-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Value on
all other
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.
bit 0 bit 1 bit 7
Word 1 bit 2 bit 0 bit 1 bit 7
RX/DT
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bi t
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
pin
TX/CK p in
TX/CK pin
(SCKP = 0)
(SCKP = 1)
RX/DT pin
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bi t
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12.4.1.5 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSAR T is config ured fo r synch ronous master receiv e
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character . The SREN bit is automatically cleared
at the com pletio n of one c har acter. When CREN is se t,
clocks are continuously generated until CREN is
cleared . If CREN is cleared in the middle of a c haracter
the CK clo ck sto p s imm ed iat ely and t he p a rtia l charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cl eared at the co mpletion of the first cha racter
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
receive d into the RSR, the RCI F bit is set and the ch ar-
acter is automatically transferred to the two character
receive FIFO. The Least Sign ificant e ight bit s of the to p
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are un-read
characters in the receive FIFO.
12.4.1.6 Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous wi th the data. A device configured
as a slave receives the cloc k on the TX/CK line . The TX/
CK pin output driver is automatically disabled when the
device is configured for synchronous slave transmit or
receive operation. Serial dat a bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One data bit is transferred for each clock cycle.
Only as many clock cycles should be received as there
are data bits.
12.4.1.7 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be genera ted if a th ird charac ter , in it s
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be recei ved until the erro r is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then th e error conditi on is cleared b y either clearin g
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
12.4.1.8 Receiving 9-bit Characters
The EUSAR T support s 9-bit chara cter receptio n. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
charact er i n t he rec eiv e FIFO . Whe n r ead ing 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
12.4.1.9 Synchronous Master Reception Set-
up:
1. Initialize the SPBRGH, SPBRG register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set bit RX9.
6. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
7. Interrupt fla g bit RCIF will be se t when receptio n
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register o r by clearing the SPEN bit which res ets
the EUSART.
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FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Value on
all other
Resets
BAUDCTL ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)
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12.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TX STA regist er configures the d evice as a slave.
Clearing the SREN and CREN bits of the RCST A register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
12.4.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes are identical (see Section 12.4.1.3
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The seco nd word will rem ain in TXRE G registe r .
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5. If the PEIE and TXIE bits are set, the interrupt
will wa ke the dev ice from Sleep and e xecute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
12.4.2.2 Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the CREN and SREN bits.
3. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant eight bits to the TXREG register.
TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Value on
all other
Resets
BAUDCTL ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave T r ansmission.
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12.4.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 12.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
nev er Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is rec eived, th e RSR regist er will tran sfer the da ta
to the RCREG register . If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
12.4.2.4 Synchronous Slave Reception Set-
up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
3. If 9-bit reception is desired, set the RX9 bit.
4. Set the CREN bit to enable reception.
5. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
6. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
7. Retrieve t he eig ht Leas t Sign ifican t bit s from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register o r by clearing the SPEN bit which res ets
the EUSART.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Value on
all other
Resets
BAUDCTL ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 01-0 0-00 01-0 0-00
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
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12.5 EUSART Operation During Sleep
The EUSART WILL remain active during Sleep only in
the Synchronous Slave mode. All other modes require
the system clock and therefore cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally genera ted
clock to run the Transmit and R eceive Shift registers.
12.5.1 SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configu red for Synchron ous Slav e Receptio n (see
Section 12.4.2.4 “Synchronous Slave
Reception Set-up:”).
• If interrupts are d esired, s et the RCI E bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• The RCIF interrupt flag must be cleared by read-
ing RCREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has b een c om ple tely
clocked in by the external device, the RCIF interrupt
flag bi t of th e PIR1 regis ter will be s et. The reb y, wakin g
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE Global
Interrupt Enable bit of the INTCON register is also set,
then the Interrupt Service Routine at address 004h will
be called.
12.5.2 SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Transmission
(see Section 12.4.2.2 “Synchronous Slave
Transmission Set-up:”).
• The TXIF interru pt flag must be c leared by w riting
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
9. If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
• Interrupt enable bits T XIE of the PIE1 re gister an d
PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE Global
Interrupt Enable bit is also set then the Interrupt
Service Routine at address 0004h will be called.
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13.0 SSP MODULE OVERVIEW
The Synchronous Serial Port (SSP) module is a serial
interface used to communicate with other peripheral or
microcontroller devices. These peripheral devices
may be serial EEPROMs, shift registers, display
drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• I nter-Integrated Circuit (I2C™)
Refer to Application Note AN578, “Use of the SSP
Module in the Multi-Master Environment” (DS00578).
13.1 SPI Mode
This section c ontains register definitions and operational
characteristics of the SPI module.
The SPI mode allows eight bits of data to be
synchronously tran smitted and received simulta neously .
To accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Seri al Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
FIGURE 13-1: SSP BLOCK DIAGRAM
(SPI MODE)
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPM<3:0> bits of
the SSPCON register = 0100), the SPI
module will reset if the SS pin is set to
VDD.
2: If the SPI is used in Slave mode with
CKE = 1, then the SS pi n control m ust be
enabled.
3: When the SPI is in Slave mode with SS
pin control enabled (SSPM<3:0> bits of
the SSPCON register = 0100), the state
of the SS pin can affect the state read
back from the TRISC<4> bit. The
peripheral OE signal from the SSP
module into PORTC controls the state
that is read back from the TRISC<4> bit
(see Section 17.0 “Electrical
Specifications” for information on
PORTC). If read-write-modify
instructions, such as BSF, are performed
on the TRIS C regi ster while t he SS pin is
high, this will cause the TRISC<7> bit to
be set, thus disabling the SDO output.
Read Write
Internal
Data Bus
SCK/
SSPSR Reg
SSPBUF Reg
SSPM<3:0>
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TCY
Prescaler
4, 16, 64
TRISB<6>
2
Edge
Select
2
4
SCL
Peripheral OE
SDI/SDA
SDO
SS
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REGISTER 13-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER(1)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2 C™ mode:
This bit must be maintained clear
bit 6 CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1 = Data transmit ted on rising edge of SCK (Microwire alternate)
0 = Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1 = Data transmitted on falling edge of SCK (Microwire default)
0 = Data transmit ted on rising edge of SCK
I2 C mode:
This bit must be maintained clear
bit 5 D/A: DATA/ADDRESS bit (I2C mode only)(2)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.
SSPEN is cleared.
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
SSPEN is cleared.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: READ/WRITE bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid fr om the address match
to the next Start bit, Stop bit or ACK bit.
1 = Read
0 = Write
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SS PB UF is empty
Note 1: PIC16F687/PIC16F689/PIC16F690 only.
2: Does not update if receive was ignored.
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REGISTER 13-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the
data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only
transmitting data, to avoid setting overflow . In Master mode, the overflow bit is not set since each new recep-
tion (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2 C™ mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in
Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level (Microwire default)
0 = Idle state for clock is a low level (Microwire alternate)
In I2 C mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Sl ave mode, 7-bit address
0111 = I2C Sl ave mode, 10-bit address
1000 = Reserved
1001 = Load SSPMSK register at SSPADD SFR address(2)
1010 = Reserved
1011 = I2C Firmware Controlled Master mode (slave IDLE)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: PIC16F687/PIC16F689/PIC16F690 only.
2: When this mode is selected, any reads or writes to the SSPADD SFR address actually accesses the SSPMSK register .
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13.2 Operation
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The SSP consists of a transmit/receive shift register
(SSPSR) and a buf fer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
unti l the rece ived da ta is ready. Once the ei ght bits of
data have been received, that byte is moved to the
SSPBUF regis ter. T hen , the Buffer Fu ll Stat us b it BF of
the SSPSTAT register, and the interrupt flag bit SSPIF,
are set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just r eceived. Any write to the
SSPBUF registe r during tra nsmission/recep tion of data
will be ignored and the Write Collision Detect bit,
WCOL of the SSPCON register, will be set. User
software must clear the WCOL bit so that it can be
determined if the following write(s) to the SSPBUF
regi ster completed successfully.
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of dat a to transfer is writ ten to the SSPBUF. Buffer
Full bit BF of the SSPSTAT register indicates when
SSPBUF has been loaded with the received data
(transmiss ion is complete ). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is o nly a t ransmitter. Genera lly, the SSP interrupt is
used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then sof tware pol ling can be d one to ensure that a write
collision does not occur. Example 13-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
The SSPSR is n ot directly re adable or wri table and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 13-1: LOADING THE SSPBUF (SSPSR) REGISTER
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)?
GOTO LOOP ;No
BCF STATUS,RP0 ;Bank 0
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
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13.3 Enabling SPI I/O
To enable th e serial port, SSP En able bit SSPEN of th e
SSPCON register must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRISB and TRISC registers) appropriately
programmed. T hat is:
• SDI is automa tic all y c on t rol led by the SP I module
• SDO must have TRISC<7> bit cleared
• SCK (Master mode) must have TRISB<6> bit
cleared
• SCK (Slave mode) must have TRISB<6> bit set
•SS
must have TRISC<6> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRISB and TRISC) registers to the opposite
value.
13.4 Typical Connect ion
Figure 13-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same tim e. Whet her the dat a is meaningful (or dum m y
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data–Slave send s dummy data
• Master sends data–Slave sends data
• Master sends du mmy data–Slave sends data
FIGURE 13-2: SPI MASTE R/S LAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
Processor 1
SCK
SPI Master SSPM<3:0> = 00xxb
Serial Input Buf fe r
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
Processo r 2
SCK
SPI Slave SSPM<3:0> = 010xb
Serial Clock
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13.5 Master Mode
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 13-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF registe r is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will conti nue to shif t in the signa l present on th e
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set). This could be useful in receiver
applications as a Line Activity Monitor mode.
The clock polarity is selected by appropriately
pro gr am m ing t he C KP bi t of the SSPCON regi ster. T hi s
then, would give waveforms for SPI communication as
shown in Figure 13-3, Figure 13-5 and Figure 13-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2 (No SSP module, PIC16F690
only)
Figure 13-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
dat a is shown.
FIGURE 13-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7 bit 0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
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13.6 Slave Mode
In Slave m ode , the data is trans mi tted and r ece iv ed a s
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
13.7 Slave Select Synchroni zation
The SS pin allows a Sync hronous Slave mode. The SPI
must be in Slave mode with SS pin control enabled
(SSPCON<3:0> = 04h). The pin must not be driven low
for the SS pin to function as an input. The data latch
must be high. Wh en the SS pi n is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted by te, and becom es
a floating output. External pull-up/pull-down resistors
may be desira ble, dependin g on the applic ation.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function)
since it cann ot cre ate a bus con flict.
FIGURE 13-4: SLAVE SYNCHRONIZA TION WAVEFORM
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is us ed in Slave Mode wi th CKE
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bi t 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7 bit 0
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FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 13-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
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13.8 Sleep Operation
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operat es asy nchron ously to the devi ce. Th is al lows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all eight bits have been received, the SSP inter-
rupt flag bit will be set and if enabled, will wake the
device from Sleep.
13.9 Effects of a Reset
A Reset disables the SSP module and terminates the
current transfer.
13.10 Bus Mode Compatibility
Table 13-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 13-1: SPI BUS MODES
There is also a SMP bit w hich co ntrols whe n the dat a is
sampled.
TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION(1)
Standard SP I Mode
Terminology
Control Bit s S tate
CKP CKE
0, 001
0, 100
1, 011
1, 110
Add re ss Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
Resets
0Bh/8Bh/
10Bh/18Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
0Ch PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
86h/186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 ————1111 ---- 1111 ----
87h/187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
8Ch PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
Note 1: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
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13.11 SSP I2C Operation
The SSP module in I2C mode, fully im plement s all slave
functions, except general call support, and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the Standard mode
specifications, as w ell as 7 -bit and 10-bit address ing.
T wo pins are used for da ta transfer . These are the RB6/
SCK/ SCL pin, which i s the cl ock (SCL) , and th e RB4/
AN10/SDI/SDA pin, which is the data (SDA).
The SSP mod ule fun ctions a re enabl ed by settin g SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 13-7: SSP BLOCK DIAGRAM
(I2C™ MODE)
The SSP module has six registers for the I2C operation,
which are listed below.
• SSP Control register (SSPCON)
• SSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift register (SSPSR) – Not directly
accessible
• SSP Address register (SSPADD)
• SSP Mask register (SSPMSK)
The SSPCON register allows control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I2C modes to be selected:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit add res s), with Start and
Stop bit interrupts enabled to support Firmware
Master mode
•I
2C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled to support Firmware
Master mode
•I
2C Start and Stop bit interrupts enabled to
support Firmware Master mode; Slave is idle
Selection of any I2C mode with the SSPEN bit set
forces the SCL and SDA pins to be open drain,
provided these pins are programmed to inputs by
setting the appropriate TRISB bits. Pull-up resistors
must be provided externally to the SCL and SDA pins
for proper operation of the I2C module.
13.12 Slave Mode
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISB<6,4> are set). The SSP
module will overrid e the input sta te with the ou tput dat a
when required (slave-transmitter).
When an address is m atc he d, or the dat a transfer after
an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
pulse, and then load the SSPBUF register with the
received value currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pul se. They in clude (eith er
or both):
a) The Buffer Full bit BF of the SSPSTAT register
was set before the transfer was received.
b) The overflow bit SSPOV of the SSPCON
register was set before the transfer was
received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 13-3 shows the results of when a data
transfer byte is receiv ed, given the statu s of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow
condition. Flag bit BF is cleared by reading the
SSPBUF register, while bit SSPOV is cleared through
software.
The SCL clock input must have a minimum high and low
for proper operation. For high and low times of the I2C
specification, as well as the requirements of the SSP
module, see Section 17.0 “Electrical Specifications”.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
Start and
Stop bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
RB6/
RB4/
Shift
Clock
MSb
AN10/ LSb
SDI/SDA
SCL
SCK/
SSPMSK Reg
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13.12.1 ADDRESSING
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the eight bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF of the PIR1 register
is set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 13-8). The five Most
Significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the
second address byte. For a 10-bit address, the first
byt e would equ al ‘1111 0 A9 A8 0’, where A9 and
A8 are the two MSbs of the address.
The sequence of events for 10-bit address is as
follows, with ste p s 7-9 for slave -tran sm itt er:
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update t he SSPADD register w ith the f irst (hig h)
byte of a ddre ss ; if match releas es SCL li ne, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 13-3: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received SSPSR SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 No No Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
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13.12.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleare d. The re ceived ad dre ss is loa ded in to
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set , or bi t SSPOV of the SSPCON regi ster is
set. This is an error condition due to the user’s firm-
ware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF of the PIR1 register must be
cleared in software. The SSPSTAT register is used to
determine the status of the byte.
FIGURE 13-8: I2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
765
D0
D1
D2
D3
D4
D5D6
D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678912
34
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4D5D6
D7
ACK
R/W = 0
Receiving Ad dr ess
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
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13.12.3 SSP MASK REGIST ER
An SSP Mask (SSPMSK) register is available in I2C
Slave mode as a mask for the value held in the
SSPSR register during an address comparison
operation. A zero (‘0’) bit in the SSPMSK register has
the effect of making the corresponding bit in the
SSPSR register a ‘don’t care’.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
This register must be initiated prior to setting
SSPM<3:0> bits to select the I2C Slave mode (7-bit or
10-bit address).
This register can only be accessed when the appropriate
mode is selected by bits (SSPM<3:0> of SSPCON).
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Addres s mode: address c ompare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
REGISTER 13-3: SSPMSK: SSP MASK REGISTER(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(2)
I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
Note 1: When SSPCON bit s SSPM<3:0> = 1001, any reads o r writes to th e SSPADD SFR a ddress are acces sed
through the SSPMSK register. The SSPEN bit of the SSPCON register should be zero when accessing
the SSPMSK register.
2: In all other SSP modes, this bit has no effect.
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FIGURE 13-9: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
SSPIF
BF (SSPSTAT<0>)
Receive Data Byte
R/W = 0
Receive First Byte of Address
Cleared in softwa re
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Cleared by har dwar e
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating
that the SSPADD needs to
be updated
UA is set indicating
that SSPA DD needs to
be updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written
with contents of SSPSR Dummy read of SSPBUF
to clear BF flag
CKP
Receive Data Byte
Bus master
terminates
transfer
ACK
Cleared in software Cleared in software
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
SDA
SCL S123456789 123456789 12345 789P
11110A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
ACK
ACK D2
6
ACK
12345789
D7 D6 D5 D4 D3 D1 D0D2
6
ACK
0
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13.12.4 TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RB6/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR
register. Then, pin RB6/SCK/SCL should be enabled
by setting bit CKP (SSPCON<4>). The master must
monitor the SCL pin prior to asserting another clock
pulse. T he sla ve devices may be h olding of f the m aster
by stretching the clock. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 13-10).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the dat a tran sfer is com plete. When th e ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another
occurrence of the Start bit. If the SDA line was low
(ACK), the transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR
register. Then pi n RB6/SCK/ SCL should be enabled b y
setting bit CKP.
FIGURE 13-10 : I2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting DataR/W = 1Receiving Ad dr ess
123456789 123456789 P
Cleared in software
SSPBUF is written in software From SSP Interrupt
Service R out i ne
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written to
before the CKP bit can be set)
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FIGURE 13-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789123456789 12345 789P
11110A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating
that the SSPADD needs to
be updated
UA is set indicating
that SSPADD needs to
be updated
Cleared by hardwa re w hen
SSPADD is updated with high
byte of address
SSPBUF is written
with contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Clear ed in softwa re Cleared i n software
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
0
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13.13 Master Mode
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and S t op conditio ns. The S top (P) and S t art (S) bits are
cleared from a Reset or when the SSP module is
disabled. The Stop (P) and Start (S) bits will toggle
bas ed on the Start and Stop co nditio ns. Co ntrol of the
I2C bus may be taken when the P bit is set or the bus
is idle and both the S and P bits are clear.
In Master mode, the SCL and SDA lines are
manipulated by clearing the corresponding
TRISB<6,4> bit(s). The output level is always low,
irrespective of the value(s) in PORTB<6,4>. So when
transmitting data, a ‘1’ data bit must have the
TRISB<4> bit set (input) and a ‘0’ data bit must have
the TRISB<4> bit cleared (output). The same scenario
is tru e for the S CL line wit h the TRISB <6> bit . Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I2C module.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt will occur if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM<3:0> = 1011), or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
13.14 Multi-Master Mode
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions, allows the
determin ation of when the bu s is free. The S top (P) an d
S tart (S) bits are cl eared from a Reset or when the SSP
module is disabled. The Stop (P) and Start (S) bits will
toggle based on the Start and Stop conditions. Control
of the I 2C bus may be t aken when bit P (SSPS T AT<4>)
is set, or th e bus is idle and both the S and P bit s clear.
When the bus is busy, enabling the SSP Interrupt will
generate the interrupt when the Stop condition occurs.
In Multi-Master operation, the SDA line must be
monitored to see if the signal level is the expected
output level. This check only needs to be done when a
high lev el is output. If a high lev el is expec ted and a low
level is present, the device needs to release the SDA
and SCL l ines (set T RISB<6, 4>). There are two sta ges
where this arbitration can be lost, these are:
• Address T r ansfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address
transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be generated.
If arbitration was lost during the data transfer stage, the
device will need to re-transfer the dat a a t a later time.
13.14.1 CLOCK SYNCHRONIZATION AND
THE CKP BIT
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL outpu t low until the SCL outpu t is already sam pled
low. Therefore, the CKP bit will not assert the SCL line
until an external I2C master device has already
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I2C
bus have deassert ed SCL. Thi s en sure s tha t a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 13-12).
PIC16F631/677/685/687/689/690
DS40001262F-page 192 2005-2015 Microchip Technology Inc.
FIGURE 13-12: CLOCK SYNCHRONIZATION TIMING
TABLE 13-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION(1)
Addr Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on
POR, BOR
Va lue on
all othe r
Resets
0Bh/8Bh/
10Bh/18Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
0Ch PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 ————1111 ---- 1111 ----
93h SSPMSK(2) MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111
94h SSPSTAT SMP(3) CKE(3) D/A PSR/WUA BF 0000 0000 0000 0000
8Ch PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IF TMR1IF -000 0000 -000 0000
Legend: – = Unimplemented locations, read as ‘0’, u = unchange d, x = unknown. Shaded cells are not used by the SSP module.
Note 1: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
2: SSPMSK register (Register 13-3) can be accessed by reading or writing to SSPADD register with bits SSPM<3:0> = 1001.
See Regist ers 13-2 and 13-3 for mo re detai ls.
3: Maintain these bits clear.
SDA
SCL
DX-1DX
WR
Table 0-1:
Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4Q
1Q
2Q
3Q
4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
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PIC16F631/677/685/687/689/690
14.0 SPECIAL FEATURES OF THE
CPU
The PIC16F631/677/685/687/689/690 have a host of
features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving features and offer code
protection.
These features are:
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Oscillator selection
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming
The PIC1 6F63 1/6 77/ 685 /687/689/690 h av e two timers
that offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in Reset until the crystal oscillator is stable. The
other is t he Power-up Timer (PWRT ), w h ic h p rov ide s a
fixed delay of 64 ms (nominal) on power-up only,
designed to keep the part in Reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs , which can use the Power-
up Timer to provide at least a 64 ms Rese t. With thes e
three functions-on-chip, most applications need no
external Reset circuitry.
The Sleep mode is de signe d to of fer a very low-c urrent
Power-down mode. The user can wake-up from Sleep
through:
• External Reset
• Watchdog Timer Wake-up
• An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 14-2).
14.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left un programmed (read as ‘ 1’) to select various
device configurations as shown in Register 14-2.
These bits are mapped in program memory location
2007h.
Note: Address 2007h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h-
3FFFh), which can be accessed only during
programming. See “PIC12F6XX/16F6XX
Memory Programming Specification”
(DS41204) for more information.
PIC16F631/677/685/687/689/690
DS40001262F-page 194 2005-2015 Microchip Technology Inc.
REGISTER 14-1: CONFIG: CONFIGURATION WORD REGISTER
Reserved Reserved FCMEN IESO BOREN1(1) BOREN0(1) CPD(2
bit 13 bit 7
CP(3) MCLRE(4) PWRTE WDTE FOSC2 FOSC1 FOSC0
bit 6 bit 0
Legend:
R = Readable bi t W = Writable bit P = Programmable’ U = Unimplemented
bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 13-12 Reserved: Reserved bits. Do Not Use.
bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Saf e Cloc k Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 10 IESO: Internal External Switchover bit
1 = Internal External Swit chover mode is enabled
0 = Internal External Switchover mode is disable d
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the PCON register
00 = BOR disabled
bit 7 CPD: Data Cod e Pr otec ti o n bit (2)
1 = Data memory code protection is disabled
0 = Data memory code prote ct i on is enabled
bit 6 CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: MCLR Pin Function Select bit(4)
1 = MCLR pin function is MCLR
0 = MCLR pin function is digit al input, MCLR internally tied to VDD
bit 4 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Wat chdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 =RC oscillat or: CLKO UT funct i on on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN
110 =RCI O oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/ OSC1/CLKIN
101 =INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin,
I/O function on RA5/OSC1/CLKIN
100 = I NTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin,
I/O func tion on RA5/OSC1/CLKIN
011 =EC: I/O functi on on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN
010 =HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonat or on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
000 = LP oscillator : Low-power crystal on RA4/OSC2/C LKOUT and RA5/OSC1/CLKIN
Note 1: Enabling Brown-ou t Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off.
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
2005-2015 Microchip Technology Inc. DS40001262F-page 195
PIC16F631/677/685/687/689/690
14.2 Reset
The PIC16F631/677/685/687/689/690 differentiates
between various kinds of Reset:
a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR Reset during normal operation
e) MCLR Reset duri ng Sl eep
f) Brown-out Reset (BOR)
Some regi sters a re not af fected in any Rese t condi tion;
their st at us is un kn ow n o n POR a nd un ch ang ed in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
•MCLR
Reset
•MCLR
Reset during Sleep
•WDT Reset
• Brown-out Reset (BOR)
They are not affected by a WDT Wake-up since this is
viewe d as the resumptio n of normal opera tion. TO an d
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 14-2. These bits are
used in software to determine the nature of the Reset.
See Table 14-4 for a full description of Reset states of
all registers.
A simplif ied block diagra m of the On-Chip Rese t Circuit
is shown i n Figure 14-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 17.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 14-1: SIMPLI FIED B LOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR/VPP pin
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
LFINTOSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable OST
Enable PWRT
Sleep
Brown-out(1)
Reset SBOREN
BOREN
CLKI pin
Note 1: Refer to the Configuration Word register (Register 14-1).
PIC16F631/677/685/687/689/690
DS40001262F-page 196 2005-2015 Microchip Technology Inc.
14.2.1 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level fo r proper operation. A
maximum rise time for VDD is required. See
Section 17.0 “Electr ical Specifications” for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry w ill keep the device in
Reset until VDD reaches VBOR (see Section 14.2.4
“Brown- ou t Re set (B OR )”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
14.2.2 MCLR
PIC16F631/677/685/687/689/690 has a noise filter in
the MCLR Reset path. The filter will detect and ignore
small pul ses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from early devices of this family.
Voltages appli ed to the p in th at exceed i t s spe cific ation
can resu lt in both MCL R Rese t s a nd e xc es sive c urre nt
bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .
For this rea son, Microc hip recomme nds that the MC LR
pin no long er be tied direc tl y to VDD. The use of an RC
netw ork, as show n in Figure 14-2, is s uggested .
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RA3/MCLR pin
becomes an external Reset input. In this mode, the
RA3/MCLR pin has a weak pull-up to VDD. However,
for robustness in noisy environments, the circuit shown
in Figure 14-2 is still recommended.
FIGURE 14-2: RECOMMENDED MCLR
CIRCUIT
14.2.3 POWER-UP TIMER (PWRT)
The P owe r-u p Timer pr ov ides a fi xed 64 ms (nom inal )
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.5 “Internal Clock Mo des”. Th e ch ip is ke pt
in Reset as long as PWRT is active. The PWRT delay
allows the VDD to rise to an acceptable level. A
Configuration bit, PWRTE, can disable (if set) or enable
(if cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
•V
DD variation
• Temperature variation
• Process variation
See DC parameters for details (Section 17.0 “Electrical
Specifications”).
Note: The POR circuit does not produce an
internal Reset when VDD declines. To re-
enable the POR, VDD must reach Vss for
a minimum of 100 s.
VDD PIC16F685
MCLR
R1
1kor greater)
C1
0.1 F
(optional, not critical)
2005-2015 Microchip Technology Inc. DS40001262F-page 197
PIC16F631/677/685/687/689/690
14.2.4 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word register select one of four BOR modes. Two
modes h ave been a dded to all ow softwa re or hardwa re
control of the BOR enable. When BOREN<1:0> = 01,
the SBOREN bit (PCON<4>) enables/disables the
BOR allowing it to be controlled in software. By
selecting BOREN<1:0>, the BOR is automatically
disabled in Sleep to conserve power and enabled on
wake-up. In this mode, the SBOREN bit is disabled.
See Register 14-2 for the Configuration Word
definition.
If VDD falls below VBOR for greater than parameter
(TBOR) (see Section 17.0 “Electrical Specifications”),
the Brown-out situation will reset the device. This will
occur regardless of VDD slew rate. A Reset is not insured
to occur if VDD falls b elow VBOR for less than p arameter
(TBOR).
On any Reset (Power-on, Brown-out Reset, Watchdog
Timer, etc.), the chip will remain in Reset until VDD rises
above VBOR (see Figure 14-3). The Power-up Timer
will no w be invoked, if enabled and will keep the chip in
Reset an additional 64 ms.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Pow er-up T imer will be re-initial ized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
FIGURE 14-3: BROWN-OUT SITUATIONS
Note: The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
64 ms(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset 64 ms(1)
< 64 ms
64 ms(1)
VBOR
VDD
Internal
Reset
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
PIC16F631/677/685/687/689/690
DS40001262F-page 198 2005-2015 Microchip Technology Inc.
14.2.5 TIME-OUT SEQUENCE
On power- up, the t ime-out sequ ence is a s follows: first,
PWR T time-out is invoked after PO R has ex pired, the n
OST is act iv ated af te r the PWRT time-ou t has exp ire d.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in
EC mode with PWRTE bit erased (PWRT disabled),
there will be no time-out at all. Figures 14-4,14-5
and 14-6 depict time-out sequences. The device can
execute code from the INTOSC while OST is active by
enablin g Two-Speed Start-up or Fail-Safe M on itor (see
Section 3.7.2 “Two-speed Start-up Sequence” and
Section 3.8 “Fail-Safe Clock Monitor”).
Since the time-outs oc cur from the PO R pulse, if MCLR
is kept low long enough, the time-outs will expire. The n,
bringing MCLR high will begin execution immediately
(see Figure 14-5). This is useful for testing purposes or
to synchronize more than one PIC16F631/677/685/
687/689/690 device operating in parallel.
Table 14-5 shows the Reset conditions for some
special registers, while Table 14-4 shows the Reset
conditions for all the registers.
14.2.6 POWER CONTROL (PCON)
REGISTER
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word
register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaf fec ted oth erwise. T he user m ust write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 4.2.4 “Ultra Low-
Power Wake-up” and Section 14.2.4 “Brown-out
Reset (BOR)”.
TABLE 14-1: TIME-OUT IN VARIOUS SITUATIONS
TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE
TABLE 14-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Oscillator Configuration Powe r-up Brown-out Reset Wake-up from
Sleep
PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1
XT, HS, LP TPWRT +
1024 • TOSC 1024 • TOSC TPWRT +
1024 • TOSC 1024 • TOSC 1024 • TOSC
LP, T1OSCIN = 1TPWRT —TPWRT ——
RC, EC, INTOSC TPWRT —TPWRT ——
POR BOR TO PD Condition
0x11Power-on Reset
u011Brown-out Reset
uu0uWDT Reset
uu00WDT Wake-up
uuuuMCLR Reset during normal operation
uu10MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all ot her
Resets
PCON — — ULPWUE SBOREN ——PORBOR --01 --qq --0u --uu
STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Re set dur ing nor mal operati on .
2005-2015 Microchip Technology Inc. DS40001262F-page 199
PIC16F631/677/685/687/689/690
FIGURE 14-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
FIGURE 14-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
FIGURE 14-6: TIME-O UT SEQU ENCE ON POWER-UP (MCLR WITH VDD)
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT T ime-out
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
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TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER
Register Address P owe r-on Reset MCLR Reset
WDT Res et
Brown-out Reset (1)
Wake-up from Sleep
through In terrupt
Wake-up from Sleep
through WDT Time-out
W—xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/
100h/180h xxxx xxxx xxxx xxxx uuuu uuuu
TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/
102h/182h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h/
103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h/84h/
104h184h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h/105h --xx xxxx --uu uuuu --uu uuuu
PORTB 06h/106h xxxx ---- uuuu ---- uuuu ----
PORTC 07h/107h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah/8Ah/
10Ah/18Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh/
10Bh/18Bh 0000 000x 0000 000u uuuu uuuu(2)
PIR1 0Ch -000 0000 -000 0000 -uuu uuuu(2)
PIR2 0Dh 0000 ---- 0000 ---- uuuu ----(2)
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h 0000 0000 uuuu uuuu uuuu uuuu
TMR2 11h 0000 0000 0000 0000 uuuu uuuu
T2CON 12h -000 0000 -000 0000 -uuu uuuu
SSPBUF 13h xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 14h 0000 0000 0000 0000 uuuu uuuu
CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 17h 0000 0000 0000 0000 uuuu uuuu
RCSTA 18h 0000 000x 0000 000x uuuu uuuu
TXREG 19h 0000 0000 0000 0000 uuuu uuuu
RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu
PWM1CON 1Ch 0000 0000 0000 0000 uuuu uuuu
ECCPAS 1Dh 0000 0000 0000 0000 uuuu uuuu
ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1Fh 0000 0000 0000 0000 uuuu uuuu
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h/185h --11 1111 --11 1111 --uu uuuu
Legend: u = unchang ed, x = unknown, — = unimplem e nt ed bi t , rea ds as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Powe r-on Reset will be activated and registers will be affected differently.
2: One or mor e bi ts in IN TC O N and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
6: Accessible only when SSPM<3:0> = 1001.
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PIC16F631/677/685/687/689/690
TABLE 14-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
TRISB 86h/186h 1111 ---- 1111 ---- uuuu ----
TRISC 87h/187h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch -000 0000 -000 0000 -uuu uuuu
PIE2 8Dh 0000 ---- 0000 ---- uuuu uuuu
PCON 8Eh --01 --0x --0u --uq1, 5) --uu --uu
OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu
OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu
PR2 92h 1111 1111 1111 1111 uuuu uuuu
SSPADD 93h 0000 0000 1111 1111 uuuu uuuu
SSPMSK(6) 93h ---- ---- 1111 1111 uuuu uuuu
SSPSTAT 94h 0000 0000 1111 1111 uuuu uuuu
WPUA 95h --11 -111 --11 -111 uuuu uuuu
IOCA 96h --00 0000 --00 0000 --uu uuuu
WDTCON 97h ---0 1000 ---0 1000 ---u uuuu
TXSTA 98h 0000 0010 0000 0010 uuuu uuuu
SPBRG 99h 0000 0000 0000 0000 uuuu uuuu
SPBRGH 9Ah 0000 0000 0000 0000 uuuu uuuu
BAUDCTL 9Bh 01-0 0-00 01-0 0-00 uu-u u-uu
ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 9Fh -000 ---- -000 ---- -uuu ----
EEDAT 10Ch 0000 0000 0000 0000 uuuu uuuu
EEADR 10Dh 0000 0000 0000 0000 uuuu uuuu
EEDATH 10Eh --00 0000 --00 0000 --uu uuuu
EEADRH 10Fh ---- 0000 ---- 0000 ---- uuuu
WPUB 115h 1111 ---- 1111 ---- uuuu ----
IOCB 116h 0000 ---- 0000 ---- uuuu ----
VRCON 118h 0000 0000 0000 0000 uuuu uuuu
CM1CON0 119h 0000 -000 0000 -000 uuuu -uuu
CM2CON0 11Ah 0000 -000 0000 -000 uuuu -uuu
CM2CON1 11Bh 00-- --00 00-- --10 uu-- --uu
ANSEL 11Eh 1111 1111 1111 1111 uuuu uuuu
ANSELH 11Fh ---- 1111 ---- 1111 ---- uuuu
EECON1 18Ch x--- x000 u--- q000 ---- uuuu
EECON2 18Dh ---- ---- ---- ---- ---- ----
PSTRCON 19Dh ---0 0001 ---0 0001 ---u uuuu
SRCON 19EH 0000 00-- 0000 00-- uuuu uu--
TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED)
Register Address P owe r-on Reset MCLR Reset
WDT Reset (Con tinued)
Brown-out Reset (1)
Wake-up from Sleep
through In terrupt
Wake-up from Sleep
through WDT Time-out
Legend: u = unchang ed, x = unknown, — = uni m pl em ented bit, rea ds as ‘0’, q = value depends on co ndition.
Note 1: If VDD goes too low, Pow er-on Reset will be activated and registers will be affected differently.
2: One or mor e bi ts in IN TC O N and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
6: Accessible only when SSPM <3:0> = 1001.
PIC16F631/677/685/687/689/690
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Condition Program
Counter Status
Register PCON
Register
Power-on Reset 000h 0001 1xxx --01 --0x
MCLR Reset during normal operation 000h 000u uuuu --0u --uu
MCLR Reset during Sleep 000h 0001 0uuu --0u --uu
WDT Reset 000h 0000 uuuu --0u --uu
WDT Wake- up PC + 1 uuu0 0uuu --uu --uu
Brown-out Reset 000h 0001 1uuu --01 --u0
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu
Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interr upt and Glob al Interrupt Enab le bit, GIE, is set, the PC is loaded w ith
the interrupt vec tor (0004h) after execution o f PC + 1.
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PIC16F631/677/685/687/689/690
14.3 Interrupts
The PIC16F631/677/685/687/689/690 have multiple
sources of interrupt:
• External Interrupt RA2/INT
• TMR0 Overflow Interru pt
• PORTA/PORTB Change Interrupts
• 2 Comparator Interrupts
• A/D Interrupt (except PIC16F631)
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt (PIC16F685/PIC16F690
only)
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• Enhanced CCP Interrup t (PIC16F685/PIC1 6F690
only)
• EUSART Receive and Transmit interrupts
(PIC16F687/PIC16F689/PIC16F690 only)
The Interrup t Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in the
INTCON, PIE1 and PIE2 re gis ter s, respe ctive ly. GIE is
cleared on R eset .
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmaske d inte rrupts.
The following interrupt flags are contained in the
INTCON register:
• I NT Pin Interrupt
• PORTA/PORTB Change Interrupts
• TMR0 Overflow Interru pt
The perip heral interru pt flags ar e cont ained in the PIR1
and PIR2 registers. The correspondi ng interrupt enable
bits are contained in PIE1 and PIE2 registers.
The following interrupt flags are contained in the PIR1
register:
• A/D Interrupt
• EUSART Receive and Transmit Interrupts
• Timer1 Overflow Interrupt
• Synchronous Serial Port (SSP) Interrupt
• Enhanced CCP1 Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
The following interrupt flags are contained in the PIR2
register:
• Fail-Safe Clock Monitor Interrupt
• 2 Comparator Interrupts
• EEPROM Data Write Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any fu rthe r interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
For external interrupt events, such as the INT pin,
PORTA/PORTB change interrupts, the interrupt
latency will be three or four instruction cycles. The
exact latency depends upon when the interrupt event
occurs (see Figure 14-8). The latency is the same for
one or 2-cycle instructions. Once in the Interrupt
Service Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For additional information on Timer1, Timer2,
comparators, A/D, data EEPROM, EUSART, SSP or
Enhanced CCP modules, refer to the respective
peripheral section.
14.3.1 RA2/INT INTERRUPT
External interrupt on RA2/INT pin is edge-triggered;
either rising if the INTEDG bit (OPTION_REG<6>) is
set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RA2/INT pin, the INTF bit
(INTCO N<1>) is set. This interr upt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cl eared in software in the Inte rrupt Servi ce
Routine b efore re- enabling t his interr upt. The RA 2/INT
interru pt can wake-up t he processor fr om Sleep, if th e
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up
(0004h). See Section 14.6 “Power-Down Mode
(Sleep)” for details on Sleep and Figure 14-10 for
timing of wake-up from Sleep through RA2/INT
interrupt.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
Note: The ANSEL and CM2CON0 registers
must be initialized to configure an analog
channel as a di gital input. Pins conf igu r ed
as analog inputs will read ‘0’.
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14.3.2 TIMER0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE (INTCON<5>)
bit. See Section 5.0 “Timer0 Module” for operation of
the Timer0 module.
14.3.3 PORTA/PORTB INTERRUPT
An inpu t change on POR TA or PORTB change sets the
RABIF (INTC ON<0>) bit. The interrupt can be e nabled/
disabled by setting/clearing the RABIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA or IOCB registers.
FIGURE 14-7: INTERRUPT LOGIC
Note: If a change on the I/O pin should occur
when the read operation is being
executed (start of the Q2 cycle), then the
RABIF interrupt flag may not get set. See
Section 4.2.3 “Interrupt-on-change” for
more information.
C1IF
C1IE
T0IF
T0IE
INTF
INTE
RABIF
RABIE
GIE
PEIE
Wake-up (If in Sleep mode)(1)
Inter rupt to CPU
EEIE
EEIF
ADIF
ADIE
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
CCP1IF
CCP1IE
OSFIF
OSFIE
C2IF
C2IE
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
RCIF
RCIE
TMR2IE
TMR2IF
SSPIE
SSPIF
TXIE
TXIF
TMR1IE
TMR1IF
Note 1: S ome peripherals depend upon the system
clock for operation. Since the system clock is
suspended during Sleep, these peripherals
will not wake the part from Sleep. See
Section 14.6.1 “Wake-up from Sleep”.
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PIC16F631/677/685/687/689/690
FIGURE 14-8: INT PIN INTERRUPT TIMING
TABLE 14-6: SUMMARY OF INTERRUPT REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 0000 ----
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
PIR2 OSFIF C2IF C1IF EEIF — — — — 0000 ---- 0000 ----
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) I nst (0005h)
Dummy Cycl e
Inst (PC) Inst (PC + 1)
Inst (PC – 1) Inst (0004h)
Dummy Cycl e
Inst ( PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 17.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1) (2)
(3) (4)
(5)
(1)
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14.4 Context Saving During Interr upts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Since the upper 16 bytes of all GPR banks are common
in the PIC16F631/677/685/687/689/690 (see
Figures 2-2 and 2-3), temporary holding registers,
W_TEMP and STATUS_TEMP, should be placed in
here. These 16 locations do not require banking and
therefore, make it easier to context save and restore.
The same code shown in Example 14-1 can be used
to:
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
EXAMPLE 14-1: SAVING STATUS AND W REGISTERS IN RAM
Note: The PIC16F631/677/685/687/689/690
normally does not require saving the
PCLATH. However, if computed GOTO’s
are used in the ISR and the main code,
the PCLATH must be saved and restored
in the ISR.
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
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14.5 Watchdog Ti mer (WDT)
The WDT has the following features:
• Operates from the LFINTOSC (31 kHz)
• Contains a 16-bit prescaler
• Shares an 8-bit prescaler with Ti mer0
• Time-out period is from 1 ms to 268 seconds
• Configuration bit and software controlled
WDT is cleared under certain conditions described in
Table 14-7.
14.5.1 WD T OSCILLATOR
The WDT derives its time base from the 31 kHz
LFINTOSC. The LTS bit of the OSCCO N regi ste r doe s
not reflect that the LFINTOSC is enabled.
The value of WDTCON is ‘---0 1000’ on all Rese ts.
This gives a nominal time base of 17 ms.
14.5.2 WDT CONTROL
The WDTE bit is located in the Configuration Word
register. When set, the WDT runs continuously.
When the WDTE b it in the Confi g urat ion Word register
is set, the SWDT EN bit of the WDTCON register ha s no
effect. If WDTE is clear, then the SWDTEN bit can be
used to e nable and d isable the WDT. Setting the b it will
enable it and clearing the bit will disable it.
The PSA and PS<2:0> bits of the OPTION register
have the same function as in previous versions of the
PIC16F631/677/685/687/689/690 Family of microcon-
trollers. See Section 5.0 “Timer0 Module” for more
information.
FIGURE 14-9: WATCHDOG TIMER BLOCK DIAGRAM
Note: When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
TABLE 14-7: WDT STATUS
Conditions WDT
WDTE = 0Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
31 kHz
PSA
16-bit WDT Prescaler
From TMR0 Clock Source
Prescaler(1)
8
PS<2:0>
PSA
WDT Time-out
To TMR0
WDTPS<3:0>
WDTE from the Configuration Word Register
1
1
0
0
SWDTEN from WDTCON
LFINTOSC Clock
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.
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TABLE 14-8: SUMMARY OF WATCHDOG TIMER REGISTER
REGISTER 14-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512 (Reset v alue)
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16384
1010 = 1:32768
1011 = 1:65536
1100 = reserved
1101 = reserved
1110 = reserved
1111 = reserved
bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE
Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
Name B it 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
CONFIG(1) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
OPTION_REG RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 14-1 for operation of all Configuration Word register bits.
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14.6 Power-Down Mode (Sleep)
The Power-Down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
•PD
bit in the STATUS register is cleared.
•TO
bit is set.
• Oscillator driver is turned off.
• I/O ports maintain the status they had before
SLEEP was executed (driving high, low or high-
impedance).
For lowest cu rrent consumption in this mode, all I/O pins
should be either at VDD or VSS, with no external circuitry
drawing current from the I/O pin and the comparators
and CVREF should be disabled. I/O pins that are high-
impedance inputs should be pulled high or low externally
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for lowest
current cons umption. The contribution from on-chip pull-
ups on PORTA should be considered.
The MCLR pin must be at a logic high level.
14.6.1 WAKE-UP FROM SLEEP
The devi ce can wa ke-up from Sleep through one of th e
following events:
1. External Reset input on MCLR pin.
2. W atchdog Timer W ake-up (if WDT was enable d).
3. Interrupt from RA2/INT p in, POR TA chan ge or a
peripheral interrupt.
The firs t event wi ll ca use a de vice Res et. The two latter
events are considered a continuation of program exe-
cution. The T O an d PD bit s in the STATUS register can
be used to determ ine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleare d if W DT Wake-up occurre d.
The follo wing periph eral interrupt s can wake the device
from Sleep:
1. TMR1 interrup t. T imer1 m ust be ope rating as a n
asynchronous counter.
2. ECCP Capture mode interrupt.
3. A/D conversion (when A/D clock source is FRC).
4. EEPROM write operation completion.
5. Comparator output changes state.
6. Interrupt-on-change.
7. External Interrupt from INT pin.
8. EUSART Break detect, I2C slave.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being e xecuted, the next
instruction (PC + 1) is prefetched. For the device to
wake-up thro ugh an interrupt eve nt, the correspon din g
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the inst ruction af ter the SLEEP ins truction. If the GIE b it
is set (enabled), the device executes the instruction
after the SLEEP instruction, then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
14.6.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llow ing wil l occu r:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
comple te as a NOP. Therefore, th e WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, th e devi ce will imme-
diately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. The refore, the WDT and WDT pres caler
and pos tsc aler (if enable d) wi ll be c leared , the T O
bit will be set and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP ins tructio n execut ed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT ins truction
should be executed before a SLEEP instruction.
Note: It shou ld be no ted tha t a Reset generated
by a W DT time-o ut does n ot driv e MCLR
pin low.
Note: If the global interrupts are disabled (GIE is
cleared), but an y interrupt source has both
its interrupt enable bit and the
corresponding interrupt flag bits set, the
device will immediately wake-up from
Sleep. The SLEEP instruction is complete ly
executed.
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FIGURE 14-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
14.7 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification pu rposes.
14.8 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only t he Least Si gnifican t seven b its of t he ID locat ions
are used.
14.9 In-Circuit Seri al Programming
The PIC16 F631/677/685/ 687/689/690 mi crocontrollers
can be serially programmed while in the end applica-
tion circuit. This is simply done with two lines for clock
and data and three other lines for:
• power
• ground
• programming voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
The device is placed into a Program/Verify mode by
holding the RA0/AN0/C1IN+/ICSPDAT/ULPWU and
RA1/AN1/C12IN-/VREF/ICSPCLK pins low, while
raising the MCLR (VPP) pin from VIL to VIHH. See the
“PIC12F6XX/16F6XX Memory Programming
Specification” (DS41204) for more information. RA0
become s the prog ramming d ata and RA 1 becom es the
programming clock. Both RA0 and RA1 are Schmitt
Trigger inputs in this mode.
After Reset, to place the device into Program/Verify
mode, the Program Counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending on
whether the command was a load or a read. For
complete details of serial programming, please refer to
the “PIC12F6XX/16F6XX Memory Programming
Specification” (DS41204).
A typical In-Circuit Serial Programming connection is
shown in Figure 14-11.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC – 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(3)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy Cycle
PC + 2 0004h 0 005h
Dummy Cycle
TOST(2)
PC + 2
Note 1: XT, HS or LP Oscillator mode assume d.
2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
Note: The entire data EEPROM and Flash
program memory will be erased when the
code prot ection is switc hed from on to o f f.
See the “PIC12F6XX/16F6XX Memory
Programming Specification” (DS41204)
for more information.
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FIGURE 14-11: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16F631/677/
VDD
VSS
RA3/MCLR/VPP
RA1
RA0
+5V
0V
VPP
CLK
Data I/O
* * *
*
* Isolation devices (as required)
685/687/689/690
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15.0 INSTRUCTION SET SUMMARY
The PIC 16F690 i nstructio n set i s highly orthogon al and
is comprised of three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction typ e and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 15-1, while the various opcode
fields are sum m ariz ed in Table 15-1.
Table 15-2 lists the instructions recognized by the
MPASMTM assembler.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W regis ter . If ‘d’ is one, the res ult is place d
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency o f 4 MHz, t his gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
change d as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
15.1 Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a CLRF PORTA instruction will read
PORTA, clear all the data bits, then write the result back
to PORTA. This example would have the unintended
consequence of clearing the condition that set the RAIF
flag.
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store re sult in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
CCarry bit
DC Digit carry bit
ZZero bit
PD Power-down bit
Byte-oriente d file regis ter operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriente d file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (lite ra l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
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TABLE 15-2: PIC16F684 INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-OR IENTED FILE REG ISTER OPERATI O N S
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
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15.2 Instruction Descriptions
ADDLW Add literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the 8-bit literal ‘k’
and the result is placed in the
W register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 12 7
d 0,1
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Desc ription: Add the conten ts of the W regis ter
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W registe r . I f
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the 8-bit literal ‘k’.
The result is placed in the W reg-
ister.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 12 7
d 0,1
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the resu lt is stored in
the W register. If ‘d’ is ‘1’, the
result is sto r ed bac k in regi ste r ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Affe cte d: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Affe cte d: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Affe cte d: None
Descr iption: If bit ‘b’ in register ‘f’ is ‘1’ , the next
instruction is executed.
If bit ‘b’ in reg ister ‘f’ is ‘0’, t he ne xt
instruction is disc arded, and a NOP
is exec uted ins tea d, m ak ing thi s a
2-cycle instruction.
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BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Desc ription: If bit ‘b ’ in registe r ‘f’ is ‘0’, the next
instructi on is exec uted .
If bit ‘b’ is ‘1’, then the next
instructi on is dis ca rded and a NOP
is exec ute d i nst ead, making thi s a
2-cycle instruction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The 11-bit immediate
address is loaded into PC bits
<10:0>. The upper bits of the PC
are load ed from PCLA TH. CALL is
a 2-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Desc ript ion : The content s of regi ste r ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affe cte d: TO , PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Affe cte d: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Affe cte d: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
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DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decremen ted. If ‘ d’ is ‘ 0’, the res ult
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘ 0’, then a NOP is
executed instead, making it a
2-cycle instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The 11-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
2-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremen ted. If ‘ d’ is ‘0’, the res ult
is place d in the W registe r. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Affe cte d: None
Description: The contents of register ‘f ’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
registe r ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a 2-cycle
instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Affe cte d: Z
Descr iption: The c ontents of the W regis ter are
OR’ed with th e 8-bit literal ‘k ’. The
resu lt is placed in the W register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 12 7
d [0,1]
Operation: (W) .OR. (f) (dest ination)
Status Affe cte d: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
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MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Desc ript ion : The content s of regi ste r ‘f’ is
moved to a dest ination dependent
upon the status of ‘d’. If d = 0,
destination is W register. If d = 1,
the destination is file register ‘f’
itself. d = 1 is useful to test a file
register since status flag Z is
affected.
Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
W= value in FSR
register
Z= 1
MOVLW Move literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The 8-bit literal ‘k’ is loaded into W
register. The “don’t cares” will
assemble as ‘0’s.
Words: 1
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W= 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
Status Affe cte d: None
Description: Move data from W register to
register ‘f’.
Words: 1
Cycles: 1
Example: MOVW
FOPTION
Before Instruction
OPTION= 0xFF
W = 0x4F
After Instruction
OPTION= 0x4F
W = 0x4F
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affe cte d: None
Description: No operation.
Words: 1
Cycles: 1
Example: NOP
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RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
Description: Return from Interrupt. Stack is
POPed an d Top-of-S tack (T OS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a 2-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affe cte d: None
Description: The W register is loaded with the
8-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a 2-cycle instruction.
Words: 1
Cycles: 2
Example:
TABLE
CALL TABLE;W contains
table ;offset value
• ;W now has
• ;table value
•
•
ADDWF PC;W = offset
RETLW k1;Begin table
RETLW k2 ;
•
•
•
RETLW kn ;End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affe cte d: None
Description: Return from subroutine. The stack
is POPed an d t he top of th e s t a ck
(TOS) is loaded into the program
counter. This is a 2-cycle in struc-
tion.
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RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C=1
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 12 7
d [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The con ten t s of regis te r ‘f’ are
rotat ed one bit to the r ight throug h
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is place d
back in register ‘f ’.
Register fC
Register fC
SLEEP Enter Sleep mode
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affe cte d: TO , PD
Descripti on: The power-d own Status b it, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep
mode with th e oscillat or stopped.
SUBLW Subtract W from literal
Syntax: [ label ] SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
compl ement method) fro m the 8-bit
literal ‘ k’. The resul t is placed in the
W register.
C = 0W k
C = 1W k
DC = 0W<3:0> k<3:0>
DC = 1W<3:0> k<3:0>
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SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
C = 0W f
C = 1W f
DC = 0W<3:0> f<3:0>
DC = 1W<3:0> f<3:0>
XORLW Exclusive OR literal with W
Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affe cte d: Z
Description: The contents of the W register
are XOR’ed with the 8-bi t
literal ‘k’. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Affe cte d: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
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16.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a ful l range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Co s t Demonstration/Develo pment Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
16.1 MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With com plete projec t managem ent, visual cal l graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multipl e project s with simu ltane ous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic cod e f orm atti ng bas ed on us er-d efi ned
rules
• Liv e parsing
User-Friendly, Customiz abl e Interfa ce :
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project -Bas ed Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Loc al file history feature
• Built-in support for Bugzilla issue tracker
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16.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Co mpilers inc lude an asse mbler , li nker and
utilities. The assembler generates relocatable object
files that can then be archived o r l inked wi th ot her rel o-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler inclu de:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
16.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly co de
• Conditional assembly for multipurpose
sour ce fil es
• Directives that allow complete control over the
assembly process
16.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB O bject Li brarian manage s the cre ation an d
modification of library files of precompiled code. When
a rout in e from a l ibra ry is cal led fro m a so urc e file, o nl y
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion an d extraction
16.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archive d o r li nk ed w ith ot her relocatable ob jec t
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
2005-2015 Microchip Technology Inc. DS40001262F-page 223
PIC16F631/677/685/687/689/690
16.6 MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and i nternal regi sters.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent tool .
16.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgrad able through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cable s.
16.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 int erface and is connected to t he target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
16.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
af fordable pr ice point us ing the powerfu l graphica l user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
16.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) f or menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer ca n read, verif y and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 h as high-spe ed co mmunicat ions an d
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
PIC16F631/677/685/687/689/690
DS40001262F-page 224 2005-2015 Microchip Technology Inc.
16.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
use d in teaching envi ronments, for prototyping c ustom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a l ine of evaluation k its and demonstr a-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
16.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools f rom companies, such as Gimpel
and Trace S ystems
• Protocol Analyz er s from com p a nie s, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
2005-2015 Microchip Technology Inc. DS40001262F-page 225
PIC16F631/677/685/687/689/690
17.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias..........................................................................................................-40° to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V
Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin .....................................................................................................................300 mA
Maximum current into VDD pin........................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp cur rent, IOK (Vo < 0 or Vo >VDD)20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin ..............................................................................................25 mA
Maximum current sunk by PORTA, PORTB and PORTC (combined)............................................................200 mA
Maximum current sourced PORTA, PORTB and PORTC (combined)............................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This is a stre ss rating onl y and functi onal operati on of the devi ce at those or an y other condi tions abov e those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather
than pulling this pin directly to VSS.
PIC16F631/677/685/687/689/690
DS40001262F-page 226 2005-2015 Microchip Technology Inc.
FIGURE 17-1: PIC16F63 1/6 77/6 85/6 87/6 89/ 690 VOLTAGE-FREQUE NCY GR APH,
-40°C
TA
+125°C
FIGURE 17-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
Frequency (MHz)
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
82010
125
25
2.0
0
60
85
VDD (V)
4.0 5.04.5
Temperature (°C)
2.5 3.0 3.5 5.5
± 1%
± 2%
± 5%
2005-2015 Microchip Technology Inc. DS40001262F-page 227
PIC16F631/677/685/687/689/690
17.1 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)
PIC16F631/677/685/687/689/690-E (Extended)
DC CHARACTERISTICS Standard Operat ing Conditi ons (unle ss otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym Characteristic Min. Typ† Max. Units Conditions
D001
D001C
D001D
VDD Supply Voltage 2.0
2.0
3.0
4.5
—
—
—
—
5.5
5.5
5.5
5.5
V
V
V
V
FOSC < = 8 MHz: HFINTOSC, EC
FOSC < = 4 MHz
FOSC < = 10 MHz
FOSC < = 20 MHz
D002* VDR RAM Data Retention
Voltage(1) 1.5 — — V Device in Sleep mode
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
—VSS —VSee Section 14.2.1 “Power- on Reset
(POR)” for details.
D004* SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05 — — V/ms See Section 14.2.1 “Power-on Res et
(POR)” for details.
* These parameters are characterized but not tested.
† Data in “Ty p” col um n is at 5.0V, 25°C unless otherwis e st a ted . Thes e p arameters are for des ig n gui dance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
PIC16F631/677/685/687/689/690
DS40001262F-page 228 2005-2015 Microchip Technology Inc.
17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)
PIC16F631/677/685/687/689/690-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40C TA +85C for industrial
-40°C TA +125°C for extended
Param
No. Device Characteristics Min. Typ† Max. Units Conditions
VDD Note
D010 Supply Current (IDD)(1, 2) —1319A2.0FOSC = 32 kHz
LP Oscillator mode
—2230A3.0
—3360A5.0
D011* — 140 240 A2.0F
OSC = 1 MHz
XT Oscillator mode
— 220 380 A3.0
— 380 550 A5.0
D012 — 260 360 A2.0F
OSC = 4 MHz
XT Oscillator mode
— 420 650 A3.0
—0.81.1mA 5.0
D013* — 130 220 A2.0F
OSC = 1 MHz
EC Oscillator mode
— 215 360 A3.0
— 360 520 A5.0
D014 — 220 340 A2.0F
OSC = 4 MHz
EC Oscillator mode
— 375 550 A3.0
—0.651.0mA 5.0
D015 — 8 20 A2.0F
OSC = 31 kHz
LFINTOSC mode
—1640A3.0
—3165A5.0
D016* — 340 450 A2.0F
OSC = 4 MHz
HFINTOSC mode
— 500 700 A3.0
—0.81.2mA 5.0
D017 — 410 650 A2.0F
OSC = 8 MHz
HFINTOSC mode
— 700 950 A3.0
— 1.30 1.65 mA 5.0
D018 — 230 400 A2.0F
OSC = 4 MHz
EXTRC mode(3)
— 400 680 A3.0
—0.631.1mA 5.0
D019 — 3.8 5.0 mA 4.5 FOSC = 20 MHz
HS Oscillator mode
— 4.0 5.45 mA 5.0
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Th e test conditions for all IDD m easurem ents in Active Operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCL R = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. T he current through the resistor can be ext ended
by the formula IR = VDD/2REXT (mA ) with REXT in k.
4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from th i s l imit. Ma x
values should be used when calculating total current consumption.
5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down curre nt is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
2005-2015 Microchip Technology Inc. DS40001262F-page 229
PIC16F631/677/685/687/689/690
D020 Power-down Base
Current(IPD)(2) —0.051.2 A 2.0 WDT, BOR, Comparators, VREF and
T1OSC disabled
—0.151.5 A3.0
—0.351.8 A5.0
— 90 500 nA 3.0 -40°C TA +25°C
D021 — 1.0 2.2 A 2.0 WDT Current (1)
—2.04.0A3.0
—3.07.0A5.0
D022 — 42 60 A 3.0 BOR Current(1)
— 85 122 A5.0
D023 — 32 45 A 2.0 Comparator Current(1), both
comparators enabled
—6078A3.0
— 120 160 A5.0
D024 — 30 36 A2.0CV
REF Current(1) (high range)
—4555A3.0
—7595A5.0
D024a* — 39 47 A2.0CV
REF Current(1) (low range)
—5972A3.0
— 98 124 A5.0
D025 — 2.0 5.0 A 2.0 T1OSC Current, 32.768 kHz
—2.55.5A3.0
—3.07.0A5.0
D026 — 0.30 1.6 A 3.0 A/D Current(1), no conversion in
progress
—0.361.9 A5.0
D027 — 90 125 A 3.0 VP6 Current
— 125 162 A5.0
17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)
PIC16F631/677/685/687/689/690-E (Extended) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40C TA +85C for industrial
-40°C TA +125°C for extended
Param
No. Device Characteristics Min. Typ† Max. Units Conditions
VDD Note
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurem ents in Active Operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCL R = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA ) with REXT in k.
4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD curr e n t fr om thi s l im i t. Max
values should be used when calculating total current consumption.
5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down curre nt is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
PIC16F631/677/685/687/689/690
DS40001262F-page 230 2005-2015 Microchip Technology Inc.
17.3 DC Characteristics: PIC16F631/677/685/687/689/690-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Device Characteristics Min. Typ† Max. Units Conditions
VDD Note
D020E Power-down Base
Current(IPD)(2) —0.05 9 A 2.0 WDT, BOR, Comparators, VREF and
T1OSC disabled
—0.1511 A3.0
—0.3515 A5.0
— 90 500 nA 3.0 -40°C TA +25°C
D021E — 1.0 17.5 A 2.0 WDT Current(1)
—2.019A3.0
—3.022A5.0
D022E — 42 65 A 3.0 B OR Current(1)
— 85 127 A5.0
D023E — 32 45 A 2.0 Comparator Current(1), both
comparators enabled
—6078A3.0
— 120 160 A5.0
D024E — 30 70 A2.0CV
REF Current(1) (high range)
—4590A3.0
— 75 120 A5.0
D024AE* — 39 91 A2.0CV
REF Current(1) (low range)
—59117A3.0
— 98 156 A5.0
D025E — 2.0 18 A 2.0 T1OSC Current
—2.521A3.0
—3.024A5.0
D026E — 0.30 12 A 3.0 A/D Current(1), no conversion in
progress
—0.3616 A5.0
D027E — 90 130 A 3.0 V P6 Current
— 125 170 A5.0
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These p arameters are for design guidance only and are
not tested.
Note 1: Th e test conditions for all IDD m easurem ents in Active Operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCL R = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA ) with REXT in k.
4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from th i s l imit. Ma x
values should be used when calculating total current consumption.
5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down curre nt is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
2005-2015 Microchip Technology Inc. DS40001262F-page 231
PIC16F631/677/685/687/689/690
17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)
PIC16F631/677/685/687/689/690-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
VIL Input Low Volt a ge
I/O Port:
D030 with TTL buffer Vss — 0.8 V 4.5V VDD 5.5V
D030A Vss — 0.15 VDD V2.0V VDD 4.5V
D031 with Schmitt Trigger buff er Vss — 0.2 VDD V2.0V VDD 5.5V
D032 MCLR, OSC1 (RC mode)(1) VSS —0.2 VDD V
D033 O SC1 (XT and LP modes) VSS —0.3V
D033A OSC1 (HS mode) VSS —0.3 VDD V
VIH Input High Voltage
I/O Ports: —
D040 with TTL buffer 2.0 — VDD V4.5V VDD 5.5V
D040A 0.25 VDD + 0.8 — VDD V2.0V VDD 4.5V
D041 with Schmitt Trigger buffer 0.8 VDD —VDD V2.0V VDD 5.5V
D042 MCLR 0.8 VDD —VDD V
D043 O SC1 (XT and LP modes) 1.6 — VDD V
D043A OSC1 (HS mode) 0.7 VDD —VDD V
D043B OSC1 (RC mode) 0.9 VDD —VDD V(Note 1)
IIL Input Leakage Current(2)
D060 I /O ports — 0.1 1AVSS VPIN VDD,
Pin at high-impedance
D061 MCLR(3) —0.1 5AVSS VPIN VDD
D063 OSC1 — 0.1 5AVSS VPIN VDD, XT, HS and
LP oscillator configuration
D070* IPUR PORTA Weak Pull-up Current 50 250 400 AVDD = 5.0V, VPIN = VSS
VOL Output Low Voltage(5)
D080 I /O ports — — 0.6 V I OL = 8.5 mA, VDD = 4.5V (Ind.)
VOH Outp ut H i gh Vo ltage(5)
D090 I /O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.)
D100 IULP Ultra Low-Power Wake-up
Current — 200 — nA See Application Note AN879,
“Using the Microchip Ultra
Low-Power Wake-up Module”
(DS00879)
Capacitive Loading S pecs on
Output Pins
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
Note 1: In RC oscillator configuration, the OSC1/ CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 10.2.1 “Using the Data EEPROM” for additional information.
5: Including OSC2 in CLKOUT mode.
PIC16F631/677/685/687/689/690
DS40001262F-page 232 2005-2015 Microchip Technology Inc.
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
Data EEPROM Memory
D120 EDByte Endurance 100K 1M — E/W -40°C TA +85°C
D120A EDByte Endurance 10K 100K — E/W +85°C TA +125°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V U s ing EECON1 to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time — 5 6 ms
D123 TRETD Characteristic Retention 40 — — Y ear Provided no other specifications
are violated
D124 TREF Number of Total Erase/Write
Cycles before Refresh(4) 1M 10M — E/W -40°C TA +85°C
Program Flash Memory
D130 EPCell Endurance 10K 100K — E/W -40°C TA +85°C
D130A EDCell Endurance 1K 10K — E/W +85°C TA +125°C
D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating
voltage
D132 VPEW VDD for Erase/Write 4.5 — 5.5 V
D133 TPEW Erase/Write cycle time — 2 2.5 ms
D134 TRETD Characteristic Retention 40 — — Y ear Provided no other specifications
are violated
17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)
PIC16F631/677/685/687/689/690-E (Extended) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
no t te sted.
Note 1: In RC oscillator configuration, the O SC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 10.2.1 “Using the Data EEPROM” for additional information.
5: Including OSC2 in CLKOUT mode.
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17.5 Thermal Considerati ons
Standard Operating Conditions (unless otherwise stated)
Ope rati ng temperature -40°C TA +125°C
Param
No. Sym. Characteristic Typ. Units Conditions
TH01 JA Thermal Resistance
Junction to Ambient 62.4 C/W 20-pin PDIP package
85.2 C/W 20-pin SOIC package
108 .1 C/W 20-pin SSOP package
40 C/W 20-pin QFN 4x4mm package
TH02 JC Thermal Resistance
Junction to Case 28.1 C/W 20-pin PDIP package
24.2 C/W 20-pin SOIC package
32.2 C/W 20-pin SSOP package
2.5 C/W 20-pin QFN 4x4mm package
TH03 TDIE Die Temperature 150 C For derated power calculations
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD
(Note 1)
TH06 PI/OI/O Power Dissipation — W PI/O = (IOL * V OL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TDIE - TA)/JA
(Note 2, 3)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature.
3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power
dissipation or derated power.
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17.6 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
FIGURE 17-3: LOAD CONDITIONS
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O Port t1 T1CKI
mc MCLR wr WR
Uppe rcase lett ers an d thei r meanings:
SFFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
V
SS
C
L
Legend: CL= 50 pFfor all pins
15 pF for OSC2 output
Load Con dition
Pin
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17.7 AC Characteristics: PIC16F631/677/685/687/689/690 (Industrial, Extended)
FIGURE 17-4: CLOCK TIMING
TABLE 17-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode
DC — 4 MHz XT Oscillator mode
DC — 20 MHz HS Oscillator mode
DC — 20 MHz EC Oscillator mode
Oscillator Frequency(1) — 32.768 — kHz LP Os cillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 20 MHz HS Oscillator mode
DC — 4 MHz RC Oscillator mode
OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator mode
250 — ns XT Oscillator mode
50 — ns HS Oscillator mode
50 — ns EC Oscillator mode
Oscillator Period(1) — 30.5 — s LP Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,000 ns HS Oscillator mode
250 — — ns RC Oscillator mode
OS03 TCY Instruction Cycle Time (1) 200 TCY DC ns TCY = 4/FOSC
OS04* TOSH,
TOSLExternal CLKIN High,
External CLKIN Low 2——s LP oscillator
100 — — ns XT oscillator
20 — — ns HS oscillator
OS05* TOSR,
TOSFExternal CLKIN Rise,
External CLKIN Fall 0—ns LP oscillator
0—ns XT oscillator
0—ns HS oscillator
* These parameters are characterized but not tested.
† Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an
external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.
OSC1/CLKIN
OSC2/CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
OS02
OS03OS04 OS04
OSC2/CLKOUT
(LP,XT,HS Modes)
(CLKOUT Mode)
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TABLE 17-2: OSCILLATOR PARAMETERS
Standard Operati ng Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Freq.
Tolerance Min. Typ† Max. Units Conditions
OS06 TWARM Internal Oscillator Switch
when running(3) ———2TOSC Slowest clock
OS07 TSC Fail-Safe Sample Clock
Period(1) ——21—msLFINTOSC/64
OS08 HFOSC Internal Calibrated
HFINTOSC Frequency(2) 1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C
2% 7.84 8.0 8.16 MHz 2.5V VDD 5.5V,
0°C TA +85°C
5% 7.60 8.0 8.40 MHz 2.0V VDD 5.5V,
-40°C TA +85°C (Ind.),
-40°C TA +125°C (Ext.)
OS09* LFOSC Internal Uncalibrated
LFINTOSC Frequency — 153145kHz
OS10* TIOSC ST HFINTOSC Oscillator
Wake-up from Sleep
Start-up Time
— 5.5 12 24 sVDD = 2.0V, -40°C to +85°C
—3.5714sV
DD = 3.0V, -40°C to +85°C
—3611sV
DD = 5.0V, -40°C to +85°C
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruc tion cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the OSC1 pin.
When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
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FIGURE 17-5: CLKOUT AND I/O TIMING
FOSC
CLKOUT
I/O pi n
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
OS11
OS19
OS13
OS15
OS18, OS19
OS20
OS21
OS17 OS16
OS14
OS12
OS18
Old Value New Value
Write Fetch Read ExecuteCycle
TABLE 17-3: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditi ons (unle ss otherw is e stated )
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
OS11 TOSH2CKLFOSC to CLKOUT (1) — — 70 ns VDD = 5.0V
OS12 TOSH2CKHFOSC to CLKOUT (1) — — 72 ns VDD = 5.0V
OS13 TCKL2IOVCLKOUT to port out valid(1) — — 20 ns
OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TOSH2IOVFOSC (Q1 cycle) to port out valid — 50 70* ns VDD = 5.0V
OS16 TOSH2IOIFOSC (Q2 cycle) to port input invalid
(I/O in hold time) 50 — — ns VDD = 5.0V
OS17 TIOV2OSH Port input valid to FOSC(Q2 cycle)
(I/O in setup time) 20 — — ns
OS18 TIOR Port output rise time(2) —
—15
40 72
32 ns VDD = 2.0V
VDD = 5.0V
OS19 TIOF Port output fall time(2) —
—28
15 55
30 ns VDD = 2.0V
VDD = 5.0V
OS20* TINP INT pin input high or low time 25 — — ns
OS21* TRAP PORT A interrupt-on-change new input
level time TCY ——ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Includes OSC2 in CLKOUT mode.
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FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 17-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-up T ime
Internal Reset(1)
Wat c hdog Timer
33
32
30
31
34
I/O pins
34
Note 1: Asserted low.
Reset(1)
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33*
37
* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
Reset
(due to BOR)
VBOR + VHYST
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TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditi ons (unle ss otherw is e stated )
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
30 TMCLMCLR Pulse Width (low ) 2
5—
——
—s
sVDD = 5V, -40°C to +8 5°C
VDD = 5V
31 TWDT Watch dog Timer Ti me-out
Period (No Prescaler) 10
10 17
17 25
30 ms
ms VDD = 5V, -40°C to +85°C
VDD = 5V
32 TOST Oscillation Start-up Timer
Period(1, 2) —1024—TOSC (Note 3)
33* TPWRT Power-up Timer Period 40 65 140 ms
34* TIOZ I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
——2.0s
35 VBOR Brown-out Reset Voltage 2.0 — 2.2 V (Note 4)
36* VHYST Brown-out R eset Hyster esis — 50 — mV
37* TBOR Brown-out Reset Minimu m
Detection Period 100 — — sVDD VBOR
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: Instruct ion cy cle pe riod (TCY) equals four times the input oscillator time base period. All specified values
are based on charac teri za tion data for that particular oscilla tor type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values
with an external clock applied to the OSC1 pin. When an external clock input is used, the ‘max’ cycle time
limit is ‘DC’ (no clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure thes e voltag e toleranc es, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
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FIGURE 17-8: TIMER0 AND TIMER1 EX TERNAL CLOCK TIMINGS
TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CK I Period Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* TT1H T1CKI High
Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous,
with Presc aler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CK I Low
Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous,
with Presc aler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI Input
Period Synchronous Greater of:
30 or TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Asynchronous 60 — — ns
48 FT1 Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN) — 32.768 — kHz
49* TCKEZTMR1 Delay from External Clock Edge to Timer
Increment 2 TOSC —7 TOSC — Timers in Sync
mode
* These parameters are characterized but not tested.
† Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
T0CKI
T1CKI
40 41
42
45 46
47 49
TMR0 or
TMR1
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FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP)
TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)
Standard Operating Conditi ons (unle ss otherw is e stated )
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns
With Prescaler 20 — — ns
CC03* TccP CCP1 Input Period 3TCY + 40
N— — ns N = prescale
value (1, 4 or
16)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note: Refer to Figure 17-3 for load conditions.
(Capture mode)
CC01 CC02
CC03
CCP1
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TABLE 17-7: COMPARATOR SPEC IFICATIONS
TABLE 17-8: COMPA RATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
TABLE 17-9: VOLTAGE (VR) REFERENCE SPECIFICATIONS
Comparator Specifications Standard Operating Condit ions (unless otherwi se stated)
Operating temperature -40°C TA +125°C
Param.
No. Sym. Characteristics Min. Typ. Max. Units Comments
CM01 VOS Input Offset Voltage — 5.0 10 mV
CM02 VCM Input Co mmon Mode Voltage 0 — VDD - 1.5 V
CM03* CMRR Common Mode Rejection Ratio +55 — — db
CM04* TRT Response Time Falling — 150 600 ns (Note 1)
Rising — 200 1000 ns
CM05* TMC2COV Comparator Mode Change to Output
Valid —— 10 s
* These parameters are characterized but not tested.
Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/ 2 + 20 mV.
S tandard Operating Conditi ons (unle ss otherwise st ated )
Operati ng tem pera ture -40°C TA +125°C
Param
No. Sym. Characteristics Min. Typ† Max. Units Comments
CV01* CLSB Step Size(2) —
—VDD/24
VDD/32 —
—V
VLow Range (VRR = 1)
High Range (VRR = 0)
CV02* CACC Absolute Accuracy —
——
— 1/2
1/2 LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
CV03* CRUnit Resistor Value (R) — 2k —
CV04* CST Settli ng Time(1) ——10s
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
2: See Section 8.10 “Comparator Voltage Reference” for more information.
VR Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No. Symbol Characteristics Min. Typ. Max. Units Comments
VR01 VROUT VR volt ag e outp ut 0.5 0.6 0.7 V
VR02* TSTABLE Settling Time — 10 100* s
* These parameters are characterized but not tested.
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FIGURE 17-10: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 17-10: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 17-11: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 17-11: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
120 TCKH2DTV SYNC XMIT (Master & Slave)
Clock high to data-out valid —40ns
121 TCKRF Clock out rise time and fall time (Master mode) — 20 ns
122 TDTRF Data-out rise time and fall time — 20 ns
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
No. Symbol Characteristic Min. Max. Units Conditions
125 TDTV2CKL SYNC RCV (Master & Slave)
Data-hold before CK (DT hold time) 10 — ns
126 TCKL2DTL Data-hold after CK (DT hold time) 15 — ns
Note: Refer to Figure 17-3 for load conditions.
121 121
120 122
RB7/TX/CK
RB5/AN11/RX/DT
pin
pin
Note: Refer to Figure 17-3 for load conditions.
125
126
RB7/TX/CK
RB5/AN11/RX/DT
pin
pin
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FIGURE 17-12 : SP I MAST ER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 17-13 : SP I MAST ER MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In LSb In
bit 6 - - - -1
Note: Refer to Figure 17-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 17-3 for load conditions.
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FIGURE 17-14 : SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 17-15 : SPI SLAVE MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In bit 6 - - - -1 LSb In
83
Note: Refer to Figure 17-3 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
74
75, 76
MSb bit 6 - - - - - -1 LSb
77
MSb In bit 6 - - - -1 LSb In
80
83
Note: Refer to Figure 17-3 for load conditions.
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TABLE 17-12: SPI MODE REQUIREMENTS
FIGURE 17-16 : I2C™ BUS START/STOP BITS TIMING
Param
No. Symbol Characteristic Min. Typ† Max. Units Conditions
70* TSSL2SCH,
TSSL2SCLSS to SCK or SCK input TCY ——ns
71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
73* TDIV2SCH,
TDIV2SCLSetup time of SDI data i nput to SCK edge 100 — — ns
74* TSCH2DIL,
TSCL2DILHold time of SDI data input to SCK edge 100 — — ns
75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns
2.0-5.5V — 25 50 ns
76* TDOF SDO data output fall time — 10 25 ns
77* TSSH2DOZSS to SDO output high-impedance 10 — 50 ns
78* TSCR SCK output rise time
(Master mode) 3.0-5.5V — 10 25 ns
2.0-5.5V — 25 50 ns
79* TSCF SCK output fall time (Master mode) — 10 25 ns
80* TSCH2DOV,
TSCL2DOVSDO data output valid after
SCK edge 3.0-5.5V — — 50 ns
2.0-5.5V — — 145 ns
81* TDOV2SCH,
TDOV2SCLSDO data output setup to SCK edge Tcy — — ns
82* TSSL2DOV SDO data output valid after SS edge — — 50 ns
83* TSCH2SSH,
TSCL2SSHSS after SCK edge 1.5TCY + 40 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note: Refer to Figure 17-3 for load conditions.
91
92
93
SCL
SDA
Start
Condition Stop
Condition
90
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TABLE 17-13: I2C™ BUS STAR T/STOP BITS REQUIREMENTS
FIGURE 17-17 : I2C™ BUS DATA TIMING
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Start conditio n
Setup time 400 kHz mode 600 — —
91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
clock pulse is generated
Hold time 400 kHz mode 600 — —
92* TSU:STO Stop condition 100 kHz mo de 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO Stop condition 100 kHz mo de 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
Note: Refer to Figure 17-3 for load conditions.
90
91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
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TABLE 17-14: I2C™ BUS DATA REQUIREM ENTS
Param.
No. Symbol Characteristic Min. Max. Units Conditions
100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP Module 1.5TCY —
102* TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1CB300 ns CB is specified to be from
10-400 pF
103* TFSDA and SCL fall
time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1CB300 ns CB is specified to be from
10-400 pF
90* TSU:STA Start condition
setup time 100 kHz mode 4.7 — s Only relevant for
Repeated Start condition
400 kHz mode 0.6 — s
91* THD:STA Start condition hold
time 100 kHz mode 4.0 — s After this period the firs t
clock pulse is generated
400 kHz mode 0.6 — s
106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
107* TSU:DAT Data input setup
time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92* TSU:STO Stop condition
setup time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109* TAA Output valid from
clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110* TBUF Bus free time 100 kHz mode 4.7 — s T ime th e bus m ust be free
before a new transmission
can start
400 kHz mode 1.3 — s
CBBus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus de vice can be used in a Standard m ode (10 0 kH z) I2C bus system, but the
requiremen t TSU:DAT 250 ns mus t then be m et. This will a utom at ic all y be the c ase if the device do es n ot
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must outpu t the next dat a b it to the SDA line TR max. + TSU:DAT = 1000 + 250 = 12 50 ns (accord ing to th e
Standard mode I2C bus specification), before the SCL line i s released.
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TABLE 17-15: A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Ope rati ng temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
AD01 NRResolution — — 10 bits bit
AD02 EIL Integral Error — — 1LSbVREF = 5.12V
AD03 EDL Differential Error — — 1 LSb No missing codes to 10 bits
VREF = 5.12V
AD04 EOFF Offset Error — — 1LSbVREF = 5.12V
AD04A — +1.5 +3.0 LSb (PIC16F677 only)
AD07 EGN Gain Error — — 1LSbVREF = 5.12V
AD06
AD06A VREF Reference Voltage(3) 2.2
2.5 ——
VDD VAbsolute minimum to ensure 1 LSb
accuracy
AD07 VAIN Full-Scale Range VSS —VREF V
AD08 ZAIN Recommended
Impedance of Analog
Voltage Source
—— 10k
AD09* IREF VREF Input Current(3) 10 — 1000 ADuring VAIN acquisition.
Based on differential of VHOLD to VAIN.
—— 50A During A/D conver sion cycle
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current
specification includes any such leakage from the ADC module.
PIC16F631/677/685/687/689/690
DS40001262F-page 250 2005-2015 Microchip Technology Inc.
FIGURE 17-18: A/D CONVERSION TIMING (NORMAL MODE)
TABLE 17-16: A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
130* TAD A/D Clock Pe riod 1.5 — — sTOSC-based, VREF 2.5V
3.0* — — sT
OSC-based, VREF full range
A/D Internal RC
Oscillator Perio d 3.0* 6.0 9.0* sADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0* 4.0 6.0* sAt V
DD = 5.0V
131 TCNV Conversion Time
(not includin g
Acquisiti on Time)(1)
—11—TAD Set GO bit to ne w data in A/D Result
register
132* TACQ Acquisition Time (2)
5*
11.5
—
—
—
s
s The minimum time is the amplifier
settling time. This may be used if th e
“new” in put v olt age has n ot ch an ged
by more than 1 LSb (i.e., 4.1 mV @
4.096V) from the last sampled
volt a ge (as sto red on CHOLD).
134 TGO Q4 to A/D Clock
Start —TOSC/2 — — If the A/ D clock sou rce is se lected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEP instruction to be executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.
2: See Table 9-1 for minimum conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
987 3210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
6
134 (TOSC/2)(1)
1 TCY
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FIGURE 17-19 : A/D C ONV ER SION TIMING (SLEEP MODE)
TABLE 1: A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
130* TAD A/D Internal RC
Oscillator Period 3.0* 6.0 9.0* sADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0* 4.0 6.0* sAt V
DD = 5.0V
131 TCNV Conversion Time
(not including
Acquisition T ime)(1)
—11—TAD
132* TACQ Acquisition Time (2)
5*
11.5
—
—
—
s
s The minimum time is the am pli fie r
settling time. This may be used if
the “new” input voltage has not
changed by m ore than 1 LS b (i.e. ,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
CHOLD).
134 TGO Q4 to A/D Clock
Start —TOSC/2 + TCY — — If the A/D clock s ource is sel ected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruc tion to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: ADRES register may be read on the following TCY cy cle.
2: See Table 9-1 for minimum conditions.
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
9 7 3210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
134
6
8
132
1 TCY
(TOSC/2 + TCY)(1)
1 TCY
PIC16F631/677/685/687/689/690
DS40001262F-page 252 2005-2015 Microchip Technology Inc.
17.8 High Temperature Operation
This se ction outl ines the sp ecifica tions for the following
devices operating in the high temperature range
between -40°C and 150°C.(4)
•PIC16F685
•PIC16F687
•PIC16F689
•PIC16F690
When the value of any parameter is identical for both
the 125°C Extended and the 150°C High Temp.
tempera ture rang es, then tha t value w ill be f ound in th e
standard specification tables shown earlier in this
chapter, under the fields listed for the 125°C Extended
temperature range. If the value of any parameter is
unique to the 150°C High Temp. temperature range,
then it will be listed here, in this section of the data
sheet.
If a Silicon Errata exists for the product and it lists a
modific ation to the 1 25°C Extende d temp erature range
value, one that is al so shared at th e 1 50°C High Temp.
temperature range, then that modified value will apply
to both temperature ranges.
TABLE 17-17: ABSOLUTE MAXIMUM RATINGS
Note 1: Writes are not allowed for Flash
program memory above 125°C.
2: All AC timing specifications are incre ased
by 30%. This derating factor will include
param ete rs such as TPWRT.
3: The temperature range indicator in the
catalog part number and device marking
is “H” for -40°C to 150°C.
Example: PIC16F685T-H/SS indicates
the device is shipped in a Tape and reel
confi g ur at io n, in t he SSO P packa g e, an d
is rated for operation from -40°C to
150°C.
4: AEC-Q100 reliability testing for devices
intended to operate at 150°C is 1,000
hours. An y design in which t he tot al oper-
ating time from 125°C to 150°C will be
greate r than 1,000 hours is not warranted
without prior written approval from
Microchip Technology Inc.
5: Endurance of the data EEPROM
decreases with increasing temperature. It
is recommended that the number of pro-
gramming cycles to any individual
address at temperatures above +125°C
not exceed 25,000. Error correction tech-
niques are advised for data requiring
more programming cycles above +125°C.
6: DS80243 Table 1 refers to various revi-
sions of the PIC16F685, but operation
above +125°C will only be available for
revision A6 or later.
7: The +150°C version of the PIC16F685
will not be offered in PDIP. It will only be
offered in SSOP, SOIC, and QFN.
Parameter Source/Sink Value Units
Max. Current: VDD Source 20 mA
Max. Current: VSS Sink 50 mA
Max. Current: Pin Source 5 mA
Max. Current: Pin Sink 10 mA
Max. Pin Current: at VOH Source 3 mA
Max. Pin Current: at VOL Sink 8.5 mA
Max. Port Current: A, B, and C
combined Source 20 mA
Max. Port Current: A, B, and C
combined Sink 50 mA
Max. Junction Temperature 155 °C
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device . This is a stres s rating only, and functional op era tion of the devic e at thos e or any other con di tions
above those indicated in the operation listings of this specification is not implied. Exposure above
maximum rating conditions for extended periods may affect device reliability.
2005-2015 Microchip Technology Inc. DS40001262F-page 253
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FIGURE 17-20 : VOL TAGE-FREQUENCY GRAPH, -40°C
TA
+150°C
FIGURE 17-21: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
Frequency (MHz)
VDD (V)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
82010
125
25
2.1
0
60
85
VDD (V)
4.0 5.04.5
Temperature (°C)
2.5 3.0 3.5 5.5
± 1%
± 2%
± 5%
150
-40
± 7.5%
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TABLE 17-18: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V,
VREF > 2.5V)
ADC Clock Period (TAD) Device Freque ncy (FOSC)
ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz
Fosc/2 000 100 ns 250 ns 500 ns 2.0 s
Fosc/4 100 200 ns 500 ns 1.0 s4.0 s
Fosc/8 001 400 ns 1.0 s2.0 s8.0 s
Fosc/16 101 800 ns 2.0 s4.0 s16.0 s
Fosc/32 010 1.6 s4.0 s8.0 s32.0 s
Fosc/64 110 3.2 s8.0 s16.0 s64.0 s
Frc x11 2-6 s2-6 s2-6 s2-6 s
Legend: Shaded cells should not be used for conversions at temperatures above +125°C.
Note 1: TAD mus t be between 1.6 s and 4.0 s.
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TABLE 17-19: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC16F685/687/689/690-H
(High Temp.)
Param
No. Device
Characteristics Min. Typ. Max. Units Condition
VDD Note
D001 VDD 2.1 — 5.5 V — FOSC 8 MHz: HFINTOSC, EC
2.1 — 5.5 V — FOSC 4 MHz
D010 Supply Current (IDD)— —47
A2.1 Fosc = 32 kHz
LP Oscillator
— — 69 3.0
——108 5.0
D011 — — 357
A2.1 Fosc = 1 MHz
XT Oscill ator
——533 3.0
——729 5.0
D012 — — 535 A2.1 Fosc = 4 MHz
XT Oscill ator
——875 3.0
— — 1.32 mA 5.0
D013 — — 336
A2.1 Fosc = 1 MHz
EC Oscillator
——477 3.0
——777 5.0
D014 — — 505 A2.1 Fosc = 4 MHz
EC Oscillator
——724 3.0
— — 1.30 mA 5.0
D015 — — 51 A2.1 Fosc = 31 kHz
LFINTOSC
— — 92 3.0
——117mA 5.0
D016 — — 665 A2.1 Fosc = 4 MHz
HFINTOSC
——970 3.0
— — 1.56 mA 5.0
D017 — — 936 A2.1
Fosc = 8 MHz
HFINTOSC
——1.34
mA 3.0
— — 2.27 5.0
D018 — — 605 A2.1 Fosc = 4 MHz
EXTRC
——903 3.0
— — 1.43 mA 5.0
D019 — — 6.61 mA 4.5 Fosc = 20 MHz
HS Oscillator
— — 7.81 5.0
PIC16F631/677/685/687/689/690
DS40001262F-page 256 2005-2015 Microchip Technology Inc.
TABLE 17-20: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC16F685/687/689/690-H
(High Temp.)
TABLE 17-21: LEAKAGE CURRENT SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.)
TABLE 17-22: DATA EEPROM MEMORY ENDURANCE SPECIFICATIONS FOR
PIC16F685/687/689/690-H (High Temp.)
Param
No. Device
Characteristics Units Min. Typ. Max. Condition
VDD Note
D020E Power Down Base
Current (IPD)—— 27
A2.1 IPD Base: WDT, BOR,
Compar ators, VREF and
T1OSC disabled
—— 29 3.0
—— 32 5.0
D021E — — 55
A2.1 WDT Current—— 59 3.0
—— 69 5.0
D022E — — 75 A3.0 BOR Cu rrent
—— 147 5.0
D023E — — 73
A2.1 Co mparator current, both
comparators enabled
—— 117 3.0
—— 235 5.0
D024E — — 102
A2.1 CVREF current, high range—— 128 3.0
—— 170 5.0
D024AE — — 133
A2.1 CVREF current, low range—— 167 3.0
—— 222 5.0
D025E — — 36
A2.1 T1OSC current, 32 kHz—— 41 3.0
—— 47 5.0
D026E — — 22 A3.0 Analog-to-Digital current,
no conver sion in progress
—— 24 5.0
D027E — — 189 A3.0 VP6 current (Fixed Voltage
Reference)
—— 250 5.0
Param
No. Sym. Characteristic Min. Typ. Max. Unit s Conditions
D061 IIL Input Leakage Current(1)
(RA3/MCLR)— ±0.5 ±5.0 µA VSS VPIN VDD
D062 IIL Input Leakage Current(2)
(RA3/MCLR)50 250 400 µA VDD = 5.0V
Note 1: This specification applies when RA3/MCLR is configured as an input with the pull-up disabled. The
leakage current for the RA3/MCLR pin is higher than for the standard I/O port pins.
2: This specification applies when RA3/MCLR is configured as the MCLR reset pin function with the weak
pull-up enabled.
Param
No. Sym. Characteristic Min. Typ. Max. Unit s Conditions
D120A EDByte Endurance 5K 50K — E/W 126°C TA 150°C
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TABLE 17-23: OSCILLATOR PARAMETERS FOR PIC1 6F685/68 7/68 9/69 0-H (High Temp.)
TABLE 17-24: WATCHDOG TIMER SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.)
TABLE 17-25: BROWN-OUT RESET SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.)
TABLE 17-26: COMPARATOR SPECIFICATIONS FOR PIC16F685/687/689/690-H (High Temp.)
Param
No. Sym. Characteristic Frequency
Tolerance Min. Typ. Max. Units Conditions
OS08 INTOSC Int. Calibrated INT O SC
Freq.(1) ±7.5% 7.4 8.0 8.6 MHz 2.1V VDD 5.5V
-40°C TA 150°C
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended.
Param
No. Sym. Characteristic Min. Typ. Max. Unit s Conditions
31 TWDT Watchdog Timer Time-out Period
(No Prescaler) 10 20 70 ms 150°C Temperature
Param
No. Sym. Characteristic Min. Typ. Max. Unit s Conditions
35 VBOR Brown-Out Reset Voltage 2.0 — 2.3 V 150°C Temperature
Param
No. Sym. Characteristic Min. Typ. Max. Unit s Conditions
CM01 VOS Input Offset Voltage — ±5 ±20 mV (VDD - 1.5)/2
PIC16F631/677/685/687/689/690
DS40001262F-page 258 2005-2015 Microchip Technology Inc.
18.0 DC AND AC CH ARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
“Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents
(mean + 3) or (mean - 3) respectively , where is a standard deviation, over each temperature range.
FIGURE 18-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
Note: The gra phs an d tables provided foll ow in g thi s n ote a r e a s t ati st ica l s um mar y based on a limite d number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
3.0V
4.0V
5.0V
5.5V
2.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FOSC
IDD (mA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -c ase Tem p) + 3
(-40°C to 125°C)
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FIGURE 18-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
EC Mode
3.0V
4.0V
5.0V
2.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
FOSC
IDD (mA)
5.5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -c ase Tem p) + 3
(-40°C to 125°C)
Typical IDD vs FOSC Over Vdd
HS Mode
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4 MHz 10 MHz 16 MHz 20 MHz
FOSC
IDD (mA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
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FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
FIGURE 18-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE)
Maximum IDD vs FOSC Over Vdd
HS Mode
3.5V
4.0V
4.5V
5.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4 MHz 10 MHz 16 MHz 20 MHz
FOSC
IDD (mA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
3.0V
5.5V
XT Mode
0
100
200
300
400
500
600
700
800
900
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
4 MHz
1 MHz
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FIGURE 18-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)
FIGURE 18-7: IDD vs. VDD (LP MODE)
XT Mode
0
200
400
600
800
1,000
1,200
1,400
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
4 MHz
1 MHz
0
10
20
30
40
50
60
70
80
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (uA)
Typical: Statisti cal Mean @25°C
Maximum: Mean (Worst-cas e Temp) + 3
(-40°C to 125°C)
32 kHz Maximum
32 kHz Typical
PIC16F631/677/685/687/689/690
DS40001262F-page 262 2005-2015 Microchip Technology Inc.
FIGURE 18-8: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)
FIGURE 18-9: MAXIMUM IDD vs. VDD OVER FOSC (EXTRC MODE)
EXTRC Mode
0
100
200
300
400
500
600
700
800
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (A)
1 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
4 MHz
EXTRC Mode
0
200
400
600
800
1,000
1,200
1,400
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IDD (A)
Typical: Statistical Mean @25°C
Maximum: Mea n (Worst-c ase Tem p) + 3
(-40°C to 125°C)
4 MHz
1 MHz
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FIGURE 18-10 : IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)
FIGURE 18-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)
LFINTOSC Mode, 31KHZ
Typical
Maximum
0
10
20
30
40
50
60
70
80
VDD (V)
IDD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
HFINTOSC
2.0V
3.0V
4.0V
5.0V
5.5V
0
200
400
600
800
1,000
1,200
1,400
1,600
125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
FOSC
IDD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
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FIGURE 18-12 : MAXIMU M IDD vs. FOSC OVER VDD (HFINTOSC MODE)
FIGURE 18-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
HFINTOSC
2.0V
3.0V
4.0V
5.0V
5.5V
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz
FOSC
IDD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
Typical
(Sleep Mode all Peripherals Disabled)
0.0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -case Temp) + 3
(-40°C to 125°C)
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PIC16F631/677/685/687/689/690
FIGURE 18-14 : MAXIMU M IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
FIGURE 18-15 : CO MPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)
Maximum
(Sleep Mode all Peripherals Disabled)
Max. 125°C
Max. 85°C
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
2.02.5 3.03.5 4.04.5 5.05.5
VDD (V)
IPD (A)
Maximum: Mean + 3
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
0
20
40
60
80
100
120
140
160
180
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Wors t-c ase Tem p) + 3
(-40°C to 125°C)
PIC16F631/677/685/687/689/690
DS40001262F-page 266 2005-2015 Microchip Technology Inc.
FIGURE 18-16 : BO R IPD vs. VDD OV ER TEMP ER ATURE
FIGURE 18-17: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE
0
20
40
60
80
100
120
140
160
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
Maximum
Typical
Typical
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typical: Statistical Mean @25°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
2005-2015 Microchip Technology Inc. DS40001262F-page 267
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FIGURE 18-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
FIGURE 18-19 : WD T PERIO D vs. VDD OVER TEMPERATURE
Maximum
Max. 125°C
Max. 85°C
0.0
5.0
10.0
15.0
20.0
25.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Wors t-case Tem p) + 3
(-40°C to 125°C)
Minimum
Typical
10
12
14
16
18
20
22
24
26
28
30
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (ms)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C) Max. (125°C)
Max. (85°C)
PIC16F631/677/685/687/689/690
DS40001262F-page 268 2005-2015 Microchip Technology Inc.
FIGURE 18-20: WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V)
FIGURE 18-21 : CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)
Vdd = 5V
10
12
14
16
18
20
22
24
26
28
30
-40°C 25°C 85°C 125°C
Temperature (°C)
Time (ms)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
Maximum
Typical
Minimum
High Range
Typical
Max. 85°C
0
20
40
60
80
100
120
140
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Max. 125°C
Typical: Statistical Mean @25°C
Maximum: Me an (Wors t-case Te mp) + 3
(-40°C to 125°C)
2005-2015 Microchip Technology Inc. DS40001262F-page 269
PIC16F631/677/685/687/689/690
FIGURE 18-22 : CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)
FIGURE 18-23: TYPICAL VP6 REFERENCE IPD vs. VDD (25°C)
Typical
Max. 85°C
0
20
40
60
80
100
120
140
160
180
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Max. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
VP6 Reference IPD vs. VDD (25×C)
0
20
40
60
80
100
120
140
160
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (uA)
Typical
PIC16F631/677/685/687/689/690
DS40001262F-page 270 2005-2015 Microchip Technology Inc.
FIGURE 18-24: MAXIMUM VP6 REFERENCE IPD vs. VDD OVER TEMPERATURE
FIGURE 18-25 : T1O SC IPD vs. VDD OVER TEMPERATURE (32 kHz)
Max VP6 Reference IPD vs. VDD Over Temperature
0
20
40
60
80
100
120
140
160
180
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (uA)
Max 125C
Max 85C
Typ 25×C Max 85×C Max 125×C
2 2.022 4.98 17.54
2.5 2.247 5.23 19.02
3 2.472 5.49 20.29
3.5 2.453 5.79 21.50
4 2.433 6.08 22.45
4.5 2.711 6.54 23.30
5 2.989 7.00 24.00
5.5 3.112 7.34 Typ. 25°C
Max. 85°C
Max. 125°C
0
5
10
15
20
25
30
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (uA)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
2005-2015 Microchip Technology Inc. DS40001262F-page 271
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FIGURE 18-26 : VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
FIGURE 18-27 : VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
(VDD = 3V, -40×C TO 125×C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (m A)
VOL (V)
Max. 85°C
Max. 125°C
Typical 25°C
Min. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -case Temp) + 3
(-40°C to 125°C)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
VOL (V)
Typical: Statistical Mean @25×C
Maximum: Meas + 3 (-40×C to 125×C)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
Max. 85°C
Typ. 25°C
Min. -40°C
Max. 125°C
PIC16F631/677/685/687/689/690
DS40001262F-page 272 2005-2015 Microchip Technology Inc.
FIGURE 18-28 : VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
FIGURE 18-29 : VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)
VOH (V)
Typ. 25°C
Max. -40°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst -case Temp) + 3
(-40°C to 125°C)
(, )
3.0
3.5
4.0
4.5
5.0
5.5
-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0 IOH (mA)
VOH (V)
Max. -40°C
Typ. 25°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
2005-2015 Microchip Technology Inc. DS40001262F-page 273
PIC16F631/677/685/687/689/690
FIGURE 18-30: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
FIGURE 18-31: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(TTL Input, -40×C TO 125×C)
0.5
0.7
0.9
1.1
1.3
1.5
1.7
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
Typ. 25°C
Max. -40°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Wors t-c ase Tem p) + 3
(-40°C to 125°C)
(ST Input, -40×C TO 125×C)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VIH Max. 125°C
VIH Min. -40°C
VIL Min. 125°C
VIL Max. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Wors t-case Tem p) + 3
(-40°C to 125°C)
PIC16F631/677/685/687/689/690
DS40001262F-page 274 2005-2015 Microchip Technology Inc.
FIGURE 18-32: COMPARATOR RESPONSE TIME (RISING EDGE)
FIGURE 18-33 : CO MPARATOR RESP ONSE TIME (FALLING EDGE)
531 806
0
100
200
300
400
500
600
700
800
900
1000
2.0 2.5 4.0 5.5
VDD (V)
Response Time (nS)
Max. 85°C
Typ. 25°C
Min. -40°C
Max. 125°C
Note:
V- input = Transition from VCM + 100MV to VCM - 20MV
V+ input = VCM
VCM = VDD - 1.5V)/2
0
100
200
300
400
500
600
700
800
900
1000
2.0 2.5 4.0 5.5
VDD (V)
Response Time (nS)
Max. 85°C
Typ. 25°C
Min. -40°C
Max. 125°C
Note:
V- input = Transition from VCM - 100MV to VCM + 20MV
V+ input = VCM
VCM = VDD - 1.5V)/2
2005-2015 Microchip Technology Inc. DS40001262F-page 275
PIC16F631/677/685/687/689/690
FIGURE 18-34: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)
FIGURE 18-35: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE
LFINTOSC 31Khz
0
5,000
10,000
15,000
20,000
25,000
30,000
35,000
40,000
45,000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Frequency (Hz)
Max. -40°C
Typ. 25°C
Min. 85°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
0
2
4
6
8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (s)
25°C
85°C
125°C
-40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
PIC16F631/677/685/687/689/690
DS40001262F-page 276 2005-2015 Microchip Technology Inc.
FIGURE 18-36: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
FIGURE 18-37: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
0
2
4
6
8
10
12
14
16
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (s)
85°C
25°C
-40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
-40C to +85C
0
5
10
15
20
25
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (s)
-40°C
85°C
25°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
2005-2015 Microchip Technology Inc. DS40001262F-page 277
PIC16F631/677/685/687/689/690
FIGURE 18-38: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
FIGURE 18-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C)
-40C to +85C
0
1
2
3
4
5
6
7
8
9
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (s)
-40°C
25°C
85°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3
(-40°C to 125°C)
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Cha n ge f r o m C a libration (% )
PIC16F631/677/685/687/689/690
DS40001262F-page 278 2005-2015 Microchip Technology Inc.
FIGURE 18-40: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C)
FIGURE 18-41: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C)
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Change from Calibration (%)
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Change fr om Calibrati on (%)
2005-2015 Microchip Technology Inc. DS40001262F-page 279
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FIGURE 18-42: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C)
FIGURE 18-43: TYPICAL VP6 REFERENCE VOLTAGE vs. VDD (25°C)
-5
-4
-3
-2
-1
0
1
2
3
4
5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Change fr om Calibrati on (%)
VP6 Reference Voltage vs. VDD (25×C)
0.55
0.56
0.57
0.58
0.59
0.60
0.61
0.62
0.63
0.64
0.65
23455.5
VDD (V)
VP6 (V)
Typical
PIC16F631/677/685/687/689/690
DS40001262F-page 280 2005-2015 Microchip Technology Inc.
FIGURE 18-44: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (3V)
FIGURE 18-45: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (5V)
Typical VP6 Reference Voltage vs. Temperature (VDD=3V)
0.52
0.54
0.56
0.58
0.6
0.62
0.64
0.66
-40°C 25°C 85°C 125°C
Temperature (°C)
VP6 (V)
Min.
Max.
Typical
Typical VP6 Reference Voltage vs. Temperature (VDD=5V)
0.52
0.54
0.56
0.58
0.6
0.62
0.64
0.66
-40 °C 25 °C 85 °C 125 °C
Temperature (°C)
VP6 (V)
Max.
Typical
Min.
2005-2015 Microchip Technology Inc. DS40001262F-page 281
PIC16F631/677/685/687/689/690
FIGURE 18-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C)
FIGURE 18-47: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C)
Typical VP6 Reference Voltage Distribution (VDD=3V, 25×C)
0
5
10
15
20
25
30
35
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
Number of Parts
Parts=118
Typical VP6 Reference Voltage Distribution (VDD=3V, 85×C)
0
5
10
15
20
25
30
35
40
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
Number of Parts
Parts=118
PIC16F631/677/685/687/689/690
DS40001262F-page 282 2005-2015 Microchip Technology Inc.
FIGURE 18-48: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C)
FIGURE 18-49: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40°C)
Typical VP6 Reference Voltage Distribution (VDD=3V, 125×C)
0
5
10
15
20
25
30
35
40
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
Number of Parts
Parts=118
Typical VP6 Reference Voltage Distribution (VDD=3V, -40×C)
0
5
10
15
20
25
30
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
Number of Parts
Parts=118
2005-2015 Microchip Technology Inc. DS40001262F-page 283
PIC16F631/677/685/687/689/690
FIGURE 18-50: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C)
FIGURE 18-51: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C)
Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C)
0
5
10
15
20
25
30
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
Number of Parts
Parts=118
Typical VP6 Reference Voltage Distribution (VDD=5V, 85×C)
0
5
10
15
20
25
30
35
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
Number of Parts
Parts=118
PIC16F631/677/685/687/689/690
DS40001262F-page 284 2005-2015 Microchip Technology Inc.
FIGURE 18-52: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C)
FIGURE 18-53: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40°C)
Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C)
0
5
10
15
20
25
30
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
Number of Parts
Parts=118
Typical VP6 Reference Voltage Distribution (VDD=5V, -40×C)
0
5
10
15
20
25
30
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
0.670
0.680
0.690
0.700
Voltage (V)
Number of Parts
Parts=118
2005-2015 Microchip Technology Inc. DS40001262F-page 285
PIC16F631/677/685/687/689/690
19.0 PACKAGING INFORMATION
19.1 Package Marking Information
20-Lead PDIP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F685-I/P
0710017
20-Lead SOIC (7.50 mm)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F685-I
/SO 0710017
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
PIC16F687
-I/SS
0710017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Mi croch ip p art numb er canno t be mark ed on one l ine, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
3
e
3
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20-Lead QFN Example
XXXXXX
XXXXXX
YWWNNN
16F690
-I/ML
710017
PIC16F631/677/685/687/689/690
DS40001262F-page 286 2005-2015 Microchip Technology Inc.
19.2 Package Details
The following sections give the technical details of the packages.
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2005-2015 Microchip Technology Inc. DS40001262F-page 287
PIC16F631/677/685/687/689/690
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F631/677/685/687/689/690
DS40001262F-page 288 2005-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2015 Microchip Technology Inc. DS40001262F-page 289
PIC16F631/677/685/687/689/690
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F631/677/685/687/689/690
DS40001262F-page 290 2005-2015 Microchip Technology Inc.
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2005-2015 Microchip Technology Inc. DS40001262F-page 291
PIC16F631/677/685/687/689/690
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F631/677/685/687/689/690
DS40001262F-page 292 2005-2015 Microchip Technology Inc.
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2005-2015 Microchip Technology Inc. DS40001262F-page 293
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DS40001262F-page 294 2005-2015 Microchip Technology Inc.
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (March 2005)
This is a new data sheet.
Revision B (May 2006)
Added 631/677 part numbers; Added pin summary
tables after pin diagrams; Incorporated Golden
Chapters.
Revision C (July 2006)
Revised Section 4.2.1, ANSEL and ANSELH
Registers; Register 4-3, ANSEL Analog Select; Added
Register 4-4, ANSELH Analog Select High; Section
11.3.2, Revised CCP1<1:0> to DC1B<1:0>; Section
11.3.7, Number 4 - Revised CCP1 to DC1B; Figure 1 1-
5, Revised CCP1 to DC1B; Table 1 1-4, Revised P1M to
P1M<1:0>; Section 12.3.1, Revised Paragraph 3;
Revised Note 2; Revised Figure 12-6 Title.
Revision D (February 2007)
Removed Preliminary status; Changed PICmicro to
PIC; Replaced Dev. Tool Section; Replaced Package
Drawings.
Revision E (March 2008)
Add Char Data charts; Updated EUSART Golden
Chapter; Updated the Electrical Specification section;
Updated Package Drawings as needed.
Revision F (April 2015)
Added Section 17.8: High Temperature Operation in
the Electrical Specifications section.
APPENDIX B: MIGRATING FROM
OTHER PIC®
DEVICES
This discusses some of the issues in migrating from
other PIC devices to the PIC16F6XX Family of de vices.
B.1 PIC16F676 to PIC16F685
TABLE B-1: FEATURE COMPARISON
Feature PIC16F676 PIC16F685
Max Operating
Speed 20 MHz 20 MHz
Max Program
Memory (Words) 1024 4096
SRAM (bytes) 64 128
A/D Resolution 10-bit 10-bit
Data EEPROM
(Bytes) 128 256
Timers (8/16-bit) 1/1 2/1
Oscillator Modes 8 8
Brown-out Reset Y Y
Internal Pull -up s RA0/1/2/4/5 RA0/1/2/4/ 5,
MCLR
Interrupt-on-change RA0/1/2/3/4/5 RA0/1/2/3/4/5
Comparator 1 2
ECCP+ N Y
Ultra Low-Power
Wake-up NY
Extended WDT N Y
Software Control
Option of WDT/BOR NY
INTOSC
Frequencies 4 MHz 31 kHz-8 MHz
Clock Switch in g N Y
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than it s earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
2005-2015 Microchip Technology Inc. DS40001262F-page 295
PIC16F631/677/685/687/689/690
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at
www.microchip.com. Thi s web si te i s us ed as a m ean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Micro chi p con sul t an t
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminar s and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sal es Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical s upport is avail able throug h the web si te
at: http://www.microchip.com/support
DS40001262F-page 296 2005-2015 Microchip Technology Inc.
PIC16F631/677/685/687/689/690
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: PIC16F631(1), PIC16F677(1), PIC16F68 5(1),
PIC16F687(1), PIC16F689(1), PIC16F690(1);
VDD range 2.0V to 5.5V
Temperature Range: I= -40C to +85C (Industrial)
E= -40C to +125C (Extended)
Package: ML = QFN (Quad Flat, no lead)
P=PDIP
SO = SOIC
SS = SSOP
Pattern: QTP, SQTP, Code or Special Requirements
(blank oth erwis e )
Examples:
a) PI C 16F 68 5 - I /ML 30 1 = In du s t ria l tem p ., Q FN
package, QTP pattern #301.
b) PIC16F689 - I/SO = Industrial temp., SOIC
package.
c) PIC16F690T - E/SS = Extended temp., SSOP
package.
Note 1: T = in tape and reel SSOP, SOIC and
QFN packages only.
2005-2015 Microchip Technology Inc. DS40001262F-page 297
Information contained in this publication regarding device
applications a nd the lik e is provid ed only for your convenien ce
and may be supers ed ed by u pdates. I t is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer ,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoL yzer , PIC, PICSTART, PIC32 logo, RightTouch, S pyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsP ICDEM. net, ECA N, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPAS M, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, V ariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsid ia r y of Mic rochip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2005-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-235-0
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its f amily of products is one of the most secure famili es of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS40001262F-page 298 2005-2015 Microchip Technology Inc.
AMERICAS
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Technical Support:
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Worldwide Sales and Service
01/27/15
