APW7078 Single Step-up DC/DC Controller Features * * * * * * * General Description The APW7078 is a single PWM, step-up DC-DC controller with low operating voltage application integrating soft- 2.5 to 5.5V Input Voltage Range Adjustable Frequency: Maximum 1MHZ start and short circuit detection function. The oscillator switching frequency on chip can be operated by terminat- Incorporates Soft-Start Function ing OSC pin to connect capacitor and resistor for adjustable operating frequency. Soft-start is adjusted with the Built-in Short-Circuit Detection Circuit (SCP) Low Operating Current: Maximum to 1mA external capacitor, which sets the input current ramp. Besides, the external compensation FB pin will apply the Low Shutdown Current: Maximum to 1A flexibility in the dynamic loop status, which allows using small and low equivalent series resistance (ESR) ce- Package: SOP-8, MSOP-8, TDFN2x2-8 and TSSOP-8 * * ramic output capacitors. Under-Voltage Lockout Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration Applications * * * * LCD Display Power Source Camcorders VCRs, MP3, and Digital Still Camera INV 1 8 FB SCP 2 7 OSC VDD 3 6 GND 4 APW70785 OUT CTL Hand-held and Communication Instruments PDAs ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 1 www.anpec.com.tw APW7078 Ordering and Marking Information Package Code K : SOP-8 X : MSOP-8 O : TSSOP-8 QB : TDFN2x2-8 Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW7078 Assembly Material Handling Code Temperature Range Package Code APW7078 K : APW7078 XXXXX XXXXX - Date Code APW7078 X : W7078 XXX XX XXXXX - Date Code APW7078 O : APW7078 XXXXX XXXXX - Date Code APW7078 QB : 7078 X X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol Parameter Rating Unit VDD Supply Voltage -0.3 to 7 V VIO Input / Output Pins -0.3 to 7 V TA Operating Ambient Temperature Range -40 to 85 C TJ Junction Temperature Range -40 to 150 C TSTG Storage Temperature Range -65 to +150 C TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Recommended Operating Conditions Rating Symbol Parameter Unit Min. Typ. Max. VDD Supply Voltage 2.5 - 5.5 V VINV Error Amplifier Invert Input Voltage -0.2 - 1 V Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 2 www.anpec.com.tw APW7078 Recommended Operating Conditions (Cont.) Rating Symbol Parameter Unit Min. Typ. Max. -0.2 - VDD V VCTL Control Pin Input Voltage CSCP SCP Pin Capacitor - 0.1 - F RT Timing Resistance 1.0 3.3 10 k CT Timing Capacitor 100 - 270 pF FSW Oscillator Frequency 200 600 1000 kHz Electrical Characteristics (TA = 25C, VDD = 3.3V, unless otherwise specified) Symbol Parameter Test Conditions APW7078 Min. Unit Typ. Max. 2.5 - 5.5 V - 0.7 1 mA ENTIRE DEVICE VDD Supply Voltage IDD Supply Current ISD Shutdown Current CTL pin open or VDD - 0.1 1 A Maximum Duty Cycle RT =3.3K, CT =270pF 80 85 92 % 2.0 - 2.4 V - 150 - mV 0.7 0.8 0.9 V -0.7 -1.0 -1.5 A 0.7 0.8 0.9 V VSCP =0V -0.7 -1.0 -1.5 A 0.7 0.8 0.9 V VSCP =0V -0.7 -1.0 -1.5 A 500 600 700 kHz DMAX VDD=2.5V to 5.5V UNDER-VOLTAGE LOCKOUT PROTECTION VTH VDD Startup Threshold Voltage VR Hysteresis voltage - SOFT-START VSS Voltage at Soft-Start Completion ICS Soft-Start Charge Current VSS Voltage at Soft-Start Completion ICS Soft-Start Charge Current VSCP =0V - SHORT CIRCUIT PROTECTION (SCP) VSCP Threshold Voltage ISCP Charge Current SAWTOOTH WAVEFORM OSCILLATOR (OSC) FOSC Oscillator Frequency RT =3.3k, CT =270pF FDV Frequency Stability for Voltage VDD=2.5V to 5.5V - 2 5 % FDT Frequency Stability for Temperature TA=-40C to 85C - 5 - % Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 3 www.anpec.com.tw APW7078 Electrical Characteristics (Cont.) (TA = 25C, VDD = 3.3V, unless otherwise specified) APW7078 Symbol Parameter Test Conditions Unit Min. Typ. Max. 0.493 0.5 0.508 V ERROR AMPLIFIER VREF Reference Voltage VFB=INV VREF Stability VDD=2.5V to 5.5V - 5 20 mV VREF Variation with Temperature TA =-40C to 85C - 1 - % 1000 1300 1600 A/V - - 1 A - 1.6 1.8 - V - - - 0.01 V gm Transconductance IB Input Bias Current INV=0V VOH Output Voltage Range VOL Output Source Current INV=0V,FB=0.5V -150 -180 -210 A Output Sink Current INV=1V,FB=0.5V 140 170 200 A Output Source Current Duty<5%, OUT=0V -150 -200 - mA Output Sink Current Duty>5%, OUT=5V 150 200 - mA - - 0.2VDD 0.8VDD - - PWM CONTROLLER DRIVER ISOURCE ISINK CONTROL BLOCK VIL Active mode Control Voltage VIH Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 Switch-off mode 4 www.anpec.com.tw APW7078 Pin Description PIN NO. SYMBOL I/O FUNCTION 1 INV I Internal 0.5V reference voltage. Use a resistor divider to set the output voltage. 2 SCP - Soft-start and short-circuit detection, connects a capacitor from the pin to ground. 3 VDD - Power supply input pin for IC voltage. 4 CTL I Output control pin. Low = operating mode; High = shutdown mode. 5 OUT O External MOSFET driving pin. 6 GND - Ground pins of the IC. 7 OSC - Setting capacitor and resister to provide oscillation switching frequency adjustment. 8 FB O Error amplifier output pin. Setting circuit for IC compensation. Exposde Pad GND - Connect this pad to GND (pin6). Block Diagram VDD UVLO OSC 0.9 V Sawtooth wave oscillator 0.16 V 0.1 V VDD INV VDD Error Amp. - + + + + VREF 0.5V PWM Comp. Output drive circuit OUT DTC 0.8V FB Soft-start SCP GND Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 SCP CTL 5 www.anpec.com.tw APW7078 Application Schematic VIN 2.5V~4.2V L1 10H C1 22F C2 0.1F R1 390K C7 1F 1 INV 2 SCP FB 8 OSC 7 3 VDD GND 6 4 CTL OUT 5 R3 R2 91K Q2 2N7002 D1 VOUT SS12 5V 300mA Q1 APM2300A R5 1K C5 47F R4 3.3K C3 270pF C6 0.1F C4 0.1F 820K Cp *R2100k is recommended 33pF Figure 1: APW7078 Step-up Application for Adjustable Voltage VIN 2.5V~5.5V L1 10H R6 2R2 C1 22F C2 0.1F C8 1F R1 390K 1 INV 2 SCP FB 8 OSC 7 3 VDD GND 6 4 CTL OUT 5 R3 R2 9.1K Q2 2N7002 D1 VOUT SS12 9V 100mA Q1 APM2300A R5 2K C5 33F R4 4.3K C3 270pF C6 0.1F C4 0.1F 150K Cp 68pF Figure 2: APW7078 Step-up Application for Adjustable Voltage Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 6 www.anpec.com.tw APW7078 Application Schematic D2 26V C10 -9V 0.1uF C8 D3 C12 C11 1F 0.1F VIN 3V~3.6V 1F L1 D1 22H C1 22F C2 0.1F C7 1F R10 390K 1 INV 2 SCP FB 8 OSC 7 3 VDD GND 6 4 CTL OUT 5 R3 R2 75K C13 3.3F C9 1F R6 2R2 D4 C3 270pF 9V SS12 Q1 APM2300A R5 1K C5 100F R4 3.3K C6 0.1F C4 0.1F 1.2M Q2 2N7002 Figure 3. APW7078 Multiple-output for TFT LCD Panel Power Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 7 www.anpec.com.tw APW7078 Timing Diagram FB input voltage Short cirucit detect comparator Sawtooth wave output Soft-start setting voltage Output pin waveform SCP detect voltage SCP pin waveform tscp ts Soft start Output short circuit ON Power supply control SW Output short circuit detection OFF Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 Output short circuit 8 www.anpec.com.tw APW7078 Typical Operating Characteristics (TA = 25C, VDD = 3.3V, unless otherwise specified) SHDN and Release Supply Current vs. Supply Voltage 800 600 Maximum Duty(%) Supply Current(A) 700 500 400 300 200 TA=25 C RT=3.3k CT=270pF 100 0 1 2 3 4 5 CH1=VOUT 2V/DIV TIME=20ms/DIV CH2=VCTL 2V/DIV CH3=VSS 0.5V/DIV CH4=IL 1A/DIV Supply Voltage(V) Reference Voltage vs. Temperature Reference Voltage vs. Supply Voltage 520 0.54 516 0.53 Reference Voltage(V) Reference Voltage(mV) 512 508 504 TA=25 C 500 496 492 0.52 0.51 VDD=3.3V 0.50 0.49 0.48 488 0.47 484 0.46 480 1 2 3 4 -40 5 0 20 40 60 80 Temperature(C) Supply Voltage(V) Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 -20 9 www.anpec.com.tw APW7078 Typical Operating Characteristics (Cont.) (TA = 25C, VDD = 3.3V, unless otherwise specified) Oscillator Frequency vs. Timing Resistor Maximum Duty vs. Oscillator Frequency 100 CT=270pF 90 800 CT=100pF Maximum Duty(%) Oscillator Frequency(kHz) 1000 600 400 CT=270pF 200 80 CT=200pF 70 CT=100pF 60 50 40 0 0 2 4 6 8 10 10 100 1000 Timing Resistor(k) Oscillator Frequency(kHz) Power on and off under light load Power on and off under heavy load IOUT= 400mA, TIME=40ms/DIV CH1=VOUT 5VDIV CH2=VOUT=VDD 2V/DIV CH3=IL 0.5A/DIV CH4=VSS 1V/DIV IOUT= 5mA, TIME=40ms/DIV CH1=VOUT 5VDIV CH2=VOUT=VDD 2V/DIV CH3=IL 0.5A/DIV CH4=VSS 1V/DIV Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 10 www.anpec.com.tw APW7078 Typical Operating Characteristics (Cont.) (TA = 25C, VDD = 3.3V, unless otherwise specified) Efficiency Efficiency 100 100 90 95 90 VDD=3.3V Efficiency(%) Efficiency(%) 80 70 60 VDD=5V 50 40 10 80 VDD=3.6V 75 VOUT=5V L=10H CT=270pF RT=3.3K 65 60 20 1 85 70 VOUT=9V L=10H CT=270pF RT=4.3K 30 10 100 100 1000 Output Current(mA) Output Current(mA) Frequency Variation Ratio vs. Temperature Frequency Variation Ratio vs. Supply Voltage 10 5 TA=25 C RT=3.3k CT=270pF 8 6 Frequency Variation Ration f/f(%) Frequency Variation Ration f/f(%) VDD=3.3V VDD=2.5V 4 2 0 -2 -4 -6 -8 1 2 3 4 5 2 1 0 -1 -2 -3 -4 -20 0 20 40 60 80 Temperature(C) Supply Voltage(V) Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 3 -5 -40 -10 CT=270pF RT=3.3k 4 11 www.anpec.com.tw APW7078 Function Description Setting Oscillating Frequency voltage gain is fixed, and connecting a phase compensation resistor and capacitor to the FB pin (pin 8) provides The oscillator circuit generates a triangular sawtooth wave stable phase compensation for the system. with a peak of 0.9V and through 0.16V using the timing capacitor (CT) and the timing resistor (RT) that are con- PWM Comparator nected to OSC pin. This oscillator can provide oscillating frequency up to 1MHz. The voltage comparator has one inverting and three noninverting inputs. The comparator is a voltage/pulse width Vosc converter that controls the ON time of the output pulse depending on the input voltage. The output level is high VH (H) when the sawtooth wave is lower than the error amplifier output voltage, soft-start setting voltage, and idle pe- 0.9V riod setting voltage. Output Circuit V(t) The output circuit is a typical push-pull configuration to 0.16V VL t1 drive an external NMOS transistor directly. It can provide a 200mA source/sink to/from OUT (pin 5). t2 Time t Soft-Start and Short Circuit Detection i=c V t t1 = CT Soft-start operation is set by connecting capacitor CSCP to the SCP pin (pin 2). Soft-start prevents a current spike on start-up. On completion of the soft-start operation, the 0.9V - 0.16V = 370 CT 2mA V( t ) = VH e - SCP pin (pin 2) stays low and enters the short circuit t RTCT detection wait state.When an output short circuit occurs, the error amplifier output is fixed at 1.8V and capacitor t 2 = R TCT ln(VH / VL ) = 1.72 RT CT CSCP starts charging. T = t1 + t 2 = CT (370 + 1.72RT ) After charging to approximately 0.8 V, the output pin (pin 5) is set low and the SCP pin stays low. Once the protec- Setting Output Voltage tion circuit operates, the circuit can be restored by resetting the power supply. Short circuit detection time can be The output voltage is set using the INV pin and a re- calculate as below: sistor divider connected to the output is shown in the Typical Operating Circuit. The internal reference volt- t SCP = 0.8 x CSCP(F) age is 0.5V with 2% variation, so the ratio of the feedback resistors sets the output voltage according to the follow- Under-Voltage Lock Out (UVLO) ing equation: Transients during powering on or instantaneous glitches in the supply voltage can cause system damage or failure. The circuit prevents malfunction at low input volt- R3 VOUT = 1 + x 0. 5 V R2 To avoid the thermal noise from feedback resistor, the age detects a low input voltage by comparing the supply voltage with the internal reference voltage. On detection, resistance R2 is smaller than 100k and 1% variation is recommended. the circuit fixes the output pin to low. The system recovers when the supply voltage rises back above the threshold voltage of the malfunction prevention circuit. Error Amplifier The error amplifier detects the output voltage of the switching regulator and outputs the PWM control signal. The Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 12 www.anpec.com.tw APW7078 Function Description (Cont.) Top Layer Layout Consideration Switching Noise Decoupling Capacitor A 0.1F ceramic capacitor should be placed close to the VOUT pin and the GND pin of the chip to filter the switching spikes in the output voltage monitored by the VOUT pin. Feedback Network In APW7078 application, the feedback networks should be connected directly to a dedicated analog ground plane and this ground plane must connect to the GND pin. If no analog ground plane is available, and then this ground must tie directly to the GND pin. The feedback network, resistors R2 and R3, should be kept close to the FB pin, and away from the inductor. Input Capacitor The input capacitor CIN in VIN must be placed close to the IC. This will reduce copper trace resistance which effects Bottom Layer input voltage ripple of the IC. For additional input voltage filtering, a 1F capacitor can be placed in parallel with CIN, close to the VDD pin, to shunt any high frequency noise to the ground. Demo Board Circuit Layout Inductor To minimize copper trace connections that can inject noise into the system, the inductor, switch, and schottky diode should be placed as close as possible to minimize the noise coupling into other circuits. Output Capacitor The output capacitor, COUT, should be placed close to the diode and output terminals to obtain better smoothing effect on the output ripple. Any copper trace connections for the COUT capacitor can increase the series resistance, which directly effects output voltage ripple and efficiency. Ground Plane One point grounding should be used for the output power return ground, the input power return to the ground and the device switches the ground to reduce noise. The input ground and output ground traces must be thick enough for current to flow through and for reducing the ground bounce. Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 13 www.anpec.com.tw APW7078 Package Information SOP-8 D E E1 SEE VIEW A h X 45 c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0 8 0 8 Note: 1. Follow JEDEC MS-012 AA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 14 www.anpec.com.tw APW7078 Package Information MSOP-8 D b 0.25 A A1 A2 c L GAUGE PLANE SEATING PLANE 0 e E E1 SEE VIEW A VIEW A S Y M B O L MSOP-8 MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.10 0.043 A1 0.00 0.15 0.000 0.006 A2 0.75 0.95 0.030 0.037 0.015 b 0.22 0.38 0.009 c 0.08 0.23 0.003 0.009 D 2.90 3.10 0.114 0.122 E 4.70 5.10 0.185 0.201 E1 2.90 3.10 0.114 e 0.65 BSC 0.122 0.026 BSC L 0.40 0.80 0.016 0.031 0 0 8 0 8 Note: 1. Follow JEDEC MO-187 AA. 2. Dimension "D"does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1"does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 5 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 15 www.anpec.com.tw APW7078 Package Information TSSOP-8 D E E1 SEE VIEW A C A 0.25 b A2 e GAUGE PLANE A1 SEATING PLANE S Y M B O L VIEW A L TSSOP-8 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 2.90 3.10 0.114 0.122 E 6.20 6.60 0.244 0.260 E1 4.30 4.50 0.169 0.177 0.65 BSC e L 0.45 0 0 0.026 BSC 0.75 8 0.018 0.030 0 8 Note : 1. Follow JEDEC MO-153 AA 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 16 www.anpec.com.tw APW7078 Package Information TDFN2x2-8 D b E A A1 D2 E2 A3 L K Pin 1 Corner e TDFN2x2-8 S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 0.05 0.000 0.002 A1 MILLIMETERS 0.00 A3 INCHES 0.20 REF 0.008 REF 0.30 0.007 0.012 1.90 2.10 0.075 0.083 D2 1.00 1.60 0.039 0.063 E 1.90 2.10 0.075 0.083 1.00 0.024 0.039 0.45 0.012 b D E2 0.18 0.60 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.018 0.008 Note : 1. Followed from JEDEC MO-229 WCCD-3. Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 17 www.anpec.com.tw APW7078 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 B A0 A OD1 B T SECTION A-A SECTION B-B H A d T1 Application S O P -8 Application M S O P -8 A H 330.0 2.00 50 MIN. P0 P1 4.0 0.10 8.0 0.10 A H 330.0 2.00 50 MIN. P0 P1 T1 TSSOP-8 A 50 MIN. P0 P1 D0 D1 T 2.0 0.05 1.5 MIN. 0.6+0.00 -0.4 0 T1 C d D 12.4+2.00 13.0+0.50 -0.00 -0.20 P2 T1 P2 TDFN2x2-8 1.5 MIN. D0 D1 T 1.5 MIN. 0.6+0.00 -0.40 C d D D0 1.5+0.10 -0.00 1.5 MIN. W E1 A0 B0 W E1 T 1.5 MIN. 0.6+0.00 -0.40 K0 A0 B0 F 5.5 0.05 K0 5.300.20 3.300.20 1.400.20 W E1 20.2 MIN. 12.0 0.30 1.750.10 D1 F 5.5 0.05 6.400.20 5.200.20 2.100.20 20.2 MIN. 12.0 0.30 1.750.10 1.5+0.10 -0.00 12.4+2.00 13.0+0.50 -0.00 -0.20 4.000.10 8.000.10 2.000.05 Application D 20.2 MIN. 12.0 0.30 1.750.10 1.5+0.10 -0.00 H 330.0 2.00 d 1.5 MIN. P2 4.000.10 8.000.10 2.000.05 Application C 12.4+2.00 13.0+0.50 -0.00 -0.20 A0 B0 F 5.5 0.10 K0 6.900.20 3.400.20 1.600.20 A H T1 C d D W E1 F 178.02.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.00.20 1.750.10 3.500.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.00.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.4 3.35 MIN 3.35 MIN 1.300.20 4.00.10 4.00.10 (mm) Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 18 www.anpec.com.tw APW7078 Devices Per Unit Package Type SOP-8 MSOP- 8 Unit Tape & Reel Tape & Reel Quantity 2500 3000 TDFN2x2-8 Tape & Reel 3000 TSSOP-8 Tape & Reel 2500 Taping Direction Information SOP-8 USER DIRECTION OF FEED MSOP-8 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 19 www.anpec.com.tw APW7078 Taping Direction Information TSSOP-8 USER DIRECTION OF FEED TDFN2x2-8 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 20 www.anpec.com.tw APW7078 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3 C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 21 www.anpec.com.tw APW7078 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Volume mm <350 235 C 220 C 3 Volume mm 350 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ Tj=125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV VMM200V 10ms, 1tr100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.7 - Jul., 2011 22 www.anpec.com.tw