EFR32MG13 Mighty Gecko Multi-Protocol

Wireless SoC Family Data Sheet

The Mighty Gecko multi-protocol family of SoCs is part of the

Wireless Gecko portfolio. Mighty Gecko SoCs are ideal for ena-

bling energy-friendly multi-protocol, multi-band networking for IoT

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup

times, a scalable power amplifier, and no-compromise MCU features.

Mighty Gecko applications include:

• 12-channel Peripheral Reflex System

enabling autonomous interaction of MCU

• Autonomous Hardware Crypto Accelerator

and True Random Number Generator

• Integrated PA with up to 19 dBm (2.4

GHz) or 20 dBm (Sub-GHz) tx power

• Integrated balun for 2.4 GHz

• Robust peripheral set and up to 31 GPIO

• IoT Multi-Protocol Devices

32-bit bus

Peripheral Reflex System

Energy Management

ARM CortexTM M4 processor

ETM Debug Interface RAM Memory LDMA

The EFR32MG13 highlighted features are listed below.

• 2.4 GHz and Sub-GHz radio operation

• Transmit power:

• 2.4 GHz radio: Up to 19 dBm

• Sub-GHz radio: Up to 20 dBm

• 10.2 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz

• 9.5 mA RX current at 1 Mbps, GFSK, 2.4 GHz

• 8.4 mA RX current at 38.4 kbps, GFSK, 169 MHz

• 8.5 mA TX current at 0 dBm output power at 2.4 GHz

• 35.3 mA TX current at 14 dBm output power at 868 MHz

• -103.3 dBm sensitivity at 125 kbit/s GFSK, 2.4 GHz

• -94.8 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz

• -91.5 dBm sensitivity at 2 Mbit/s GFSK, 2.4 GHz

• -102.7 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz

• -126.2 dBm sensitivity at 600 bps, GFSK, 915 MHz

• -120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz

• -107.4 dBm sensitivity at 4.8 kbps, OOK, 433 MHz

• -112.2 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz

• 2/4 (G)FSK with fully configurable shaping

• Proprietary

• Multiproto-

Tape and Reel (Optional)

Pin Count

Package – M (QFN), L (BGA)

Performance Grade – P (Performance), B (Basic), V (Value)

Family – M (Mighty), B (Blue), F (Flex)

Device Configuration

3.1 Introduction

The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for

any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a

short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG13 Reference

ARM Cortex-M4 Core

64 KB RAM A

(shared w/GPIO)

Brown Out /

Power-On

Reset

Management

Serial Wire

and ETM

Debug /

3.2.1 Antenna Interface

The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The

2G4RF_ION pin should be grounded externally.

The sub-GHz antenna interface consists of a differential transmit interface (pins SUBGRF_OP and SUBGRF_ON) and a differential re-

ceive interface (pinsSUBGRF_IP and SUBGRF_IN).

The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching

Networks section.

optimize system energy consumption.

3.2.3 Receiver Architecture

The EFR32MG13 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion

mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital

converter (IFADC).

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-

ing flexibility with respect to known interferers at the image frequency.

The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-

tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz

radio can be calibrated on-demand by the user for the desired frequency band.

frame and the dynamic RSSI measurement can be monitored throughout reception.

The EFR32MG13 features integrated support for antenna diversity to mitigate the problem of frequency-selective fading due to multi-

path propagation and improve link budget. Support for antenna diversity is available for specific PHY configurations in 2.4 GHz and

sub-GHz bands. Internal configurable hardware controls an external switch for automatic switching between antennae during RF re-

ceive detection operations.

Note: Due to the shorter preamble of 802.15.4 and BLE packets, RX diversity is not supported.

3.2.4 Transmitter Architecture

The EFR32MG13 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls

phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping

3.9.3 Analog to Digital Converter (ADC)

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of

sources, including pins configurable as either single-ended or differential.

The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches

as well as digital threshold comparators to reduce software overhead.

3.9.5 Digital to Analog Current Converter (IDAC)

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any

space, and cost as compared with standalone opamps because they are integrated on-chip.

3.10 Reset Management Unit (RMU)

The RMU is responsible for handling reset of the EFR32MG13. A wide range of reset sources are available, including several power

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

3.11 Core and Memory

3.11.1 Processor Core

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz

• Memory Protection Unit (MPU) supporting up to 8 memory segments

• Up to 512 kB flash program memory

3.11.2 Memory System Controller (MSC)

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a

read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-

3.12 Memory Map

The EFR32MG13 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

The features of the EFR32MG13 are a subset of the feature set described in the device reference manual. The table below describes

device specific implementation of the features. Remaining modules support full configuration.

Module Configuration Pin Connections

USART0 IrDA SmartCard US0_TX, US0_RX, US0_CLK, US0_CS

USART1 IrDA I2S SmartCard US1_TX, US1_RX, US1_CLK, US1_CS

USART2 IrDA SmartCard US2_TX, US2_RX, US2_CLK, US2_CS

TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 - TIM1_CC[3:0]

WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]

4.1 Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

4.1.1 Absolute Maximum Ratings

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-

bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Parameter Symbol Test Condition Min Typ Max Unit

Storage temperature range TSTG -50 — 150 °C

Voltage on any supply pin VDDMAX -0.3 — 3.8 V

Voltage ramp rate on any

supply pin

DC voltage on any GPIO pin VDIGPIN 5V tolerant GPIO pins1 2 3-0.3 — Min of 5.25

Absolute voltage on RF pins

2G4RF_IOP and

Absolute voltage on Sub-

GHz RF pins

Total current into VDD power

Junction temperature TJ-G grade devices -40 — 105 °C

Parameter Symbol Test Condition Min Typ Max Unit

1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.

3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.

4.1.2 Operating Conditions

When assigning supply sources, the following requirements must be observed:

4.1.2.1 General Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Operating ambient tempera-

ture range6

AVDD supply voltage2VAVDD 1.8 3.3 3.8 V

VREGVDD operating supply

PAVDD operating supply

IOVDD operating supply volt-

DECOUPLE output capaci-

Difference between AVDD

and VREGVDD, ABS(AVDD-

HFCORECLK frequency fCORE VSCALE2, MODE = WS1 — — 40 MHz

2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.

3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-

4. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV / usec for approximately 20 usec. During this transi-

5. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.

6. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific appli-

4.1.3 Thermal Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Thermal resistance THETAJA QFN48 Package, 2-Layer PCB,

4.1.5.3 Current Consumption 1.8 V without DC-DC Converter

Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.

mode with all peripherals dis-

— 97 — µA/MHz

— 98 — µA/MHz

— 119 — µA/MHz

— 100 — µA/MHz

— 243 — µA/MHz

Current consumption in EM0

mode with all peripherals dis-

abled and voltage scaling

— 86 — µA/MHz

— 206 — µA/MHz

Current consumption in EM1

mode with all peripherals dis-

abled and voltage scaling

Current consumption in EM2

mode, with voltage scaling

— 1.8 — µA

— 2.0 — µA

Current consumption in

EM4H mode, with voltage

scaling enabled

— 0.83 — µA

— 0.37 — µA

Current consumption in

EM4S mode

Parameter Symbol Test Condition Min Typ Max Unit

1. CMU_HFXOCTRL_LOWPOWER=0.

4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC

°C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25

Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in re-

38.4 MHz, peripheral clocks

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in re-

ceive mode, listening for

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in

transmit mode (MCU in EM1

— 9.5 — mA

— 16.5 — mA

— 26.0 — mA

— 34.0 — mA

— 86.0 — mA

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in

transmit mode (MCU in EM1

— — 134.3 mA

— — 109.8 mA

— — 41.3 mA

— — 130.8 mA

— — 122.8 mA

4.1.6 Wake Up Times

Parameter Symbol Test Condition Min Typ Max Unit

Wakeup time from EM1 tEM1_WU — 3 — AHB

Wake up from EM2 tEM2_WU Code execution from flash — 10.9 — µs

Power mode scaling time tSCALE VSCALE0 to VSCALE2, HFCLK =

1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.

2. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,

4.1.7 Brown Out Detector (BOD)

Parameter Symbol Test Condition Min Typ Max Unit

DVDD BOD threshold VDVDDBOD DVDD rising — — 1.62 V

AVDD BOD hysteresis VAVDDBOD_HYST — 20 — mV

AVDD BOD response time tAVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs

EM4 BOD threshold VEM4DBOD AVDD rising — — 1.7 V

EM4 BOD hysteresis VEM4BOD_HYST — 25 — mV

EM4 BOD response time tEM4BOD_DELAY Supply drops at 0.1V/µs rate — 300 — µs

4.1.8 Frequency Synthesizer

Parameter Symbol Test Condition Min Typ Max Unit

RF synthesizer frequency

LO tuning frequency resolu-

Frequency deviation resolu-

tion with 38.4 MHz crystal

Maximum frequency devia-

tion with 38.4 MHz crystal

4.1.9 2.4 GHz RF Transceiver Characteristics

RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.

Parameter Symbol Test Condition Min Typ Max Unit

Maximum TX power1POUTMAX 19 dBm-rated part numbers.

Minimum active TX Power POUTMIN CW -30 — dBm

Output power step size POUTSTEP -5 dBm< Output power < 0 dBm — 1 — dB

— 3.8 — dB

— 2.2 — dB

Output power variation vs

temperature at POUTMAX

— 1.5 — dB

— 2.2 — dB

frequency at POUTMAX

RF tuning frequency range FRANGE 2400 — 2483.5 MHz

1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-