LTC2945
1
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For more information www.linear.com/LTC2945
TYPICAL APPLICATION
FEATURES DESCRIPTION
Wide Range
I2C Power Monitor
Wide Range Power Monitor with Onboard ADC and I2C
APPLICATIONS
n Rail-to-Rail Input Range: 0V to 80V
n Wide Input Supply Range: 2.7V to 80V
n Shunt Regulator for Supplies >80V
n Δ∑ ADC with less than ±0.75% Total Unadjusted Error
n 12-Bit Resolution for Current and Voltages
n Internal Multiplier Calculates 24-Bit Power Value
n Stores Minimum and Maximum Values
n Alerts When Limits Exceeded
n Additional ADC Input Monitors an External Voltage
n Continuous Scan and Snapshot Modes
n Shutdown Mode with IQ < 80µA
n Split SDA for Opto-Isolation
n Available in 12-Lead 3mm × 3mm QFN and MSOP
Packages
n Telecom Infrastructure
n Industrial
n Automotive
n Consumer
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
I2C
INTERFACE
NINE I2C
ADDRESSES
SENSE+SENSE–
ALERT
SCL
SDAI
SDAO
ADIN
VDD
INTVCC
ADR1
ADR0
GND
LTC2945
MEASURED
VOLTAGE
TO
LOAD
0.1µF
0.02Ω
VIN
4V TO 80V
2945 TA01
ADC Differential
Nonlinearity (ADIN)
ADC Integral Nonlinearity
(ADIN)
The LT C
®
2945 is a rail-to-rail system monitor that mea-
sures current, voltage, and power. It features an operating
range of 2.7V to 80V and includes a shunt regulator for
supplies above 80V to allow flexibility in the selection of
input supply. The current measurement range of 0V to
80V is independent of the input supply. An onboard 0.75%
accurate 12-bit ADC measures load current, input voltage
and an auxiliary external voltage. A 24-bit power value is
generated by digitally multiplying the measured 12-bit load
current and input voltage data. Minimum and maximum
values are stored and an overrange alert with program-
mable thresholds minimizes the need for software polling.
Data is reported via a standard I2C interface. Shutdown
mode reduces power consumption to 20µA.
The LTC2945 I2C interface includes separate data input
and output pins for use with standard or opto-isolated I2C
connections. The LTC2945-1 has an inverted data output
for use with inverting opto-isolator configurations.
CODE
0
–0.3
ADC DNL (LSB)
0.3
0.0
0.1
0.2
–0.2
–0.1
3072 40961024 2048
2945 TA01a
CODE
0
–0.3
ADC INL (LSB)
0.3
0.0
0.1
0.2
–0.2
–0.1
3072 40961024 2048
2945 TA01b
LTC2945
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For more information www.linear.com/LTC2945
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VDD Voltage .............................................. –0.3V to 100V
SENSE+ Voltage ...........................................–1V to 100V
SENSE– Voltage .....–1V or SENSE+ – 1V to SENSE+ + 1V
INTVCC Voltage (Note 3) ........................... –0.3V to 5.9V
ADR1, ADR0, ADIN, ALERT, SDAO, SDAO
Voltage ......................................................... –0.3V to 7V
INTVCC Clamp Current ...........................................35mA
(Notes 1, 2)
LTC2945
12 11 10
456
TOP VIEW
13
UD PACKAGE
12-LEAD (3mm
×
3mm) PLASTIC QFN
7
8
9
3
2
1INTVCC
ADR1
ADR0
ALERT
SDAO
SDAI
VDD
SENSE+
SENSE–
ADIN
GND
SCL
TJMAX = 125°C, qJA = 58.7°C/W
EXPOSED PAD (Pin 13) PCB GND CONNECTION OPTIONAL
1
2
3
4
5
6
VDD
INTVCC
ADR1
ADR0
ADIN
GND
12
11
10
9
8
7
SENSE+
SENSE–
ALERT
SDAO
SDAI
SCL
TOP VIEW
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 125°C, qJA = 135°C/W
LTC2945-1
12 11 10
456
TOP VIEW
13
UD PACKAGE
12-LEAD (3mm
×
3mm) PLASTIC QFN
7
8
9
3
2
1INTVCC
ADR1
ADR0
ALERT
SDAO
SDAI
VDD
SENSE+
SENSE–
ADIN
GND
SCL
TJMAX = 125°C, qJA = 58.7°C/W
EXPOSED PAD (Pin 13) PCB GND CONNECTION OPTIONAL
1
2
3
4
5
6
VDD
INTVCC
ADR1
ADR0
ADIN
GND
12
11
10
9
8
7
SENSE+
SENSE–
ALERT
SDAO
SDAI
SCL
TOP VIEW
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 125°C, qJA = 135°C/W
SCL, SDAI Voltages (Note 4) ..................... –0.3V to 5.9V
SCL, SDAI Clamp Current ........................................5mA
Operating Temperature Range
LTC2945C ................................................ 0°C to 70°C
LTC2945I .............................................–40°C to 85°C
LTC2945H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10sec)
MS Package Only ..............................................300°C
LTC2945
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For more information www.linear.com/LTC2945
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2945CUD#PBF LTC2945CUD#TRPBF LFWK 12-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C
LTC2945IUD#PBF LTC2945IUD#TRPBF LFWK 12-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C
LTC2945HUD#PBF LTC2945HUD#TRPBF LFWK 12-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C
LTC2945CUD-1#PBF LTC2945CUD-1#TRPBF LFYX 12-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C
LTC2945IUD-1#PBF LTC2945IUD-1#TRPBF LFYX 12-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C
LTC2945HUD-1#PBF LTC2945HUD-1#TRPBF LFYX 12-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C
LTC2945CMS#PBF LTC2945CMS#TRPBF 2945 12-Lead Plastic MSOP 0°C to 70°C
LTC2945IMS#PBF LTC2945IMS#TRPBF 2945 12-Lead Plastic MSOP –40°C to 85°C
LTC2945HMS#PBF LTC2945HMS#TRPBF 2945 12-Lead Plastic MSOP –40°C to 125°C
LTC2945CMS-1#PBF LTC2945CMS-1#TRPBF 29451 12-Lead Plastic MSOP 0°C to 70°C
LTC2945IMS-1#PBF LTC2945IMS-1#TRPBF 29451 12-Lead Plastic MSOP –40°C to 85°C
LTC2945HMS-1#PBF LTC2945HMS-1#TRPBF 29451 12-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SUPPLIES
VDD VDD Supply Voltage Range l4 80 V
VINTVCC INTVCC Supply Voltage Range l2.7 5.9 V
IDD VDD Supply Current VDD = 48V, INTVCC Open
Shutdown
l
l
0.8
40
1.2
70
mA
µA
ICC INTVCC Supply Current INTVCC = VDD = 5V
Shutdown, INTVCC = VDD = 5V
l
l
0.6
20
0.9
80
mA
µA
ICCSRC INTVCC Linear Regulator Output Current VDD = 7V l–10 mA
VCC INTVCC Linear Regulator Voltage 7V < VDD < 80V, ILOAD = 1mA (C-, I-Grade)
7V < VDD < 80V, ILOAD = 1mA (H-Grade)
l
l
4.5
4.5
5
5
5.5
5.7
V
V
ΔVCC INTVCC Linear Regulator Load Regulation 7V < VDD < 80V, ILOAD = 1mA to 10mA l100 200 mV
VCCZ INTVCC Shunt Regulator Voltage VDD = 48V, ICC = 1mA l5.9 6.3 6.7 V
ΔVCCZ INTVCC Shunt Regulator Load Regulation VDD = 48V, ICC = 1mA to 35mA l250 mV
VCC(UVL) INTVCC Supply Undervoltage Lockout INTVCC Rising, VDD = INTVCC l2.2 2.6 2.69 V
VDD(UVL) VDD Supply Undervoltage Lockout VDD Rising, INTVCC Open (C-, I-Grade)
VDD Rising, INTVCC Open (H-Grade)
l
l
2.9
2.6
3.2
3.2
3.5
3.5
V
V
VDDI2C(RST) VDD I2C Logic Reset VDD Falling, INTVCC Open (C-, I-Grade)
VDD Falling, INTVCC Open (H-Grade)
l
l
2
1.7
2.5
2.5
V
V
VCCI2C(RST) INTVCC I2C Logic Reset INTVCC Falling, VDD = INTVCC l1.5 1.8 V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 80V unless otherwise noted. (Note 2)
LTC2945
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SENSE INPUTS
VCM SENSE+, SENSE– Common Mode Voltage l0 80 V
ISENSE+(HI) 48V SENSE+ Input Current SENSE+, SENSE–, VDD = 48V
Shutdown
l
l
100 150
2
µA
µA
ISENSE–(HI) 48V SENSE– Input Current SENSE+, SENSE–, VDD = 48V
Shutdown
l
l
20
1
µA
µA
ISENSE+(LO) 0V SENSE+ Source Current SENSE+, SENSE– = 0V VDD = 48V
Shutdown
l
l
–10
–2
µA
µA
ISENSE–(LO) 0V SENSE– Source Current SENSE+, SENSE– = 0V, VDD = 48V
Shutdown
l
l
–5
±1
µA
µA
ADC
RES Resolution (No missing codes) (Note 5) l12 Bits
VFS Full-Scale Voltage ΔSENSE (Note 7)
VIN
ADIN
l
l
l
101.7
101.7
2.033
102.4
102.4
2.048
103.1
103.1
2.063
mV
V
V
LSB LSB Step Size ΔSENSE
VIN
ADIN
25
25
0.5
µV
mV
mV
TUE Total Unadjusted Error (Note 6) ΔSENSE
VIN
ADIN
l
l
l
±0.75
±0.75
±0.75
%
%
%
VOS Offset Error ΔSENSE
VIN
ADIN
l
l
l
±3.1
±1.5
±1.1
LSB
LSB
LSB
INL Integral Nonlinearity ΔSENSE
VIN
ADIN
l
l
l
±3
±2
±2
LSB
LSB
LSB
sTTransition Noise (Note 5) ΔSENSE
VIN
ADIN
1.2
0.3
10
µVRMS
mVRMS
µVRMS
fCONV Conversion Rate (Continuous Mode) l6 7.5 9 Hz
tCONV Conversion Time (Snapshot Mode) ΔSENSE
VIN, ADIN
l
l
60
30
66
33
72
36
ms
ms
RADIN ADIN Pin Input Resistance VDD = 48V, ADIN = 3V l3 10 MΩ
IADIN ADIN Pin Input Current VDD = 48V, ADIN = 3V l±1 µA
I2C INTERFACE (VDD = 48V)
VADR(H) ADR0, ADR1 Input High Threshold l2.1 2.4 2.7 V
VADR(L) ADR0, ADR1 Input Low Threshold l0.3 0.6 0.9 V
IADR(IN) ADR0, ADR1 Input Current ADR0, ADR1 = 0V, 3V l±13 µA
IADR(IN,Z) Allowable Leakage When Open l±7 µA
VOD(OL) SDAO, SDAO, ALERT Output Low Voltage ISDAO, ISDAO, IALERT = 8mA l0.15 0.4 V
ISDA,SCL(IN) SDAI, SDAO, SDAO, SCL Input Current SDAI, SDAO, SDAO, SCL = 5V l0 ±1 µA
VSDA,SCL(TH) SDAI, SCL Input Threshold l1.5 1.9 2.2 V
VSDA,SCL(CL) SDAI, SCL Clamp Voltage ISDAI, ISCL = 3mA l5.9 6.4 6.9 V
IALERT(IN) ALERT Input Current ALERT = 5V l0 ±1 µA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 80V unless otherwise noted. (Note 2)
LTC2945
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive. All voltages are referenced to
ground, unless otherwise noted.
Note 3: An internal shunt regulator limits the INTVCC pin to a minimum of
5.9V. Driving this pin to voltages beyond 5.9V may damage the part. This
pin can be safely tied to higher voltages through a resistor that limits the
current below 35mA.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I2C INTERFACE TIMING
fSCL(MAX) Maximum SCL Clock Frequency 400 kHz
tLOW Minimum SCL Low Period 0.65 1.3 µs
tHIGH Minimum SCL High Period 50 600 ns
tBUF(MIN) Minimum Bus Free Time Between Stop/Start
Condition
0.12 1.3 µs
tHD,STA(MIN) Minimum Hold Time After (Repeated) Start
Condition
140 600 ns
tSU,STA(MIN) Minimum Repeated Start Condition Set-Up
Time
30 600 ns
tSU,STO(MIN) Minimum Stop Condition Set-Up Time 30 600 ns
tHD,DATI(MIN) Minimum Data Hold Time Input –100 0 ns
tHD,DATO(MIN) Minimum Data Hold Time Output 300 600 900 ns
tSU,DAT(MIN) Minimum Data Set-Up Time 30 100 ns
tSP(MAX) Maximum Suppressed Spike Pulse Width 50 110 250 ns
tRST Stuck Bus Reset Time SCL or SDAI Held Low 25 33 ms
CXSCL, SDAI Input Capacitance (Note 5) 5 10 pF
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 80V unless otherwise noted. (Note 2)
Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of 5.9V.
Driving these pins to voltages beyond the clamp may damage the part. The
pins can be safely tied to higher voltages through resistors that limit the
current below 5mA.
Note 5: Guaranteed by design and not subject to test.
Note 6:
T
UE =ACTUAL CODE
−
IDEAL CODE
( )
4096
×100
%
where IDEAL CODE is derived from a straight line passing through Code 0
at 0V and Theoretical Code of 4096 at VFS.
Note 7: ΔSENSE is defined as VSENSE+ – VSENSE–
LTC2945
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TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Supply Current in
Shutdown INTVCC Load Regulation INTVCC Line Regulation
ADC Integral Nonlinearity (ADIN)
ADC Differential Nonlinearity
(ADIN)
ADC Total Unadjusted Error
(ADIN)
VDD Supply Current VDD Supply Current in Shutdown INTVCC Supply Current
VDD = 48V, TA = 25°C, unless noted.
VDD SUPPLY VOLTAGE (V)
0
600
SUPPLY CURRENT (µA)
800
750
700
650
60
80
20 40
2945 G01
VDD SUPPLY VOLTAGE (V)
0
10
SUPPLY CURRENT (µA)
70
60
40
50
20
30
60
80
20 40
2945 G02
VCC SUPPLY VOLTAGE (V)
2
500
SUPPLY CURRENT (µA)
600
575
525
550
5
6
3 4
2945 G03
VCC SUPPLY VOLTAGE (V)
2
10.0
SUPPLY CURRENT (µA)
22.5
17.5
20.0
12.5
15.0
5 63 4
2945 G04
CODE
0
–0.3
ADC INL (LSB)
0.3
0.0
0.1
0.2
–0.2
–0.1
3072
4096
1024 2048
2945 G07
CODE
0
–0.3
ADC DNL (LSB)
0.3
0.0
0.1
0.2
–0.2
–0.1
3072
4096
1024 2048
2945 G08
CODE
0
–0.02
ADC TOTAL UNADJUSTED ERROR (%)
0.02
0.01
–0.01
0
3072
4096
1024 2048
2945 G09
LOAD CURRENT (mA)
0
4.8
INTVCC VOLTAGE (V)
5.2
5.1
4.9
5.0
86 102 4
2945 G05
VDD SUPPLY VOLYAGE (V)
0
3.0
INTVCC VOLTAGE (V)
5.5
4.5
5.0
3.5
4.0
6040 8020
2945 G06
LTC2945
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TYPICAL PERFORMANCE CHARACTERISTICS
SDAO, SDAO, ALERT Loaded
Output Low Voltage
SENSE+ Input Current
SCL, SDAI Loaded Clamp Voltage
SENSE– Input Current
INTVCC Shunt Regulator Load
Regulation
ADRO, ADR1 Voltage with Current
Sink or Source
ADC Integral Nonlinearity
(ΔSENSE)
ADC Differential Nonlinearity
(ΔSENSE)
ADC Total Unadjusted Error
(ΔSENSE)
VDD = 48V, TA = 25°C, unless noted.
CODE
0
–0.4
ADC INL (LSB)
0.4
0.2
–0.2
0.0
3072
4096
1024 2048
2945 G10
CODE
0
–0.3
ADC DNL (LSB)
0.3
0.0
0.1
0.2
–0.2
–0.1
3072
4096
1024 2048
2945 G11
CODE
0
–0.50
ADC TOTAL UNADJUSTED ERROR (%)
0.50
0.25
–0.25
0.00
3072
4096
1024 2048
2945 G12
ISDA,ALERT (mA)
0
0.0
V
SDA
,
ALERT(OL)
(V)
0.4
0.3
0.1
0.2
8
10
246
2945 G13
ILOAD (mA)
0.01
6.0
V
SDA
,
SCL(CL)
(V)
6.6
6.5
6.1
6.2
6.3
6.4
10.00
0.10 1.00
2945 G14
VSENSE+ (V)
0
–10
I
SENSE
+ (µA)
150
110
30
70
80
20 40 60
2945 G16
VSENSE+ (V)
0
–2
I
SENSE
– (µA)
10
8
6
0
4
2
80
20 40 60
2945 G17
IADR (µA)
–10
0.0
V
ADR
(V)
3.0
2.5
2.0
0.5
1.5
1.0
10
–5 0 5
2945 G18
VCC SHUNT CURRENT (mA)
0
6.0
INTV
CC
VOLTAGE (V)
6.6
6.4
6.2
30
40
10 20
2945 G15
LTC2945
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PIN FUNCTIONS
ADIN: ADC Input. The onboard ADC measures voltages
between 0V and 2.048V. Tie to ground if unused.
ADR1, ADR0: I2C Device Address Inputs. Connecting these
pins to INTVCC, GND or leaving the pins open configures
one of nine possible addresses. See Table 1 in Applications
Information section for details.
ALERT: Fault Alert Output. Open drain logic output that
is pulled to ground after an ADC conversion resulted in
a fault to alert the host controller. A fault alert is enabled
by setting the corresponding bit in the ALERT register
as shown in Table 4. This device is compatible with the
SMBus alert protocol. See Applications Information. Tie
to ground if unused.
EXPOSED PAD (Pin 13, DD Package Only): Exposed pad
may be left open or connected to device ground. For best
thermal performance, connect to a large PCB area.
GND: Device Ground.
INTVCC: Internal Low Voltage Supply Input/Output. This
pin is used to power internal circuitry. It can be config-
ured as a direct input for a low voltage supply, as linear
regulator from higher voltage supply connected to VDD,
or as a shunt regulator. Connect this pin directly to a 2.7V
to 5.9V supply if available. When INTVCC is powered from
an external supply, short the VDD pin to INTVCC. If VDD
is connected to a 4V to 80V supply, INTVCC becomes the
5V output of an internal series regulator that can supply
up to 10mA to external circuitry. For even higher supply
voltages or if a floating topology is desired, INTVCC can
be used as a 6.3V shunt regulator. Connect the supply to
INTVCC through a shunt resistor that limits the current to
less than 35mA. An undervoltage lockout circuit disables
the ADC when the voltage at this pin drops below 2.5V.
Connect a bypass capacitor between 0.1µF and 1µF from
this pin to ground.
SCL: I2C Bus Clock Input. Data at the SDAI pin is shifted
in or out on rising edges of SCL. This pin is driven by an
open-collector output from a master controller. An external
pull-up resistor or current source is required and can be
placed between SCL and VDD or INTVCC. The voltage at
SCL is internally clamped to 6.4V (5.9V minimum)
SDAI: I2C Bus Data Input. Used for shifting in address,
command or data bits. This pin is driven by an open-
collector output from a master controller. An external
pull-up resistor or current source is required and can be
placed between SDAI and VDD or INTVCC. The voltage at
SDAI is internally clamped to 6.4V (5.9V minimum)
SDAO: I2C Bus Data Output. Open-drain output used for
sending data back to the master controller or acknowledging
a write operation. An external pull-up resistor or current
source is required.
SDAO: Inverted I2C Bus Data Output. Open-drain output
used for sending data back to the master controller or
acknowledging a write operation. Data is inverted for
convenience of opto-isolation. An external pull-up resistor
or current source is required.
SENSE+: Supply Voltage and Current Sense Input. Used as
a supply and current sense input for the internal current
sense amplifier. The voltage at this pin is monitored by the
onboard ADC with a full-scale input range of 102.4V. See
Figure 16 for recommended Kelvin connection.
SENSE–: Current Sense Input. Connect an external sense
resistor between SENSE+ and SENSE–. The differential
voltage between SENSE+ and SENSE– is monitored by the
onboard ADC with a full-scale sense voltage of 102.4mV.
VDD: High Voltage Supply Input. This pin powers an internal
series regulator with input voltages ranging from 4V to
80V and produces 5V at INTVCC when the input voltage
is above 7V. Connect a bypass capacitor between 0.1µF
and 1µF from this pin to ground if external load is pres-
ent on the INTVCC pin. The onboard 12-bit ADC can be
configured to monitor the voltage at VDD with a full-scale
input range of 102.4V.
LTC2945
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2945 F01
C2
0.1µF
VIN
4V TO 80V
R
SNS
0.02Ω
VOUT
VADIN
R1
2k
R2
2k
R3
2k
3.3V
VDD
SCL
SDA
INT
GND
ADR0
SCL
VDD
INTVCC SDAI
SDAO
ADIN
ALERT
ADR1
SENSE+
GND
SENSE–
LTC2945 µP
Figure 1. Monitoring High Side Current and Voltages
Using the LTC2945
The LTC2945 offers a compact and complete solution for
high- and low-side power monitoring. With an input com-
mon mode range of 0V to 80V and a wide input supply
operating voltage range from 2.7V to 80V
, this device is
ideal for a large variety of power management applications
including automotive, industrial and telecom infrastructure.
The basic application circuit shown in Figure 1 provides
monitoring of high side current with a 0.02Ω resistor
(5.12A full-scale), input voltage (102.4V full-scale) and an
external voltage (2.048V full-scale), all using an internal
12-bit resolution ADC.
Data Converter
The LTC2945 features an onboard, 12-bit Δ∑ ADC that inher-
ently averages input noise over the measurement window.
The ADC continuously monitors three voltages in sequence:
ΔSENSE first, VDD or VSENSE+ second, and VADIN third. The
differential voltage between SENSE+ and SENSE– is moni-
tored with 25μV resolution (102.4mV full-scale) to allow
accurate measurement across very low value shunt resistors.
APPLICATIONS INFORMATION
The supply voltage at VDD or SENSE+ is directly measured
with 25mV resolution (102.4V full-scale). The voltage at
the uncommitted ADIN pin is measured with 0.5mV resolu-
tion (2.048V full-scale) to allow monitoring of an arbitrary
external voltage. A 12-bit digital word corresponding to
each measured voltage is stored in two adjacent registers
OPERATION
The LTC2945 accurately monitors current, voltage, and
power of any supply rail from 0V to 80V. An internal linear
regulator allows the LTC2945 to operate directly from a
4V to 80V rail, or from an external supply voltage between
2.7V and 5.9V. Quiescent current is less than 0.9mA in
normal operation. Enabling shutdown mode via the I2C
interface reduces the quiescent current to below 80μA.
The LTC2945 includes a shunt regulator for operation from
supply voltages above 80V.
The onboard 12-bit analog-to-digital converter (ADC) runs
either continuously or on-demand using snapshot mode.
In the default continuous scan mode, the ADC repeatedly
measures the differential voltage between SENSE+ and
SENSE– (full-scale 102.4mV) the voltage at the SENSE+
or VDD pin (full-scale 102.4V), and the voltage at the ADIN
pin (full-scale 2.048V). The conversion results are stored
in onboard registers.
In snapshot mode, the LTC2945 performs a single mea-
surement of one selected voltage or current. Snapshot
mode is enabled by setting the snapshot mode enable bit
in the CONTROL register via the I2C interface. A status bit
in the CONTROL register monitors the ADC’s conversion;
when complete, the conversion result is stored in the cor-
responding data registers.
Onboard logic tracks the minimum and maximum values
for each ADC measurement, calculates power data by
digitally multiplying the stored current and voltage data,
and triggers a user-configurable alert by pulling the ALERT
pin low when the ADC measured value falls outside the
programmed window thresholds. All logic outputs are
stored in onboard registers. The LTC2945 includes an
I2C interface to access the onboard data registers and to
program the alert threshold and control registers. Two
three-state pins, ADR1 and ADR0, are decoded to allow
nine device addresses (see Table 1). The SDA pin is split
into SDAI (input) and SDAO (output, LTC2945) or SDAO
(output, LTC2945-1) to facilitate opto-isolation.
LTC2945
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SENSE pins can be biased independent of the part’s supply
voltage. Alternatively, if a low voltage supply is present it
can be connected to the INTVCC pin as shown in Figure 2c
to minimize on-chip power dissipation. When INTVCC is
powered from a secondary supply, connect VDD to INTVCC.
For supply voltages above 80V, the shunt regulator at
INTVCC can be used in both high and low side configura-
tions to provide power to the LTC2945 through an external
shunt resistor, RSHUNT. Figure 3a shows a high side power
monitor with an input monitoring range beyond 80V in a
high side shunt regulator configuration. The device ground
is separated from ground through RSHUNT and clamped at
6.3V below the input supply. Note that due to the different
ground levels, the I2C signals from the part need to be level
shifted for communication with other ground referenced
components. The bus voltage can be measured with the
ADIN pin as shown in Figure 3a. To mitigate the effect of VBE
mismatch in the PNP mirror, select R1 (=R2) to drop 1V at
the operating voltage. For details on the power calculation,
refer to the Power Calculation and Configuration section.
Figure 3b shows a high side rail-to-rail power monitor which
derives power from a greater than 80V secondary supply.
The voltage at INTVCC is clamped at 6.3V above ground in a
low side shunt regulator configuration to power the part. In
low side power monitors, the device ground and the current
sense inputs are connected to the negative terminal of the
input supply and the ADIN pin can be used to measure the
bus voltage with an external resistive divider as shown in
Figure 3c. The low side shunt regulator configuration allows
operation with input supplies above 80V by clamping the
voltage at INTVCC. RSHUNT should be sized according to the
following equation:
V
S(MAX )
– 5.9V
35mA ≤RSHUNT ≤
V
S(MIN)
– 6.7V
1mA +ILOAD(MAX )
where VS(MAX) and VS(MIN) are the operating maximum
and minimum of the supply. ILOAD(MAX) is the maximum
external current load that is connected to the shunt regula-
tor. The shunt resistor must also be rated to safely dissipate
the worst-case power
. As an example, consider the –48V
Telecom System where the supply operates from –36V to
–72V and the shunt regulator is used to supply an external
load up to 4mA. RSHUNT needs to be between 1.9k and
5.9k according to the above equation, and for reduced
APPLICATIONS INFORMATION
out of the six total ADC data registers (ΔSENSE MSB/LSB,
VIN MSB/LSB, and ADIN MSB/LSB), with the eight MSBs
in the first register and the four LSBs in the second (see
Table 2). The lowest 4 bits in the LSB registers are set to 0.
These data registers are updated immediately following the
corresponding ADC conversion, giving an effective refresh
rate of 7.5Hz in continuous scan mode.
The data converter also features a snapshot mode which
makes a measurement of a single selected voltage (either
ΔSENSE, VDD or VSENSE+, or VADIN). To make a snapshot
measurement, set CONTROL register bit A7 and write the
two-bit code of the desired ADC channel to A6 and A5 (Table
3) using a Write Byte command. When the Write Byte com-
mand is completed, the ADC converts the selected voltage
and the Busy Bit (A3 in the CONTROL register) will be set to
indicate that the conversion is in progress. After completing
the conversion, the ADC will halt and the Busy Bit will reset
to indicate that the data is ready. To make another snapshot
measurement, rewrite the CONTROL register.
Flexible Power Supply to LTC2945
The LTC2945 can be externally configured to flexibly derive
power from a wide range of supplies. The LTC2945 includes
an onboard linear regulator to power the low-voltage internal
circuitry connected to the INTVCC pin from high VDD voltages.
The regulator operates with VDD voltages from 4V to 80V,
and produces a 5V output capable of supplying 10mA at the
INTVCC pin when VDD is greater than 7V. The regulator is
disabled when die temperature rises above 150°C, and the
output is protected against accidental shorts. Bypass capaci-
tors between 0.1μF and 1μF at both the VDD and INTVCC pins
are recommended for optimal transient performance. Note
that operation with high VDD voltages can cause significant
power dissipation, and care is required to ensure the operating
junction temperature stays below 125°C. For improved power
dissipation, use the QFN package and solder the exposed pad
to a large copper region for improved thermal resistance.
Figure 2a shows the LTC2945 being used to monitor an input
supply that ranges from 4V to 80V. No secondary supply
is needed since VDD can be connected directly to the input
supply. If the LTC2945 is used to monitor an input supply of
0V to 80V, it can derive power from a wide range secondary
supply connected to the VDD pin as shown in Figure 2b. The
(1)
LTC2945
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APPLICATIONS INFORMATION
C2
VIN
4V TO 80V
R
SNS
V
OUT
VDD
INTVCC
SENSE+
GND
2945 F02a
SENSE–
LTC2945
C2
VIN
0V TO 80V
4V TO 80V
R
SNS
V
OUT
VDD
INTVCC
SENSE+
GND
2945 F02b
SENSE–
LTC2945
VIN
0V TO 80V
2.7V TO 5.9V
C2
R
SNS
V
OUT
VDD
INTVCC
SENSE+
GND
2945 F02c
SENSE–
LTC2945
Figure 2a. LTC2945 Derives Power from
the Supply Being Monitored
Figure 3a. LTC2945 Derives Power
Through High-Side Shunt Regulator
Figure 3b. LTC2945 Derives Power Through Low-Side
Shunt Regulator in High-Side Current Sense Topology
Figure 2b. LTC2945 Derives Power from
a Wide Range Secondary Supply
Figure 2c. LTC2945 Derives Power from
a Low Voltage Secondary Supply
GND
C2R1
R2
VNEG
>
–80V RSNS
V
OUT
VDD
RSHUNT
INTVCC
SENSE–
GND
ADIN
2945 F03a
SENSE+
LTC2945
Figure 3c. LTC2945 Derives Power Through Low-Side
Shunt Regulator in Low-Side Current Sense Topology
VIN
>80V
R4
R2
RSHUNT
ADIN
Q1
GND
2945 F03a
LTC2945
R3
R1INTVCC
R
SNS
SENSE+SENSE–
VIN
0V TO 80V
>80V
C2
R
SNS
V
OUT
RSHUNT
VDD
INTVCC
SENSE+
GND
2945 F03b
SENSE–
LTC2945
LTC2945
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APPLICATIONS INFORMATION
GND
C2
VNEG
–4V TO –80V
R
SNS
V
OUT
VDD
INTVCC
SENSE–
GND
2945 F03b
SENSE+
LTC2945
Figure 3d. LTC2945 Derives Power from the Supply
Being Monitored in Low-Side Current Sense Topology
power dissipation, a larger resistance is advantageous.
The worst-case power dissipated in an RSHUNT of 5.4k is
calculated to be 0.8W. So, three 0.5W rated 1.8k resistors
in series would suffice for this example.
If the supply input is nominally below 80V and transient
is limited to below 100V, the shunt resistor is not required
and VDD can be connected to GND of the supply as shown
in Figure 3d.
Supply Undervoltage Lockout
During power-up, the internal I2C logic and the ADC are
enabled when either VDD or INTVCC rises above its under-
voltage lockout threshold. During power-down, the ADC is
disabled when VDD and INTVCC fall below their respective
undervoltage lockout thresholds. The internal I2C logic is
reset when VDD and INTVCC fall below their respective I2C
reset thresholds.
Shutdown Mode
The LTC2945 includes a low quiescent current shutdown
mode, controlled by bit A1 in the CONTROL register
(Table 3). Setting A1 puts the part in shutdown mode,
powering down the ADC and internal reference. The internal
I2C bus remains active, and although the ADR1 and ADR0
pins are disabled, the device will retain the most recently
programmed I2C bus address. All on-board registers re-
tain their contents and can be accessed through the I2C
interface. To re-enable ADC conversions, reset bit A1 in
the CONTROL register. The analog circuitry will power up
and all registers will retain their contents.
The onboard linear regulator is disabled in shutdown mode
to conserve power. If low IQ mode is not required and the
regulator is used to power I2C bus-related circuitry such as
opto-couplers or pull-ups, ensure bit A1 in the CONTROL
register is masked off during software development. In such
applications, the user is advised that accidentally disabling
the regulator would prevent I2C communication from the
master and cause the LTC2945 to disengage from the system.
The LTC2945 would then have to be reset by cycling its power
to come out of shutdown. It is recommended that external
regulators be used in such applications if powering down
the LTC2945 is desirable. Quiescent current drops below
80µA in shutdown mode with the internal regulator disabled.
Power Calculation and Configuration
The LTC2945 calculates power by multiplying the measured
current with the measured voltage. In continuous mode, the
differential voltage between SENSE+ and SENSE– is measured
to obtain load current data. The supply voltage data for mul-
tiplication can be selected between VDD, SENSE+, or ADIN.
SENSE+ is selected by default as it is normally connected
to the supply voltage. In negative supply voltage systems
such as shown in Figure 3d, the device ground (GND pin
of LTC2945) and SENSE– are connected to the supply and
VDD measures the supply voltage at GND with respect to the
device ground. For negative supply voltages of more than
80V, use external resistors to divide down the voltage to suit
the ADIN measurement range. In the CONTROL register,
• write bits A2=1, A0=1 to select SENSE+ (Default)
• write bits A2=0, A0=1 to select VDD
• write bits A2=1, A0=0 to select ADIN
More details on the CONTROL register can be found in
Table 3.
Once the ADC conversions are complete, a 24-bit power
value is generated by digitally multiplying the 12-bit load
current data with the 12-bit supply voltage data. 1LSB of
power is 1LSB of voltage multiplied by 1LSB of ΔSENSE
(current). The result is held in the three adjacent POWER
registers (Table 2). The POWER registers initialize with
undefined data and subsequently refresh at a frequency
of 7.5Hz in continuous scan mode. In snapshot mode, the
POWER registers are not refreshed.
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APPLICATIONS INFORMATION
Storing Minimum and Maximum Values
The LTC2945 compares each measurement including the
calculated power with the stored values in the respective
MIN and MAX registers for each parameter (Table 2). If
the new conversion is beyond the stored minimum or
maximum values, the MIN or MAX registers are updated
with the new values. The MIN and MAX of the registers are
refreshed at the end of their respective ADC conversions
in both continuous scan mode and snapshot mode. They
are also refreshed if the ADC registers are written via the
I2C bus with values beyond the stored values. To initiate
a new peak hold cycle, write all 1’s to the MIN registers
and all 0’s to the MAX registers via the I2C bus. These
registers will be updated when the next respective ADC
conversion is done.
The LTC2945 also includes MIN and MAX THRESHOLD
registers (Table 2) for the measured parameters including
the calculated power. At power-up, the maximum thresh-
olds are set to all 1’s and minimum thresholds are set to
all 0’s, effectively disabling them. The thresholds can be
reprogrammed to any desired value via the I2C bus.
Fault Alert and Resetting Faults
As soon as a measured quantity falls below the minimum
threshold or exceeds the maximum threshold, the LTC2945
sets the corresponding flag in the STATUS register and
latches it into the FAULT register (see Figure 4). The ALERT
pin is pulled low if the appropriate bit in the ALERT register
is set. More details on the alert behavior can be found in
the Alert Response Protocol section.
An active fault indication can be reset by writing zeros
to the corresponding FAULT register bits or by reading
the FAULT CoR register (Table 2), which clears all FAULT
register bits. All FAULT register bits are also cleared if the
VDD and INTVCC fall below their respective I2C logic reset
threshold. Note that faults that are still present, as indi-
cated in the STATUS registers, will immediately reappear.
I2C Interface
The LTC2945 includes an I2C/SMBus-compatible inter-
face to provide access to the onboard registers. Figure 5
shows a general data transfer format using the I2C bus.
The LTC2945 is a read-write slave device and supports
the SMBus Read Byte, Write Byte, Read Word and Write
Word protocols. The LTC2945 also supports extended
Read and Write commands that allow reading or writing
more than two bytes of data. When using the Read/Write
Word or extended Read and Write commands, the bus
master issues an initial register address and the internal
register address pointer automatically increments by 1
after each byte of data is read or written. After the register
address reaches 31h, it will roll over to 00h and continue
incrementing. A Stop condition resets the register address
pointer to 00h. The data formats for the above commands
are shown in Figures 6 to 11.
I2C Device Addressing
Nine distinct I2C bus addresses are configurable using the
three-state pins ADR0 and ADR1, as shown in Table 1.
ADR0 and ADR1 should be tied to INTVCC, to GND, or left
floating (NC) to configure the lower four address bits.
During low power shutdown, the address select state
is latched into memory powered from standby supply.
Address bits a6, a5 and a4 are permanently set to (110)
and the least significant bit is the R/W bit. In addition, all
LTC2945 devices will respond to a common Mass Write
address (1100 110)b; this allows the bus master to write
to several LTC2945s simultaneously, regardless of their
individual address settings. The LTC2945 will also respond
to the standard ARA address (0001100)b if the Alert pin
is asserted; see the Alert Response Protocol section for
more details. The LTC2945 will not respond to the ARA
address if no alerts are pending.
Start and Stop Conditions
When the I2C bus is idle, both SCL and SDA are in the high
state. A bus master signals the beginning of a transmission
with a Start condition by transitioning SDA from high to
low while SCL stays high. When the master has finished
communicating with the slave, it issues a Stop condition
by transitioning SDA from low to high while SCL stays
high. The bus is then free for another transmission.
LTC2945
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Figure 4. LTC2945 Fault Alert Generation Blocks
APPLICATIONS INFORMATION
Figure 5. General Data Transfer over I2C
DIGITAL
COMPARATOR
LOGIC LATCH
STATUS
RESET
FAULT
ALERT
ENA_ALERT_RESPONSE
MEASURED
DATA
THRESHOLD
DATA
2945 F04
SDA
SCL
S P
a6 - a0 b7 - b0 b7 - b0
1 - 7 1 - 7 1 - 78 8 89 9 9
START
CONDITION
STOP
CONDITION
ADDRESS ACK DATA DATAACK ACKR/W
2945 F05
Figure 6. LTC2945 Serial Bus SDA Write Byte Protocol Figure 7. LTC2945 Serial Bus SDA Write Word Protocol
Figure 8. LTC2945 Serial Bus SDA Write Page Protocol Figure 9. LTC2945 Serial Bus SDA Read Byte Protocol
Figure 10. LTC2945 Serial Bus SDA Read Word Protocol
Figure 11. LTC2945 Serial Bus SDA Read Page Protocol
S ADDRESS
1 1 0 a3:a0
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
COMMAND DATA
X X b5:b00
W
0 0 0b7:b0
A A A P
2945 F06
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
S ADDRESS
1 1 0 a3:a0
COMMAND DATA DATA
X X b5:b00
W
0 0 0 0
2945 F07
b7:b0b7:b0
AA A A P
S ADDRESS
1 1 0 a3:a0
COMMAND
0X X b5:b00
W
0 0
2945 F08
A A A P
b7:b0
DATA
0
A
b7:b0
DATA
0
A
...
...
b7:b0
DATA S ADDRESS
1 1 0 a3:a0 1 1 0 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X b5:b00
W
0 0
2945 F09
A A AP
S ADDRESS
1 1 0 a3:a0 1 1 0 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X b5:b00
W
0 0
2945 F10
A
0
A
b7:b0
DATA
AAP
S ADDRESS
1 1 0 a3:a0 1 1 0 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X b5:b00
W
0 0
2945 F11
A
0
A
b7:b0
DATA
AAP
...
...
b7:b0
DATA
LTC2945
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APPLICATIONS INFORMATION
Stuck-Bus Reset
The LTC2945 I2C interface features a stuck bus reset timer
to prevent it from holding the bus lines low indefinitely if
the SCL signal is interrupted during a transfer. The timer
starts when either SCL or SDAI is low, and resets when
both SCL and SDAI are pulled high. If either SCL or SDAI
are low for over 33ms, the stuck-bus timer will expire and
the internal I2C interface and the SDAO pin pulldown logic
will be reset to release the bus. Normal communication
will resume at the next Start command.
Acknowledge
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last
byte of data was received. The transmitter always releases
the SDA line during the acknowledge clock pulse. The
LTC2945 will pull the SDA line low on the 9th clock cycle
to acknowledge receipt of the data. If the slave fails to
acknowledge by leaving SDA high, then the master can
abort the transmission by generating a Stop condition.
When the master is receiving data from the slave, the
master must acknowledge the slave by pulling down the
SDA line during the 9th clock pulse to indicate receipt of
a data byte. After the last byte has been received by the
master, it will leave the SDA line high (not acknowledge)
and issue a Stop condition to terminate the transmission.
Write Protocol
The master begins a write operation with a Start condition
followed by the seven-bit slave address and the R/W bit
set to zero. After the addressed LTC2945 acknowledges
the address byte, the master then sends a command byte
that indicates which internal register the master wishes to
write. The LTC2945 acknowledges this and then latches the
lower six bits of the command byte into its internal register
address pointer. The master then delivers the data byte and
the LTC2945 acknowledges once more and writes the data
into the internal register pointed to by the register address
pointer. If the master continues sending additional data
bytes with a Write Word or extended Write command, the
additional data bytes will be acknowledged by the LTC2945,
the register address pointer will automatically increment by
one, and data will be written as above. The write operation
terminates and the register address pointer resets to 00h
when the master sends a Stop condition.
Read Protocol
The master begins a read operation with a Start condition
followed by the 7-bit slave address and the R/W bit set
to zero. After the addressed LTC2945 acknowledges the
address byte, the master then sends a command byte
that indicates which internal register the master wishes to
read. The LTC2945 acknowledges this and then latches the
lower six bits of the command byte into its internal register
address pointer. The master then sends a repeated Start
condition followed by the same 7-bit address with the R/W
bit now set to 1. The LTC2945 acknowledges and sends
the contents of the requested register. The transmission
terminates when the master sends a Stop condition. If the
master acknowledges the transmitted data byte, as in a
Read Word command, the LTC2945 will send the contents
of the next register. If the master keeps acknowledging,
the LTC2945 will keep incrementing the register address
pointer and sending out data bytes. The read operation
terminates and the register address pointer resets to 00h
when the master sends a Stop condition.
Alert Response Protocol
When any of the fault bits in the FAULT register are set, a
bus alert is generated if the appropriate bit in the ALERT
register has been set. This allows the bus master to select
which faults will generate alerts. At power-up, the ALERT
register is cleared (no alerts enabled) and the ALERT pin is
high. If an alert is enabled, the corresponding fault causes
the ALERT pin to pull low. The bus master responds to the
alert in accordance with the SMBus alert response protocol
by broadcasting the Alert Response Address (0001100)b,
and the LTC2945 replies with its own address and releases
its ALERT pin as shown in Figure 12. The ALERT line is also
released if the FAULT or FAULT CoR registers are read (see
Table 2) since the faulting event can be identified by the
content in these registers. The ALERT signal is not pulled
low again until the Fault register indicates a different fault
has occurred or the original fault is cleared and it occurs
again. Note that this means repeated or continuing faults
will not generate additional alerts until the associated
FAULT register bits have been cleared.
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APPLICATIONS INFORMATION
If two or more LTC2945s on the same bus are generating
alerts when the ARA is broadcasted, the bus master will
repeat the alert response protocol until the ALERT line
is released. The device with the highest priority (lowest
address) will reply first and the device with the lowest
priority (highest address) will reply last.
RSHUNT can then be calculated using Equation 1. Note that
both LTC2945 and LTC2945-1 can be used in the shunt
regulator applications mentioned.
Figure 16 shows an alternate connection for use with low-
speed opto-couplers and the LTC2945-1. This circuit uses
a limited-current pullup on the internally clamped SDAI
pin and clamps the SDAO pin with the input diode of the
outgoing opto-isolator, removing the need to use INTVCC
for biasing in the absence of an auxiliary low voltage sup-
ply. For proper clamping:
V
S(MAX )
– 5.9V
5mA
≤R4≤
V
S(MIN)
– 6.9V
0.5mA
As an example, a supply that operates from 36V to 72V
would require the value of R4 to be between 13k and 58k.
The LTC2945-1 must be used in this application to ensure
that the SDAO signal polarity is correct.
The LTC2945-1 can also be used with high-speed opto-
couplers with push-pull outputs and inverted logic as
shown in Figure 17. The incoming opto-isolator draws
power from the INTVCC, and the data output is connected
directly to the SDAI pin with no pullup required. Ensure
the current drawn does not exceed the 10mA maximum
capability of the INTVCC pin. The SDAO pin is connected
to the cathode of the outgoing optocoupler with a current
limiting resistor connected back to INTVCC. An additional
discrete N-channel MOSFET is required at the output of
the outgoing optocoupler to provide the open-drain pull-
down that the I2C bus requires. Finally, the input of the
incoming opto-isolator is connected back to the output
as in the low-speed case.
Layout Considerations
A Kelvin connection between the sense resistor RSNS and
the LTC2945 is recommended to achieve accurate current
sensing (Figure 18). The recommended minimum trace
width for 1oz copper foil is 0.02” per amp to ensure the
trace stays at a reasonable temperature. Using 0.03” per
amp or wider is preferred. Note that 1oz copper exhibits
a sheet resistance of about 530μΩ per square.
Figure 12. LTC2945 Serial Bus SDA Alert Response Protocol
S
ALERT
RESPONSE
ADDRESS
0 0 0 1 1 0 0
DEVICE
ADDRESS
a7:a0 11
R
0
2945 F12
AAP
Opto-Isolating the I2C Bus
Opto-isolating a standard I2C device is complicated
by the bidirectional SDA pin. The LTC2945/LTC2945-1
minimize this problem by splitting the standard I2C SDA
line into SDAI (input) and SDAO (output, LTC2945) or
SDAO (inverted output, LTC2945-1). The SCL is an input
only pin and does not require special circuitry to isolate.
For conventional non-isolated I2C applications, use the
LTC2945 and tie the SDAI and SDAO pins together to form
a standard I2C SDA pin.
Low speed isolated interfaces that use standard open-
drain opto-isolators typically use the LTC2945 with the
SDAI and SDAO pins separated as shown in Figure 13.
Connect SDAI to the output of the incoming opto-isolator
with a pullup resistor to INTVCC or a local 5V supply; con-
nect SDAO to the cathode of the outgoing opto-isolator
with a current-limiting resistor in series with the anode.
The input and output must be connected together on the
isolated side of the bus to allow the LTC2945 to participate
in I2C arbitration. Note that maximum I2C bus speed will
generally be limited by the speed of the opto-couplers
used in this application.
Both low and high side shunt regulators can supply up to
34mA of current to drive opto-isolator and pullup resis-
tors as shown in Figure 14 and 15. For identical SDAI/SCL
pullup resistors the maximum load is:
ILOAD(MAX)=6.7 2
R1+1
R3
(2)
(3)
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APPLICATIONS INFORMATION
Figure 13. Opto-Isolation of a 10kHz I2C Interface Between LTC2945 and Microcontroller (SCL Omitted for Clarity)
Figure 14. Low Speed 10kHz Opto-Isolators Powered from Low-Side Shunt Regulator
Figure 15. Low Speed 10kHz Opto-Isolators Powered from High-Side Shunt Regulator
LTC2945
SDAI
SDAO
GND
3.3V
GND
SDA
µP
1/2 MOCD207M
1/2 MOCD207M
5V
R4
10k
R5
0.82k
R6
0.51k
R7
10k
VDD
2945 F13
LTC2945
SDAI
SDAO
GND
GND
3.3V
GND
SDA
µP
1/2 MOCD207M
1/2 MOCD207M
R3
1k
R1
10k
R2
0.51k
R4
10k
VDD
RSHUNT
2945 F14
RSNS
0.02Ω
SENSE–SENSE+
INTVCC
VDD
C1
1µF
VOUT
VEE
VEE
LTC2945-1
SDAI
SDAO
GND
3.3V
GND
SDA
µP
1/2 MOCD207M
1/2 MOCD207M
R3
1k
R1
10k
R2
1k
R4
10k
VDD
RSHUNT
VOUT
VIN
2945 F15
RSNS
0.02Ω
SENSE+SENSE–
INTVCC
VDD
C1
1µF
LTC2945
20
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For more information www.linear.com/LTC2945
APPLICATIONS INFORMATION
V
IN
48V 1/2 ACPL-064L*
1/2 ACPL-064L*
* CMOS OUTPUT
ISO_SDA
C1
1µF
C2
1µF R5
2k
VDD INTVCC
LTC2945-1
SDAO
SDAI
GND
VCC
VCC
GND
GND
BS170
M1
R6
2k
R7
2k
2945 F17
3.3V
GND
SDA
µP
VDD
Figure 16. Opto-Isolation of a 1.5kHz I2C Interface Between LTC2945-1 and Microcontroller (SCL Omitted for Clarity)
Figure 17. Opto-Isolation of I2C Interface with Low Power, High Speed Opto-couplers (SCL Omitted for Clarity)
LTC2945-1
SDAI
SDAO
GND
3.3V
GND
SDA
µP
1/2 MOCD207M
1/2 MOCD207M
48V
R4
20k
R5
7.5k
R6
0.51k
R7
10k
VDD
2945 F16
Figure 18. Recommended Layout for Kelvin Connection
10
9
6 7
8
4
5
11
3
2
112
V
IN
R
SNS
TO
LOAD
SENSE
+
SENSE
–
2945 F18
LTC2945
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For more information www.linear.com/LTC2945
APPLICATIONS INFORMATION
Table 1. LTC2945 Device Addressing
DESCRIPTION
HEX
DEVICE
ADDRESS BINARY DEVICE ADDRESS
LTC2945
ADDRESS
PINS
h a6 a5 a4 a3 a2 a1 a0 R/WADR1 ADR0
Mass Write CC 1 1 0 0 1 1 0 0 X X
Alert Response 19 0 0 0 1 1 0 0 1 X X
0 CE 1 1 0 0 1 1 1 X H L
1 D0 1 1 0 1 0 0 0 X NC H
2 D2 1 1 0 1 0 0 1 X H H
3 D4 1 1 0 1 0 1 0 X NC NC
4 D6 1 1 0 1 0 1 1 X NC L
5 D8 1 1 0 1 1 0 0 X L H
6 DA 1 1 0 1 1 0 1 X H NC
7 DC 1 1 0 1 1 1 0 X L NC
8 DE 1101111XLL
Table 2. LTC2945 Register Addresses and Contents
REGISTER
ADDRESS REGISTER NAME READ/WRITE DESCRIPTION DEFAULT
00h CONTROL (A) R/W Controls ADC Operation Mode and Test Mode 05h
01h ALERT (B) R/W Selects Which Faults Generate Alerts 00h
02h STATUS (C) R System Status Information 00h
03h FAULT (D) R/W Fault Log 00h
04h FAULT CoR (E) CoR Same Data as Register D, D Content Cleared on Read 00h
05h POWER MSB2 R/W** Power MSB2 Data XXh
06h POWER MSB1 R/W** Power MSB1 Data XXh
07h POWER LSB R/W** Power LSB Data XXh
08h MAX POWER MSB2 R/W** Maximum Power MSB2 Data 00h
09h MAX POWER MSB1 R/W** Maximum Power MSB1 Data 00h
0Ah MAX POWER LSB R/W** Maximum Power LSB Data 00h
0Bh MIN POWER MSB2 R/W** Minimum Power MSB2 Data FFh
0Ch MIN POWER MSB1 R/W** Minimum Power MSB1 Data FFh
0Dh MIN POWER LSB R/W** Minimum Power LSB Data FFh
0Eh MAX POWER THRESHOLD MSB2 R/W Maximum Power Threshold MSB2 to Generate Alert FFh
0Fh MAX POWER THRESHOLD MSB1 R/W Maximum Power Threshold MSB1 to Generate Alert FFh
10h MAX POWER THRESHOLD LSB R/W Maximum Power Threshold LSB to Generate Alert FFh
11h MIN POWER THRESHOLD MSB2 R/W Minimum Power Threshold MSB2 to Generate Alert 00h
12h MIN POWER THRESHOLD MSB1 R/W Minimum Power Threshold MSB1 to Generate Alert 00h
13h MIN POWER THRESHOLD LSB R/W Minimum Power Threshold LSB to Generate Alert 00h
14h ΔSENSE MSB R/W** ΔSENSE MSB Data XXh
15h ΔSENSE LSB R/W** ΔSENSE LSB Data X0h
16h MAX ΔSENSE MSB R/W** Maximum ΔSENSE MSB Data 00h
LTC2945
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For more information www.linear.com/LTC2945
APPLICATIONS INFORMATION
17h MAX ΔSENSE LSB R/W** Maximum ΔSENSE LSB Data 00h
18h MIN ΔSENSE MSB R/W** Minimum ΔSENSE MSB Data FFh
19h MIN ΔSENSE LSB R/W** Minimum ΔSENSE LSB Data FOh
1Ah MAX ΔSENSE THRESHOLD MSB R/W Maximum ΔSENSE Threshold MSB to Generate Alert FFh
1Bh MAX ΔSENSE THRESHOLD LSB R/W Maximum ΔSENSE Threshold LSB to Generate Alert FOh
1Ch MIN ΔSENSE THRESHOLD MSB R/W Minimum ΔSENSE Threshold MSB to Generate Alert 00h
1Dh MIN ΔSENSE THRESHOLD LSB R/W Minimum ΔSENSE Threshold LSB to Generate Alert 00h
1Eh VIN MSB R/W** ADC VIN MSB Data XXh
1Fh VIN LSB R/W** ADC VIN LSB Data X0h
20h MAX VIN MSB R/W** Maximum VIN MSB Data 00h
21h MAX VIN LSB R/W** Maximum VIN LSB Data 00h
22h MIN VIN MSB R/W** Minimum VIN MSB Data FFh
23h MIN VIN LSB R/W** Minimum VIN LSB Data FOh
24h MAX VIN THRESHOLD MSB R/W Maximum VIN Threshold MSB to Generate Alert FFh
25h MAX VIN THRESHOLD LSB R/W Maximum VIN Threshold LSB to Generate Alert FOh
26h MIN VIN THRESHOLD MSB R/W Minimum VIN Threshold MSB to Generate Alert 00h
27h MIN VIN THRESHOLD LSB R/W Minimum VIN Threshold LSB to Generate Alert 00h
28h ADIN MSB R/W** ADIN MSB Data XXh
29h ADIN LSB R/W** ADIN LSB Data X0h
2Ah MAX ADIN MSB R/W** Maximum ADIN MSB Data 00h
2Bh MAX ADIN LSB R/W** Maximum ADIN LSB Data 00h
2Ch MIN ADIN MSB R/W** Minimum ADIN MSB Data FFh
2Dh MIN ADIN LSB R/W** Minimum ADIN LSB Data FOh
2Eh MAX ADIN THRESHOLD MSB R/W Maximum ADIN Threshold MSB to Generate Alert FFh
2Fh MAX ADIN THRESHOLD LSB R/W Maximum ADIN Threshold LSB to Generate Alert FOh
30h MIN ADIN THRESHOLD MSB R/W Minimum ADIN Threshold MSB to Generate Alert 00h
31h MIN ADIN THRESHOLD LSB R/W Minimum ADIN Threshold LSB to Generate Alert 00h
*Register address MSBs b7-b6 are ignored. ** Writable if bit A4 is set
LTC2945
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For more information www.linear.com/LTC2945
APPLICATIONS INFORMATION
Table 3. CONTROL Register A (00h) - Read/Write
BIT NAME OPERATION
A7 ADC Snapshot Mode Enable Enables ADC Snapshot Mode; 1 = Snapshot Mode Enabled. Only channel selected by A6 and A5 is
measured by the ADC. After the conversion, the BUSY bit is reset and the ADC is halted.
0 = Snapshot Mode Disabled (Continuous Scan Mode. Default)
A6 ADC Channel Label for Snapshot Mode ADC Channel Label for Snapshot Mode
A6 A5 ADC Channel
0 0 ΔSENSE (Default)
0 1 VIN
1 0 ADIN
A5
A4 Test Mode Enable Test Mode Halts ADC Operation and Enables Writes to Internal ADC/LOGIC Registers;
1 = Enable Test Mode, 0 = Disable Test Mode (Default)
A3 ADC Busy in Snapshot Mode ADC Current Status; 1 = ADC Converting, 0 = ADC Conversion Completed (Default), Not Writable
A2 VIN Monitor Enables VDD or SENSE+ Voltage Monitoring; 1 = Monitor SENSE+ Voltage (Default),
0 = Monitor VDD Voltage
A1 Shutdown Enable Enables Low-IQ / Shutdown Mode; 1 = Enable Shutdown, 0 = Normal Operation (Default)
A0 Multiplier Select Selects ADIN or SENSE+/VDD (depends on A2) data for digital multiplication with SENSE data;
1 = Select SENSE+/VDD (Default), 0 = Select ADIN
Table 4. ALERT Register B (01h) - Read/Write
BIT NAME OPERATION
B7 Maximum POWER Alert Enables Alert When POWER Calculation Data is > Maximum Power Threshold;
1 = Enable Alert,
0 = Disable Alert (Default)
B6 Minimum POWER Alert Enables Alert When POWER Calculation Data is < Minimum Power Threshold;
1 = Enable Alert,
0 = Disable Alert (Default)
B5 Maximum ΔSENSE Alert Enables Alert When ADC ΔSENSE Measurement Data is > Maximum ΔSENSE Threshold;
1 = Enable Alert,
0 = Disable Alert (Default)
B4 Minimum ΔSENSE Alert Enables Alert When ADC ΔSENSE Measurement Data is < Minimum ΔSENSE Threshold;
1 = Enable Alert,
0 = Disable Alert (Default)
B3 Maximum VIN Alert Enables Alert When ADC VIN Measurement Data is > Maximum VIN Threshold;
1 = Enable Alert,
0 = Disable Alert (Default)
B2 Minimum VIN Alert Enables Alert When ADC VIN Measurement Data is < Minimum VIN Threshold;
1 = Enable Alert,
0 = Disable Alert (Default)
B1 Maximum ADIN Alert Enables Alert When ADC ADIN Measurement Data is > Maximum ADIN Threshold;
1 = Enable Alert,
0 = Disable Alert (Default)
B0 Minimum ADIN Alert Enables Alert When ADC ADIN Measurement Data is < Minimum ADIN Threshold;
1 = Enable Alert,
0 = Disable Alert (Default)
LTC2945
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For more information www.linear.com/LTC2945
APPLICATIONS INFORMATION
Table 5. STATUS Register C (02h) - Read
BIT NAME OPERATION
C7 POWER Overvalue Present Indicates POWER Overvalue When POWER is > Maximum Power Threshold;
1 = POWER Overvalue,
0 = POWER Not Overvalue
C6 POWER Undervalue Present Indicates POWER Undervalue When POWER is < Minimum Power Threshold;
1 = POWER Undervalue,
0 = POWER Not Undervalue
C5 ΔSENSE Overvalue Present Indicates ΔSENSE Overvalue When ΔSENSE is > Maximum ΔSENSE Threshold;
1 = ΔSENSE Overvalue,
0 = ΔSENSE Not Overvalue
C4 ΔSENSE Undervalue Present Indicates ΔSENSE Undervalue When ΔSENSE is < Minimum ΔSENSE Threshold;
1 = ΔSENSE Undervalue,
0 = ΔSENSE Not Undervalue
C3 VIN Overvalue Present Indicates VIN Overvalue When VIN is > Maximum VIN Threshold;
1 = VIN Overvalue,
0 = VIN Not Overvalue
C2 VIN Undervalue Present Indicates VIN Undervalue When VIN is < Minimum VIN Threshold;
1 = VIN Undervalue,
0 = VIN Not Undervalue
C1 ADIN Overvalue Present Indicates ADIN Overvalue When ADIN is > Maximum ADIN Threshold;
1 = ADIN Overvalue,
0 = ADIN Not Overvalue
C0 ADIN Undervalue Present Indicates ADIN Undervalue When ADIN is < Minimum ADIN Threshold;
1 = ADIN Undervalue,
0 = ADIN Not Undervalue
Table 6. FAULT Register D (03h) - Read/Write
BIT NAME OPERATION
D7 POWER Overvalue Fault
Occurred
Indicates POWER Overvalue Fault When POWER was > Maximum Power Threshold;
1 = POWER Overvalue Fault Occurred,
0 = No POWER Overvalue Faults
D6 POWER Undervalue Fault
Occurred
Indicates POWER Undervalue Fault When POWER was < Minimum Power Threshold;
1 = POWER Undervalue Fault Occurred,
0 = No POWER Undervalue Faults
D5 ΔSENSE Overvalue Fault
Occurred
Indicates ΔSENSE Overvalue Fault When ΔSENSE was > Maximum ΔSENSE Threshold;
1 = ΔSENSE Overvalue Fault Occurred,
0 = No ΔSENSE Overvalue Faults
D4 ΔSENSE Undervalue Fault
Occurred
Indicates ΔSENSE Undervalue Fault When ΔSENSE was < Minimum ΔSENSE Threshold;
1 = ΔSENSE Undervalue Fault Occurred,
0 = No ΔSENSE Undervalue Faults
D3 VIN Overvalue Fault
Occurred
Indicates VIN Overvalue Fault When VIN was > Maximum VIN Threshold;
1 = VIN Overvalue Fault Occurred,
0 = No VIN Overvalue Faults
D2 VIN Undervalue Fault
Occurred
Indicates VIN Undervalue Fault When VIN was < Minimum VIN Threshold;
1 = VIN Undervalue Fault Occurred,
0 = No VIN Undervalue Faults
D1 ADIN Overvalue Fault
Occurred
Indicates ADIN Overvalue Fault When ADIN was > Maximum ADIN Threshold;
1 = ADIN Overvalue Fault Occurred,
0 = No ADIN Overvalue Faults
D0 ADIN Undervalue Fault
Occurred
Indicates ADIN Undervalue Fault When ADIN was < Minimum ADIN Threshold;
1 = ADIN Undervalue Fault Occurred,
0 = No ADIN Undervalue Faults
LTC2945
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For more information www.linear.com/LTC2945
APPLICATIONS INFORMATION
Table 9. POWER, MIN/MAX POWER, MIN/MAX POWER THRESHOLD Register Data Format: MSB2 Bytes- Read/Write*
BIT (7) BIT (6) BIT (5) BIT (4) BIT (3) BIT (2) BIT (1) BIT (0)
Data (23) Data (22) Data (21) Data (20) Data (19) Data (18) Data (17) Data (16)
* Set Bit A4 before writing to POWER and MIN/MAX POWER Registers
Table 10. POWER, MIN/MAX POWER, MIN/MAX POWER THRESHOLD Register Data Format: MSB1 Bytes- Read/Write*
BIT (7) BIT (6) BIT (5) BIT (4) BIT (3) BIT (2) BIT (1) BIT (0)
Data (15) Data (14) Data (13) Data (12) Data (11) Data (10) Data (9) Data (8)
* Set Bit A4 before writing to POWER and MIN/MAX POWER Registers
Table 8. ADC, ADC MIN/MAX, MIN/MAX THRESHOLD Register Data Format: LSB Bytes-Read/Write*
BIT (7) BIT (6) BIT (5) BIT (4) BIT (3) BIT (2) BIT (1) BIT (0)
Data (3) Data (2) Data (1) Data (0) Reserved** Reserved** Reserved** Reserved**
* Set Bit A4 before writing to ADC and MIN/MAX ADC Registers
** Read as ‘0’
Table 7. ADC, ADC MIN/MAX, MIN/MAX ADC THRESHOLD Register Data Format: MSB Bytes-Read/Write*
BIT (7) BIT (6) BIT (5) BIT (4) BIT (3) BIT (2) BIT (1) BIT (0)
Data (11) Data (10) Data (9) Data (8) Data (7) Data (6) Data (5) Data (4)
*Set Bit A4 before writing to ADC and MIN/MAX ADC Registers
Table 11. POWER, MIN/MAX POWER, MIN/MAX POWER THRESHOLD Register Data Format: LSB Bytes- Read/Write*
BIT (7) BIT (6) BIT (5) BIT (4) BIT (3) BIT (2) BIT (1) BIT (0)
Data (7) Data (6) Data (5) Data (4) Data (3) Data (2) Data (1) Data (0)
* Set Bit A4 before writing to POWER and MIN/MAX POWER Registers
LTC2945
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For more information www.linear.com/LTC2945
TYPICAL APPLICATIONS
A Wide Range Supply Monitor
2945 TA02
2.7V TO 5.9V
C2
0.1µF
VIN
0V TO 80V
R
SNS
0.02Ω
VOUT
VADIN
R1
2k
R2
2k
R3
2k
3.3V
VDD
SCL
SDA
INT
GND
ADR0
SCL
VDD
INTVCC SDAI
SDAO
ADIN
ALERT
ADR1
SENSE+
GND
SENSE–
LTC2945 µP
2945 TA03
VIN
4V TO 80V
C2
0.1µF
R
SNS
0.02Ω
VOUT
VADIN
R1
2k
R2
2k
R3
2k
3.3V
VDD
SCL
SDA
INT
GND
ADR0
SCL
VDD
INTVCC SDAI
SDAO
ADIN
ALERT
ADR1
SENSE+
GND
SENSE–
LTC2945 µP
Wide Range Supply Monitor with Wide Range VDD Input
Dual Supply Monitor with Common Opto-coupler for Galvanic Isolation
VADIN1
VADIN2
VIN1
24V
V
CC1
V
CC2
VCC2
VCC1
VIN2
48V
RSNS1
0.02Ω
RSNS2
0.02Ω
R4
10k
R5
10k
R6
1k
R7
1k
R8
0.51k
R9
0.51k
R10
10k
R11
10k
R12
10k
VOUT1
VOUT2
C1
1µF
C2
0.1µF
C3
1µF
C4
0.1µF
ADR0
SCL
VDD
INTVCC SDAI
SDAO
ADIN
ALERT
ADR1
SENSE+SENSE–
LTC2945
HCPL063L
HCPL063L
3.3V
SCL
SDA
VDD
INT GND
µP
ADR0
SCL
VDD
INTVCC SDAI
SDAO
ADIN
ALERT
ADR1
SENSE+
GND
GND
SENSE–
LTC2945
2945 TA04
VCC
VCC
3.3V
GND
GND
LTC2945
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For more information www.linear.com/LTC2945
Power Monitoring in –48V System Using Low Side Sensing (1.5kHz I2C Interface)
TYPICAL APPLICATIONS
C1
1µF
CONTROL REGISTER A2 = 0
MOCD207M
MOCD207M
2945 TA05
ADR0
ADR1
SCL
VDD INTVCC
VEE
SDAI
SDAO
ADIN
ALERT
SENSE–
GND
SENSE+
LTC2945
C2
0.1µF
–48V
RTN
VEE
–48V INPUT
R7
0.51k
R3
1k
R4
1k
VOUT
R8
0.51k
R9
10k
R10
10k
R11
10k
3.3V
RSNS
0.02Ω
VDD
GND
µP
SCL
SDA
INT
R1
20k
R2
20k
VCC
GND
RSHUNT
3 × 1.8k IN SERIES
C1
1µF
HCPL-063L
CONTROL REGISTER A0 = 0
VEE
VEE
HCPL-063L
2945 TA06
ADR0
ADR1
SCL
VDD
INTVCC
SDAI
SDAO
ADIN
ALERT
SENSE–
GND
SENSE+
LTC2945
VCC
GND
–48V
RTN
VEE
–48V INPUT
R7
0.51k
R3
0.51k
R4
1k
VOUT
C2
1µF R8
0.51k
R9
1k
R10
1k
R11
10k
3.3V
3.3V
RSNS
0.02Ω
VDD
GND
µP
SCL
SDA
INT
R12
100 Q1
PZTA42
D1
1N4148WS
R1
1k
R2
1k
R5
735k
R6
15k
Power Monitoring in –48V Harsh Environment Using INTVCC Shunt Regulator to Tolerate 200V Transients
LTC2945
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TYPICAL APPLICATIONS
Power Monitoring in –48V System Using External Linear Regulator to Supply Opto-couplers and SCL/SDA Resistive Pull-Ups
Wide Range Dual Supply Monitor with Single LTC2945
VCC
GND
C1
1µF
PS9817-2
CONTROL REGISTER A2 = 0
VEE
PS9817-2
2945 TA07
ADR0
ADIN
ADR1
SCL
VDD
INTVCC
VEE
SDAI
SDAO
ALERT
SENSE–
GND
SENSE+
LTC2945
LT3010-5
VCC
GND
–48V
RTN
VEE
–48V INPUT
R7
0.5k
R3
0.51k
R4
1k
VOUT
R8
0.51k
R9
1k
R10
1k
R11
10k
5V
5V
RSNS
0.02Ω
VDD
GND
µP
SCL
SDA
INT
R1
1k
R2
10k
IN
SHDN
OUT
SENSE
GND
C3
0.1µF
C2
1µF
* SELECT RSHUNT ACCORDING TO THE EQUATION IN THE “FLEXIBLE POWER SUPPLY TO LTC2945” SECTION.
** VOLTAGE DATA HAS AN OFFSET VALUE DUE TO D1’S DROP, IF DESIRABLE THIS CAN BE COMPENSATED THROUGH SOFTWARE.
RADIN
20k
2945 TA08
RSNS
0.02Ω
C3
0.1µF
C2
0.1µF
ADR0
ADR1
VDD
INTVCC
SDAI
SCL
SDAO
ALERT
ADIN
SENSE+
GND
SENSE–
LTC2945
LTC6102
RIN2
1k
RSHUNT*
D2
BAT54
D1
BAT54
RIN1
1k
C1
0.1µF
RSNS1
0.02Ω
V+
V–
VREG
–INF –INS
OUT
+IN
SUPPLY B
4.5V TO 80V
SUPPLY A
4.5V TO 80V
I2C
INTERFACE
TO
LOAD
SUPPLY A SENSE+∆SENSE INTERNALLY GENERATED
USE EXTERNAL µP TO MULTIPLY VOLTAGE (VDD)
AND CURRENT (ADIN) DATA
ADINVDD**
1
VOLTAGE
DATA
CURRENT
DATA
POWER
DATA
CONTROL REG
A2
0SUPPLY B
LTC2945
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Ruggedized 4V to 70V High Side Power Monitor with Surge Protection Up to 200V
Isolated Wide Range I2C Power Monitor
TYPICAL APPLICATIONS
VCC
GND
C1
0.1µF
HCPL-063L
FGND
HCPL-063L
2945 TA09
ADR1
ADR0
ADIN
SCL
VDD
VIN VOUT
INTVCC
SDAI
SDAO
ALERT
SENSE+
GND
SENSE–
LTC2945
VCC
GND
R7
0.51k
R3
0.51k
R12
100Ω
R4
1k
FGND
FGND
C2
1µF R8
0.51k
R9
1k
R10
1k
R11
10k
3.3V
3.3V
R
SNS
0.02Ω
VDD
GND
µP
SCL
SDA
INT
T1
SMAJ70A
DIODES, INC
Q1
PZTA42
R1
1k
R5
1Ω
M1
BSP149
R2
1k
2945 TA09a
1µF
3.3V
10k 10k
VIN
0V TO 80V VOUT
RSNS
0.02Ω
VADIN
VCC
VL
ON
GND
DI1
SDA
SCL
DNC
DO2
DO1
GND
VDD
INTVCC
ADR0
ADR1
ADIN
ALERT
SDAO
SDAI
SCL
SENSE+
GND
SCL2
SDA2
O1
AV–
AV+
V–
V+
AVCC2
VCC2
I2
DNC
I1
GND2
SENSE–
LTC2945
LTM2883-3I
SCL
INT
SDA
VCC
GND
µP
C2
0.1µF
R2
10k
LTC2945
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For more information www.linear.com/LTC2945
TYPICAL APPLICATIONS
Wide Range –4V to –500V Negative Power Monitor (10kHz I2C Interface)
VEE
VEE
C2
0.1µF
CONTROL REGISTER A2 = 0
MOCD207M
MOCD207M
2945 TA10
ADR0
ADR1
ADIN
SCL
VDD
INTVCC
SDAI
SDAO
ALERT
SENSE–
GND
SENSE+
LTC2945
C1
0.1µF
V
EE
R7
0.51k
R3
1k
R13
10k
M1
BSP135
R4
1k
VOUT
R8
0.51k
R9
10k
R10
10k
R11
10k
3.3V
RSNS
0.02Ω
VDD
GND
µP
SCL
SDA
INT
R1
2k
R2
2k
R12
5k
R6
750k
Z1
4.7V
R5
750k
RTN
LTC2945
31
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For more information www.linear.com/LTC2945
PACKAGE DESCRIPTION
MSOP (MS12) 0213 REV A
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.22 –0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.650
(.0256)
BSC
12 11 10 9 8 7
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ±0.038
(.0165
±.0015)
TYP
0.65
(.0256)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.1016 ±
0.0508
(.004 ±.002)
1 2 3 4 5 6
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.406 ±0.076
(.016 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev A)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC2945
32
2945fb
For more information www.linear.com/LTC2945
PACKAGE DESCRIPTION
3.00 ± 0.10
(4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(4-SIDES)
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
11 12
2
0.50 BSC
0.200 REF
2.10 ±0.05
3.50
±0.05
0.70 ±0.05
0.00 – 0.05
(UD12) QFN 0709 REV Ø
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
UD Package
12-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1855 Rev Ø)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC2945
33
2945fb
For more information www.linear.com/LTC2945
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/13 Added Limits to Full-Scale Voltage
Removed Note 5 from I2C Interface Timing
Added Note 5 to SCL, SDAI Input Capacitance
Added ADIN and Resistive Divider Information with Regards to Figure 3a and Figure 3c
Revised Figure 3a and Figure 3c
Revised Figure 13 and Figure 17
Revised Bottom Figure
Top Figure: Replaced SMAJ78A with SMAJ70A and Changed C2 Connection from VEE to FGND
Added “Isolated Wide Range I2C Power Monitor” Figure
4
5
5
12
13
19, 20
26
29
29
B 9/15 Added H-grade 2, 3
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2945
34
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For more information www.linear.com/LTC2945
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC4151 High Voltage I2C Current and Voltage Monitor 7V to 80V Operation, 12-Bit Resolution with ±1.25% TUE
LT6105 Rail-to-Rail Input Current Sense Amplifier Very Wide Input Common Mode Range, 2.85V to 36V Operation
LTC2450 Easy-to-Use, Ultra-Tiny 16-Bit ADC GND to VCC Single-Ended Input Range, 0.02 LSB RMS Noise, 2 LSB INL
(No Missing Codes), 2 LSB Offset Error, 4 LSB Full-Scale Error
LTC4215 Single Channel, Hot Swap Controller with I2C Monitoring 8-Bit ADC, Adjustable Current Limit and Inrush, 2.9V to 15V Operation
LTC4222 Dual Channel, Hot Swap Controller with I2C Monitoring 10-Bit ADC, Adjustable Current Limit and Inrush, 2.9V to 29V Operation
LTC4260 Positive High Voltage Hot Swap Controller with I2C Monitoring 8-Bit ADC, Adjustable Current Limit and Inrush, 8.5V to 80V Operation
LTC4261 Negative High Voltage Hot Swap Controller with I2C Monitoring 10-Bit ADC, Floating Topology, Adjustable Inrush
LTC2940 Power and Current Monitor Four-Quadrant Multiplication, ±5% Power Accuracy, 4V to 80V Operation
LTC2970 Dual I2C Power Supply Monitor and Margining Controller 14-Bit ADC with ±0.5% TUE, Dual 8-Bit DACs
LTC2974 Quad Digital Power Supply Manager with EEPROM 16-Bit ADC with ±0.25% TUE, Supervise/Sequence/Monitor/Margin/
Trim, Configuration/Fault Logging EEPROM, I2C, Supervise/Monitor
Current and Temperature
LTC2978 Octal Digital Power Supply Manager with EEPROM 16-Bit ADC with ±0.25% TUE, Supervise/Sequence/Monitor/Margin/
Trim, Configuration/Fault Logging EEPROM, I2C
Rail-to-Rail Bidirectional Current and Power Monitor3.3V Input Supply Monitor with 12V VDD Input
V
+
IN
–
IN
+
V
–
LT6105
2.7V TO 5.9V
VOUT
VIN
0V TO 44V
SENSE
+
SENSE–
ALERT
SCL
SDAI
ADINADR0
ADR1
LTC2945
SDAO
INTVCC
VDD
RSNS
0.02Ω
RIN1
1k
RIN2
1k
TO
LOAD
R
ADIN
20k
I2C
INTERFACE
2945 TA11
GND
FORWARD SENSE+∆SENSE INTERNALLY GENERATED
USE EXTERNAL µP TO
MULTIPLY VOLTAGE (SENSE+)
AND CURRENT (ADIN) DATA
ADINSENSE+
1
VOLTAGE
DATA
CURRENT
DATA
POWER
DATA
CONTROL REG
A2
1REVERSE
C2
0.1µF
R1
2k
R2
2k
R3
2k
VIN
3.3V
3.3V
12V
R
SNS
0.02Ω
VOUT
VDD
VADIN
VDD
ADR0
INTVCC
SENSE+
GND GND
2945 TA12
SENSE–
LTC2945
ADR1
SCL SCL
SDA
SDAI
SDAO
ADIN
ALERT INT
µP
LINEAR TECHNOLOGY CORPORATION 2012
LT 0915 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2945
