BS62LV4003TI - Brilliance Semiconductor, Inc.

R0201-BS62LV4003 Revision 2.0

April 2002

BSI Low Power/Voltage CMOS SRAM

512K X 8 bit

• Very low operation voltage : 2.4V ~ 3.6V

• Very low power consumption

Vcc = 3.0V C-grade: 20mA (Max.) operating current

I -grade: 25mA (Max.) operating current

0.25uA (Typ.) CMOS standby current

• High speed access time :

-70 70ns (Max.) at Vcc = 3.0V

-10 100ns (Max.) at Vcc = 3.0V

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

The BS62LV4003 is a high performance , very low power CMOS Static

Random Access Memory organized as 524,288 words by 8 bits and

operates from a wide range of 2.4V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current

of 0.25uA and maximum access time of 70ns in 3.0V operation.

Easy memory expansion is provided by an active LOW chip

enable (CE), and active LOW output enable (OE) and three-state

output drivers.

The BS62LV4003 has an automatic power down feature , reducing the

power consumption significantly when chip is deselected.

The BS62LV4003 is available in the JEDEC standard 32 pin SOP,

32 pin PDIP, 32 pin TSOPII, 32 pin TSOP and 32 pin Small TSOP.

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

Address

Input

Buffer

Row

Decoder

Memory Array

2048 X 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Data

Buffer

Output

Address Input Buffer

Data

Buffer

Input

Control

Gnd

Vdd

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

A13

A17

A15

A18

A16

A14

A12

256

2048

A11 A9 A8 A3 A2 A1 A0 A10

BS62LV4003

POWER DISSIPATION

SPEED

( ns ) STANDBY

( ICCSB1, Max )

Operating

( ICC, Max )

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

Vcc=3.0V

PKG TYPE

BS62LV4003SC SOP-32

BS62LV4003EC TSOP2-32

BS62LV4003TC TSOP- 32

BS62LV4003STC STSOP- 32

BS62LV4003PC

+0OC to +70OC 2.4V ~ 3.6V 70 / 100 1.5uA 20mA

PDIP- 32

BS62LV4003SI SOP- 32

BS62LV4003EI TSOP2- 32

BS62LV4003TI TSOP- 32

BS62LV4003STI STSOP- 32

BS62LV4003PI

-40 OC to +85OC 2.4V ~ 3.6V 70 / 100 3uA 25mA

PDIP- 32

A18

A16

A14

A12

DQ0

DQ1

DQ2

GND

VCC

A15

A17

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

•

BS62LV4003SC

BS62LV4003SI

BS62LV4003EC

BS62LV4003EI

BS62LV4003PC

BS62LV4003PI

A10

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A11

A13

A17

A15

VCC

A18

A16

A14

A12

•

BS62LV4003TC

BS62LV4003STC

BS62LV4003TI

BS62LV4003STI

Vcc=3V Vcc=3V

R0201-BS62LV4003 Revision 2.0

April 2002

Name Function

A0-A18 Address Input These 19 address inputs select one of the 524,288 x 8-bit words in the RAM

CE Chip Enable Input CE is active LOW. Chip enable must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

DQ0-DQ7 Data Input/Output

Ports

These 8 bi-directional ports are used to read data from or write data into the RAM.

Vcc Power Supply

Gnd Ground

TRUTH TABLE

PIN DESCRIPTIONS

BSI

MODE WE CE OE I/O OPERATION Vcc CURRENT

Not selected X H X High Z ICCSB, ICCSB1

Output Disabled H L H High Z ICC

Read H L L DOUT ICC

Write L L X DIN ICC

SYMBOL PARAMETER CONDITIONS MAX. UNIT

CIN Input

Capacitance VIN=0V 6 pF

CDQ Input/Output

Capacitance VI/O=0V 8 pF

ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE

CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

1. This parameter is guaranteed and not 100% tested.

SYMBOL PARAMETER RATING UNITS

TERM Terminal Voltage with

Respect to GND

-0.5 to

Vcc+0.5 V

BIAS Temperature Under Bias -40 to +125 O C

STG Storage Temperature -60 to +150 O C

TPower Dissipation 1.0 W

OUT DC Output Current 20 mA

BS62LV4003

RANGE AMBIENT

TEMPERATURE Vcc

Commercial 0 O C to +70 O C 2.4~3.6V

Industrial -40 O C to +85 O C 2.4~3.6V

R0201-BS62LV4003 Revision 2.0

April 2002

PARAMETER

NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS

VIL Guaranteed Input Low

Voltage(2) Vcc=3.0V -0.5 -- 0.8 V

VIH Guaranteed Input High

Voltage(2) Vcc=3.0V 2.0 -- Vcc+0.2 V

IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA

ILO Output Leakage Current

Vcc = Max, CE = VIH, or OE = VIH,

VI/O = 0V to Vcc -- -- 1 uA

VOL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=3.0V -- -- 0.4 V

VOH Output High Voltage Vcc = Min, IOH = -1mA Vcc=3.0V 2.4 -- -- V

ICC Operating Power Supply

Current CE = VIL, IDQ = 0mA, F = Fmax(3) Vcc=3.0V -- -- 20 mA

ICCSB Standby Current-TTL CE = VIH, IDQ = 0mA Vcc=3.0V -- -- 1 mA

ICCSB1 Standby Current-CMOS

CE ≧ Vcc-0.2V,

VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V Vcc=3.0V -- 0.25 1.5 uA

1. Typical characteristics are at TA= 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/tRC .

DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )

1. Vcc = 1.5V, TA= + 25OC

2. tRC = Read Cycle Time

DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )

BSI

LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

Vcc

tCDR

Vcc

VIHVIH

Vcc VDR 1.5V

≥

CE Vcc - 0.2V

≥

BS62LV4003

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS

VDR Vcc for Data Retention CE ≧ Vcc - 0.2V

VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 -- -- V

ICCDR Data Retention Current CE ≧ Vcc - 0.2V

VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V -- 0.1 1 uA

tCDR Chip Deselect to Data

Retention Time 0 -- -- ns

tR Operation Recovery Time

See Retention Waveform

TRC

(2) -- -- ns

R0201-BS62LV4003 Revision 2.0

April 2002

JEDEC

PARAMETER

NAME

PARAMETER

NAME DESCRIPTION BS62LV4003-70

MIN. TYP. MAX.

BS62LV4003-10

MIN. TYP. MAX. UNIT

tAVAX tRC Read Cycle Time 70 -- -- 100 -- -- ns

tAVQV tAA Address Access Time -- -- 70 -- -- 100 ns

tELQV tACS Chip Select Access Time -- -- 70 -- -- 100 ns

tGLQV tOE Output Enable to Output Valid -- -- 35 -- -- 50 ns

tELQX tCLZ Chip Select to Output Low Z 10 -- -- 15 -- -- ns

tGLQX tOLZ Output Enable to Output in Low Z 10 -- -- 15 -- -- ns

tEHQZ tCHZ Chip Deselect to Output in High Z 0 -- 35 0 -- 40 ns

tGHQZ tOHZ Output Disable to Output in High Z 0 -- 30 0 -- 35 ns

tAXOX tOH Output Disable to Output Address Change 10 -- -- 15 -- -- ns

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )

READ CYCLE

BSI BS62LV4003

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE

STEADY

MAY CHANGE

FROM H TO L

DON T CARE:

ANY CHANGE

PERMITTED

DOES NOT

APPLY

MUST BE

STEADY

WILL BE

CHANGE

FROM H TO L

CHANGE :

STATE

UNKNOWN

CENTER

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

MAY CHANGE

FROM L TO H

WILL BE

CHANGE

FROM L TO H

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

Vcc / 0V

Input Rise and Fall Times

1V/ns

Input and Output

Timing Reference Level

0.5Vcc

Output Load

CL = 100pF+1TTL

CL = 30pF+1TTL

R0201-BS62LV4003 Revision 2.0

April 2002

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = VIL.

3. Address valid prior to or coincident with CE transition low.

4. OE = VIL .

5. The parameter is guaranteed but not 100% tested.

BSI BS62LV4003

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 (1,2,4)

t RC

t OH

t AA

DOUT

ADDRESS

t OH

READ CYCLE3 (1,4)

READ CYCLE2 (1,3,4)

tCLZ (5)

t CHZ (5)

D OUT

tACS

t OH

t RC

tOE

D OUT

ADDRESS

tCLZ (5)

t ACS

t CHZ

(1,5)

t OHZ (5)

tOLZ

tAA

R0201-BS62LV4003 Revision 2.0

April 2002

JEDEC

PARAMETER

NAME

PARAMETER

NAME DESCRIPTION BS62LV4003-70

MIN. TYP. MAX.

BS62LV4003-10

MIN. TYP. MAX. UNIT

tAVAX tWC Write Cycle Time 70 -- -- 100 -- -- ns

tE1LWH tCW Chip Select to End of Write 70 -- -- 100 -- -- ns

tAVWLtAS Address Set up Time 0----0---- ns

tAVWH tAW Address Valid to End of Write 70 -- -- 100 -- -- ns

tWLWH tWP Write Pulse Width 35 -- -- 50 -- -- ns

tWHAX tWR Write Recovery Time (CE , WE) 0----0---- ns

tWLOZ tWHZ Write to Output in High Z -- -- 30 -- -- 40 ns

tDVWH tDW Data to Write Time Overlap 30 -- -- 40 -- -- ns

tWHDX tDH Data Hold from Write Time 0----0---- ns

tGHOZ tOHZ Output Disable to Output in High Z 0 -- 30 0 -- 40 ns

tWHQX tOW End ot Write to Output Active 5----10---- ns

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )

WRITE CYCLE

BSI BS62LV4003

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1 (1)

t WR

(3)

t CW

(10)

(2)

t WP

t AW

t OHZ

(4,11)

t AS

t DH

t DW

DIN

D OUT

ADDRESS

(5)

t WC

R0201-BS62LV4003 Revision 2.0

April 2002

BSI BS62LV4003

WRITE CYCLE2 (1,6)

t WC

tCW

(10)

(2)

t WP

t AW

t WHZ

(4,11)

t AS

t DH

t DW

DIN

D OUT

ADDRESS

(5)

t OW (7) (8)

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.

The data input setup and hold timing should be referenced to the second transition edge of

the signal that terminates the write.

3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = VIL ).

7. DOUT is the same phase of write data of this write cycle.

8. DOUT is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. TCW is measured from the later of CE going low to the end of write.

11. The parameter is guaranteed but not 100% tested.

R0201-BS62LV4003 Revision 2.0

April 2002

BSI BS62LV4003

PACKAGE

S: SOP

E: TSOP 2

ST: Small TSOP

T: TSOP

P: PDIP

ORDERING INFORMATION

BS62LV4003 X X -- Y Y

GRADE

C: +0oC ~ +70oC

I: -40oC ~ +85oC

SPEED

70: 70ns

10: 100ns

PACKAGE DIMENSIONS

BASE METAL

WITH PLATING

cc1

SECTION A-A

SOP -32

R0201-BS62LV4003 Revision 2.0

April 2002

BSI BS62LV4003

PACKAGE DIMENSIONS (continued)

TSOP - 32

TSOP2 - 32

R0201-BS62LV4003 Revision 2.0

April 2002

BSI BS62LV4003

PACKAGE DIMENSIONS (continued)

PDIP - 32

STSOP - 32